[deliverable/linux.git] / drivers / staging / imx-drm / ipu-v3 / ipu-dc.c

/*
 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */

#include <linux/export.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/io.h>

#include "../imx-drm.h"
#include "imx-ipu-v3.h"
#include "ipu-prv.h"

#define DC_MAP_CONF_PTR(n)	(0x108 + ((n) & ~0x1) * 2)
#define DC_MAP_CONF_VAL(n)	(0x144 + ((n) & ~0x1) * 2)

#define DC_EVT_NF		0
#define DC_EVT_NL		1
#define DC_EVT_EOF		2
#define DC_EVT_NFIELD		3
#define DC_EVT_EOL		4
#define DC_EVT_EOFIELD		5
#define DC_EVT_NEW_ADDR		6
#define DC_EVT_NEW_CHAN		7
#define DC_EVT_NEW_DATA		8

#define DC_EVT_NEW_ADDR_W_0	0
#define DC_EVT_NEW_ADDR_W_1	1
#define DC_EVT_NEW_CHAN_W_0	2
#define DC_EVT_NEW_CHAN_W_1	3
#define DC_EVT_NEW_DATA_W_0	4
#define DC_EVT_NEW_DATA_W_1	5
#define DC_EVT_NEW_ADDR_R_0	6
#define DC_EVT_NEW_ADDR_R_1	7
#define DC_EVT_NEW_CHAN_R_0	8
#define DC_EVT_NEW_CHAN_R_1	9
#define DC_EVT_NEW_DATA_R_0	10
#define DC_EVT_NEW_DATA_R_1	11

#define DC_WR_CH_CONF		0x0
#define DC_WR_CH_ADDR		0x4
#define DC_RL_CH(evt)		(8 + ((evt) & ~0x1) * 2)

#define DC_GEN			0xd4
#define DC_DISP_CONF1(disp)	(0xd8 + (disp) * 4)
#define DC_DISP_CONF2(disp)	(0xe8 + (disp) * 4)
#define DC_STAT			0x1c8

#define WROD(lf)		(0x18 | ((lf) << 1))
#define WRG			0x01
#define WCLK			0xc9

#define SYNC_WAVE 0
#define NULL_WAVE (-1)

#define DC_GEN_SYNC_1_6_SYNC	(2 << 1)
#define DC_GEN_SYNC_PRIORITY_1	(1 << 7)

#define DC_WR_CH_CONF_WORD_SIZE_8		(0 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_16		(1 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_24		(2 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_32		(3 << 0)
#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)	(((i) & 0x1) << 3)
#define DC_WR_CH_CONF_DISP_ID_SERIAL		(2 << 3)
#define DC_WR_CH_CONF_DISP_ID_ASYNC		(3 << 4)
#define DC_WR_CH_CONF_FIELD_MODE		(1 << 9)
#define DC_WR_CH_CONF_PROG_TYPE_NORMAL		(4 << 5)
#define DC_WR_CH_CONF_PROG_TYPE_MASK		(7 << 5)
#define DC_WR_CH_CONF_PROG_DI_ID		(1 << 2)
#define DC_WR_CH_CONF_PROG_DISP_ID(i)		(((i) & 0x1) << 3)

#define IPU_DC_NUM_CHANNELS	10

struct ipu_dc_priv;

enum ipu_dc_map {
	IPU_DC_MAP_RGB24,
	IPU_DC_MAP_RGB565,
	IPU_DC_MAP_GBR24, /* TVEv2 */
	IPU_DC_MAP_BGR666,
	IPU_DC_MAP_BGR24,
};

struct ipu_dc {
	/* The display interface number assigned to this dc channel */
	unsigned int		di;
	void __iomem		*base;
	struct ipu_dc_priv	*priv;
	int			chno;
	bool			in_use;
};

struct ipu_dc_priv {
	void __iomem		*dc_reg;
	void __iomem		*dc_tmpl_reg;
	struct ipu_soc		*ipu;
	struct device		*dev;
	struct ipu_dc		channels[IPU_DC_NUM_CHANNELS];
	struct mutex		mutex;
};

static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
{
	u32 reg;

	reg = readl(dc->base + DC_RL_CH(event));
	reg &= ~(0xffff << (16 * (event & 0x1)));
	reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
	writel(reg, dc->base + DC_RL_CH(event));
}

static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
		int map, int wave, int glue, int sync, int stop)
{
	struct ipu_dc_priv *priv = dc->priv;
	u32 reg1, reg2;

	if (opcode == WCLK) {
		reg1 = (operand << 20) & 0xfff00000;
		reg2 = operand >> 12 | opcode << 1 | stop << 9;
	} else if (opcode == WRG) {
		reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
		reg2 = operand >> 17 | opcode << 7 | stop << 9;
	} else {
		reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
		reg2 = operand >> 12 | opcode << 4 | stop << 9;
	}
	writel(reg1, priv->dc_tmpl_reg + word * 8);
	writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
}

static int ipu_pixfmt_to_map(u32 fmt)
{
	switch (fmt) {
	case V4L2_PIX_FMT_RGB24:
		return IPU_DC_MAP_RGB24;
	case V4L2_PIX_FMT_RGB565:
		return IPU_DC_MAP_RGB565;
	case IPU_PIX_FMT_GBR24:
		return IPU_DC_MAP_GBR24;
	case V4L2_PIX_FMT_BGR666:
		return IPU_DC_MAP_BGR666;
	case V4L2_PIX_FMT_BGR24:
		return IPU_DC_MAP_BGR24;
	default:
		return -EINVAL;
	}
}

int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
		u32 pixel_fmt, u32 width)
{
	struct ipu_dc_priv *priv = dc->priv;
	u32 reg = 0;
	int map;

	dc->di = ipu_di_get_num(di);

	map = ipu_pixfmt_to_map(pixel_fmt);
	if (map < 0) {
		dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
		return map;
	}

	if (interlaced) {
		dc_link_event(dc, DC_EVT_NL, 0, 3);
		dc_link_event(dc, DC_EVT_EOL, 0, 2);
		dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);

		/* Init template microcode */
		dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
	} else {
		if (dc->di) {
			dc_link_event(dc, DC_EVT_NL, 2, 3);
			dc_link_event(dc, DC_EVT_EOL, 3, 2);
			dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
			/* Init template microcode */
			dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
			dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
			dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
			dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
		} else {
			dc_link_event(dc, DC_EVT_NL, 5, 3);
			dc_link_event(dc, DC_EVT_EOL, 6, 2);
			dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
			/* Init template microcode */
			dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
			dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
			dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
			dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
		}
	}
	dc_link_event(dc, DC_EVT_NF, 0, 0);
	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
	dc_link_event(dc, DC_EVT_EOF, 0, 0);
	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);

	reg = readl(dc->base + DC_WR_CH_CONF);
	if (interlaced)
		reg |= DC_WR_CH_CONF_FIELD_MODE;
	else
		reg &= ~DC_WR_CH_CONF_FIELD_MODE;
	writel(reg, dc->base + DC_WR_CH_CONF);

	writel(0x0, dc->base + DC_WR_CH_ADDR);
	writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));

	ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dc_init_sync);

void ipu_dc_enable_channel(struct ipu_dc *dc)
{
	int di;
	u32 reg;

	di = dc->di;

	reg = readl(dc->base + DC_WR_CH_CONF);
	reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
	writel(reg, dc->base + DC_WR_CH_CONF);
}
EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);

void ipu_dc_disable_channel(struct ipu_dc *dc)
{
	struct ipu_dc_priv *priv = dc->priv;
	u32 val;
	int irq = 0, timeout = 50;

	if (dc->chno == 1)
		irq = IPU_IRQ_DC_FC_1;
	else if (dc->chno == 5)
		irq = IPU_IRQ_DP_SF_END;
	else
		return;

	/* should wait for the interrupt here */
	mdelay(50);

	if (dc->di == 0)
		val = 0x00000002;
	else
		val = 0x00000020;

	/* Wait for DC triple buffer to empty */
	while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
		msleep(2);
		timeout -= 2;
		if (timeout <= 0)
			break;
	}

	val = readl(dc->base + DC_WR_CH_CONF);
	val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
	writel(val, dc->base + DC_WR_CH_CONF);
}
EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);

static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
		int byte_num, int offset, int mask)
{
	int ptr = map * 3 + byte_num;
	u32 reg;

	reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
	reg &= ~(0xffff << (16 * (ptr & 0x1)));
	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
	writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));

	reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
	writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
}

static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
{
	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));

	writel(reg & ~(0xffff << (16 * (map & 0x1))),
		     priv->dc_reg + DC_MAP_CONF_PTR(map));
}

struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
{
	struct ipu_dc_priv *priv = ipu->dc_priv;
	struct ipu_dc *dc;

	if (channel >= IPU_DC_NUM_CHANNELS)
		return ERR_PTR(-ENODEV);

	dc = &priv->channels[channel];

	mutex_lock(&priv->mutex);

	if (dc->in_use) {
		mutex_unlock(&priv->mutex);
		return ERR_PTR(-EBUSY);
	}

	dc->in_use = 1;

	mutex_unlock(&priv->mutex);

	return dc;
}
EXPORT_SYMBOL_GPL(ipu_dc_get);

void ipu_dc_put(struct ipu_dc *dc)
{
	struct ipu_dc_priv *priv = dc->priv;

	mutex_lock(&priv->mutex);
	dc->in_use = 0;
	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dc_put);

int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
		unsigned long base, unsigned long template_base)
{
	struct ipu_dc_priv *priv;
	static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
		0x78, 0, 0x94, 0xb4};
	int i;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	mutex_init(&priv->mutex);

	priv->dev = dev;
	priv->ipu = ipu;
	priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
	priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
	if (!priv->dc_reg || !priv->dc_tmpl_reg)
		return -ENOMEM;

	for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
		priv->channels[i].chno = i;
		priv->channels[i].priv = priv;
		priv->channels[i].base = priv->dc_reg + channel_offsets[i];
	}

	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
			DC_WR_CH_CONF_PROG_DI_ID,
			priv->channels[1].base + DC_WR_CH_CONF);
	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
			priv->channels[5].base + DC_WR_CH_CONF);

	writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1, priv->dc_reg + DC_GEN);

	ipu->dc_priv = priv;

	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
			base, template_base);

	/* rgb24 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */

	/* rgb565 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */

	/* gbr24 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */

	/* bgr666 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */

	/* bgr24 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */

	return 0;
}

void ipu_dc_exit(struct ipu_soc *ipu)
{
}
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
	3	* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	12	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*/
	15
	16	#include <linux/export.h>
	17	#include <linux/module.h>
	18	#include <linux/types.h>
	19	#include <linux/errno.h>
	20	#include <linux/delay.h>
	21	#include <linux/io.h>
	22
eeb14ec8	23	#include "../imx-drm.h"
aecfbdb1 SH	24	#include "imx-ipu-v3.h"
	25	#include "ipu-prv.h"
	26
	27	#define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
	28	#define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
	29
	30	#define DC_EVT_NF 0
	31	#define DC_EVT_NL 1
	32	#define DC_EVT_EOF 2
	33	#define DC_EVT_NFIELD 3
	34	#define DC_EVT_EOL 4
	35	#define DC_EVT_EOFIELD 5
	36	#define DC_EVT_NEW_ADDR 6
	37	#define DC_EVT_NEW_CHAN 7
	38	#define DC_EVT_NEW_DATA 8
	39
	40	#define DC_EVT_NEW_ADDR_W_0 0
	41	#define DC_EVT_NEW_ADDR_W_1 1
	42	#define DC_EVT_NEW_CHAN_W_0 2
	43	#define DC_EVT_NEW_CHAN_W_1 3
	44	#define DC_EVT_NEW_DATA_W_0 4
	45	#define DC_EVT_NEW_DATA_W_1 5
	46	#define DC_EVT_NEW_ADDR_R_0 6
	47	#define DC_EVT_NEW_ADDR_R_1 7
	48	#define DC_EVT_NEW_CHAN_R_0 8
	49	#define DC_EVT_NEW_CHAN_R_1 9
	50	#define DC_EVT_NEW_DATA_R_0 10
	51	#define DC_EVT_NEW_DATA_R_1 11
	52
	53	#define DC_WR_CH_CONF 0x0
	54	#define DC_WR_CH_ADDR 0x4
	55	#define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
	56
	57	#define DC_GEN 0xd4
	58	#define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
	59	#define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
	60	#define DC_STAT 0x1c8
	61
	62	#define WROD(lf) (0x18 \| ((lf) << 1))
	63	#define WRG 0x01
85eacb06	64	#define WCLK 0xc9
aecfbdb1 SH	65
aecfbdb1 SH	66	#define SYNC_WAVE 0
85eacb06	67	#define NULL_WAVE (-1)
aecfbdb1 SH	68
	69	#define DC_GEN_SYNC_1_6_SYNC (2 << 1)
	70	#define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
	71
	72	#define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
	73	#define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
	74	#define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
	75	#define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
	76	#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
	77	#define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
	78	#define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
	79	#define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
	80	#define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
	81	#define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
	82	#define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
	83	#define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
	84
	85	#define IPU_DC_NUM_CHANNELS 10
	86
	87	struct ipu_dc_priv;
	88
	89	enum ipu_dc_map {
	90	IPU_DC_MAP_RGB24,
	91	IPU_DC_MAP_RGB565,
eeb14ec8	92	IPU_DC_MAP_GBR24, /* TVEv2 */
7d0a66c0	93	IPU_DC_MAP_BGR666,
0b186416	94	IPU_DC_MAP_BGR24,
aecfbdb1 SH	95	};
	96
	97	struct ipu_dc {
	98	/* The display interface number assigned to this dc channel */
	99	unsigned int di;
	100	void __iomem *base;
	101	struct ipu_dc_priv *priv;
	102	int chno;
	103	bool in_use;
	104	};
	105
	106	struct ipu_dc_priv {
	107	void __iomem *dc_reg;
	108	void __iomem *dc_tmpl_reg;
	109	struct ipu_soc *ipu;
	110	struct device *dev;
	111	struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
	112	struct mutex mutex;
	113	};
	114
	115	static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
	116	{
	117	u32 reg;
	118
	119	reg = readl(dc->base + DC_RL_CH(event));
	120	reg &= ~(0xffff << (16 * (event & 0x1)));
	121	reg \|= ((addr << 8) \| priority) << (16 * (event & 0x1));
	122	writel(reg, dc->base + DC_RL_CH(event));
	123	}
	124
	125	static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
85eacb06	126	int map, int wave, int glue, int sync, int stop)
aecfbdb1 SH	127	{
aecfbdb1 SH	128	struct ipu_dc_priv *priv = dc->priv;
85eacb06 PZ	129	u32 reg1, reg2;
	130
	131	if (opcode == WCLK) {
	132	reg1 = (operand << 20) & 0xfff00000;
	133	reg2 = operand >> 12 \| opcode << 1 \| stop << 9;
	134	} else if (opcode == WRG) {
	135	reg1 = sync \| glue << 4 \| ++wave << 11 \| ((operand << 15) & 0xffff8000);
	136	reg2 = operand >> 17 \| opcode << 7 \| stop << 9;
	137	} else {
	138	reg1 = sync \| glue << 4 \| ++wave << 11 \| ++map << 15 \| ((operand << 20) & 0xfff00000);
	139	reg2 = operand >> 12 \| opcode << 4 \| stop << 9;
	140	}
	141	writel(reg1, priv->dc_tmpl_reg + word * 8);
	142	writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
aecfbdb1 SH	143	}
	144
	145	static int ipu_pixfmt_to_map(u32 fmt)
	146	{
	147	switch (fmt) {
	148	case V4L2_PIX_FMT_RGB24:
	149	return IPU_DC_MAP_RGB24;
	150	case V4L2_PIX_FMT_RGB565:
	151	return IPU_DC_MAP_RGB565;
eeb14ec8 PZ	152	case IPU_PIX_FMT_GBR24:
eeb14ec8 PZ	153	return IPU_DC_MAP_GBR24;
7d0a66c0 MV	154	case V4L2_PIX_FMT_BGR666:
7d0a66c0 MV	155	return IPU_DC_MAP_BGR666;
0b186416 PZ	156	case V4L2_PIX_FMT_BGR24:
0b186416 PZ	157	return IPU_DC_MAP_BGR24;
aecfbdb1 SH	158	default:
	159	return -EINVAL;
	160	}
	161	}
	162
	163	int ipu_dc_init_sync(struct ipu_dc dc, struct ipu_di di, bool interlaced,
	164	u32 pixel_fmt, u32 width)
	165	{
	166	struct ipu_dc_priv *priv = dc->priv;
df2da9a3 DC	167	u32 reg = 0;
df2da9a3 DC	168	int map;
aecfbdb1 SH	169
	170	dc->di = ipu_di_get_num(di);
	171
	172	map = ipu_pixfmt_to_map(pixel_fmt);
	173	if (map < 0) {
	174	dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
df2da9a3	175	return map;
aecfbdb1 SH	176	}
	177
	178	if (interlaced) {
	179	dc_link_event(dc, DC_EVT_NL, 0, 3);
	180	dc_link_event(dc, DC_EVT_EOL, 0, 2);
	181	dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
	182
	183	/* Init template microcode */
85eacb06	184	dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
aecfbdb1 SH	185	} else {
	186	if (dc->di) {
	187	dc_link_event(dc, DC_EVT_NL, 2, 3);
	188	dc_link_event(dc, DC_EVT_EOL, 3, 2);
da0cedec	189	dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
aecfbdb1	190	/* Init template microcode */
85eacb06	191	dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
da0cedec PZ	192	dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
	193	dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
	194	dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
aecfbdb1 SH	195	} else {
	196	dc_link_event(dc, DC_EVT_NL, 5, 3);
	197	dc_link_event(dc, DC_EVT_EOL, 6, 2);
da0cedec	198	dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
aecfbdb1	199	/* Init template microcode */
85eacb06	200	dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
da0cedec PZ	201	dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
	202	dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
	203	dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
aecfbdb1 SH	204	}
	205	}
	206	dc_link_event(dc, DC_EVT_NF, 0, 0);
	207	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
	208	dc_link_event(dc, DC_EVT_EOF, 0, 0);
	209	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
	210	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
	211	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
	212
	213	reg = readl(dc->base + DC_WR_CH_CONF);
	214	if (interlaced)
	215	reg \|= DC_WR_CH_CONF_FIELD_MODE;
	216	else
	217	reg &= ~DC_WR_CH_CONF_FIELD_MODE;
	218	writel(reg, dc->base + DC_WR_CH_CONF);
	219
	220	writel(0x0, dc->base + DC_WR_CH_ADDR);
	221	writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
	222
	223	ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
	224
	225	return 0;
	226	}
	227	EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
	228
	229	void ipu_dc_enable_channel(struct ipu_dc *dc)
	230	{
	231	int di;
	232	u32 reg;
	233
	234	di = dc->di;
	235
	236	reg = readl(dc->base + DC_WR_CH_CONF);
	237	reg \|= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
	238	writel(reg, dc->base + DC_WR_CH_CONF);
	239	}
	240	EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
	241
	242	void ipu_dc_disable_channel(struct ipu_dc *dc)
	243	{
	244	struct ipu_dc_priv *priv = dc->priv;
	245	u32 val;
	246	int irq = 0, timeout = 50;
	247
	248	if (dc->chno == 1)
	249	irq = IPU_IRQ_DC_FC_1;
	250	else if (dc->chno == 5)
	251	irq = IPU_IRQ_DP_SF_END;
	252	else
	253	return;
	254
	255	/* should wait for the interrupt here */
	256	mdelay(50);
	257
	258	if (dc->di == 0)
	259	val = 0x00000002;
	260	else
	261	val = 0x00000020;
	262
	263	/* Wait for DC triple buffer to empty */
	264	while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
	265	msleep(2);
	266	timeout -= 2;
	267	if (timeout <= 0)
268	break;
269	}
270
271	val = readl(dc->base + DC_WR_CH_CONF);
272	val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
273	writel(val, dc->base + DC_WR_CH_CONF);
274	}
275	EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
276
277	static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
278	int byte_num, int offset, int mask)
279	{
280	int ptr = map * 3 + byte_num;
281	u32 reg;
282
283	reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
284	reg &= ~(0xffff << (16 * (ptr & 0x1)));
285	reg \|= ((offset << 8) \| mask) << (16 * (ptr & 0x1));
286	writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
287
288	reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
289	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
290	reg \|= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
291	writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
292	}
293
294	static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
295	{
296	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
297
298	writel(reg & ~(0xffff << (16 * (map & 0x1))),
299	priv->dc_reg + DC_MAP_CONF_PTR(map));
300	}
301
302	struct ipu_dc ipu_dc_get(struct ipu_soc ipu, int channel)
303	{
304	struct ipu_dc_priv *priv = ipu->dc_priv;
305	struct ipu_dc *dc;
306
307	if (channel >= IPU_DC_NUM_CHANNELS)
308	return ERR_PTR(-ENODEV);
309
310	dc = &priv->channels[channel];
311
312	mutex_lock(&priv->mutex);
313
314	if (dc->in_use) {
315	mutex_unlock(&priv->mutex);
316	return ERR_PTR(-EBUSY);
317	}
318
319	dc->in_use = 1;
320
321	mutex_unlock(&priv->mutex);
322
323	return dc;
324	}
325	EXPORT_SYMBOL_GPL(ipu_dc_get);
326
327	void ipu_dc_put(struct ipu_dc *dc)
328	{
329	struct ipu_dc_priv *priv = dc->priv;
330
331	mutex_lock(&priv->mutex);
332	dc->in_use = 0;
333	mutex_unlock(&priv->mutex);
334	}
335	EXPORT_SYMBOL_GPL(ipu_dc_put);
336
337	int ipu_dc_init(struct ipu_soc ipu, struct device dev,
338	unsigned long base, unsigned long template_base)
339	{
340	struct ipu_dc_priv *priv;
341	static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
342	0x78, 0, 0x94, 0xb4};
343	int i;
344
345	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
346	if (!priv)
347	return -ENOMEM;
348
349	mutex_init(&priv->mutex);
350
351	priv->dev = dev;
352	priv->ipu = ipu;
353	priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
354	priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
355	if (!priv->dc_reg \|\| !priv->dc_tmpl_reg)
356	return -ENOMEM;
357
358	for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
359	priv->channels[i].chno = i;
360	priv->channels[i].priv = priv;
361	priv->channels[i].base = priv->dc_reg + channel_offsets[i];
362	}
363
364	writel(DC_WR_CH_CONF_WORD_SIZE_24 \| DC_WR_CH_CONF_DISP_ID_PARALLEL(1) \|
365	DC_WR_CH_CONF_PROG_DI_ID,
366	priv->channels[1].base + DC_WR_CH_CONF);
367	writel(DC_WR_CH_CONF_WORD_SIZE_24 \| DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
368	priv->channels[5].base + DC_WR_CH_CONF);
369
370	writel(DC_GEN_SYNC_1_6_SYNC \| DC_GEN_SYNC_PRIORITY_1, priv->dc_reg + DC_GEN);
371
372	ipu->dc_priv = priv;
373
374	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
375	base, template_base);
376
377	/* rgb24 */
378	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
379	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
380	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
381	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
382
383	/* rgb565 */
384	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
385	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
386	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
387	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
388
eeb14ec8 PZ	389	/* gbr24 */
	390	ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
	391	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
	392	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
	393	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
	394
7d0a66c0 MV	395	/* bgr666 */
	396	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
	397	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
	398	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
	399	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
	400
0b186416 PZ	401	/* bgr24 */
	402	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
	403	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
	404	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
	405	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
	406
aecfbdb1 SH	407	return 0;
	408	}
	409
	410	void ipu_dc_exit(struct ipu_soc *ipu)
	411	{
	412	}