[deliverable/linux.git] / drivers / staging / imx-drm / ipu-v3 / ipu-dmfc.c

/*
 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */
#include <linux/export.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/io.h>

#include "imx-ipu-v3.h"
#include "ipu-prv.h"

#define DMFC_RD_CHAN		0x0000
#define DMFC_WR_CHAN		0x0004
#define DMFC_WR_CHAN_DEF	0x0008
#define DMFC_DP_CHAN		0x000c
#define DMFC_DP_CHAN_DEF	0x0010
#define DMFC_GENERAL1		0x0014
#define DMFC_GENERAL2		0x0018
#define DMFC_IC_CTRL		0x001c
#define DMFC_STAT		0x0020

#define DMFC_WR_CHAN_1_28		0
#define DMFC_WR_CHAN_2_41		8
#define DMFC_WR_CHAN_1C_42		16
#define DMFC_WR_CHAN_2C_43		24

#define DMFC_DP_CHAN_5B_23		0
#define DMFC_DP_CHAN_5F_27		8
#define DMFC_DP_CHAN_6B_24		16
#define DMFC_DP_CHAN_6F_29		24

#define DMFC_FIFO_SIZE_64		(3 << 3)
#define DMFC_FIFO_SIZE_128		(2 << 3)
#define DMFC_FIFO_SIZE_256		(1 << 3)
#define DMFC_FIFO_SIZE_512		(0 << 3)

#define DMFC_SEGMENT(x)			((x & 0x7) << 0)
#define DMFC_BURSTSIZE_128		(0 << 6)
#define DMFC_BURSTSIZE_64		(1 << 6)
#define DMFC_BURSTSIZE_32		(2 << 6)
#define DMFC_BURSTSIZE_16		(3 << 6)

struct dmfc_channel_data {
	int		ipu_channel;
	unsigned long	channel_reg;
	unsigned long	shift;
	unsigned	eot_shift;
	unsigned	max_fifo_lines;
};

static const struct dmfc_channel_data dmfcdata[] = {
	{
		.ipu_channel	= 23,
		.channel_reg	= DMFC_DP_CHAN,
		.shift		= DMFC_DP_CHAN_5B_23,
		.eot_shift	= 20,
		.max_fifo_lines	= 3,
	}, {
		.ipu_channel	= 24,
		.channel_reg	= DMFC_DP_CHAN,
		.shift		= DMFC_DP_CHAN_6B_24,
		.eot_shift	= 22,
		.max_fifo_lines	= 1,
	}, {
		.ipu_channel	= 27,
		.channel_reg	= DMFC_DP_CHAN,
		.shift		= DMFC_DP_CHAN_5F_27,
		.eot_shift	= 21,
		.max_fifo_lines	= 2,
	}, {
		.ipu_channel	= 28,
		.channel_reg	= DMFC_WR_CHAN,
		.shift		= DMFC_WR_CHAN_1_28,
		.eot_shift	= 16,
		.max_fifo_lines	= 2,
	}, {
		.ipu_channel	= 29,
		.channel_reg	= DMFC_DP_CHAN,
		.shift		= DMFC_DP_CHAN_6F_29,
		.eot_shift	= 23,
		.max_fifo_lines	= 1,
	},
};

#define DMFC_NUM_CHANNELS	ARRAY_SIZE(dmfcdata)

struct ipu_dmfc_priv;

struct dmfc_channel {
	unsigned			slots;
	unsigned			slotmask;
	unsigned			segment;
	int				burstsize;
	struct ipu_soc			*ipu;
	struct ipu_dmfc_priv		*priv;
	const struct dmfc_channel_data	*data;
};

struct ipu_dmfc_priv {
	struct ipu_soc *ipu;
	struct device *dev;
	struct dmfc_channel channels[DMFC_NUM_CHANNELS];
	struct mutex mutex;
	unsigned long bandwidth_per_slot;
	void __iomem *base;
	int use_count;
};

int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;
	mutex_lock(&priv->mutex);

	if (!priv->use_count)
		ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);

	priv->use_count++;

	mutex_unlock(&priv->mutex);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);

void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;

	mutex_lock(&priv->mutex);

	priv->use_count--;

	if (!priv->use_count)
		ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);

	if (priv->use_count < 0)
		priv->use_count = 0;

	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);

static int ipu_dmfc_setup_channel(struct dmfc_channel *dmfc, int slots,
		int segment, int burstsize)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;
	u32 val, field;

	dev_dbg(priv->dev,
			"dmfc: using %d slots starting from segment %d for IPU channel %d\n",
			slots, segment, dmfc->data->ipu_channel);

	if (!dmfc)
		return -EINVAL;

	switch (slots) {
	case 1:
		field = DMFC_FIFO_SIZE_64;
		break;
	case 2:
		field = DMFC_FIFO_SIZE_128;
		break;
	case 4:
		field = DMFC_FIFO_SIZE_256;
		break;
	case 8:
		field = DMFC_FIFO_SIZE_512;
		break;
	default:
		return -EINVAL;
	}

	switch (burstsize) {
	case 16:
		field |= DMFC_BURSTSIZE_16;
		break;
	case 32:
		field |= DMFC_BURSTSIZE_32;
		break;
	case 64:
		field |= DMFC_BURSTSIZE_64;
		break;
	case 128:
		field |= DMFC_BURSTSIZE_128;
		break;
	}

	field |= DMFC_SEGMENT(segment);

	val = readl(priv->base + dmfc->data->channel_reg);

	val &= ~(0xff << dmfc->data->shift);
	val |= field << dmfc->data->shift;

	writel(val, priv->base + dmfc->data->channel_reg);

	dmfc->slots = slots;
	dmfc->segment = segment;
	dmfc->burstsize = burstsize;
	dmfc->slotmask = ((1 << slots) - 1) << segment;

	return 0;
}

static int dmfc_bandwidth_to_slots(struct ipu_dmfc_priv *priv,
		unsigned long bandwidth)
{
	int slots = 1;

	while (slots * priv->bandwidth_per_slot < bandwidth)
		slots *= 2;

	return slots;
}

static int dmfc_find_slots(struct ipu_dmfc_priv *priv, int slots)
{
	unsigned slotmask_need, slotmask_used = 0;
	int i, segment = 0;

	slotmask_need = (1 << slots) - 1;

	for (i = 0; i < DMFC_NUM_CHANNELS; i++)
		slotmask_used |= priv->channels[i].slotmask;

	while (slotmask_need <= 0xff) {
		if (!(slotmask_used & slotmask_need))
			return segment;

		slotmask_need <<= 1;
		segment++;
	}

	return -EBUSY;
}

void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;
	int i;

	dev_dbg(priv->dev, "dmfc: freeing %d slots starting from segment %d\n",
			dmfc->slots, dmfc->segment);

	mutex_lock(&priv->mutex);

	if (!dmfc->slots)
		goto out;

	dmfc->slotmask = 0;
	dmfc->slots = 0;
	dmfc->segment = 0;

	for (i = 0; i < DMFC_NUM_CHANNELS; i++)
		priv->channels[i].slotmask = 0;

	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
		if (priv->channels[i].slots > 0) {
			priv->channels[i].segment =
				dmfc_find_slots(priv, priv->channels[i].slots);
			priv->channels[i].slotmask =
				((1 << priv->channels[i].slots) - 1) <<
				priv->channels[i].segment;
		}
	}

	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
		if (priv->channels[i].slots > 0)
			ipu_dmfc_setup_channel(&priv->channels[i],
					priv->channels[i].slots,
					priv->channels[i].segment,
					priv->channels[i].burstsize);
	}
out:
	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dmfc_free_bandwidth);

int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
		unsigned long bandwidth_pixel_per_second, int burstsize)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;
	int slots = dmfc_bandwidth_to_slots(priv, bandwidth_pixel_per_second);
	int segment = -1, ret = 0;

	dev_dbg(priv->dev, "dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
			bandwidth_pixel_per_second / 1000000,
			dmfc->data->ipu_channel);

	ipu_dmfc_free_bandwidth(dmfc);

	mutex_lock(&priv->mutex);

	if (slots > 8) {
		ret = -EBUSY;
		goto out;
	}

	/* Always allocate at least 128*4 bytes (2 slots) */
	if (slots < 2)
		slots = 2;

	/* For the MEM_BG channel, first try to allocate twice the slots */
	if (dmfc->data->ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC)
		segment = dmfc_find_slots(priv, slots * 2);
	if (segment >= 0)
		slots *= 2;
	else
		segment = dmfc_find_slots(priv, slots);
	if (segment < 0) {
		ret = -EBUSY;
		goto out;
	}

	ipu_dmfc_setup_channel(dmfc, slots, segment, burstsize);

out:
	mutex_unlock(&priv->mutex);

	return ret;
}
EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth);

int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width)
{
	struct ipu_dmfc_priv *priv = dmfc->priv;
	u32 dmfc_gen1;

	dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);

	if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
		dmfc_gen1 |= 1 << dmfc->data->eot_shift;
	else
		dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);

	writel(dmfc_gen1, priv->base + DMFC_GENERAL1);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dmfc_init_channel);

struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
{
	struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
	int i;

	for (i = 0; i < DMFC_NUM_CHANNELS; i++)
		if (dmfcdata[i].ipu_channel == ipu_channel)
			return &priv->channels[i];
	return ERR_PTR(-ENODEV);
}
EXPORT_SYMBOL_GPL(ipu_dmfc_get);

void ipu_dmfc_put(struct dmfc_channel *dmfc)
{
	ipu_dmfc_free_bandwidth(dmfc);
}
EXPORT_SYMBOL_GPL(ipu_dmfc_put);

int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
		struct clk *ipu_clk)
{
	struct ipu_dmfc_priv *priv;
	int i;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base = devm_ioremap(dev, base, PAGE_SIZE);
	if (!priv->base)
		return -ENOMEM;

	priv->dev = dev;
	priv->ipu = ipu;
	mutex_init(&priv->mutex);

	ipu->dmfc_priv = priv;

	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
		priv->channels[i].priv = priv;
		priv->channels[i].ipu = ipu;
		priv->channels[i].data = &dmfcdata[i];
	}

	writel(0x0, priv->base + DMFC_WR_CHAN);
	writel(0x0, priv->base + DMFC_DP_CHAN);

	/*
	 * We have a total bandwidth of clkrate * 4pixel divided
	 * into 8 slots.
	 */
	priv->bandwidth_per_slot = clk_get_rate(ipu_clk) * 4 / 8;

	dev_dbg(dev, "dmfc: 8 slots with %ldMpixel/s bandwidth each\n",
			priv->bandwidth_per_slot / 1000000);

	writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
	writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
	writel(0x00000003, priv->base + DMFC_GENERAL1);

	return 0;
}

void ipu_dmfc_exit(struct ipu_soc *ipu)
{
}
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
	3	* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	12	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*/
	15	#include <linux/export.h>
	16	#include <linux/types.h>
	17	#include <linux/errno.h>
	18	#include <linux/io.h>
	19
	20	#include "imx-ipu-v3.h"
	21	#include "ipu-prv.h"
	22
	23	#define DMFC_RD_CHAN 0x0000
	24	#define DMFC_WR_CHAN 0x0004
	25	#define DMFC_WR_CHAN_DEF 0x0008
	26	#define DMFC_DP_CHAN 0x000c
	27	#define DMFC_DP_CHAN_DEF 0x0010
	28	#define DMFC_GENERAL1 0x0014
	29	#define DMFC_GENERAL2 0x0018
	30	#define DMFC_IC_CTRL 0x001c
	31	#define DMFC_STAT 0x0020
	32
	33	#define DMFC_WR_CHAN_1_28 0
	34	#define DMFC_WR_CHAN_2_41 8
	35	#define DMFC_WR_CHAN_1C_42 16
	36	#define DMFC_WR_CHAN_2C_43 24
	37
	38	#define DMFC_DP_CHAN_5B_23 0
	39	#define DMFC_DP_CHAN_5F_27 8
	40	#define DMFC_DP_CHAN_6B_24 16
	41	#define DMFC_DP_CHAN_6F_29 24
	42
	43	#define DMFC_FIFO_SIZE_64 (3 << 3)
	44	#define DMFC_FIFO_SIZE_128 (2 << 3)
	45	#define DMFC_FIFO_SIZE_256 (1 << 3)
	46	#define DMFC_FIFO_SIZE_512 (0 << 3)
	47
	48	#define DMFC_SEGMENT(x) ((x & 0x7) << 0)
	49	#define DMFC_BURSTSIZE_128 (0 << 6)
	50	#define DMFC_BURSTSIZE_64 (1 << 6)
	51	#define DMFC_BURSTSIZE_32 (2 << 6)
	52	#define DMFC_BURSTSIZE_16 (3 << 6)
	53
	54	struct dmfc_channel_data {
	55	int ipu_channel;
	56	unsigned long channel_reg;
	57	unsigned long shift;
	58	unsigned eot_shift;
	59	unsigned max_fifo_lines;
	60	};
	61
	62	static const struct dmfc_channel_data dmfcdata[] = {
	63	{
	64	.ipu_channel = 23,
65	.channel_reg = DMFC_DP_CHAN,
66	.shift = DMFC_DP_CHAN_5B_23,
67	.eot_shift = 20,
68	.max_fifo_lines = 3,
69	}, {
70	.ipu_channel = 24,
71	.channel_reg = DMFC_DP_CHAN,
72	.shift = DMFC_DP_CHAN_6B_24,
73	.eot_shift = 22,
74	.max_fifo_lines = 1,
75	}, {
76	.ipu_channel = 27,
77	.channel_reg = DMFC_DP_CHAN,
78	.shift = DMFC_DP_CHAN_5F_27,
79	.eot_shift = 21,
80	.max_fifo_lines = 2,
81	}, {
82	.ipu_channel = 28,
83	.channel_reg = DMFC_WR_CHAN,
84	.shift = DMFC_WR_CHAN_1_28,
85	.eot_shift = 16,
86	.max_fifo_lines = 2,
87	}, {
88	.ipu_channel = 29,
89	.channel_reg = DMFC_DP_CHAN,
90	.shift = DMFC_DP_CHAN_6F_29,
91	.eot_shift = 23,
92	.max_fifo_lines = 1,
93	},
94	};
95
96	#define DMFC_NUM_CHANNELS ARRAY_SIZE(dmfcdata)
97
98	struct ipu_dmfc_priv;
99
100	struct dmfc_channel {
101	unsigned slots;
102	unsigned slotmask;
103	unsigned segment;
104	int burstsize;
105	struct ipu_soc *ipu;
106	struct ipu_dmfc_priv *priv;
107	const struct dmfc_channel_data *data;
108	};
109
110	struct ipu_dmfc_priv {
111	struct ipu_soc *ipu;
112	struct device *dev;
113	struct dmfc_channel channels[DMFC_NUM_CHANNELS];
114	struct mutex mutex;
115	unsigned long bandwidth_per_slot;
116	void __iomem *base;
117	int use_count;
118	};
119
120	int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
121	{
122	struct ipu_dmfc_priv *priv = dmfc->priv;
123	mutex_lock(&priv->mutex);
124
125	if (!priv->use_count)
126	ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);
127
128	priv->use_count++;
129
130	mutex_unlock(&priv->mutex);
131
132	return 0;
133	}
134	EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
135
136	void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
137	{
138	struct ipu_dmfc_priv *priv = dmfc->priv;
139
140	mutex_lock(&priv->mutex);
141
142	priv->use_count--;
143
144	if (!priv->use_count)
145	ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
146
147	if (priv->use_count < 0)
148	priv->use_count = 0;
149
150	mutex_unlock(&priv->mutex);
151	}
152	EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);
153
154	static int ipu_dmfc_setup_channel(struct dmfc_channel *dmfc, int slots,
155	int segment, int burstsize)
156	{
157	struct ipu_dmfc_priv *priv = dmfc->priv;
158	u32 val, field;
159
160	dev_dbg(priv->dev,
161	"dmfc: using %d slots starting from segment %d for IPU channel %d\n",
162	slots, segment, dmfc->data->ipu_channel);
163
164	if (!dmfc)
165	return -EINVAL;
166
167	switch (slots) {
168	case 1:
169	field = DMFC_FIFO_SIZE_64;
170	break;
171	case 2:
172	field = DMFC_FIFO_SIZE_128;
173	break;
174	case 4:
175	field = DMFC_FIFO_SIZE_256;
176	break;
177	case 8:
178	field = DMFC_FIFO_SIZE_512;
179	break;
180	default:
181	return -EINVAL;
182	}
183
184	switch (burstsize) {
185	case 16:
186	field \|= DMFC_BURSTSIZE_16;
187	break;
188	case 32:
189	field \|= DMFC_BURSTSIZE_32;
190	break;
191	case 64:
192	field \|= DMFC_BURSTSIZE_64;
193	break;
194	case 128:
195	field \|= DMFC_BURSTSIZE_128;
196	break;
197	}
198
199	field \|= DMFC_SEGMENT(segment);
200
201	val = readl(priv->base + dmfc->data->channel_reg);
202
203	val &= ~(0xff << dmfc->data->shift);
204	val \|= field << dmfc->data->shift;
205
206	writel(val, priv->base + dmfc->data->channel_reg);
207
208	dmfc->slots = slots;
209	dmfc->segment = segment;
210	dmfc->burstsize = burstsize;
211	dmfc->slotmask = ((1 << slots) - 1) << segment;
212
213	return 0;
214	}
215
216	static int dmfc_bandwidth_to_slots(struct ipu_dmfc_priv *priv,
217	unsigned long bandwidth)
218	{
219	int slots = 1;
220
221	while (slots * priv->bandwidth_per_slot < bandwidth)
222	slots *= 2;
223
224	return slots;
225	}
226
227	static int dmfc_find_slots(struct ipu_dmfc_priv *priv, int slots)
228	{
229	unsigned slotmask_need, slotmask_used = 0;
230	int i, segment = 0;
231
232	slotmask_need = (1 << slots) - 1;
233
234	for (i = 0; i < DMFC_NUM_CHANNELS; i++)
235	slotmask_used \|= priv->channels[i].slotmask;
236
237	while (slotmask_need <= 0xff) {
238	if (!(slotmask_used & slotmask_need))
239	return segment;
240
241	slotmask_need <<= 1;
242	segment++;
243	}
244
245	return -EBUSY;
246	}
247
248	void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
249	{
250	struct ipu_dmfc_priv *priv = dmfc->priv;
251	int i;
252
253	dev_dbg(priv->dev, "dmfc: freeing %d slots starting from segment %d\n",
254	dmfc->slots, dmfc->segment);
255
256	mutex_lock(&priv->mutex);
257
258	if (!dmfc->slots)
259	goto out;
260
261	dmfc->slotmask = 0;
262	dmfc->slots = 0;
263	dmfc->segment = 0;
264
265	for (i = 0; i < DMFC_NUM_CHANNELS; i++)
266	priv->channels[i].slotmask = 0;
267
268	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
269	if (priv->channels[i].slots > 0) {
270	priv->channels[i].segment =
271	dmfc_find_slots(priv, priv->channels[i].slots);
272	priv->channels[i].slotmask =
273	((1 << priv->channels[i].slots) - 1) <<
274	priv->channels[i].segment;
275	}
276	}
277
278	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
279	if (priv->channels[i].slots > 0)
280	ipu_dmfc_setup_channel(&priv->channels[i],
281	priv->channels[i].slots,
282	priv->channels[i].segment,
283	priv->channels[i].burstsize);
284	}
285	out:
286	mutex_unlock(&priv->mutex);
287	}
288	EXPORT_SYMBOL_GPL(ipu_dmfc_free_bandwidth);
289
290	int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
291	unsigned long bandwidth_pixel_per_second, int burstsize)
292	{
293	struct ipu_dmfc_priv *priv = dmfc->priv;
294	int slots = dmfc_bandwidth_to_slots(priv, bandwidth_pixel_per_second);
0b92e2f4	295	int segment = -1, ret = 0;
aecfbdb1 SH	296
	297	dev_dbg(priv->dev, "dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
	298	bandwidth_pixel_per_second / 1000000,
	299	dmfc->data->ipu_channel);
	300
	301	ipu_dmfc_free_bandwidth(dmfc);
	302
	303	mutex_lock(&priv->mutex);
	304
	305	if (slots > 8) {
	306	ret = -EBUSY;
	307	goto out;
	308	}
	309
0b92e2f4 PZ	310	/* Always allocate at least 1284 bytes (2 slots) /
	311	if (slots < 2)
	312	slots = 2;
	313
	314	/* For the MEM_BG channel, first try to allocate twice the slots */
	315	if (dmfc->data->ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC)
	316	segment = dmfc_find_slots(priv, slots * 2);
	317	if (segment >= 0)
	318	slots *= 2;
	319	else
	320	segment = dmfc_find_slots(priv, slots);
aecfbdb1 SH	321	if (segment < 0) {
	322	ret = -EBUSY;
	323	goto out;
	324	}
	325
	326	ipu_dmfc_setup_channel(dmfc, slots, segment, burstsize);
	327
	328	out:
	329	mutex_unlock(&priv->mutex);
	330
	331	return ret;
	332	}
	333	EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth);
	334
	335	int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width)
	336	{
	337	struct ipu_dmfc_priv *priv = dmfc->priv;
	338	u32 dmfc_gen1;
	339
	340	dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
	341
	342	if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
	343	dmfc_gen1 \|= 1 << dmfc->data->eot_shift;
	344	else
	345	dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);
	346
	347	writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
	348
	349	return 0;
	350	}
	351	EXPORT_SYMBOL_GPL(ipu_dmfc_init_channel);
	352
	353	struct dmfc_channel ipu_dmfc_get(struct ipu_soc ipu, int ipu_channel)
	354	{
	355	struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
	356	int i;
	357
	358	for (i = 0; i < DMFC_NUM_CHANNELS; i++)
	359	if (dmfcdata[i].ipu_channel == ipu_channel)
	360	return &priv->channels[i];
	361	return ERR_PTR(-ENODEV);
	362	}
	363	EXPORT_SYMBOL_GPL(ipu_dmfc_get);
	364
	365	void ipu_dmfc_put(struct dmfc_channel *dmfc)
	366	{
	367	ipu_dmfc_free_bandwidth(dmfc);
	368	}
	369	EXPORT_SYMBOL_GPL(ipu_dmfc_put);
	370
	371	int ipu_dmfc_init(struct ipu_soc ipu, struct device dev, unsigned long base,
	372	struct clk *ipu_clk)
	373	{
	374	struct ipu_dmfc_priv *priv;
	375	int i;
	376
	377	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	378	if (!priv)
	379	return -ENOMEM;
	380
	381	priv->base = devm_ioremap(dev, base, PAGE_SIZE);
	382	if (!priv->base)
	383	return -ENOMEM;
	384
385	priv->dev = dev;
386	priv->ipu = ipu;
387	mutex_init(&priv->mutex);
388
389	ipu->dmfc_priv = priv;
390
391	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
392	priv->channels[i].priv = priv;
393	priv->channels[i].ipu = ipu;
394	priv->channels[i].data = &dmfcdata[i];
395	}
396
397	writel(0x0, priv->base + DMFC_WR_CHAN);
398	writel(0x0, priv->base + DMFC_DP_CHAN);
399
400	/*
401	* We have a total bandwidth of clkrate * 4pixel divided
402	* into 8 slots.
403	*/
0b92e2f4	404	priv->bandwidth_per_slot = clk_get_rate(ipu_clk) * 4 / 8;
aecfbdb1 SH	405
	406	dev_dbg(dev, "dmfc: 8 slots with %ldMpixel/s bandwidth each\n",
	407	priv->bandwidth_per_slot / 1000000);
	408
	409	writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
	410	writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
	411	writel(0x00000003, priv->base + DMFC_GENERAL1);
	412
	413	return 0;
	414	}
	415
	416	void ipu_dmfc_exit(struct ipu_soc *ipu)
	417	{
	418	}