[deliverable/linux.git] / drivers / staging / imx-drm / ipuv3-crtc.c

/*
 * i.MX IPUv3 Graphics driver
 *
 * Copyright (C) 2011 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/export.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>

#include "ipu-v3/imx-ipu-v3.h"
#include "imx-drm.h"

#define DRIVER_DESC		"i.MX IPUv3 Graphics"

struct ipu_framebuffer {
	struct drm_framebuffer	base;
	void			*virt;
	dma_addr_t		phys;
	size_t			len;
};

struct ipu_crtc {
	struct device		*dev;
	struct drm_crtc		base;
	struct imx_drm_crtc	*imx_crtc;
	struct ipuv3_channel	*ipu_ch;
	struct ipu_dc		*dc;
	struct ipu_dp		*dp;
	struct dmfc_channel	*dmfc;
	struct ipu_di		*di;
	int			enabled;
	struct drm_pending_vblank_event *page_flip_event;
	struct drm_framebuffer	*newfb;
	int			irq;
	u32			interface_pix_fmt;
	unsigned long		di_clkflags;
	int			di_hsync_pin;
	int			di_vsync_pin;
};

#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)

static int calc_vref(struct drm_display_mode *mode)
{
	unsigned long htotal, vtotal;

	htotal = mode->htotal;
	vtotal = mode->vtotal;

	if (!htotal || !vtotal)
		return 60;

	return mode->clock * 1000 / vtotal / htotal;
}

static int calc_bandwidth(struct drm_display_mode *mode, unsigned int vref)
{
	return mode->hdisplay * mode->vdisplay * vref;
}

static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
{
	if (ipu_crtc->enabled)
		return;

	ipu_di_enable(ipu_crtc->di);
	ipu_dmfc_enable_channel(ipu_crtc->dmfc);
	ipu_idmac_enable_channel(ipu_crtc->ipu_ch);
	ipu_dc_enable_channel(ipu_crtc->dc);
	if (ipu_crtc->dp)
		ipu_dp_enable_channel(ipu_crtc->dp);

	ipu_crtc->enabled = 1;
}

static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
{
	if (!ipu_crtc->enabled)
		return;

	if (ipu_crtc->dp)
		ipu_dp_disable_channel(ipu_crtc->dp);
	ipu_dc_disable_channel(ipu_crtc->dc);
	ipu_idmac_disable_channel(ipu_crtc->ipu_ch);
	ipu_dmfc_disable_channel(ipu_crtc->dmfc);
	ipu_di_disable(ipu_crtc->di);

	ipu_crtc->enabled = 0;
}

static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);

	switch (mode) {
	case DRM_MODE_DPMS_ON:
		ipu_fb_enable(ipu_crtc);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
		ipu_fb_disable(ipu_crtc);
		break;
	}
}

static int ipu_page_flip(struct drm_crtc *crtc,
		struct drm_framebuffer *fb,
		struct drm_pending_vblank_event *event)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	int ret;

	if (ipu_crtc->newfb)
		return -EBUSY;

	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	if (ret) {
		dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
		list_del(&event->base.link);

		return ret;
	}

	ipu_crtc->newfb = fb;
	ipu_crtc->page_flip_event = event;

	return 0;
}

static const struct drm_crtc_funcs ipu_crtc_funcs = {
	.set_config = drm_crtc_helper_set_config,
	.destroy = drm_crtc_cleanup,
	.page_flip = ipu_page_flip,
};

static int ipu_drm_set_base(struct drm_crtc *crtc, int x, int y)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_gem_cma_object *cma_obj;
	struct drm_framebuffer *fb = crtc->fb;
	unsigned long phys;

	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	if (!cma_obj) {
		DRM_LOG_KMS("entry is null.\n");
		return -EFAULT;
	}

	phys = cma_obj->paddr;
	phys += x * (fb->bits_per_pixel >> 3);
	phys += y * fb->pitches[0];

	dev_dbg(ipu_crtc->dev, "%s: phys: 0x%lx\n", __func__, phys);
	dev_dbg(ipu_crtc->dev, "%s: xy: %dx%d\n", __func__, x, y);

	ipu_cpmem_set_stride(ipu_get_cpmem(ipu_crtc->ipu_ch), fb->pitches[0]);
	ipu_cpmem_set_buffer(ipu_get_cpmem(ipu_crtc->ipu_ch),
			  0, phys);

	return 0;
}

static int ipu_crtc_mode_set(struct drm_crtc *crtc,
			       struct drm_display_mode *orig_mode,
			       struct drm_display_mode *mode,
			       int x, int y,
			       struct drm_framebuffer *old_fb)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	struct drm_framebuffer *fb = ipu_crtc->base.fb;
	int ret;
	struct ipu_di_signal_cfg sig_cfg = {};
	u32 out_pixel_fmt;
	struct ipu_ch_param __iomem *cpmem = ipu_get_cpmem(ipu_crtc->ipu_ch);
	int bpp;
	u32 v4l2_fmt;

	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
			mode->hdisplay);
	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
			mode->vdisplay);

	ipu_ch_param_zero(cpmem);

	switch (fb->pixel_format) {
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		v4l2_fmt = V4L2_PIX_FMT_RGB32;
		bpp = 32;
		break;
	case DRM_FORMAT_RGB565:
		v4l2_fmt = V4L2_PIX_FMT_RGB565;
		bpp = 16;
		break;
	case DRM_FORMAT_RGB888:
		v4l2_fmt = V4L2_PIX_FMT_RGB24;
		bpp = 24;
		break;
	default:
		dev_err(ipu_crtc->dev, "unsupported pixel format 0x%08x\n",
				fb->pixel_format);
		return -EINVAL;
	}

	out_pixel_fmt = ipu_crtc->interface_pix_fmt;

	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		sig_cfg.interlaced = 1;
	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
		sig_cfg.Hsync_pol = 1;
	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
		sig_cfg.Vsync_pol = 1;

	sig_cfg.enable_pol = 1;
	sig_cfg.clk_pol = 0;
	sig_cfg.width = mode->hdisplay;
	sig_cfg.height = mode->vdisplay;
	sig_cfg.pixel_fmt = out_pixel_fmt;
	sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
	sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
	sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;

	sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
	sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
	sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
	sig_cfg.pixelclock = mode->clock * 1000;
	sig_cfg.clkflags = ipu_crtc->di_clkflags;

	sig_cfg.v_to_h_sync = 0;

	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;

	if (ipu_crtc->dp) {
		ret = ipu_dp_setup_channel(ipu_crtc->dp, IPUV3_COLORSPACE_RGB,
				IPUV3_COLORSPACE_RGB);
		if (ret) {
			dev_err(ipu_crtc->dev,
				"initializing display processor failed with %d\n",
				ret);
			return ret;
		}
		ipu_dp_set_global_alpha(ipu_crtc->dp, 1, 0, 1);
	}

	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
			out_pixel_fmt, mode->hdisplay);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing display controller failed with %d\n",
				ret);
		return ret;
	}

	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing panel failed with %d\n", ret);
		return ret;
	}

	ipu_cpmem_set_resolution(cpmem, mode->hdisplay, mode->vdisplay);
	ipu_cpmem_set_fmt(cpmem, v4l2_fmt);
	ipu_cpmem_set_high_priority(ipu_crtc->ipu_ch);

	ret = ipu_dmfc_init_channel(ipu_crtc->dmfc, mode->hdisplay);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"initializing dmfc channel failed with %d\n",
				ret);
		return ret;
	}

	ret = ipu_dmfc_alloc_bandwidth(ipu_crtc->dmfc,
			calc_bandwidth(mode, calc_vref(mode)), 64);
	if (ret) {
		dev_err(ipu_crtc->dev,
				"allocating dmfc bandwidth failed with %d\n",
				ret);
		return ret;
	}

	ipu_drm_set_base(crtc, x, y);

	return 0;
}

static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
{
	unsigned long flags;
	struct drm_device *drm = ipu_crtc->base.dev;

	spin_lock_irqsave(&drm->event_lock, flags);
	if (ipu_crtc->page_flip_event)
		drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
	ipu_crtc->page_flip_event = NULL;
	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
	spin_unlock_irqrestore(&drm->event_lock, flags);
}

static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
{
	struct ipu_crtc *ipu_crtc = dev_id;

	imx_drm_handle_vblank(ipu_crtc->imx_crtc);

	if (ipu_crtc->newfb) {
		ipu_crtc->base.fb = ipu_crtc->newfb;
		ipu_crtc->newfb = NULL;
		ipu_drm_set_base(&ipu_crtc->base, 0, 0);
		ipu_crtc_handle_pageflip(ipu_crtc);
	}

	return IRQ_HANDLED;
}

static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
				  const struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void ipu_crtc_prepare(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_disable(ipu_crtc);
}

static void ipu_crtc_commit(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_fb_enable(ipu_crtc);
}

static void ipu_crtc_load_lut(struct drm_crtc *crtc)
{
}

static struct drm_crtc_helper_funcs ipu_helper_funcs = {
	.dpms = ipu_crtc_dpms,
	.mode_fixup = ipu_crtc_mode_fixup,
	.mode_set = ipu_crtc_mode_set,
	.prepare = ipu_crtc_prepare,
	.commit = ipu_crtc_commit,
	.load_lut = ipu_crtc_load_lut,
};

static int ipu_enable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	enable_irq(ipu_crtc->irq);

	return 0;
}

static void ipu_disable_vblank(struct drm_crtc *crtc)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	disable_irq(ipu_crtc->irq);
}

static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
		u32 pixfmt, int hsync_pin, int vsync_pin)
{
	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);

	ipu_crtc->interface_pix_fmt = pixfmt;
	ipu_crtc->di_hsync_pin = hsync_pin;
	ipu_crtc->di_vsync_pin = vsync_pin;

	switch (encoder_type) {
	case DRM_MODE_ENCODER_DAC:
	case DRM_MODE_ENCODER_TVDAC:
	case DRM_MODE_ENCODER_LVDS:
		ipu_crtc->di_clkflags = IPU_DI_CLKMODE_SYNC |
			IPU_DI_CLKMODE_EXT;
		break;
	case DRM_MODE_ENCODER_NONE:
		ipu_crtc->di_clkflags = 0;
		break;
	}

	return 0;
}

static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	.enable_vblank = ipu_enable_vblank,
	.disable_vblank = ipu_disable_vblank,
	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	.crtc_funcs = &ipu_crtc_funcs,
	.crtc_helper_funcs = &ipu_helper_funcs,
};

static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
{
	if (!IS_ERR_OR_NULL(ipu_crtc->ipu_ch))
		ipu_idmac_put(ipu_crtc->ipu_ch);
	if (!IS_ERR_OR_NULL(ipu_crtc->dmfc))
		ipu_dmfc_put(ipu_crtc->dmfc);
	if (!IS_ERR_OR_NULL(ipu_crtc->dp))
		ipu_dp_put(ipu_crtc->dp);
	if (!IS_ERR_OR_NULL(ipu_crtc->di))
		ipu_di_put(ipu_crtc->di);
}

static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ipu_crtc->ipu_ch = ipu_idmac_get(ipu, pdata->dma[0]);
	if (IS_ERR(ipu_crtc->ipu_ch)) {
		ret = PTR_ERR(ipu_crtc->ipu_ch);
		goto err_out;
	}

	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	if (IS_ERR(ipu_crtc->dc)) {
		ret = PTR_ERR(ipu_crtc->dc);
		goto err_out;
	}

	ipu_crtc->dmfc = ipu_dmfc_get(ipu, pdata->dma[0]);
	if (IS_ERR(ipu_crtc->dmfc)) {
		ret = PTR_ERR(ipu_crtc->dmfc);
		goto err_out;
	}

	if (pdata->dp >= 0) {
		ipu_crtc->dp = ipu_dp_get(ipu, pdata->dp);
		if (IS_ERR(ipu_crtc->dp)) {
			ret = PTR_ERR(ipu_crtc->dp);
			goto err_out;
		}
	}

	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	if (IS_ERR(ipu_crtc->di)) {
		ret = PTR_ERR(ipu_crtc->di);
		goto err_out;
	}

	return 0;
err_out:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
		struct ipu_client_platformdata *pdata)
{
	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	int ret;

	ret = ipu_get_resources(ipu_crtc, pdata);
	if (ret) {
		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
				ret);
		return ret;
	}

	ret = imx_drm_add_crtc(&ipu_crtc->base,
			&ipu_crtc->imx_crtc,
			&ipu_crtc_helper_funcs, THIS_MODULE,
			ipu_crtc->dev->parent->of_node, pdata->di);
	if (ret) {
		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
		goto err_put_resources;
	}

	ipu_crtc->irq = ipu_idmac_channel_irq(ipu, ipu_crtc->ipu_ch,
			IPU_IRQ_EOF);
	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
			"imx_drm", ipu_crtc);
	if (ret < 0) {
		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
		goto err_put_resources;
	}

	disable_irq(ipu_crtc->irq);

	return 0;

err_put_resources:
	ipu_put_resources(ipu_crtc);

	return ret;
}

static int ipu_drm_probe(struct platform_device *pdev)
{
	struct ipu_client_platformdata *pdata = pdev->dev.platform_data;
	struct ipu_crtc *ipu_crtc;
	int ret;

	if (!pdata)
		return -EINVAL;

	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);

	ipu_crtc = devm_kzalloc(&pdev->dev, sizeof(*ipu_crtc), GFP_KERNEL);
	if (!ipu_crtc)
		return -ENOMEM;

	ipu_crtc->dev = &pdev->dev;

	ret = ipu_crtc_init(ipu_crtc, pdata);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, ipu_crtc);

	return 0;
}

static int ipu_drm_remove(struct platform_device *pdev)
{
	struct ipu_crtc *ipu_crtc = platform_get_drvdata(pdev);

	imx_drm_remove_crtc(ipu_crtc->imx_crtc);

	ipu_put_resources(ipu_crtc);

	return 0;
}

static struct platform_driver ipu_drm_driver = {
	.driver = {
		.name = "imx-ipuv3-crtc",
	},
	.probe = ipu_drm_probe,
	.remove = ipu_drm_remove,
};
module_platform_driver(ipu_drm_driver);

MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
Commit	Line	Data
f326f799 SH	1	/*
	2	* i.MX IPUv3 Graphics driver
	3	*
	4	* Copyright (C) 2011 Sascha Hauer, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	18	* MA 02110-1301, USA.
	19	*/
	20	#include <linux/module.h>
	21	#include <linux/export.h>
	22	#include <linux/device.h>
	23	#include <linux/platform_device.h>
	24	#include <drm/drmP.h>
f326f799 SH	25	#include <drm/drm_crtc_helper.h>
	26	#include <linux/fb.h>
	27	#include <linux/clk.h>
	28	#include <drm/drm_gem_cma_helper.h>
	29	#include <drm/drm_fb_cma_helper.h>
	30
	31	#include "ipu-v3/imx-ipu-v3.h"
	32	#include "imx-drm.h"
	33
	34	#define DRIVER_DESC "i.MX IPUv3 Graphics"
	35
	36	struct ipu_framebuffer {
	37	struct drm_framebuffer base;
	38	void *virt;
	39	dma_addr_t phys;
	40	size_t len;
	41	};
	42
	43	struct ipu_crtc {
f326f799 SH	44	struct device *dev;
	45	struct drm_crtc base;
	46	struct imx_drm_crtc *imx_crtc;
	47	struct ipuv3_channel *ipu_ch;
	48	struct ipu_dc *dc;
	49	struct ipu_dp *dp;
	50	struct dmfc_channel *dmfc;
	51	struct ipu_di *di;
	52	int enabled;
f326f799 SH	53	struct drm_pending_vblank_event *page_flip_event;
	54	struct drm_framebuffer *newfb;
	55	int irq;
	56	u32 interface_pix_fmt;
	57	unsigned long di_clkflags;
2ea42608 PZ	58	int di_hsync_pin;
2ea42608 PZ	59	int di_vsync_pin;
f326f799 SH	60	};
	61
	62	#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
	63
	64	static int calc_vref(struct drm_display_mode *mode)
	65	{
	66	unsigned long htotal, vtotal;
	67
	68	htotal = mode->htotal;
	69	vtotal = mode->vtotal;
	70
	71	if (!htotal \|\| !vtotal)
	72	return 60;
	73
	74	return mode->clock * 1000 / vtotal / htotal;
	75	}
	76
	77	static int calc_bandwidth(struct drm_display_mode *mode, unsigned int vref)
	78	{
	79	return mode->hdisplay * mode->vdisplay * vref;
	80	}
	81
	82	static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
	83	{
	84	if (ipu_crtc->enabled)
	85	return;
	86
	87	ipu_di_enable(ipu_crtc->di);
	88	ipu_dmfc_enable_channel(ipu_crtc->dmfc);
	89	ipu_idmac_enable_channel(ipu_crtc->ipu_ch);
	90	ipu_dc_enable_channel(ipu_crtc->dc);
	91	if (ipu_crtc->dp)
	92	ipu_dp_enable_channel(ipu_crtc->dp);
	93
	94	ipu_crtc->enabled = 1;
	95	}
	96
	97	static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
	98	{
	99	if (!ipu_crtc->enabled)
	100	return;
	101
	102	if (ipu_crtc->dp)
	103	ipu_dp_disable_channel(ipu_crtc->dp);
	104	ipu_dc_disable_channel(ipu_crtc->dc);
	105	ipu_idmac_disable_channel(ipu_crtc->ipu_ch);
	106	ipu_dmfc_disable_channel(ipu_crtc->dmfc);
	107	ipu_di_disable(ipu_crtc->di);
	108
	109	ipu_crtc->enabled = 0;
	110	}
	111
	112	static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
	113	{
	114	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	115
a8e4e232	116	dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);
f326f799 SH	117
	118	switch (mode) {
	119	case DRM_MODE_DPMS_ON:
	120	ipu_fb_enable(ipu_crtc);
	121	break;
	122	case DRM_MODE_DPMS_STANDBY:
	123	case DRM_MODE_DPMS_SUSPEND:
	124	case DRM_MODE_DPMS_OFF:
	125	ipu_fb_disable(ipu_crtc);
	126	break;
	127	}
	128	}
	129
	130	static int ipu_page_flip(struct drm_crtc *crtc,
	131	struct drm_framebuffer *fb,
	132	struct drm_pending_vblank_event *event)
	133	{
	134	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	135	int ret;
	136
	137	if (ipu_crtc->newfb)
	138	return -EBUSY;
	139
	140	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
	141	if (ret) {
	142	dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
	143	list_del(&event->base.link);
	144
	145	return ret;
	146	}
	147
	148	ipu_crtc->newfb = fb;
	149	ipu_crtc->page_flip_event = event;
	150
	151	return 0;
	152	}
	153
	154	static const struct drm_crtc_funcs ipu_crtc_funcs = {
	155	.set_config = drm_crtc_helper_set_config,
	156	.destroy = drm_crtc_cleanup,
	157	.page_flip = ipu_page_flip,
	158	};
	159
	160	static int ipu_drm_set_base(struct drm_crtc *crtc, int x, int y)
	161	{
	162	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	163	struct drm_gem_cma_object *cma_obj;
	164	struct drm_framebuffer *fb = crtc->fb;
	165	unsigned long phys;
	166
	167	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	168	if (!cma_obj) {
	169	DRM_LOG_KMS("entry is null.\n");
	170	return -EFAULT;
	171	}
	172
	173	phys = cma_obj->paddr;
	174	phys += x * (fb->bits_per_pixel >> 3);
	175	phys += y * fb->pitches[0];
	176
	177	dev_dbg(ipu_crtc->dev, "%s: phys: 0x%lx\n", __func__, phys);
	178	dev_dbg(ipu_crtc->dev, "%s: xy: %dx%d\n", __func__, x, y);
	179
	180	ipu_cpmem_set_stride(ipu_get_cpmem(ipu_crtc->ipu_ch), fb->pitches[0]);
181	ipu_cpmem_set_buffer(ipu_get_cpmem(ipu_crtc->ipu_ch),
182	0, phys);
183
184	return 0;
185	}
186
187	static int ipu_crtc_mode_set(struct drm_crtc *crtc,
188	struct drm_display_mode *orig_mode,
189	struct drm_display_mode *mode,
190	int x, int y,
191	struct drm_framebuffer *old_fb)
192	{
193	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
194	struct drm_framebuffer *fb = ipu_crtc->base.fb;
195	int ret;
196	struct ipu_di_signal_cfg sig_cfg = {};
197	u32 out_pixel_fmt;
198	struct ipu_ch_param __iomem *cpmem = ipu_get_cpmem(ipu_crtc->ipu_ch);
199	int bpp;
200	u32 v4l2_fmt;
201
202	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
203	mode->hdisplay);
204	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
205	mode->vdisplay);
206
207	ipu_ch_param_zero(cpmem);
208
209	switch (fb->pixel_format) {
210	case DRM_FORMAT_XRGB8888:
211	case DRM_FORMAT_ARGB8888:
212	v4l2_fmt = V4L2_PIX_FMT_RGB32;
213	bpp = 32;
214	break;
215	case DRM_FORMAT_RGB565:
216	v4l2_fmt = V4L2_PIX_FMT_RGB565;
217	bpp = 16;
218	break;
219	case DRM_FORMAT_RGB888:
220	v4l2_fmt = V4L2_PIX_FMT_RGB24;
221	bpp = 24;
222	break;
223	default:
224	dev_err(ipu_crtc->dev, "unsupported pixel format 0x%08x\n",
225	fb->pixel_format);
226	return -EINVAL;
227	}
228
229	out_pixel_fmt = ipu_crtc->interface_pix_fmt;
230
231	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
232	sig_cfg.interlaced = 1;
233	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
234	sig_cfg.Hsync_pol = 1;
235	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
236	sig_cfg.Vsync_pol = 1;
237
238	sig_cfg.enable_pol = 1;
239	sig_cfg.clk_pol = 0;
240	sig_cfg.width = mode->hdisplay;
241	sig_cfg.height = mode->vdisplay;
242	sig_cfg.pixel_fmt = out_pixel_fmt;
243	sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
244	sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
245	sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;
246
247	sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
248	sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
249	sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
250	sig_cfg.pixelclock = mode->clock * 1000;
251	sig_cfg.clkflags = ipu_crtc->di_clkflags;
252
253	sig_cfg.v_to_h_sync = 0;
254
2ea42608 PZ	255	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
	256	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
	257
f326f799 SH	258	if (ipu_crtc->dp) {
	259	ret = ipu_dp_setup_channel(ipu_crtc->dp, IPUV3_COLORSPACE_RGB,
	260	IPUV3_COLORSPACE_RGB);
	261	if (ret) {
	262	dev_err(ipu_crtc->dev,
	263	"initializing display processor failed with %d\n",
	264	ret);
	265	return ret;
	266	}
	267	ipu_dp_set_global_alpha(ipu_crtc->dp, 1, 0, 1);
	268	}
	269
	270	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
	271	out_pixel_fmt, mode->hdisplay);
	272	if (ret) {
	273	dev_err(ipu_crtc->dev,
	274	"initializing display controller failed with %d\n",
	275	ret);
	276	return ret;
	277	}
	278
	279	ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
	280	if (ret) {
	281	dev_err(ipu_crtc->dev,
	282	"initializing panel failed with %d\n", ret);
	283	return ret;
	284	}
	285
	286	ipu_cpmem_set_resolution(cpmem, mode->hdisplay, mode->vdisplay);
	287	ipu_cpmem_set_fmt(cpmem, v4l2_fmt);
	288	ipu_cpmem_set_high_priority(ipu_crtc->ipu_ch);
	289
	290	ret = ipu_dmfc_init_channel(ipu_crtc->dmfc, mode->hdisplay);
	291	if (ret) {
	292	dev_err(ipu_crtc->dev,
	293	"initializing dmfc channel failed with %d\n",
	294	ret);
	295	return ret;
	296	}
	297
	298	ret = ipu_dmfc_alloc_bandwidth(ipu_crtc->dmfc,
	299	calc_bandwidth(mode, calc_vref(mode)), 64);
	300	if (ret) {
	301	dev_err(ipu_crtc->dev,
	302	"allocating dmfc bandwidth failed with %d\n",
	303	ret);
	304	return ret;
	305	}
	306
	307	ipu_drm_set_base(crtc, x, y);
	308
	309	return 0;
	310	}
	311
	312	static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
	313	{
f326f799 SH	314	unsigned long flags;
	315	struct drm_device *drm = ipu_crtc->base.dev;
	316
	317	spin_lock_irqsave(&drm->event_lock, flags);
0eca56f9 RC	318	if (ipu_crtc->page_flip_event)
0eca56f9 RC	319	drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
f326f799	320	ipu_crtc->page_flip_event = NULL;
f326f799	321	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
f326f799 SH	322	spin_unlock_irqrestore(&drm->event_lock, flags);
	323	}
	324
	325	static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
	326	{
	327	struct ipu_crtc *ipu_crtc = dev_id;
	328
	329	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
	330
	331	if (ipu_crtc->newfb) {
	332	ipu_crtc->base.fb = ipu_crtc->newfb;
	333	ipu_crtc->newfb = NULL;
	334	ipu_drm_set_base(&ipu_crtc->base, 0, 0);
	335	ipu_crtc_handle_pageflip(ipu_crtc);
	336	}
	337
	338	return IRQ_HANDLED;
	339	}
	340
	341	static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
	342	const struct drm_display_mode *mode,
	343	struct drm_display_mode *adjusted_mode)
	344	{
	345	return true;
	346	}
	347
	348	static void ipu_crtc_prepare(struct drm_crtc *crtc)
	349	{
	350	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	351
	352	ipu_fb_disable(ipu_crtc);
	353	}
	354
	355	static void ipu_crtc_commit(struct drm_crtc *crtc)
	356	{
	357	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	358
	359	ipu_fb_enable(ipu_crtc);
	360	}
	361
	362	static void ipu_crtc_load_lut(struct drm_crtc *crtc)
	363	{
	364	}
	365
	366	static struct drm_crtc_helper_funcs ipu_helper_funcs = {
	367	.dpms = ipu_crtc_dpms,
	368	.mode_fixup = ipu_crtc_mode_fixup,
	369	.mode_set = ipu_crtc_mode_set,
	370	.prepare = ipu_crtc_prepare,
	371	.commit = ipu_crtc_commit,
	372	.load_lut = ipu_crtc_load_lut,
	373	};
	374
	375	static int ipu_enable_vblank(struct drm_crtc *crtc)
	376	{
	377	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	378
	379	enable_irq(ipu_crtc->irq);
	380
	381	return 0;
	382	}
	383
	384	static void ipu_disable_vblank(struct drm_crtc *crtc)
	385	{
386	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
387
388	disable_irq(ipu_crtc->irq);
389	}
390
391	static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
2ea42608	392	u32 pixfmt, int hsync_pin, int vsync_pin)
f326f799 SH	393	{
	394	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
	395
	396	ipu_crtc->interface_pix_fmt = pixfmt;
2ea42608 PZ	397	ipu_crtc->di_hsync_pin = hsync_pin;
2ea42608 PZ	398	ipu_crtc->di_vsync_pin = vsync_pin;
f326f799 SH	399
f326f799 SH	400	switch (encoder_type) {
b60b5bcb PZ	401	case DRM_MODE_ENCODER_DAC:
b60b5bcb PZ	402	case DRM_MODE_ENCODER_TVDAC:
f326f799 SH	403	case DRM_MODE_ENCODER_LVDS:
	404	ipu_crtc->di_clkflags = IPU_DI_CLKMODE_SYNC \|
	405	IPU_DI_CLKMODE_EXT;
	406	break;
	407	case DRM_MODE_ENCODER_NONE:
	408	ipu_crtc->di_clkflags = 0;
	409	break;
	410	}
	411
	412	return 0;
	413	}
	414
	415	static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
	416	.enable_vblank = ipu_enable_vblank,
	417	.disable_vblank = ipu_disable_vblank,
	418	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
	419	.crtc_funcs = &ipu_crtc_funcs,
	420	.crtc_helper_funcs = &ipu_helper_funcs,
	421	};
	422
	423	static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
	424	{
	425	if (!IS_ERR_OR_NULL(ipu_crtc->ipu_ch))
	426	ipu_idmac_put(ipu_crtc->ipu_ch);
	427	if (!IS_ERR_OR_NULL(ipu_crtc->dmfc))
	428	ipu_dmfc_put(ipu_crtc->dmfc);
	429	if (!IS_ERR_OR_NULL(ipu_crtc->dp))
	430	ipu_dp_put(ipu_crtc->dp);
	431	if (!IS_ERR_OR_NULL(ipu_crtc->di))
	432	ipu_di_put(ipu_crtc->di);
	433	}
	434
	435	static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
	436	struct ipu_client_platformdata *pdata)
	437	{
	438	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
	439	int ret;
	440
	441	ipu_crtc->ipu_ch = ipu_idmac_get(ipu, pdata->dma[0]);
9a8f3f44	442	if (IS_ERR(ipu_crtc->ipu_ch)) {
f326f799 SH	443	ret = PTR_ERR(ipu_crtc->ipu_ch);
	444	goto err_out;
	445	}
	446
	447	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
	448	if (IS_ERR(ipu_crtc->dc)) {
	449	ret = PTR_ERR(ipu_crtc->dc);
	450	goto err_out;
	451	}
	452
	453	ipu_crtc->dmfc = ipu_dmfc_get(ipu, pdata->dma[0]);
	454	if (IS_ERR(ipu_crtc->dmfc)) {
	455	ret = PTR_ERR(ipu_crtc->dmfc);
	456	goto err_out;
	457	}
	458
	459	if (pdata->dp >= 0) {
	460	ipu_crtc->dp = ipu_dp_get(ipu, pdata->dp);
	461	if (IS_ERR(ipu_crtc->dp)) {
9a8f3f44	462	ret = PTR_ERR(ipu_crtc->dp);
f326f799 SH	463	goto err_out;
	464	}
	465	}
	466
	467	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
	468	if (IS_ERR(ipu_crtc->di)) {
	469	ret = PTR_ERR(ipu_crtc->di);
	470	goto err_out;
	471	}
	472
f326f799 SH	473	return 0;
	474	err_out:
	475	ipu_put_resources(ipu_crtc);
	476
	477	return ret;
	478	}
	479
	480	static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
	481	struct ipu_client_platformdata *pdata)
	482	{
47b1be5c	483	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
f326f799 SH	484	int ret;
	485
	486	ret = ipu_get_resources(ipu_crtc, pdata);
	487	if (ret) {
	488	dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
	489	ret);
	490	return ret;
	491	}
	492
	493	ret = imx_drm_add_crtc(&ipu_crtc->base,
	494	&ipu_crtc->imx_crtc,
	495	&ipu_crtc_helper_funcs, THIS_MODULE,
	496	ipu_crtc->dev->parent->of_node, pdata->di);
	497	if (ret) {
	498	dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
	499	goto err_put_resources;
	500	}
	501
47b1be5c PZ	502	ipu_crtc->irq = ipu_idmac_channel_irq(ipu, ipu_crtc->ipu_ch,
	503	IPU_IRQ_EOF);
	504	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
	505	"imx_drm", ipu_crtc);
	506	if (ret < 0) {
	507	dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
	508	goto err_put_resources;
	509	}
	510
	511	disable_irq(ipu_crtc->irq);
	512
f326f799 SH	513	return 0;
	514
	515	err_put_resources:
	516	ipu_put_resources(ipu_crtc);
	517
	518	return ret;
	519	}
	520
c4aabf8d	521	static int ipu_drm_probe(struct platform_device *pdev)
f326f799 SH	522	{
	523	struct ipu_client_platformdata *pdata = pdev->dev.platform_data;
	524	struct ipu_crtc *ipu_crtc;
	525	int ret;
	526
	527	if (!pdata)
	528	return -EINVAL;
	529
	530	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
	531
	532	ipu_crtc = devm_kzalloc(&pdev->dev, sizeof(*ipu_crtc), GFP_KERNEL);
	533	if (!ipu_crtc)
	534	return -ENOMEM;
	535
	536	ipu_crtc->dev = &pdev->dev;
	537
	538	ret = ipu_crtc_init(ipu_crtc, pdata);
9a8f3f44 LW	539	if (ret)
9a8f3f44 LW	540	return ret;
f326f799 SH	541
	542	platform_set_drvdata(pdev, ipu_crtc);
	543
	544	return 0;
	545	}
	546
8aa1be45	547	static int ipu_drm_remove(struct platform_device *pdev)
f326f799 SH	548	{
	549	struct ipu_crtc *ipu_crtc = platform_get_drvdata(pdev);
	550
	551	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
	552
	553	ipu_put_resources(ipu_crtc);
	554
	555	return 0;
	556	}
	557
	558	static struct platform_driver ipu_drm_driver = {
	559	.driver = {
	560	.name = "imx-ipuv3-crtc",
	561	},
	562	.probe = ipu_drm_probe,
99c28f10	563	.remove = ipu_drm_remove,
f326f799 SH	564	};
	565	module_platform_driver(ipu_drm_driver);
	566
	567	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
	568	MODULE_DESCRIPTION(DRIVER_DESC);
	569	MODULE_LICENSE("GPL");