[deliverable/linux.git] / drivers / staging / imx-drm / ipuv3-plane.c

/*
 * i.MX IPUv3 DP Overlay Planes
 *
 * Copyright (C) 2013 Philipp Zabel, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <drm/drmP.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>

#include "video/imx-ipu-v3.h"
#include "ipuv3-plane.h"

#define to_ipu_plane(x)	container_of(x, struct ipu_plane, base)

static const uint32_t ipu_plane_formats[] = {
	DRM_FORMAT_XRGB1555,
	DRM_FORMAT_XBGR1555,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_YUV420,
	DRM_FORMAT_YVU420,
};

int ipu_plane_irq(struct ipu_plane *ipu_plane)
{
	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
				     IPU_IRQ_EOF);
}

static int calc_vref(struct drm_display_mode *mode)
{
	unsigned long htotal, vtotal;

	htotal = mode->htotal;
	vtotal = mode->vtotal;

	if (!htotal || !vtotal)
		return 60;

	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
}

static inline int calc_bandwidth(int width, int height, unsigned int vref)
{
	return width * height * vref;
}

int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
		       int x, int y)
{
	struct drm_gem_cma_object *cma_obj;
	unsigned long eba;

	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	if (!cma_obj) {
		DRM_DEBUG_KMS("entry is null.\n");
		return -EFAULT;
	}

	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
		&cma_obj->paddr, x, y);

	eba = cma_obj->paddr + fb->offsets[0] +
	      fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);

	/* cache offsets for subsequent pageflips */
	ipu_plane->x = x;
	ipu_plane->y = y;

	return 0;
}

int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
		       struct drm_display_mode *mode,
		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		       unsigned int crtc_w, unsigned int crtc_h,
		       uint32_t src_x, uint32_t src_y,
		       uint32_t src_w, uint32_t src_h)
{
	struct device *dev = ipu_plane->base.dev->dev;
	int ret;

	/* no scaling */
	if (src_w != crtc_w || src_h != crtc_h)
		return -EINVAL;

	/* clip to crtc bounds */
	if (crtc_x < 0) {
		if (-crtc_x > crtc_w)
			return -EINVAL;
		src_x += -crtc_x;
		src_w -= -crtc_x;
		crtc_w -= -crtc_x;
		crtc_x = 0;
	}
	if (crtc_y < 0) {
		if (-crtc_y > crtc_h)
			return -EINVAL;
		src_y += -crtc_y;
		src_h -= -crtc_y;
		crtc_h -= -crtc_y;
		crtc_y = 0;
	}
	if (crtc_x + crtc_w > mode->hdisplay) {
		if (crtc_x > mode->hdisplay)
			return -EINVAL;
		crtc_w = mode->hdisplay - crtc_x;
		src_w = crtc_w;
	}
	if (crtc_y + crtc_h > mode->vdisplay) {
		if (crtc_y > mode->vdisplay)
			return -EINVAL;
		crtc_h = mode->vdisplay - crtc_y;
		src_h = crtc_h;
	}
	/* full plane minimum width is 13 pixels */
	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
		return -EINVAL;
	if (crtc_h < 2)
		return -EINVAL;

	switch (ipu_plane->dp_flow) {
	case IPU_DP_FLOW_SYNC_BG:
		ret = ipu_dp_setup_channel(ipu_plane->dp,
				IPUV3_COLORSPACE_RGB,
				IPUV3_COLORSPACE_RGB);
		if (ret) {
			dev_err(dev,
				"initializing display processor failed with %d\n",
				ret);
			return ret;
		}
		ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
		break;
	case IPU_DP_FLOW_SYNC_FG:
		ipu_dp_setup_channel(ipu_plane->dp,
				ipu_drm_fourcc_to_colorspace(fb->pixel_format),
				IPUV3_COLORSPACE_UNKNOWN);
		ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
		/* Enable local alpha on partial plane */
		switch (fb->pixel_format) {
		case DRM_FORMAT_ARGB8888:
		case DRM_FORMAT_ABGR8888:
			ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
			break;
		default:
			break;
		}
	}

	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	if (ret) {
		dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
		return ret;
	}

	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
			calc_bandwidth(crtc_w, crtc_h,
				       calc_vref(mode)), 64);
	if (ret) {
		dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
		return ret;
	}

	ipu_cpmem_zero(ipu_plane->ipu_ch);
	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
	if (ret < 0) {
		dev_err(dev, "unsupported pixel format 0x%08x\n",
			fb->pixel_format);
		return ret;
	}
	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);

	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	if (ret < 0)
		return ret;

	return 0;
}

void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
{
	if (!IS_ERR_OR_NULL(ipu_plane->dp))
		ipu_dp_put(ipu_plane->dp);
	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
		ipu_dmfc_put(ipu_plane->dmfc);
	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
		ipu_idmac_put(ipu_plane->ipu_ch);
}

int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
{
	int ret;

	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->ipu_ch)) {
		ret = PTR_ERR(ipu_plane->ipu_ch);
		DRM_ERROR("failed to get idmac channel: %d\n", ret);
		return ret;
	}

	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->dmfc)) {
		ret = PTR_ERR(ipu_plane->dmfc);
		DRM_ERROR("failed to get dmfc: ret %d\n", ret);
		goto err_out;
	}

	if (ipu_plane->dp_flow >= 0) {
		ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
		if (IS_ERR(ipu_plane->dp)) {
			ret = PTR_ERR(ipu_plane->dp);
			DRM_ERROR("failed to get dp flow: %d\n", ret);
			goto err_out;
		}
	}

	return 0;
err_out:
	ipu_plane_put_resources(ipu_plane);

	return ret;
}

void ipu_plane_enable(struct ipu_plane *ipu_plane)
{
	if (ipu_plane->dp)
		ipu_dp_enable(ipu_plane->ipu);
	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	if (ipu_plane->dp)
		ipu_dp_enable_channel(ipu_plane->dp);

	ipu_plane->enabled = true;
}

void ipu_plane_disable(struct ipu_plane *ipu_plane)
{
	ipu_plane->enabled = false;

	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);

	if (ipu_plane->dp)
		ipu_dp_disable_channel(ipu_plane->dp);
	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	ipu_dmfc_disable_channel(ipu_plane->dmfc);
	if (ipu_plane->dp)
		ipu_dp_disable(ipu_plane->ipu);
}

/*
 * drm_plane API
 */

static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
			    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
			    unsigned int crtc_w, unsigned int crtc_h,
			    uint32_t src_x, uint32_t src_y,
			    uint32_t src_w, uint32_t src_h)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	int ret = 0;

	DRM_DEBUG_KMS("plane - %p\n", plane);

	if (!ipu_plane->enabled)
		ret = ipu_plane_get_resources(ipu_plane);
	if (ret < 0)
		return ret;

	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
			crtc_x, crtc_y, crtc_w, crtc_h,
			src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16);
	if (ret < 0) {
		ipu_plane_put_resources(ipu_plane);
		return ret;
	}

	if (crtc != plane->crtc)
		dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
				plane->crtc, crtc);
	plane->crtc = crtc;

	if (!ipu_plane->enabled)
		ipu_plane_enable(ipu_plane);

	return 0;
}

static int ipu_disable_plane(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	if (ipu_plane->enabled)
		ipu_plane_disable(ipu_plane);

	ipu_plane_put_resources(ipu_plane);

	return 0;
}

static void ipu_plane_destroy(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	ipu_disable_plane(plane);
	drm_plane_cleanup(plane);
	kfree(ipu_plane);
}

static struct drm_plane_funcs ipu_plane_funcs = {
	.update_plane	= ipu_update_plane,
	.disable_plane	= ipu_disable_plane,
	.destroy	= ipu_plane_destroy,
};

struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
				 int dma, int dp, unsigned int possible_crtcs,
				 bool priv)
{
	struct ipu_plane *ipu_plane;
	int ret;

	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
		      dma, dp, possible_crtcs);

	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	if (!ipu_plane) {
		DRM_ERROR("failed to allocate plane\n");
		return ERR_PTR(-ENOMEM);
	}

	ipu_plane->ipu = ipu;
	ipu_plane->dma = dma;
	ipu_plane->dp_flow = dp;

	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
			     &ipu_plane_funcs, ipu_plane_formats,
			     ARRAY_SIZE(ipu_plane_formats),
			     priv);
	if (ret) {
		DRM_ERROR("failed to initialize plane\n");
		kfree(ipu_plane);
		return ERR_PTR(ret);
	}

	return ipu_plane;
}
Commit	Line	Data
b8d181e4 PZ	1	/*
	2	* i.MX IPUv3 DP Overlay Planes
	3	*
	4	* Copyright (C) 2013 Philipp Zabel, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <drm/drmP.h>
	17	#include <drm/drm_fb_cma_helper.h>
	18	#include <drm/drm_gem_cma_helper.h>
	19
39b9004d	20	#include "video/imx-ipu-v3.h"
b8d181e4 PZ	21	#include "ipuv3-plane.h"
	22
	23	#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
	24
	25	static const uint32_t ipu_plane_formats[] = {
	26	DRM_FORMAT_XRGB1555,
	27	DRM_FORMAT_XBGR1555,
	28	DRM_FORMAT_ARGB8888,
	29	DRM_FORMAT_XRGB8888,
	30	DRM_FORMAT_ABGR8888,
	31	DRM_FORMAT_XBGR8888,
	32	DRM_FORMAT_YUYV,
	33	DRM_FORMAT_YVYU,
	34	DRM_FORMAT_YUV420,
	35	DRM_FORMAT_YVU420,
	36	};
	37
	38	int ipu_plane_irq(struct ipu_plane *ipu_plane)
	39	{
	40	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
	41	IPU_IRQ_EOF);
	42	}
	43
	44	static int calc_vref(struct drm_display_mode *mode)
	45	{
	46	unsigned long htotal, vtotal;
	47
	48	htotal = mode->htotal;
	49	vtotal = mode->vtotal;
	50
	51	if (!htotal \|\| !vtotal)
	52	return 60;
	53
	54	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
	55	}
	56
	57	static inline int calc_bandwidth(int width, int height, unsigned int vref)
	58	{
	59	return width * height * vref;
	60	}
	61
	62	int ipu_plane_set_base(struct ipu_plane ipu_plane, struct drm_framebuffer fb,
	63	int x, int y)
	64	{
b8d181e4	65	struct drm_gem_cma_object *cma_obj;
ee2e072e	66	unsigned long eba;
b8d181e4 PZ	67
	68	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	69	if (!cma_obj) {
38821e64	70	DRM_DEBUG_KMS("entry is null.\n");
b8d181e4 PZ	71	return -EFAULT;
	72	}
	73
18589738 FE	74	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
18589738 FE	75	&cma_obj->paddr, x, y);
b8d181e4	76
bc2b067a LS	77	eba = cma_obj->paddr + fb->offsets[0] +
bc2b067a LS	78	fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
2eb671c4 SL	79	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
2eb671c4 SL	80	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
b8d181e4	81
32f71106 LS	82	/* cache offsets for subsequent pageflips */
	83	ipu_plane->x = x;
	84	ipu_plane->y = y;
	85
b8d181e4 PZ	86	return 0;
	87	}
	88
	89	int ipu_plane_mode_set(struct ipu_plane ipu_plane, struct drm_crtc crtc,
	90	struct drm_display_mode *mode,
	91	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	92	unsigned int crtc_w, unsigned int crtc_h,
	93	uint32_t src_x, uint32_t src_y,
	94	uint32_t src_w, uint32_t src_h)
	95	{
b8d181e4 PZ	96	struct device *dev = ipu_plane->base.dev->dev;
	97	int ret;
	98
	99	/* no scaling */
	100	if (src_w != crtc_w \|\| src_h != crtc_h)
	101	return -EINVAL;
	102
	103	/* clip to crtc bounds */
	104	if (crtc_x < 0) {
	105	if (-crtc_x > crtc_w)
	106	return -EINVAL;
	107	src_x += -crtc_x;
	108	src_w -= -crtc_x;
	109	crtc_w -= -crtc_x;
	110	crtc_x = 0;
	111	}
	112	if (crtc_y < 0) {
	113	if (-crtc_y > crtc_h)
	114	return -EINVAL;
	115	src_y += -crtc_y;
	116	src_h -= -crtc_y;
	117	crtc_h -= -crtc_y;
	118	crtc_y = 0;
	119	}
	120	if (crtc_x + crtc_w > mode->hdisplay) {
	121	if (crtc_x > mode->hdisplay)
	122	return -EINVAL;
	123	crtc_w = mode->hdisplay - crtc_x;
	124	src_w = crtc_w;
	125	}
	126	if (crtc_y + crtc_h > mode->vdisplay) {
	127	if (crtc_y > mode->vdisplay)
	128	return -EINVAL;
	129	crtc_h = mode->vdisplay - crtc_y;
	130	src_h = crtc_h;
	131	}
	132	/* full plane minimum width is 13 pixels */
	133	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
	134	return -EINVAL;
	135	if (crtc_h < 2)
	136	return -EINVAL;
	137
	138	switch (ipu_plane->dp_flow) {
	139	case IPU_DP_FLOW_SYNC_BG:
	140	ret = ipu_dp_setup_channel(ipu_plane->dp,
	141	IPUV3_COLORSPACE_RGB,
	142	IPUV3_COLORSPACE_RGB);
	143	if (ret) {
	144	dev_err(dev,
	145	"initializing display processor failed with %d\n",
	146	ret);
	147	return ret;
	148	}
e6245fc7	149	ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
b8d181e4 PZ	150	break;
	151	case IPU_DP_FLOW_SYNC_FG:
	152	ipu_dp_setup_channel(ipu_plane->dp,
	153	ipu_drm_fourcc_to_colorspace(fb->pixel_format),
	154	IPUV3_COLORSPACE_UNKNOWN);
	155	ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
e6245fc7 PZ	156	/* Enable local alpha on partial plane */
	157	switch (fb->pixel_format) {
	158	case DRM_FORMAT_ARGB8888:
	159	case DRM_FORMAT_ABGR8888:
	160	ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
	161	break;
	162	default:
	163	break;
	164	}
b8d181e4 PZ	165	}
	166
	167	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	168	if (ret) {
	169	dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
	170	return ret;
	171	}
	172
	173	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
	174	calc_bandwidth(crtc_w, crtc_h,
	175	calc_vref(mode)), 64);
	176	if (ret) {
	177	dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
	178	return ret;
	179	}
	180
2eb671c4 SL	181	ipu_cpmem_zero(ipu_plane->ipu_ch);
	182	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	183	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
b8d181e4 PZ	184	if (ret < 0) {
	185	dev_err(dev, "unsupported pixel format 0x%08x\n",
	186	fb->pixel_format);
	187	return ret;
	188	}
	189	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
7cd9bebe	190	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4 PZ	191
	192	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	193	if (ret < 0)
	194	return ret;
	195
	196	return 0;
	197	}
	198
	199	void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
	200	{
	201	if (!IS_ERR_OR_NULL(ipu_plane->dp))
	202	ipu_dp_put(ipu_plane->dp);
	203	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
	204	ipu_dmfc_put(ipu_plane->dmfc);
	205	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
	206	ipu_idmac_put(ipu_plane->ipu_ch);
	207	}
	208
	209	int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
	210	{
	211	int ret;
	212
	213	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	214	if (IS_ERR(ipu_plane->ipu_ch)) {
	215	ret = PTR_ERR(ipu_plane->ipu_ch);
	216	DRM_ERROR("failed to get idmac channel: %d\n", ret);
	217	return ret;
	218	}
	219
	220	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	221	if (IS_ERR(ipu_plane->dmfc)) {
	222	ret = PTR_ERR(ipu_plane->dmfc);
	223	DRM_ERROR("failed to get dmfc: ret %d\n", ret);
	224	goto err_out;
	225	}
	226
	227	if (ipu_plane->dp_flow >= 0) {
	228	ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
	229	if (IS_ERR(ipu_plane->dp)) {
	230	ret = PTR_ERR(ipu_plane->dp);
	231	DRM_ERROR("failed to get dp flow: %d\n", ret);
	232	goto err_out;
	233	}
	234	}
	235
	236	return 0;
	237	err_out:
	238	ipu_plane_put_resources(ipu_plane);
	239
	240	return ret;
	241	}
	242
	243	void ipu_plane_enable(struct ipu_plane *ipu_plane)
	244	{
285bbb01 PZ	245	if (ipu_plane->dp)
285bbb01 PZ	246	ipu_dp_enable(ipu_plane->ipu);
b8d181e4 PZ	247	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	248	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	249	if (ipu_plane->dp)
	250	ipu_dp_enable_channel(ipu_plane->dp);
	251
	252	ipu_plane->enabled = true;
	253	}
	254
	255	void ipu_plane_disable(struct ipu_plane *ipu_plane)
	256	{
	257	ipu_plane->enabled = false;
	258
	259	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
	260
	261	if (ipu_plane->dp)
	262	ipu_dp_disable_channel(ipu_plane->dp);
	263	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	264	ipu_dmfc_disable_channel(ipu_plane->dmfc);
285bbb01 PZ	265	if (ipu_plane->dp)
285bbb01 PZ	266	ipu_dp_disable(ipu_plane->ipu);
b8d181e4 PZ	267	}
b8d181e4 PZ	268
b8d181e4 PZ	269	/*
	270	* drm_plane API
	271	*/
	272
	273	static int ipu_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	274	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	275	unsigned int crtc_w, unsigned int crtc_h,
	276	uint32_t src_x, uint32_t src_y,
	277	uint32_t src_w, uint32_t src_h)
	278	{
	279	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	280	int ret = 0;
	281
	282	DRM_DEBUG_KMS("plane - %p\n", plane);
	283
	284	if (!ipu_plane->enabled)
	285	ret = ipu_plane_get_resources(ipu_plane);
	286	if (ret < 0)
	287	return ret;
	288
	289	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
	290	crtc_x, crtc_y, crtc_w, crtc_h,
	291	src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16);
	292	if (ret < 0) {
	293	ipu_plane_put_resources(ipu_plane);
	294	return ret;
	295	}
	296
	297	if (crtc != plane->crtc)
	298	dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
	299	plane->crtc, crtc);
	300	plane->crtc = crtc;
	301
b46355f0 SG	302	if (!ipu_plane->enabled)
b46355f0 SG	303	ipu_plane_enable(ipu_plane);
b8d181e4 PZ	304
	305	return 0;
	306	}
	307
	308	static int ipu_disable_plane(struct drm_plane *plane)
	309	{
	310	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	311
	312	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	313
b46355f0 SG	314	if (ipu_plane->enabled)
b46355f0 SG	315	ipu_plane_disable(ipu_plane);
b8d181e4 PZ	316
	317	ipu_plane_put_resources(ipu_plane);
	318
	319	return 0;
	320	}
	321
	322	static void ipu_plane_destroy(struct drm_plane *plane)
	323	{
	324	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	325
	326	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	327
	328	ipu_disable_plane(plane);
	329	drm_plane_cleanup(plane);
	330	kfree(ipu_plane);
	331	}
	332
	333	static struct drm_plane_funcs ipu_plane_funcs = {
	334	.update_plane = ipu_update_plane,
	335	.disable_plane = ipu_disable_plane,
	336	.destroy = ipu_plane_destroy,
	337	};
	338
	339	struct ipu_plane ipu_plane_init(struct drm_device dev, struct ipu_soc *ipu,
	340	int dma, int dp, unsigned int possible_crtcs,
	341	bool priv)
	342	{
	343	struct ipu_plane *ipu_plane;
	344	int ret;
	345
	346	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
	347	dma, dp, possible_crtcs);
	348
	349	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	350	if (!ipu_plane) {
	351	DRM_ERROR("failed to allocate plane\n");
	352	return ERR_PTR(-ENOMEM);
	353	}
	354
	355	ipu_plane->ipu = ipu;
	356	ipu_plane->dma = dma;
	357	ipu_plane->dp_flow = dp;
	358
	359	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
	360	&ipu_plane_funcs, ipu_plane_formats,
	361	ARRAY_SIZE(ipu_plane_formats),
	362	priv);
	363	if (ret) {
	364	DRM_ERROR("failed to initialize plane\n");
	365	kfree(ipu_plane);
	366	return ERR_PTR(ret);
	367	}
	368
	369	return ipu_plane;
	370	}