[deliverable/linux.git] / drivers / staging / imx-drm / ipuv3-plane.c

/*
 * i.MX IPUv3 DP Overlay Planes
 *
 * Copyright (C) 2013 Philipp Zabel, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <drm/drmP.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>

#include "ipu-v3/imx-ipu-v3.h"
#include "ipuv3-plane.h"

#define to_ipu_plane(x)	container_of(x, struct ipu_plane, base)

static const uint32_t ipu_plane_formats[] = {
	DRM_FORMAT_XRGB1555,
	DRM_FORMAT_XBGR1555,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_YUV420,
	DRM_FORMAT_YVU420,
};

int ipu_plane_irq(struct ipu_plane *ipu_plane)
{
	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
				     IPU_IRQ_EOF);
}

static int calc_vref(struct drm_display_mode *mode)
{
	unsigned long htotal, vtotal;

	htotal = mode->htotal;
	vtotal = mode->vtotal;

	if (!htotal || !vtotal)
		return 60;

	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
}

static inline int calc_bandwidth(int width, int height, unsigned int vref)
{
	return width * height * vref;
}

int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
		       int x, int y)
{
	struct ipu_ch_param __iomem *cpmem;
	struct drm_gem_cma_object *cma_obj;
	unsigned long eba;

	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	if (!cma_obj) {
		DRM_LOG_KMS("entry is null.\n");
		return -EFAULT;
	}

	dev_dbg(ipu_plane->base.dev->dev, "phys = 0x%x, x = %d, y = %d",
		cma_obj->paddr, x, y);

	cpmem = ipu_get_cpmem(ipu_plane->ipu_ch);
	ipu_cpmem_set_stride(cpmem, fb->pitches[0]);

	eba = cma_obj->paddr + fb->offsets[0] +
	      fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
	ipu_cpmem_set_buffer(cpmem, 0, eba);
	ipu_cpmem_set_buffer(cpmem, 1, eba);

	return 0;
}

int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
		       struct drm_display_mode *mode,
		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		       unsigned int crtc_w, unsigned int crtc_h,
		       uint32_t src_x, uint32_t src_y,
		       uint32_t src_w, uint32_t src_h)
{
	struct ipu_ch_param __iomem *cpmem;
	struct device *dev = ipu_plane->base.dev->dev;
	int ret;

	/* no scaling */
	if (src_w != crtc_w || src_h != crtc_h)
		return -EINVAL;

	/* clip to crtc bounds */
	if (crtc_x < 0) {
		if (-crtc_x > crtc_w)
			return -EINVAL;
		src_x += -crtc_x;
		src_w -= -crtc_x;
		crtc_w -= -crtc_x;
		crtc_x = 0;
	}
	if (crtc_y < 0) {
		if (-crtc_y > crtc_h)
			return -EINVAL;
		src_y += -crtc_y;
		src_h -= -crtc_y;
		crtc_h -= -crtc_y;
		crtc_y = 0;
	}
	if (crtc_x + crtc_w > mode->hdisplay) {
		if (crtc_x > mode->hdisplay)
			return -EINVAL;
		crtc_w = mode->hdisplay - crtc_x;
		src_w = crtc_w;
	}
	if (crtc_y + crtc_h > mode->vdisplay) {
		if (crtc_y > mode->vdisplay)
			return -EINVAL;
		crtc_h = mode->vdisplay - crtc_y;
		src_h = crtc_h;
	}
	/* full plane minimum width is 13 pixels */
	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
		return -EINVAL;
	if (crtc_h < 2)
		return -EINVAL;

	switch (ipu_plane->dp_flow) {
	case IPU_DP_FLOW_SYNC_BG:
		ret = ipu_dp_setup_channel(ipu_plane->dp,
				IPUV3_COLORSPACE_RGB,
				IPUV3_COLORSPACE_RGB);
		if (ret) {
			dev_err(dev,
				"initializing display processor failed with %d\n",
				ret);
			return ret;
		}
		ipu_dp_set_global_alpha(ipu_plane->dp, 1, 0, 1);
		break;
	case IPU_DP_FLOW_SYNC_FG:
		ipu_dp_setup_channel(ipu_plane->dp,
				ipu_drm_fourcc_to_colorspace(fb->pixel_format),
				IPUV3_COLORSPACE_UNKNOWN);
		ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
		break;
	}

	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	if (ret) {
		dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
		return ret;
	}

	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
			calc_bandwidth(crtc_w, crtc_h,
				       calc_vref(mode)), 64);
	if (ret) {
		dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
		return ret;
	}

	cpmem = ipu_get_cpmem(ipu_plane->ipu_ch);
	ipu_ch_param_zero(cpmem);
	ipu_cpmem_set_resolution(cpmem, src_w, src_h);
	ret = ipu_cpmem_set_fmt(cpmem, fb->pixel_format);
	if (ret < 0) {
		dev_err(dev, "unsupported pixel format 0x%08x\n",
			fb->pixel_format);
		return ret;
	}
	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);

	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	if (ret < 0)
		return ret;

	return 0;
}

void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
{
	if (!IS_ERR_OR_NULL(ipu_plane->dp))
		ipu_dp_put(ipu_plane->dp);
	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
		ipu_dmfc_put(ipu_plane->dmfc);
	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
		ipu_idmac_put(ipu_plane->ipu_ch);
}

int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
{
	int ret;

	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->ipu_ch)) {
		ret = PTR_ERR(ipu_plane->ipu_ch);
		DRM_ERROR("failed to get idmac channel: %d\n", ret);
		return ret;
	}

	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->dmfc)) {
		ret = PTR_ERR(ipu_plane->dmfc);
		DRM_ERROR("failed to get dmfc: ret %d\n", ret);
		goto err_out;
	}

	if (ipu_plane->dp_flow >= 0) {
		ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
		if (IS_ERR(ipu_plane->dp)) {
			ret = PTR_ERR(ipu_plane->dp);
			DRM_ERROR("failed to get dp flow: %d\n", ret);
			goto err_out;
		}
	}

	return 0;
err_out:
	ipu_plane_put_resources(ipu_plane);

	return ret;
}

void ipu_plane_enable(struct ipu_plane *ipu_plane)
{
	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	if (ipu_plane->dp)
		ipu_dp_enable_channel(ipu_plane->dp);

	ipu_plane->enabled = true;
}

void ipu_plane_disable(struct ipu_plane *ipu_plane)
{
	ipu_plane->enabled = false;

	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);

	if (ipu_plane->dp)
		ipu_dp_disable_channel(ipu_plane->dp);
	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	ipu_dmfc_disable_channel(ipu_plane->dmfc);
}

static void ipu_plane_dpms(struct ipu_plane *ipu_plane, int mode)
{
	bool enable;

	DRM_DEBUG_KMS("mode = %d", mode);

	enable = (mode == DRM_MODE_DPMS_ON);

	if (enable == ipu_plane->enabled)
		return;

	if (enable) {
		ipu_plane_enable(ipu_plane);
	} else {
		ipu_plane_disable(ipu_plane);

		ipu_idmac_put(ipu_plane->ipu_ch);
		ipu_dmfc_put(ipu_plane->dmfc);
		ipu_dp_put(ipu_plane->dp);
	}
}

/*
 * drm_plane API
 */

static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
			    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
			    unsigned int crtc_w, unsigned int crtc_h,
			    uint32_t src_x, uint32_t src_y,
			    uint32_t src_w, uint32_t src_h)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	int ret = 0;

	DRM_DEBUG_KMS("plane - %p\n", plane);

	if (!ipu_plane->enabled)
		ret = ipu_plane_get_resources(ipu_plane);
	if (ret < 0)
		return ret;

	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
			crtc_x, crtc_y, crtc_w, crtc_h,
			src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16);
	if (ret < 0) {
		ipu_plane_put_resources(ipu_plane);
		return ret;
	}

	if (crtc != plane->crtc)
		dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
				plane->crtc, crtc);
	plane->crtc = crtc;

	ipu_plane_dpms(ipu_plane, DRM_MODE_DPMS_ON);

	return 0;
}

static int ipu_disable_plane(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	ipu_plane_dpms(ipu_plane, DRM_MODE_DPMS_OFF);

	ipu_plane_put_resources(ipu_plane);

	return 0;
}

static void ipu_plane_destroy(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	ipu_disable_plane(plane);
	drm_plane_cleanup(plane);
	kfree(ipu_plane);
}

static struct drm_plane_funcs ipu_plane_funcs = {
	.update_plane	= ipu_update_plane,
	.disable_plane	= ipu_disable_plane,
	.destroy	= ipu_plane_destroy,
};

struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
				 int dma, int dp, unsigned int possible_crtcs,
				 bool priv)
{
	struct ipu_plane *ipu_plane;
	int ret;

	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
		      dma, dp, possible_crtcs);

	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	if (!ipu_plane) {
		DRM_ERROR("failed to allocate plane\n");
		return ERR_PTR(-ENOMEM);
	}

	ipu_plane->ipu = ipu;
	ipu_plane->dma = dma;
	ipu_plane->dp_flow = dp;

	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
			     &ipu_plane_funcs, ipu_plane_formats,
			     ARRAY_SIZE(ipu_plane_formats),
			     priv);
	if (ret) {
		DRM_ERROR("failed to initialize plane\n");
		kfree(ipu_plane);
		return ERR_PTR(ret);
	}

	return ipu_plane;
}
Commit	Line	Data
b8d181e4 PZ	1	/*
	2	* i.MX IPUv3 DP Overlay Planes
	3	*
	4	* Copyright (C) 2013 Philipp Zabel, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <drm/drmP.h>
	17	#include <drm/drm_fb_cma_helper.h>
	18	#include <drm/drm_gem_cma_helper.h>
	19
	20	#include "ipu-v3/imx-ipu-v3.h"
	21	#include "ipuv3-plane.h"
	22
	23	#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
	24
	25	static const uint32_t ipu_plane_formats[] = {
	26	DRM_FORMAT_XRGB1555,
	27	DRM_FORMAT_XBGR1555,
	28	DRM_FORMAT_ARGB8888,
	29	DRM_FORMAT_XRGB8888,
	30	DRM_FORMAT_ABGR8888,
	31	DRM_FORMAT_XBGR8888,
	32	DRM_FORMAT_YUYV,
	33	DRM_FORMAT_YVYU,
	34	DRM_FORMAT_YUV420,
	35	DRM_FORMAT_YVU420,
	36	};
	37
	38	int ipu_plane_irq(struct ipu_plane *ipu_plane)
	39	{
	40	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
	41	IPU_IRQ_EOF);
	42	}
	43
	44	static int calc_vref(struct drm_display_mode *mode)
	45	{
	46	unsigned long htotal, vtotal;
	47
	48	htotal = mode->htotal;
	49	vtotal = mode->vtotal;
	50
	51	if (!htotal \|\| !vtotal)
	52	return 60;
	53
	54	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
	55	}
	56
	57	static inline int calc_bandwidth(int width, int height, unsigned int vref)
	58	{
	59	return width * height * vref;
	60	}
	61
	62	int ipu_plane_set_base(struct ipu_plane ipu_plane, struct drm_framebuffer fb,
	63	int x, int y)
	64	{
65	struct ipu_ch_param __iomem *cpmem;
66	struct drm_gem_cma_object *cma_obj;
ee2e072e	67	unsigned long eba;
b8d181e4 PZ	68
	69	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	70	if (!cma_obj) {
	71	DRM_LOG_KMS("entry is null.\n");
	72	return -EFAULT;
	73	}
	74
	75	dev_dbg(ipu_plane->base.dev->dev, "phys = 0x%x, x = %d, y = %d",
	76	cma_obj->paddr, x, y);
	77
	78	cpmem = ipu_get_cpmem(ipu_plane->ipu_ch);
	79	ipu_cpmem_set_stride(cpmem, fb->pitches[0]);
ee2e072e	80
bc2b067a LS	81	eba = cma_obj->paddr + fb->offsets[0] +
bc2b067a LS	82	fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
ee2e072e PZ	83	ipu_cpmem_set_buffer(cpmem, 0, eba);
ee2e072e PZ	84	ipu_cpmem_set_buffer(cpmem, 1, eba);
b8d181e4 PZ	85
	86	return 0;
	87	}
	88
	89	int ipu_plane_mode_set(struct ipu_plane ipu_plane, struct drm_crtc crtc,
	90	struct drm_display_mode *mode,
	91	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	92	unsigned int crtc_w, unsigned int crtc_h,
	93	uint32_t src_x, uint32_t src_y,
	94	uint32_t src_w, uint32_t src_h)
	95	{
	96	struct ipu_ch_param __iomem *cpmem;
	97	struct device *dev = ipu_plane->base.dev->dev;
	98	int ret;
	99
	100	/* no scaling */
	101	if (src_w != crtc_w \|\| src_h != crtc_h)
	102	return -EINVAL;
	103
	104	/* clip to crtc bounds */
	105	if (crtc_x < 0) {
	106	if (-crtc_x > crtc_w)
	107	return -EINVAL;
	108	src_x += -crtc_x;
	109	src_w -= -crtc_x;
	110	crtc_w -= -crtc_x;
	111	crtc_x = 0;
	112	}
	113	if (crtc_y < 0) {
	114	if (-crtc_y > crtc_h)
	115	return -EINVAL;
	116	src_y += -crtc_y;
	117	src_h -= -crtc_y;
	118	crtc_h -= -crtc_y;
	119	crtc_y = 0;
	120	}
	121	if (crtc_x + crtc_w > mode->hdisplay) {
	122	if (crtc_x > mode->hdisplay)
	123	return -EINVAL;
	124	crtc_w = mode->hdisplay - crtc_x;
	125	src_w = crtc_w;
	126	}
	127	if (crtc_y + crtc_h > mode->vdisplay) {
	128	if (crtc_y > mode->vdisplay)
	129	return -EINVAL;
	130	crtc_h = mode->vdisplay - crtc_y;
	131	src_h = crtc_h;
	132	}
	133	/* full plane minimum width is 13 pixels */
	134	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
	135	return -EINVAL;
	136	if (crtc_h < 2)
	137	return -EINVAL;
	138
	139	switch (ipu_plane->dp_flow) {
	140	case IPU_DP_FLOW_SYNC_BG:
	141	ret = ipu_dp_setup_channel(ipu_plane->dp,
	142	IPUV3_COLORSPACE_RGB,
	143	IPUV3_COLORSPACE_RGB);
	144	if (ret) {
	145	dev_err(dev,
	146	"initializing display processor failed with %d\n",
	147	ret);
	148	return ret;
149	}
150	ipu_dp_set_global_alpha(ipu_plane->dp, 1, 0, 1);
151	break;
152	case IPU_DP_FLOW_SYNC_FG:
153	ipu_dp_setup_channel(ipu_plane->dp,
154	ipu_drm_fourcc_to_colorspace(fb->pixel_format),
155	IPUV3_COLORSPACE_UNKNOWN);
156	ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
157	break;
158	}
159
160	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
161	if (ret) {
162	dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
163	return ret;
164	}
165
166	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
167	calc_bandwidth(crtc_w, crtc_h,
168	calc_vref(mode)), 64);
169	if (ret) {
170	dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
171	return ret;
172	}
173
174	cpmem = ipu_get_cpmem(ipu_plane->ipu_ch);
175	ipu_ch_param_zero(cpmem);
176	ipu_cpmem_set_resolution(cpmem, src_w, src_h);
177	ret = ipu_cpmem_set_fmt(cpmem, fb->pixel_format);
178	if (ret < 0) {
179	dev_err(dev, "unsupported pixel format 0x%08x\n",
180	fb->pixel_format);
181	return ret;
182	}
183	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
184
185	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
186	if (ret < 0)
187	return ret;
188
189	return 0;
190	}
191
192	void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
193	{
194	if (!IS_ERR_OR_NULL(ipu_plane->dp))
195	ipu_dp_put(ipu_plane->dp);
196	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
197	ipu_dmfc_put(ipu_plane->dmfc);
198	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
199	ipu_idmac_put(ipu_plane->ipu_ch);
200	}
201
202	int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
203	{
204	int ret;
205
206	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
207	if (IS_ERR(ipu_plane->ipu_ch)) {
208	ret = PTR_ERR(ipu_plane->ipu_ch);
209	DRM_ERROR("failed to get idmac channel: %d\n", ret);
210	return ret;
211	}
212
213	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
214	if (IS_ERR(ipu_plane->dmfc)) {
215	ret = PTR_ERR(ipu_plane->dmfc);
216	DRM_ERROR("failed to get dmfc: ret %d\n", ret);
217	goto err_out;
218	}
219
220	if (ipu_plane->dp_flow >= 0) {
221	ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
222	if (IS_ERR(ipu_plane->dp)) {
223	ret = PTR_ERR(ipu_plane->dp);
224	DRM_ERROR("failed to get dp flow: %d\n", ret);
225	goto err_out;
226	}
227	}
228
229	return 0;
230	err_out:
231	ipu_plane_put_resources(ipu_plane);
232
233	return ret;
234	}
235
236	void ipu_plane_enable(struct ipu_plane *ipu_plane)
237	{
238	ipu_dmfc_enable_channel(ipu_plane->dmfc);
239	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
240	if (ipu_plane->dp)
241	ipu_dp_enable_channel(ipu_plane->dp);
242
243	ipu_plane->enabled = true;
244	}
245
246	void ipu_plane_disable(struct ipu_plane *ipu_plane)
247	{
248	ipu_plane->enabled = false;
249
250	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
251
252	if (ipu_plane->dp)
253	ipu_dp_disable_channel(ipu_plane->dp);
254	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
255	ipu_dmfc_disable_channel(ipu_plane->dmfc);
256	}
257
258	static void ipu_plane_dpms(struct ipu_plane *ipu_plane, int mode)
259	{
260	bool enable;
261
262	DRM_DEBUG_KMS("mode = %d", mode);
263
264	enable = (mode == DRM_MODE_DPMS_ON);
265
266	if (enable == ipu_plane->enabled)
267	return;
268
269	if (enable) {
270	ipu_plane_enable(ipu_plane);
271	} else {
272	ipu_plane_disable(ipu_plane);
273
274	ipu_idmac_put(ipu_plane->ipu_ch);
275	ipu_dmfc_put(ipu_plane->dmfc);
276	ipu_dp_put(ipu_plane->dp);
277	}
278	}
279
280	/*
281	* drm_plane API
282	*/
283
284	static int ipu_update_plane(struct drm_plane plane, struct drm_crtc crtc,
285	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
286	unsigned int crtc_w, unsigned int crtc_h,
287	uint32_t src_x, uint32_t src_y,
288	uint32_t src_w, uint32_t src_h)
289	{
290	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
291	int ret = 0;
292
293	DRM_DEBUG_KMS("plane - %p\n", plane);
294
295	if (!ipu_plane->enabled)
296	ret = ipu_plane_get_resources(ipu_plane);
297	if (ret < 0)
298	return ret;
299
300	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
301	crtc_x, crtc_y, crtc_w, crtc_h,
302	src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16);
303	if (ret < 0) {
304	ipu_plane_put_resources(ipu_plane);
305	return ret;
306	}
307
308	if (crtc != plane->crtc)
309	dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
310	plane->crtc, crtc);
311	plane->crtc = crtc;
312
313	ipu_plane_dpms(ipu_plane, DRM_MODE_DPMS_ON);
314
315	return 0;
316	}
317
318	static int ipu_disable_plane(struct drm_plane *plane)
319	{
320	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
321
322	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
323
324	ipu_plane_dpms(ipu_plane, DRM_MODE_DPMS_OFF);
325
326	ipu_plane_put_resources(ipu_plane);
327
328	return 0;
329	}
330
331	static void ipu_plane_destroy(struct drm_plane *plane)
332	{
333	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
334
335	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
336
337	ipu_disable_plane(plane);
338	drm_plane_cleanup(plane);
339	kfree(ipu_plane);
340	}
341
342	static struct drm_plane_funcs ipu_plane_funcs = {
343	.update_plane = ipu_update_plane,
344	.disable_plane = ipu_disable_plane,
345	.destroy = ipu_plane_destroy,
346	};
347
348	struct ipu_plane ipu_plane_init(struct drm_device dev, struct ipu_soc *ipu,
349	int dma, int dp, unsigned int possible_crtcs,
350	bool priv)
351	{
352	struct ipu_plane *ipu_plane;
353	int ret;
354
355	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
356	dma, dp, possible_crtcs);
357
358	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
359	if (!ipu_plane) {
360	DRM_ERROR("failed to allocate plane\n");
361	return ERR_PTR(-ENOMEM);
362	}
363
364	ipu_plane->ipu = ipu;
365	ipu_plane->dma = dma;
366	ipu_plane->dp_flow = dp;
367
368	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
369	&ipu_plane_funcs, ipu_plane_formats,
370	ARRAY_SIZE(ipu_plane_formats),
371	priv);
372	if (ret) {
373	DRM_ERROR("failed to initialize plane\n");
374	kfree(ipu_plane);
375	return ERR_PTR(ret);
376	}
377
378	return ipu_plane;
379	}