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1beef3c1 JW |
1 | /* |
2 | * lirc_serial.c | |
3 | * | |
4 | * lirc_serial - Device driver that records pulse- and pause-lengths | |
5 | * (space-lengths) between DDCD event on a serial port. | |
6 | * | |
7 | * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de> | |
8 | * Copyright (C) 1998 Trent Piepho <xyzzy@u.washington.edu> | |
9 | * Copyright (C) 1998 Ben Pfaff <blp@gnu.org> | |
10 | * Copyright (C) 1999 Christoph Bartelmus <lirc@bartelmus.de> | |
11 | * Copyright (C) 2007 Andrei Tanas <andrei@tanas.ca> (suspend/resume support) | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Steve's changes to improve transmission fidelity: | |
30 | * - for systems with the rdtsc instruction and the clock counter, a | |
31 | * send_pule that times the pulses directly using the counter. | |
32 | * This means that the LIRC_SERIAL_TRANSMITTER_LATENCY fudge is | |
33 | * not needed. Measurement shows very stable waveform, even where | |
34 | * PCI activity slows the access to the UART, which trips up other | |
35 | * versions. | |
36 | * - For other system, non-integer-microsecond pulse/space lengths, | |
37 | * done using fixed point binary. So, much more accurate carrier | |
38 | * frequency. | |
39 | * - fine tuned transmitter latency, taking advantage of fractional | |
40 | * microseconds in previous change | |
41 | * - Fixed bug in the way transmitter latency was accounted for by | |
42 | * tuning the pulse lengths down - the send_pulse routine ignored | |
43 | * this overhead as it timed the overall pulse length - so the | |
44 | * pulse frequency was right but overall pulse length was too | |
45 | * long. Fixed by accounting for latency on each pulse/space | |
46 | * iteration. | |
47 | * | |
48 | * Steve Davies <steve@daviesfam.org> July 2001 | |
49 | */ | |
50 | ||
51 | #include <linux/module.h> | |
52 | #include <linux/errno.h> | |
53 | #include <linux/signal.h> | |
54 | #include <linux/sched.h> | |
55 | #include <linux/fs.h> | |
56 | #include <linux/interrupt.h> | |
57 | #include <linux/ioport.h> | |
58 | #include <linux/kernel.h> | |
59 | #include <linux/serial_reg.h> | |
60 | #include <linux/time.h> | |
61 | #include <linux/string.h> | |
62 | #include <linux/types.h> | |
63 | #include <linux/wait.h> | |
64 | #include <linux/mm.h> | |
65 | #include <linux/delay.h> | |
66 | #include <linux/poll.h> | |
67 | #include <linux/platform_device.h> | |
68 | ||
69 | #include <asm/system.h> | |
70 | #include <linux/io.h> | |
71 | #include <linux/irq.h> | |
72 | #include <linux/fcntl.h> | |
73 | #include <linux/spinlock.h> | |
74 | ||
75 | #ifdef CONFIG_LIRC_SERIAL_NSLU2 | |
76 | #include <asm/hardware.h> | |
77 | #endif | |
78 | /* From Intel IXP42X Developer's Manual (#252480-005): */ | |
79 | /* ftp://download.intel.com/design/network/manuals/25248005.pdf */ | |
80 | #define UART_IE_IXP42X_UUE 0x40 /* IXP42X UART Unit enable */ | |
81 | #define UART_IE_IXP42X_RTOIE 0x10 /* IXP42X Receiver Data Timeout int.enable */ | |
82 | ||
83 | #include <media/lirc.h> | |
84 | #include <media/lirc_dev.h> | |
85 | ||
86 | #define LIRC_DRIVER_NAME "lirc_serial" | |
87 | ||
88 | struct lirc_serial { | |
89 | int signal_pin; | |
90 | int signal_pin_change; | |
91 | u8 on; | |
92 | u8 off; | |
93 | long (*send_pulse)(unsigned long length); | |
94 | void (*send_space)(long length); | |
95 | int features; | |
96 | spinlock_t lock; | |
97 | }; | |
98 | ||
99 | #define LIRC_HOMEBREW 0 | |
100 | #define LIRC_IRDEO 1 | |
101 | #define LIRC_IRDEO_REMOTE 2 | |
102 | #define LIRC_ANIMAX 3 | |
103 | #define LIRC_IGOR 4 | |
104 | #define LIRC_NSLU2 5 | |
105 | ||
106 | /*** module parameters ***/ | |
107 | static int type; | |
108 | static int io; | |
109 | static int irq; | |
110 | static int iommap; | |
111 | static int ioshift; | |
112 | static int softcarrier = 1; | |
113 | static int share_irq; | |
114 | static int debug; | |
115 | static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */ | |
116 | static int txsense; /* 0 = active high, 1 = active low */ | |
117 | ||
118 | #define dprintk(fmt, args...) \ | |
119 | do { \ | |
120 | if (debug) \ | |
121 | printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ | |
122 | fmt, ## args); \ | |
123 | } while (0) | |
124 | ||
125 | /* forward declarations */ | |
126 | static long send_pulse_irdeo(unsigned long length); | |
127 | static long send_pulse_homebrew(unsigned long length); | |
128 | static void send_space_irdeo(long length); | |
129 | static void send_space_homebrew(long length); | |
130 | ||
131 | static struct lirc_serial hardware[] = { | |
132 | [LIRC_HOMEBREW] = { | |
133 | .signal_pin = UART_MSR_DCD, | |
134 | .signal_pin_change = UART_MSR_DDCD, | |
135 | .on = (UART_MCR_RTS | UART_MCR_OUT2 | UART_MCR_DTR), | |
136 | .off = (UART_MCR_RTS | UART_MCR_OUT2), | |
137 | .send_pulse = send_pulse_homebrew, | |
138 | .send_space = send_space_homebrew, | |
139 | #ifdef CONFIG_LIRC_SERIAL_TRANSMITTER | |
140 | .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE | | |
141 | LIRC_CAN_SET_SEND_CARRIER | | |
142 | LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2) | |
143 | #else | |
144 | .features = LIRC_CAN_REC_MODE2 | |
145 | #endif | |
146 | }, | |
147 | ||
148 | [LIRC_IRDEO] = { | |
149 | .signal_pin = UART_MSR_DSR, | |
150 | .signal_pin_change = UART_MSR_DDSR, | |
151 | .on = UART_MCR_OUT2, | |
152 | .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2), | |
153 | .send_pulse = send_pulse_irdeo, | |
154 | .send_space = send_space_irdeo, | |
155 | .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE | | |
156 | LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2) | |
157 | }, | |
158 | ||
159 | [LIRC_IRDEO_REMOTE] = { | |
160 | .signal_pin = UART_MSR_DSR, | |
161 | .signal_pin_change = UART_MSR_DDSR, | |
162 | .on = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2), | |
163 | .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2), | |
164 | .send_pulse = send_pulse_irdeo, | |
165 | .send_space = send_space_irdeo, | |
166 | .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE | | |
167 | LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2) | |
168 | }, | |
169 | ||
170 | [LIRC_ANIMAX] = { | |
171 | .signal_pin = UART_MSR_DCD, | |
172 | .signal_pin_change = UART_MSR_DDCD, | |
173 | .on = 0, | |
174 | .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2), | |
175 | .send_pulse = NULL, | |
176 | .send_space = NULL, | |
177 | .features = LIRC_CAN_REC_MODE2 | |
178 | }, | |
179 | ||
180 | [LIRC_IGOR] = { | |
181 | .signal_pin = UART_MSR_DSR, | |
182 | .signal_pin_change = UART_MSR_DDSR, | |
183 | .on = (UART_MCR_RTS | UART_MCR_OUT2 | UART_MCR_DTR), | |
184 | .off = (UART_MCR_RTS | UART_MCR_OUT2), | |
185 | .send_pulse = send_pulse_homebrew, | |
186 | .send_space = send_space_homebrew, | |
187 | #ifdef CONFIG_LIRC_SERIAL_TRANSMITTER | |
188 | .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE | | |
189 | LIRC_CAN_SET_SEND_CARRIER | | |
190 | LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2) | |
191 | #else | |
192 | .features = LIRC_CAN_REC_MODE2 | |
193 | #endif | |
194 | }, | |
195 | ||
196 | #ifdef CONFIG_LIRC_SERIAL_NSLU2 | |
197 | /* | |
198 | * Modified Linksys Network Storage Link USB 2.0 (NSLU2): | |
199 | * We receive on CTS of the 2nd serial port (R142,LHS), we | |
200 | * transmit with a IR diode between GPIO[1] (green status LED), | |
201 | * and ground (Matthias Goebl <matthias.goebl@goebl.net>). | |
202 | * See also http://www.nslu2-linux.org for this device | |
203 | */ | |
204 | [LIRC_NSLU2] = { | |
205 | .signal_pin = UART_MSR_CTS, | |
206 | .signal_pin_change = UART_MSR_DCTS, | |
207 | .on = (UART_MCR_RTS | UART_MCR_OUT2 | UART_MCR_DTR), | |
208 | .off = (UART_MCR_RTS | UART_MCR_OUT2), | |
209 | .send_pulse = send_pulse_homebrew, | |
210 | .send_space = send_space_homebrew, | |
211 | #ifdef CONFIG_LIRC_SERIAL_TRANSMITTER | |
212 | .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE | | |
213 | LIRC_CAN_SET_SEND_CARRIER | | |
214 | LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2) | |
215 | #else | |
216 | .features = LIRC_CAN_REC_MODE2 | |
217 | #endif | |
218 | }, | |
219 | #endif | |
220 | ||
221 | }; | |
222 | ||
223 | #define RS_ISR_PASS_LIMIT 256 | |
224 | ||
225 | /* | |
226 | * A long pulse code from a remote might take up to 300 bytes. The | |
227 | * daemon should read the bytes as soon as they are generated, so take | |
228 | * the number of keys you think you can push before the daemon runs | |
229 | * and multiply by 300. The driver will warn you if you overrun this | |
230 | * buffer. If you have a slow computer or non-busmastering IDE disks, | |
231 | * maybe you will need to increase this. | |
232 | */ | |
233 | ||
234 | /* This MUST be a power of two! It has to be larger than 1 as well. */ | |
235 | ||
236 | #define RBUF_LEN 256 | |
237 | ||
238 | static struct timeval lasttv = {0, 0}; | |
239 | ||
240 | static struct lirc_buffer rbuf; | |
241 | ||
242 | static unsigned int freq = 38000; | |
243 | static unsigned int duty_cycle = 50; | |
244 | ||
245 | /* Initialized in init_timing_params() */ | |
246 | static unsigned long period; | |
247 | static unsigned long pulse_width; | |
248 | static unsigned long space_width; | |
249 | ||
250 | #if defined(__i386__) | |
251 | /* | |
252 | * From: | |
253 | * Linux I/O port programming mini-HOWTO | |
254 | * Author: Riku Saikkonen <Riku.Saikkonen@hut.fi> | |
255 | * v, 28 December 1997 | |
256 | * | |
257 | * [...] | |
258 | * Actually, a port I/O instruction on most ports in the 0-0x3ff range | |
259 | * takes almost exactly 1 microsecond, so if you're, for example, using | |
260 | * the parallel port directly, just do additional inb()s from that port | |
261 | * to delay. | |
262 | * [...] | |
263 | */ | |
264 | /* transmitter latency 1.5625us 0x1.90 - this figure arrived at from | |
265 | * comment above plus trimming to match actual measured frequency. | |
266 | * This will be sensitive to cpu speed, though hopefully most of the 1.5us | |
267 | * is spent in the uart access. Still - for reference test machine was a | |
268 | * 1.13GHz Athlon system - Steve | |
269 | */ | |
270 | ||
271 | /* | |
272 | * changed from 400 to 450 as this works better on slower machines; | |
273 | * faster machines will use the rdtsc code anyway | |
274 | */ | |
275 | #define LIRC_SERIAL_TRANSMITTER_LATENCY 450 | |
276 | ||
277 | #else | |
278 | ||
279 | /* does anybody have information on other platforms ? */ | |
280 | /* 256 = 1<<8 */ | |
281 | #define LIRC_SERIAL_TRANSMITTER_LATENCY 256 | |
282 | ||
283 | #endif /* __i386__ */ | |
284 | /* | |
285 | * FIXME: should we be using hrtimers instead of this | |
286 | * LIRC_SERIAL_TRANSMITTER_LATENCY nonsense? | |
287 | */ | |
288 | ||
289 | /* fetch serial input packet (1 byte) from register offset */ | |
290 | static u8 sinp(int offset) | |
291 | { | |
292 | if (iommap != 0) | |
293 | /* the register is memory-mapped */ | |
294 | offset <<= ioshift; | |
295 | ||
296 | return inb(io + offset); | |
297 | } | |
298 | ||
299 | /* write serial output packet (1 byte) of value to register offset */ | |
300 | static void soutp(int offset, u8 value) | |
301 | { | |
302 | if (iommap != 0) | |
303 | /* the register is memory-mapped */ | |
304 | offset <<= ioshift; | |
305 | ||
306 | outb(value, io + offset); | |
307 | } | |
308 | ||
309 | static void on(void) | |
310 | { | |
311 | #ifdef CONFIG_LIRC_SERIAL_NSLU2 | |
312 | /* | |
313 | * On NSLU2, we put the transmit diode between the output of the green | |
314 | * status LED and ground | |
315 | */ | |
316 | if (type == LIRC_NSLU2) { | |
317 | gpio_line_set(NSLU2_LED_GRN, IXP4XX_GPIO_LOW); | |
318 | return; | |
319 | } | |
320 | #endif | |
321 | if (txsense) | |
322 | soutp(UART_MCR, hardware[type].off); | |
323 | else | |
324 | soutp(UART_MCR, hardware[type].on); | |
325 | } | |
326 | ||
327 | static void off(void) | |
328 | { | |
329 | #ifdef CONFIG_LIRC_SERIAL_NSLU2 | |
330 | if (type == LIRC_NSLU2) { | |
331 | gpio_line_set(NSLU2_LED_GRN, IXP4XX_GPIO_HIGH); | |
332 | return; | |
333 | } | |
334 | #endif | |
335 | if (txsense) | |
336 | soutp(UART_MCR, hardware[type].on); | |
337 | else | |
338 | soutp(UART_MCR, hardware[type].off); | |
339 | } | |
340 | ||
341 | #ifndef MAX_UDELAY_MS | |
342 | #define MAX_UDELAY_US 5000 | |
343 | #else | |
344 | #define MAX_UDELAY_US (MAX_UDELAY_MS*1000) | |
345 | #endif | |
346 | ||
347 | static void safe_udelay(unsigned long usecs) | |
348 | { | |
349 | while (usecs > MAX_UDELAY_US) { | |
350 | udelay(MAX_UDELAY_US); | |
351 | usecs -= MAX_UDELAY_US; | |
352 | } | |
353 | udelay(usecs); | |
354 | } | |
355 | ||
356 | #ifdef USE_RDTSC | |
357 | /* | |
358 | * This is an overflow/precision juggle, complicated in that we can't | |
359 | * do long long divide in the kernel | |
360 | */ | |
361 | ||
362 | /* | |
363 | * When we use the rdtsc instruction to measure clocks, we keep the | |
364 | * pulse and space widths as clock cycles. As this is CPU speed | |
365 | * dependent, the widths must be calculated in init_port and ioctl | |
366 | * time | |
367 | */ | |
368 | ||
369 | /* So send_pulse can quickly convert microseconds to clocks */ | |
370 | static unsigned long conv_us_to_clocks; | |
371 | ||
372 | static int init_timing_params(unsigned int new_duty_cycle, | |
373 | unsigned int new_freq) | |
374 | { | |
375 | unsigned long long loops_per_sec, work; | |
376 | ||
377 | duty_cycle = new_duty_cycle; | |
378 | freq = new_freq; | |
379 | ||
380 | loops_per_sec = current_cpu_data.loops_per_jiffy; | |
381 | loops_per_sec *= HZ; | |
382 | ||
383 | /* How many clocks in a microsecond?, avoiding long long divide */ | |
384 | work = loops_per_sec; | |
385 | work *= 4295; /* 4295 = 2^32 / 1e6 */ | |
386 | conv_us_to_clocks = (work >> 32); | |
387 | ||
388 | /* | |
389 | * Carrier period in clocks, approach good up to 32GHz clock, | |
390 | * gets carrier frequency within 8Hz | |
391 | */ | |
392 | period = loops_per_sec >> 3; | |
393 | period /= (freq >> 3); | |
394 | ||
395 | /* Derive pulse and space from the period */ | |
396 | pulse_width = period * duty_cycle / 100; | |
397 | space_width = period - pulse_width; | |
398 | dprintk("in init_timing_params, freq=%d, duty_cycle=%d, " | |
399 | "clk/jiffy=%ld, pulse=%ld, space=%ld, " | |
400 | "conv_us_to_clocks=%ld\n", | |
401 | freq, duty_cycle, current_cpu_data.loops_per_jiffy, | |
402 | pulse_width, space_width, conv_us_to_clocks); | |
403 | return 0; | |
404 | } | |
405 | #else /* ! USE_RDTSC */ | |
406 | static int init_timing_params(unsigned int new_duty_cycle, | |
407 | unsigned int new_freq) | |
408 | { | |
409 | /* | |
410 | * period, pulse/space width are kept with 8 binary places - | |
411 | * IE multiplied by 256. | |
412 | */ | |
413 | if (256 * 1000000L / new_freq * new_duty_cycle / 100 <= | |
414 | LIRC_SERIAL_TRANSMITTER_LATENCY) | |
415 | return -EINVAL; | |
416 | if (256 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <= | |
417 | LIRC_SERIAL_TRANSMITTER_LATENCY) | |
418 | return -EINVAL; | |
419 | duty_cycle = new_duty_cycle; | |
420 | freq = new_freq; | |
421 | period = 256 * 1000000L / freq; | |
422 | pulse_width = period * duty_cycle / 100; | |
423 | space_width = period - pulse_width; | |
424 | dprintk("in init_timing_params, freq=%d pulse=%ld, " | |
425 | "space=%ld\n", freq, pulse_width, space_width); | |
426 | return 0; | |
427 | } | |
428 | #endif /* USE_RDTSC */ | |
429 | ||
430 | ||
431 | /* return value: space length delta */ | |
432 | ||
433 | static long send_pulse_irdeo(unsigned long length) | |
434 | { | |
435 | long rawbits, ret; | |
436 | int i; | |
437 | unsigned char output; | |
438 | unsigned char chunk, shifted; | |
439 | ||
440 | /* how many bits have to be sent ? */ | |
441 | rawbits = length * 1152 / 10000; | |
442 | if (duty_cycle > 50) | |
443 | chunk = 3; | |
444 | else | |
445 | chunk = 1; | |
446 | for (i = 0, output = 0x7f; rawbits > 0; rawbits -= 3) { | |
447 | shifted = chunk << (i * 3); | |
448 | shifted >>= 1; | |
449 | output &= (~shifted); | |
450 | i++; | |
451 | if (i == 3) { | |
452 | soutp(UART_TX, output); | |
453 | while (!(sinp(UART_LSR) & UART_LSR_THRE)) | |
454 | ; | |
455 | output = 0x7f; | |
456 | i = 0; | |
457 | } | |
458 | } | |
459 | if (i != 0) { | |
460 | soutp(UART_TX, output); | |
461 | while (!(sinp(UART_LSR) & UART_LSR_TEMT)) | |
462 | ; | |
463 | } | |
464 | ||
465 | if (i == 0) | |
466 | ret = (-rawbits) * 10000 / 1152; | |
467 | else | |
468 | ret = (3 - i) * 3 * 10000 / 1152 + (-rawbits) * 10000 / 1152; | |
469 | ||
470 | return ret; | |
471 | } | |
472 | ||
473 | #ifdef USE_RDTSC | |
474 | /* Version that uses Pentium rdtsc instruction to measure clocks */ | |
475 | ||
476 | /* | |
477 | * This version does sub-microsecond timing using rdtsc instruction, | |
478 | * and does away with the fudged LIRC_SERIAL_TRANSMITTER_LATENCY | |
479 | * Implicitly i586 architecture... - Steve | |
480 | */ | |
481 | ||
482 | static long send_pulse_homebrew_softcarrier(unsigned long length) | |
483 | { | |
484 | int flag; | |
485 | unsigned long target, start, now; | |
486 | ||
487 | /* Get going quick as we can */ | |
488 | rdtscl(start); | |
489 | on(); | |
490 | /* Convert length from microseconds to clocks */ | |
491 | length *= conv_us_to_clocks; | |
492 | /* And loop till time is up - flipping at right intervals */ | |
493 | now = start; | |
494 | target = pulse_width; | |
495 | flag = 1; | |
496 | /* | |
497 | * FIXME: This looks like a hard busy wait, without even an occasional, | |
498 | * polite, cpu_relax() call. There's got to be a better way? | |
499 | * | |
500 | * The i2c code has the result of a lot of bit-banging work, I wonder if | |
501 | * there's something there which could be helpful here. | |
502 | */ | |
503 | while ((now - start) < length) { | |
504 | /* Delay till flip time */ | |
505 | do { | |
506 | rdtscl(now); | |
507 | } while ((now - start) < target); | |
508 | ||
509 | /* flip */ | |
510 | if (flag) { | |
511 | rdtscl(now); | |
512 | off(); | |
513 | target += space_width; | |
514 | } else { | |
515 | rdtscl(now); on(); | |
516 | target += pulse_width; | |
517 | } | |
518 | flag = !flag; | |
519 | } | |
520 | rdtscl(now); | |
521 | return ((now - start) - length) / conv_us_to_clocks; | |
522 | } | |
523 | #else /* ! USE_RDTSC */ | |
524 | /* Version using udelay() */ | |
525 | ||
526 | /* | |
527 | * here we use fixed point arithmetic, with 8 | |
528 | * fractional bits. that gets us within 0.1% or so of the right average | |
529 | * frequency, albeit with some jitter in pulse length - Steve | |
530 | */ | |
531 | ||
532 | /* To match 8 fractional bits used for pulse/space length */ | |
533 | ||
534 | static long send_pulse_homebrew_softcarrier(unsigned long length) | |
535 | { | |
536 | int flag; | |
537 | unsigned long actual, target, d; | |
538 | length <<= 8; | |
539 | ||
540 | actual = 0; target = 0; flag = 0; | |
541 | while (actual < length) { | |
542 | if (flag) { | |
543 | off(); | |
544 | target += space_width; | |
545 | } else { | |
546 | on(); | |
547 | target += pulse_width; | |
548 | } | |
549 | d = (target - actual - | |
550 | LIRC_SERIAL_TRANSMITTER_LATENCY + 128) >> 8; | |
551 | /* | |
552 | * Note - we've checked in ioctl that the pulse/space | |
553 | * widths are big enough so that d is > 0 | |
554 | */ | |
555 | udelay(d); | |
556 | actual += (d << 8) + LIRC_SERIAL_TRANSMITTER_LATENCY; | |
557 | flag = !flag; | |
558 | } | |
559 | return (actual-length) >> 8; | |
560 | } | |
561 | #endif /* USE_RDTSC */ | |
562 | ||
563 | static long send_pulse_homebrew(unsigned long length) | |
564 | { | |
565 | if (length <= 0) | |
566 | return 0; | |
567 | ||
568 | if (softcarrier) | |
569 | return send_pulse_homebrew_softcarrier(length); | |
570 | else { | |
571 | on(); | |
572 | safe_udelay(length); | |
573 | return 0; | |
574 | } | |
575 | } | |
576 | ||
577 | static void send_space_irdeo(long length) | |
578 | { | |
579 | if (length <= 0) | |
580 | return; | |
581 | ||
582 | safe_udelay(length); | |
583 | } | |
584 | ||
585 | static void send_space_homebrew(long length) | |
586 | { | |
587 | off(); | |
588 | if (length <= 0) | |
589 | return; | |
590 | safe_udelay(length); | |
591 | } | |
592 | ||
593 | static void rbwrite(int l) | |
594 | { | |
595 | if (lirc_buffer_full(&rbuf)) { | |
596 | /* no new signals will be accepted */ | |
597 | dprintk("Buffer overrun\n"); | |
598 | return; | |
599 | } | |
600 | lirc_buffer_write(&rbuf, (void *)&l); | |
601 | } | |
602 | ||
603 | static void frbwrite(int l) | |
604 | { | |
605 | /* simple noise filter */ | |
606 | static int pulse, space; | |
607 | static unsigned int ptr; | |
608 | ||
609 | if (ptr > 0 && (l & PULSE_BIT)) { | |
610 | pulse += l & PULSE_MASK; | |
611 | if (pulse > 250) { | |
612 | rbwrite(space); | |
613 | rbwrite(pulse | PULSE_BIT); | |
614 | ptr = 0; | |
615 | pulse = 0; | |
616 | } | |
617 | return; | |
618 | } | |
619 | if (!(l & PULSE_BIT)) { | |
620 | if (ptr == 0) { | |
621 | if (l > 20000) { | |
622 | space = l; | |
623 | ptr++; | |
624 | return; | |
625 | } | |
626 | } else { | |
627 | if (l > 20000) { | |
628 | space += pulse; | |
629 | if (space > PULSE_MASK) | |
630 | space = PULSE_MASK; | |
631 | space += l; | |
632 | if (space > PULSE_MASK) | |
633 | space = PULSE_MASK; | |
634 | pulse = 0; | |
635 | return; | |
636 | } | |
637 | rbwrite(space); | |
638 | rbwrite(pulse | PULSE_BIT); | |
639 | ptr = 0; | |
640 | pulse = 0; | |
641 | } | |
642 | } | |
643 | rbwrite(l); | |
644 | } | |
645 | ||
646 | static irqreturn_t irq_handler(int i, void *blah) | |
647 | { | |
648 | struct timeval tv; | |
649 | int counter, dcd; | |
650 | u8 status; | |
651 | long deltv; | |
652 | int data; | |
653 | static int last_dcd = -1; | |
654 | ||
655 | if ((sinp(UART_IIR) & UART_IIR_NO_INT)) { | |
656 | /* not our interrupt */ | |
657 | return IRQ_NONE; | |
658 | } | |
659 | ||
660 | counter = 0; | |
661 | do { | |
662 | counter++; | |
663 | status = sinp(UART_MSR); | |
664 | if (counter > RS_ISR_PASS_LIMIT) { | |
665 | printk(KERN_WARNING LIRC_DRIVER_NAME ": AIEEEE: " | |
666 | "We're caught!\n"); | |
667 | break; | |
668 | } | |
669 | if ((status & hardware[type].signal_pin_change) | |
670 | && sense != -1) { | |
671 | /* get current time */ | |
672 | do_gettimeofday(&tv); | |
673 | ||
674 | /* New mode, written by Trent Piepho | |
675 | <xyzzy@u.washington.edu>. */ | |
676 | ||
677 | /* | |
678 | * The old format was not very portable. | |
679 | * We now use an int to pass pulses | |
680 | * and spaces to user space. | |
681 | * | |
682 | * If PULSE_BIT is set a pulse has been | |
683 | * received, otherwise a space has been | |
684 | * received. The driver needs to know if your | |
685 | * receiver is active high or active low, or | |
686 | * the space/pulse sense could be | |
687 | * inverted. The bits denoted by PULSE_MASK are | |
688 | * the length in microseconds. Lengths greater | |
689 | * than or equal to 16 seconds are clamped to | |
690 | * PULSE_MASK. All other bits are unused. | |
691 | * This is a much simpler interface for user | |
692 | * programs, as well as eliminating "out of | |
693 | * phase" errors with space/pulse | |
694 | * autodetection. | |
695 | */ | |
696 | ||
697 | /* calc time since last interrupt in microseconds */ | |
698 | dcd = (status & hardware[type].signal_pin) ? 1 : 0; | |
699 | ||
700 | if (dcd == last_dcd) { | |
701 | printk(KERN_WARNING LIRC_DRIVER_NAME | |
702 | ": ignoring spike: %d %d %lx %lx %lx %lx\n", | |
703 | dcd, sense, | |
704 | tv.tv_sec, lasttv.tv_sec, | |
705 | tv.tv_usec, lasttv.tv_usec); | |
706 | continue; | |
707 | } | |
708 | ||
709 | deltv = tv.tv_sec-lasttv.tv_sec; | |
710 | if (tv.tv_sec < lasttv.tv_sec || | |
711 | (tv.tv_sec == lasttv.tv_sec && | |
712 | tv.tv_usec < lasttv.tv_usec)) { | |
713 | printk(KERN_WARNING LIRC_DRIVER_NAME | |
714 | ": AIEEEE: your clock just jumped " | |
715 | "backwards\n"); | |
716 | printk(KERN_WARNING LIRC_DRIVER_NAME | |
717 | ": %d %d %lx %lx %lx %lx\n", | |
718 | dcd, sense, | |
719 | tv.tv_sec, lasttv.tv_sec, | |
720 | tv.tv_usec, lasttv.tv_usec); | |
721 | data = PULSE_MASK; | |
722 | } else if (deltv > 15) { | |
723 | data = PULSE_MASK; /* really long time */ | |
724 | if (!(dcd^sense)) { | |
725 | /* sanity check */ | |
726 | printk(KERN_WARNING LIRC_DRIVER_NAME | |
727 | ": AIEEEE: " | |
728 | "%d %d %lx %lx %lx %lx\n", | |
729 | dcd, sense, | |
730 | tv.tv_sec, lasttv.tv_sec, | |
731 | tv.tv_usec, lasttv.tv_usec); | |
732 | /* | |
733 | * detecting pulse while this | |
734 | * MUST be a space! | |
735 | */ | |
736 | sense = sense ? 0 : 1; | |
737 | } | |
738 | } else | |
739 | data = (int) (deltv*1000000 + | |
740 | tv.tv_usec - | |
741 | lasttv.tv_usec); | |
742 | frbwrite(dcd^sense ? data : (data|PULSE_BIT)); | |
743 | lasttv = tv; | |
744 | last_dcd = dcd; | |
745 | wake_up_interruptible(&rbuf.wait_poll); | |
746 | } | |
747 | } while (!(sinp(UART_IIR) & UART_IIR_NO_INT)); /* still pending ? */ | |
748 | return IRQ_HANDLED; | |
749 | } | |
750 | ||
751 | ||
752 | static int hardware_init_port(void) | |
753 | { | |
754 | u8 scratch, scratch2, scratch3; | |
755 | ||
756 | /* | |
757 | * This is a simple port existence test, borrowed from the autoconfig | |
758 | * function in drivers/serial/8250.c | |
759 | */ | |
760 | scratch = sinp(UART_IER); | |
761 | soutp(UART_IER, 0); | |
762 | #ifdef __i386__ | |
763 | outb(0xff, 0x080); | |
764 | #endif | |
765 | scratch2 = sinp(UART_IER) & 0x0f; | |
766 | soutp(UART_IER, 0x0f); | |
767 | #ifdef __i386__ | |
768 | outb(0x00, 0x080); | |
769 | #endif | |
770 | scratch3 = sinp(UART_IER) & 0x0f; | |
771 | soutp(UART_IER, scratch); | |
772 | if (scratch2 != 0 || scratch3 != 0x0f) { | |
773 | /* we fail, there's nothing here */ | |
774 | printk(KERN_ERR LIRC_DRIVER_NAME ": port existence test " | |
775 | "failed, cannot continue\n"); | |
776 | return -EINVAL; | |
777 | } | |
778 | ||
779 | ||
780 | ||
781 | /* Set DLAB 0. */ | |
782 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
783 | ||
784 | /* First of all, disable all interrupts */ | |
785 | soutp(UART_IER, sinp(UART_IER) & | |
786 | (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI))); | |
787 | ||
788 | /* Clear registers. */ | |
789 | sinp(UART_LSR); | |
790 | sinp(UART_RX); | |
791 | sinp(UART_IIR); | |
792 | sinp(UART_MSR); | |
793 | ||
794 | #ifdef CONFIG_LIRC_SERIAL_NSLU2 | |
795 | if (type == LIRC_NSLU2) { | |
796 | /* Setup NSLU2 UART */ | |
797 | ||
798 | /* Enable UART */ | |
799 | soutp(UART_IER, sinp(UART_IER) | UART_IE_IXP42X_UUE); | |
800 | /* Disable Receiver data Time out interrupt */ | |
801 | soutp(UART_IER, sinp(UART_IER) & ~UART_IE_IXP42X_RTOIE); | |
802 | /* set out2 = interrupt unmask; off() doesn't set MCR | |
803 | on NSLU2 */ | |
804 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); | |
805 | } | |
806 | #endif | |
807 | ||
808 | /* Set line for power source */ | |
809 | off(); | |
810 | ||
811 | /* Clear registers again to be sure. */ | |
812 | sinp(UART_LSR); | |
813 | sinp(UART_RX); | |
814 | sinp(UART_IIR); | |
815 | sinp(UART_MSR); | |
816 | ||
817 | switch (type) { | |
818 | case LIRC_IRDEO: | |
819 | case LIRC_IRDEO_REMOTE: | |
820 | /* setup port to 7N1 @ 115200 Baud */ | |
821 | /* 7N1+start = 9 bits at 115200 ~ 3 bits at 38kHz */ | |
822 | ||
823 | /* Set DLAB 1. */ | |
824 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); | |
825 | /* Set divisor to 1 => 115200 Baud */ | |
826 | soutp(UART_DLM, 0); | |
827 | soutp(UART_DLL, 1); | |
828 | /* Set DLAB 0 + 7N1 */ | |
829 | soutp(UART_LCR, UART_LCR_WLEN7); | |
830 | /* THR interrupt already disabled at this point */ | |
831 | break; | |
832 | default: | |
833 | break; | |
834 | } | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
839 | static int init_port(void) | |
840 | { | |
841 | int i, nlow, nhigh; | |
842 | ||
843 | /* Reserve io region. */ | |
844 | /* | |
845 | * Future MMAP-Developers: Attention! | |
846 | * For memory mapped I/O you *might* need to use ioremap() first, | |
847 | * for the NSLU2 it's done in boot code. | |
848 | */ | |
849 | if (((iommap != 0) | |
850 | && (request_mem_region(iommap, 8 << ioshift, | |
851 | LIRC_DRIVER_NAME) == NULL)) | |
852 | || ((iommap == 0) | |
853 | && (request_region(io, 8, LIRC_DRIVER_NAME) == NULL))) { | |
854 | printk(KERN_ERR LIRC_DRIVER_NAME | |
855 | ": port %04x already in use\n", io); | |
856 | printk(KERN_WARNING LIRC_DRIVER_NAME | |
857 | ": use 'setserial /dev/ttySX uart none'\n"); | |
858 | printk(KERN_WARNING LIRC_DRIVER_NAME | |
859 | ": or compile the serial port driver as module and\n"); | |
860 | printk(KERN_WARNING LIRC_DRIVER_NAME | |
861 | ": make sure this module is loaded first\n"); | |
862 | return -EBUSY; | |
863 | } | |
864 | ||
865 | if (hardware_init_port() < 0) | |
866 | return -EINVAL; | |
867 | ||
868 | /* Initialize pulse/space widths */ | |
869 | init_timing_params(duty_cycle, freq); | |
870 | ||
871 | /* If pin is high, then this must be an active low receiver. */ | |
872 | if (sense == -1) { | |
873 | /* wait 1/2 sec for the power supply */ | |
874 | msleep(500); | |
875 | ||
876 | /* | |
877 | * probe 9 times every 0.04s, collect "votes" for | |
878 | * active high/low | |
879 | */ | |
880 | nlow = 0; | |
881 | nhigh = 0; | |
882 | for (i = 0; i < 9; i++) { | |
883 | if (sinp(UART_MSR) & hardware[type].signal_pin) | |
884 | nlow++; | |
885 | else | |
886 | nhigh++; | |
887 | msleep(40); | |
888 | } | |
889 | sense = (nlow >= nhigh ? 1 : 0); | |
890 | printk(KERN_INFO LIRC_DRIVER_NAME ": auto-detected active " | |
891 | "%s receiver\n", sense ? "low" : "high"); | |
892 | } else | |
893 | printk(KERN_INFO LIRC_DRIVER_NAME ": Manually using active " | |
894 | "%s receiver\n", sense ? "low" : "high"); | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | static int set_use_inc(void *data) | |
900 | { | |
901 | int result; | |
902 | unsigned long flags; | |
903 | ||
904 | /* initialize timestamp */ | |
905 | do_gettimeofday(&lasttv); | |
906 | ||
907 | result = request_irq(irq, irq_handler, | |
908 | IRQF_DISABLED | (share_irq ? IRQF_SHARED : 0), | |
909 | LIRC_DRIVER_NAME, (void *)&hardware); | |
910 | ||
911 | switch (result) { | |
912 | case -EBUSY: | |
913 | printk(KERN_ERR LIRC_DRIVER_NAME ": IRQ %d busy\n", irq); | |
914 | return -EBUSY; | |
915 | case -EINVAL: | |
916 | printk(KERN_ERR LIRC_DRIVER_NAME | |
917 | ": Bad irq number or handler\n"); | |
918 | return -EINVAL; | |
919 | default: | |
920 | dprintk("Interrupt %d, port %04x obtained\n", irq, io); | |
921 | break; | |
922 | }; | |
923 | ||
924 | spin_lock_irqsave(&hardware[type].lock, flags); | |
925 | ||
926 | /* Set DLAB 0. */ | |
927 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
928 | ||
929 | soutp(UART_IER, sinp(UART_IER)|UART_IER_MSI); | |
930 | ||
931 | spin_unlock_irqrestore(&hardware[type].lock, flags); | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
936 | static void set_use_dec(void *data) | |
937 | { unsigned long flags; | |
938 | ||
939 | spin_lock_irqsave(&hardware[type].lock, flags); | |
940 | ||
941 | /* Set DLAB 0. */ | |
942 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
943 | ||
944 | /* First of all, disable all interrupts */ | |
945 | soutp(UART_IER, sinp(UART_IER) & | |
946 | (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI))); | |
947 | spin_unlock_irqrestore(&hardware[type].lock, flags); | |
948 | ||
949 | free_irq(irq, (void *)&hardware); | |
950 | ||
951 | dprintk("freed IRQ %d\n", irq); | |
952 | } | |
953 | ||
954 | static ssize_t lirc_write(struct file *file, const char *buf, | |
955 | size_t n, loff_t *ppos) | |
956 | { | |
957 | int i, count; | |
958 | unsigned long flags; | |
959 | long delta = 0; | |
960 | int *wbuf; | |
961 | ||
962 | if (!(hardware[type].features & LIRC_CAN_SEND_PULSE)) | |
963 | return -EBADF; | |
964 | ||
965 | count = n / sizeof(int); | |
966 | if (n % sizeof(int) || count % 2 == 0) | |
967 | return -EINVAL; | |
968 | wbuf = memdup_user(buf, n); | |
969 | if (PTR_ERR(wbuf)) | |
970 | return PTR_ERR(wbuf); | |
971 | spin_lock_irqsave(&hardware[type].lock, flags); | |
972 | if (type == LIRC_IRDEO) { | |
973 | /* DTR, RTS down */ | |
974 | on(); | |
975 | } | |
976 | for (i = 0; i < count; i++) { | |
977 | if (i%2) | |
978 | hardware[type].send_space(wbuf[i] - delta); | |
979 | else | |
980 | delta = hardware[type].send_pulse(wbuf[i]); | |
981 | } | |
982 | off(); | |
983 | spin_unlock_irqrestore(&hardware[type].lock, flags); | |
984 | return n; | |
985 | } | |
986 | ||
987 | static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) | |
988 | { | |
989 | int result; | |
990 | unsigned long value; | |
991 | unsigned int ivalue; | |
992 | ||
993 | switch (cmd) { | |
994 | case LIRC_GET_SEND_MODE: | |
995 | if (!(hardware[type].features&LIRC_CAN_SEND_MASK)) | |
996 | return -ENOIOCTLCMD; | |
997 | ||
998 | result = put_user(LIRC_SEND2MODE | |
999 | (hardware[type].features&LIRC_CAN_SEND_MASK), | |
1000 | (unsigned long *) arg); | |
1001 | if (result) | |
1002 | return result; | |
1003 | break; | |
1004 | ||
1005 | case LIRC_SET_SEND_MODE: | |
1006 | if (!(hardware[type].features&LIRC_CAN_SEND_MASK)) | |
1007 | return -ENOIOCTLCMD; | |
1008 | ||
1009 | result = get_user(value, (unsigned long *) arg); | |
1010 | if (result) | |
1011 | return result; | |
1012 | /* only LIRC_MODE_PULSE supported */ | |
1013 | if (value != LIRC_MODE_PULSE) | |
1014 | return -ENOSYS; | |
1015 | break; | |
1016 | ||
1017 | case LIRC_GET_LENGTH: | |
1018 | return -ENOSYS; | |
1019 | break; | |
1020 | ||
1021 | case LIRC_SET_SEND_DUTY_CYCLE: | |
1022 | dprintk("SET_SEND_DUTY_CYCLE\n"); | |
1023 | if (!(hardware[type].features&LIRC_CAN_SET_SEND_DUTY_CYCLE)) | |
1024 | return -ENOIOCTLCMD; | |
1025 | ||
1026 | result = get_user(ivalue, (unsigned int *) arg); | |
1027 | if (result) | |
1028 | return result; | |
1029 | if (ivalue <= 0 || ivalue > 100) | |
1030 | return -EINVAL; | |
1031 | return init_timing_params(ivalue, freq); | |
1032 | break; | |
1033 | ||
1034 | case LIRC_SET_SEND_CARRIER: | |
1035 | dprintk("SET_SEND_CARRIER\n"); | |
1036 | if (!(hardware[type].features&LIRC_CAN_SET_SEND_CARRIER)) | |
1037 | return -ENOIOCTLCMD; | |
1038 | ||
1039 | result = get_user(ivalue, (unsigned int *) arg); | |
1040 | if (result) | |
1041 | return result; | |
1042 | if (ivalue > 500000 || ivalue < 20000) | |
1043 | return -EINVAL; | |
1044 | return init_timing_params(duty_cycle, ivalue); | |
1045 | break; | |
1046 | ||
1047 | default: | |
1048 | return lirc_dev_fop_ioctl(filep, cmd, arg); | |
1049 | } | |
1050 | return 0; | |
1051 | } | |
1052 | ||
0f9313ad | 1053 | static const struct file_operations lirc_fops = { |
1beef3c1 JW |
1054 | .owner = THIS_MODULE, |
1055 | .write = lirc_write, | |
1056 | .unlocked_ioctl = lirc_ioctl, | |
1057 | .read = lirc_dev_fop_read, | |
1058 | .poll = lirc_dev_fop_poll, | |
1059 | .open = lirc_dev_fop_open, | |
1060 | .release = lirc_dev_fop_close, | |
1061 | }; | |
1062 | ||
1063 | static struct lirc_driver driver = { | |
1064 | .name = LIRC_DRIVER_NAME, | |
1065 | .minor = -1, | |
1066 | .code_length = 1, | |
1067 | .sample_rate = 0, | |
1068 | .data = NULL, | |
1069 | .add_to_buf = NULL, | |
1070 | .rbuf = &rbuf, | |
1071 | .set_use_inc = set_use_inc, | |
1072 | .set_use_dec = set_use_dec, | |
1073 | .fops = &lirc_fops, | |
1074 | .dev = NULL, | |
1075 | .owner = THIS_MODULE, | |
1076 | }; | |
1077 | ||
1078 | static struct platform_device *lirc_serial_dev; | |
1079 | ||
1080 | static int __devinit lirc_serial_probe(struct platform_device *dev) | |
1081 | { | |
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | static int __devexit lirc_serial_remove(struct platform_device *dev) | |
1086 | { | |
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | static int lirc_serial_suspend(struct platform_device *dev, | |
1091 | pm_message_t state) | |
1092 | { | |
1093 | /* Set DLAB 0. */ | |
1094 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
1095 | ||
1096 | /* Disable all interrupts */ | |
1097 | soutp(UART_IER, sinp(UART_IER) & | |
1098 | (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI))); | |
1099 | ||
1100 | /* Clear registers. */ | |
1101 | sinp(UART_LSR); | |
1102 | sinp(UART_RX); | |
1103 | sinp(UART_IIR); | |
1104 | sinp(UART_MSR); | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | /* twisty maze... need a forward-declaration here... */ | |
1110 | static void lirc_serial_exit(void); | |
1111 | ||
1112 | static int lirc_serial_resume(struct platform_device *dev) | |
1113 | { | |
1114 | unsigned long flags; | |
1115 | ||
1116 | if (hardware_init_port() < 0) { | |
1117 | lirc_serial_exit(); | |
1118 | return -EINVAL; | |
1119 | } | |
1120 | ||
1121 | spin_lock_irqsave(&hardware[type].lock, flags); | |
1122 | /* Enable Interrupt */ | |
1123 | do_gettimeofday(&lasttv); | |
1124 | soutp(UART_IER, sinp(UART_IER)|UART_IER_MSI); | |
1125 | off(); | |
1126 | ||
1127 | lirc_buffer_clear(&rbuf); | |
1128 | ||
1129 | spin_unlock_irqrestore(&hardware[type].lock, flags); | |
1130 | ||
1131 | return 0; | |
1132 | } | |
1133 | ||
1134 | static struct platform_driver lirc_serial_driver = { | |
1135 | .probe = lirc_serial_probe, | |
1136 | .remove = __devexit_p(lirc_serial_remove), | |
1137 | .suspend = lirc_serial_suspend, | |
1138 | .resume = lirc_serial_resume, | |
1139 | .driver = { | |
1140 | .name = "lirc_serial", | |
1141 | .owner = THIS_MODULE, | |
1142 | }, | |
1143 | }; | |
1144 | ||
1145 | static int __init lirc_serial_init(void) | |
1146 | { | |
1147 | int result; | |
1148 | ||
1149 | /* Init read buffer. */ | |
1150 | result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN); | |
1151 | if (result < 0) | |
1152 | return -ENOMEM; | |
1153 | ||
1154 | result = platform_driver_register(&lirc_serial_driver); | |
1155 | if (result) { | |
1156 | printk("lirc register returned %d\n", result); | |
1157 | goto exit_buffer_free; | |
1158 | } | |
1159 | ||
1160 | lirc_serial_dev = platform_device_alloc("lirc_serial", 0); | |
1161 | if (!lirc_serial_dev) { | |
1162 | result = -ENOMEM; | |
1163 | goto exit_driver_unregister; | |
1164 | } | |
1165 | ||
1166 | result = platform_device_add(lirc_serial_dev); | |
1167 | if (result) | |
1168 | goto exit_device_put; | |
1169 | ||
1170 | return 0; | |
1171 | ||
1172 | exit_device_put: | |
1173 | platform_device_put(lirc_serial_dev); | |
1174 | exit_driver_unregister: | |
1175 | platform_driver_unregister(&lirc_serial_driver); | |
1176 | exit_buffer_free: | |
1177 | lirc_buffer_free(&rbuf); | |
1178 | return result; | |
1179 | } | |
1180 | ||
1181 | static void lirc_serial_exit(void) | |
1182 | { | |
1183 | platform_device_unregister(lirc_serial_dev); | |
1184 | platform_driver_unregister(&lirc_serial_driver); | |
1185 | lirc_buffer_free(&rbuf); | |
1186 | } | |
1187 | ||
1188 | static int __init lirc_serial_init_module(void) | |
1189 | { | |
1190 | int result; | |
1191 | ||
1192 | result = lirc_serial_init(); | |
1193 | if (result) | |
1194 | return result; | |
1195 | ||
1196 | switch (type) { | |
1197 | case LIRC_HOMEBREW: | |
1198 | case LIRC_IRDEO: | |
1199 | case LIRC_IRDEO_REMOTE: | |
1200 | case LIRC_ANIMAX: | |
1201 | case LIRC_IGOR: | |
1202 | /* if nothing specified, use ttyS0/com1 and irq 4 */ | |
1203 | io = io ? io : 0x3f8; | |
1204 | irq = irq ? irq : 4; | |
1205 | break; | |
1206 | #ifdef CONFIG_LIRC_SERIAL_NSLU2 | |
1207 | case LIRC_NSLU2: | |
1208 | io = io ? io : IRQ_IXP4XX_UART2; | |
1209 | irq = irq ? irq : (IXP4XX_UART2_BASE_VIRT + REG_OFFSET); | |
1210 | iommap = iommap ? iommap : IXP4XX_UART2_BASE_PHYS; | |
1211 | ioshift = ioshift ? ioshift : 2; | |
1212 | break; | |
1213 | #endif | |
1214 | default: | |
1215 | result = -EINVAL; | |
1216 | goto exit_serial_exit; | |
1217 | } | |
1218 | if (!softcarrier) { | |
1219 | switch (type) { | |
1220 | case LIRC_HOMEBREW: | |
1221 | case LIRC_IGOR: | |
1222 | #ifdef CONFIG_LIRC_SERIAL_NSLU2 | |
1223 | case LIRC_NSLU2: | |
1224 | #endif | |
1225 | hardware[type].features &= | |
1226 | ~(LIRC_CAN_SET_SEND_DUTY_CYCLE| | |
1227 | LIRC_CAN_SET_SEND_CARRIER); | |
1228 | break; | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | result = init_port(); | |
1233 | if (result < 0) | |
1234 | goto exit_serial_exit; | |
1235 | driver.features = hardware[type].features; | |
1236 | driver.dev = &lirc_serial_dev->dev; | |
1237 | driver.minor = lirc_register_driver(&driver); | |
1238 | if (driver.minor < 0) { | |
1239 | printk(KERN_ERR LIRC_DRIVER_NAME | |
1240 | ": register_chrdev failed!\n"); | |
1241 | result = -EIO; | |
1242 | goto exit_release; | |
1243 | } | |
1244 | return 0; | |
1245 | exit_release: | |
1246 | release_region(io, 8); | |
1247 | exit_serial_exit: | |
1248 | lirc_serial_exit(); | |
1249 | return result; | |
1250 | } | |
1251 | ||
1252 | static void __exit lirc_serial_exit_module(void) | |
1253 | { | |
1254 | lirc_serial_exit(); | |
1255 | if (iommap != 0) | |
1256 | release_mem_region(iommap, 8 << ioshift); | |
1257 | else | |
1258 | release_region(io, 8); | |
1259 | lirc_unregister_driver(driver.minor); | |
1260 | dprintk("cleaned up module\n"); | |
1261 | } | |
1262 | ||
1263 | ||
1264 | module_init(lirc_serial_init_module); | |
1265 | module_exit(lirc_serial_exit_module); | |
1266 | ||
1267 | MODULE_DESCRIPTION("Infra-red receiver driver for serial ports."); | |
1268 | MODULE_AUTHOR("Ralph Metzler, Trent Piepho, Ben Pfaff, " | |
1269 | "Christoph Bartelmus, Andrei Tanas"); | |
1270 | MODULE_LICENSE("GPL"); | |
1271 | ||
1272 | module_param(type, int, S_IRUGO); | |
1273 | MODULE_PARM_DESC(type, "Hardware type (0 = home-brew, 1 = IRdeo," | |
1274 | " 2 = IRdeo Remote, 3 = AnimaX, 4 = IgorPlug," | |
1275 | " 5 = NSLU2 RX:CTS2/TX:GreenLED)"); | |
1276 | ||
1277 | module_param(io, int, S_IRUGO); | |
1278 | MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)"); | |
1279 | ||
1280 | /* some architectures (e.g. intel xscale) have memory mapped registers */ | |
1281 | module_param(iommap, bool, S_IRUGO); | |
1282 | MODULE_PARM_DESC(iommap, "physical base for memory mapped I/O" | |
1283 | " (0 = no memory mapped io)"); | |
1284 | ||
1285 | /* | |
1286 | * some architectures (e.g. intel xscale) align the 8bit serial registers | |
1287 | * on 32bit word boundaries. | |
1288 | * See linux-kernel/serial/8250.c serial_in()/out() | |
1289 | */ | |
1290 | module_param(ioshift, int, S_IRUGO); | |
1291 | MODULE_PARM_DESC(ioshift, "shift I/O register offset (0 = no shift)"); | |
1292 | ||
1293 | module_param(irq, int, S_IRUGO); | |
1294 | MODULE_PARM_DESC(irq, "Interrupt (4 or 3)"); | |
1295 | ||
1296 | module_param(share_irq, bool, S_IRUGO); | |
1297 | MODULE_PARM_DESC(share_irq, "Share interrupts (0 = off, 1 = on)"); | |
1298 | ||
1299 | module_param(sense, bool, S_IRUGO); | |
1300 | MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit" | |
1301 | " (0 = active high, 1 = active low )"); | |
1302 | ||
1303 | #ifdef CONFIG_LIRC_SERIAL_TRANSMITTER | |
1304 | module_param(txsense, bool, S_IRUGO); | |
1305 | MODULE_PARM_DESC(txsense, "Sense of transmitter circuit" | |
1306 | " (0 = active high, 1 = active low )"); | |
1307 | #endif | |
1308 | ||
1309 | module_param(softcarrier, bool, S_IRUGO); | |
1310 | MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)"); | |
1311 | ||
1312 | module_param(debug, bool, S_IRUGO | S_IWUSR); | |
1313 | MODULE_PARM_DESC(debug, "Enable debugging messages"); |