[deliverable/linux.git] / drivers / staging / media / cxd2099 / cxd2099.c

/*
 * cxd2099.c: Driver for the CXD2099AR Common Interface Controller
 *
 * Copyright (C) 2010-2011 Digital Devices GmbH
 *
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 only, as published by the Free Software Foundation.
 *
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA
 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/i2c.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/io.h>

#include "cxd2099.h"

#define MAX_BUFFER_SIZE 248

struct cxd {
	struct dvb_ca_en50221 en;

	struct i2c_adapter *i2c;
	struct cxd2099_cfg cfg;

	u8     regs[0x23];
	u8     lastaddress;
	u8     clk_reg_f;
	u8     clk_reg_b;
	int    mode;
	int    ready;
	int    dr;
	int    slot_stat;

	u8     amem[1024];
	int    amem_read;

	int    cammode;
	struct mutex lock;
};

static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
			 u8 reg, u8 data)
{
	u8 m[2] = {reg, data};
	struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};

	if (i2c_transfer(adapter, &msg, 1) != 1) {
		dev_err(&adapter->dev,
			"Failed to write to I2C register %02x@%02x!\n",
			reg, adr);
		return -1;
	}
	return 0;
}

static int i2c_write(struct i2c_adapter *adapter, u8 adr,
		     u8 *data, u8 len)
{
	struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};

	if (i2c_transfer(adapter, &msg, 1) != 1) {
		dev_err(&adapter->dev, "Failed to write to I2C!\n");
		return -1;
	}
	return 0;
}

static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
			u8 reg, u8 *val)
{
	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
				   .buf = &reg, .len = 1},
				  {.addr = adr, .flags = I2C_M_RD,
				   .buf = val, .len = 1} };

	if (i2c_transfer(adapter, msgs, 2) != 2) {
		dev_err(&adapter->dev, "error in i2c_read_reg\n");
		return -1;
	}
	return 0;
}

static int i2c_read(struct i2c_adapter *adapter, u8 adr,
		    u8 reg, u8 *data, u8 n)
{
	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
				 .buf = &reg, .len = 1},
				{.addr = adr, .flags = I2C_M_RD,
				 .buf = data, .len = n} };

	if (i2c_transfer(adapter, msgs, 2) != 2) {
		dev_err(&adapter->dev, "error in i2c_read\n");
		return -1;
	}
	return 0;
}

static int read_block(struct cxd *ci, u8 adr, u8 *data, u8 n)
{
	int status;

	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
	if (!status) {
		ci->lastaddress = adr;
		status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n);
	}
	return status;
}

static int read_reg(struct cxd *ci, u8 reg, u8 *val)
{
	return read_block(ci, reg, val, 1);
}


static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
	int status;
	u8 addr[3] = {2, address & 0xff, address >> 8};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status)
		status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
	return status;
}

static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
	int status;
	u8 addr[3] = {2, address & 0xff, address >> 8};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status) {
		u8 buf[256] = {3};
		memcpy(buf+1, data, n);
		status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1);
	}
	return status;
}

static int read_io(struct cxd *ci, u16 address, u8 *val)
{
	int status;
	u8 addr[3] = {2, address & 0xff, address >> 8};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status)
		status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
	return status;
}

static int write_io(struct cxd *ci, u16 address, u8 val)
{
	int status;
	u8 addr[3] = {2, address & 0xff, address >> 8};
	u8 buf[2] = {3, val};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status)
		status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
	return status;
}

#if 0
static int read_io_data(struct cxd *ci, u8 *data, u8 n)
{
	int status;
	u8 addr[3] = { 2, 0, 0 };

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status)
		status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
	return 0;
}

static int write_io_data(struct cxd *ci, u8 *data, u8 n)
{
	int status;
	u8 addr[3] = {2, 0, 0};

	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	if (!status) {
		u8 buf[256] = {3};
		memcpy(buf+1, data, n);
		status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
	}
	return 0;
}
#endif

static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
{
	int status;

	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
	if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
		status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
	ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
	if (!status) {
		ci->lastaddress = reg;
		status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
	}
	if (reg == 0x20)
		ci->regs[reg] &= 0x7f;
	return status;
}

static int write_reg(struct cxd *ci, u8 reg, u8 val)
{
	return write_regm(ci, reg, val, 0xff);
}

#ifdef BUFFER_MODE
static int write_block(struct cxd *ci, u8 adr, u8 *data, int n)
{
	int status;
	u8 buf[256] = {1};

	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
	if (!status) {
		ci->lastaddress = adr;
		memcpy(buf + 1, data, n);
		status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
	}
	return status;
}
#endif

static void set_mode(struct cxd *ci, int mode)
{
	if (mode == ci->mode)
		return;

	switch (mode) {
	case 0x00: /* IO mem */
		write_regm(ci, 0x06, 0x00, 0x07);
		break;
	case 0x01: /* ATT mem */
		write_regm(ci, 0x06, 0x02, 0x07);
		break;
	default:
		break;
	}
	ci->mode = mode;
}

static void cam_mode(struct cxd *ci, int mode)
{
	if (mode == ci->cammode)
		return;

	switch (mode) {
	case 0x00:
		write_regm(ci, 0x20, 0x80, 0x80);
		break;
	case 0x01:
#ifdef BUFFER_MODE
		if (!ci->en.read_data)
			return;
		dev_info(&ci->i2c->dev, "enable cam buffer mode\n");
		/* write_reg(ci, 0x0d, 0x00); */
		/* write_reg(ci, 0x0e, 0x01); */
		write_regm(ci, 0x08, 0x40, 0x40);
		/* read_reg(ci, 0x12, &dummy); */
		write_regm(ci, 0x08, 0x80, 0x80);
#endif
		break;
	default:
		break;
	}
	ci->cammode = mode;
}


static int init(struct cxd *ci)
{
	int status;

	mutex_lock(&ci->lock);
	ci->mode = -1;
	do {
		status = write_reg(ci, 0x00, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x01, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x02, 0x10);
		if (status < 0)
			break;
		status = write_reg(ci, 0x03, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x05, 0xFF);
		if (status < 0)
			break;
		status = write_reg(ci, 0x06, 0x1F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x07, 0x1F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x08, 0x28);
		if (status < 0)
			break;
		status = write_reg(ci, 0x14, 0x20);
		if (status < 0)
			break;

#if 0
		status = write_reg(ci, 0x09, 0x4D); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
		if (status < 0)
			break;
#endif
		status = write_reg(ci, 0x0A, 0xA7); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
		if (status < 0)
			break;

		status = write_reg(ci, 0x0B, 0x33);
		if (status < 0)
			break;
		status = write_reg(ci, 0x0C, 0x33);
		if (status < 0)
			break;

		status = write_regm(ci, 0x14, 0x00, 0x0F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x15, ci->clk_reg_b);
		if (status < 0)
			break;
		status = write_regm(ci, 0x16, 0x00, 0x0F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x17, ci->clk_reg_f);
		if (status < 0)
			break;

		if (ci->cfg.clock_mode) {
			if (ci->cfg.polarity) {
				status = write_reg(ci, 0x09, 0x6f);
				if (status < 0)
					break;
			} else {
				status = write_reg(ci, 0x09, 0x6d);
				if (status < 0)
					break;
			}
			status = write_reg(ci, 0x20, 0x68);
			if (status < 0)
				break;
			status = write_reg(ci, 0x21, 0x00);
			if (status < 0)
				break;
			status = write_reg(ci, 0x22, 0x02);
			if (status < 0)
				break;
		} else {
			if (ci->cfg.polarity) {
				status = write_reg(ci, 0x09, 0x4f);
				if (status < 0)
					break;
			} else {
				status = write_reg(ci, 0x09, 0x4d);
				if (status < 0)
					break;
			}

			status = write_reg(ci, 0x20, 0x28);
			if (status < 0)
				break;
			status = write_reg(ci, 0x21, 0x00);
			if (status < 0)
				break;
			status = write_reg(ci, 0x22, 0x07);
			if (status < 0)
				break;
		}

		status = write_regm(ci, 0x20, 0x80, 0x80);
		if (status < 0)
			break;
		status = write_regm(ci, 0x03, 0x02, 0x02);
		if (status < 0)
			break;
		status = write_reg(ci, 0x01, 0x04);
		if (status < 0)
			break;
		status = write_reg(ci, 0x00, 0x31);
		if (status < 0)
			break;

		/* Put TS in bypass */
		status = write_regm(ci, 0x09, 0x08, 0x08);
		if (status < 0)
			break;
		ci->cammode = -1;
		cam_mode(ci, 0);
	} while (0);
	mutex_unlock(&ci->lock);

	return 0;
}

static int read_attribute_mem(struct dvb_ca_en50221 *ca,
			      int slot, int address)
{
	struct cxd *ci = ca->data;
#if 0
	if (ci->amem_read) {
		if (address <= 0 || address > 1024)
			return -EIO;
		return ci->amem[address];
	}

	mutex_lock(&ci->lock);
	write_regm(ci, 0x06, 0x00, 0x05);
	read_pccard(ci, 0, &ci->amem[0], 128);
	read_pccard(ci, 128, &ci->amem[0], 128);
	read_pccard(ci, 256, &ci->amem[0], 128);
	read_pccard(ci, 384, &ci->amem[0], 128);
	write_regm(ci, 0x06, 0x05, 0x05);
	mutex_unlock(&ci->lock);
	return ci->amem[address];
#else
	u8 val;
	mutex_lock(&ci->lock);
	set_mode(ci, 1);
	read_pccard(ci, address, &val, 1);
	mutex_unlock(&ci->lock);
	/* printk(KERN_INFO "%02x:%02x\n", address,val); */
	return val;
#endif
}

static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
			       int address, u8 value)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	set_mode(ci, 1);
	write_pccard(ci, address, &value, 1);
	mutex_unlock(&ci->lock);
	return 0;
}

static int read_cam_control(struct dvb_ca_en50221 *ca,
			    int slot, u8 address)
{
	struct cxd *ci = ca->data;
	u8 val;

	mutex_lock(&ci->lock);
	set_mode(ci, 0);
	read_io(ci, address, &val);
	mutex_unlock(&ci->lock);
	return val;
}

static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
			     u8 address, u8 value)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	set_mode(ci, 0);
	write_io(ci, address, value);
	mutex_unlock(&ci->lock);
	return 0;
}

static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
#if 0
	write_reg(ci, 0x00, 0x21);
	write_reg(ci, 0x06, 0x1F);
	write_reg(ci, 0x00, 0x31);
#else
#if 0
	write_reg(ci, 0x06, 0x1F);
	write_reg(ci, 0x06, 0x2F);
#else
	cam_mode(ci, 0);
	write_reg(ci, 0x00, 0x21);
	write_reg(ci, 0x06, 0x1F);
	write_reg(ci, 0x00, 0x31);
	write_regm(ci, 0x20, 0x80, 0x80);
	write_reg(ci, 0x03, 0x02);
	ci->ready = 0;
#endif
#endif
	ci->mode = -1;
	{
		int i;
#if 0
		u8 val;
#endif
		for (i = 0; i < 100; i++) {
			msleep(10);
#if 0
			read_reg(ci, 0x06, &val);
			dev_info(&ci->i2c->dev, "%d:%02x\n", i, val);
			if (!(val&0x10))
				break;
#else
			if (ci->ready)
				break;
#endif
		}
	}
	mutex_unlock(&ci->lock);
	/* msleep(500); */
	return 0;
}

static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	dev_info(&ci->i2c->dev, "slot_shutdown\n");
	mutex_lock(&ci->lock);
	write_regm(ci, 0x09, 0x08, 0x08);
	write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
	write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
	ci->mode = -1;
	mutex_unlock(&ci->lock);
	return 0;
}

static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	write_regm(ci, 0x09, 0x00, 0x08);
	set_mode(ci, 0);
#ifdef BUFFER_MODE
	cam_mode(ci, 1);
#endif
	mutex_unlock(&ci->lock);
	return 0;
}


static int campoll(struct cxd *ci)
{
	u8 istat;

	read_reg(ci, 0x04, &istat);
	if (!istat)
		return 0;
	write_reg(ci, 0x05, istat);

	if (istat&0x40) {
		ci->dr = 1;
		dev_info(&ci->i2c->dev, "DR\n");
	}
	if (istat&0x20)
		dev_info(&ci->i2c->dev, "WC\n");

	if (istat&2) {
		u8 slotstat;

		read_reg(ci, 0x01, &slotstat);
		if (!(2&slotstat)) {
			if (!ci->slot_stat) {
				ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
				write_regm(ci, 0x03, 0x08, 0x08);
			}

		} else {
			if (ci->slot_stat) {
				ci->slot_stat = 0;
				write_regm(ci, 0x03, 0x00, 0x08);
				dev_info(&ci->i2c->dev, "NO CAM\n");
				ci->ready = 0;
			}
		}
		if (istat&8 && ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
			ci->ready = 1;
			ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
		}
	}
	return 0;
}


static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
{
	struct cxd *ci = ca->data;
	u8 slotstat;

	mutex_lock(&ci->lock);
	campoll(ci);
	read_reg(ci, 0x01, &slotstat);
	mutex_unlock(&ci->lock);

	return ci->slot_stat;
}

#ifdef BUFFER_MODE
static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
	struct cxd *ci = ca->data;
	u8 msb, lsb;
	u16 len;

	mutex_lock(&ci->lock);
	campoll(ci);
	mutex_unlock(&ci->lock);

	dev_info(&ci->i2c->dev, "read_data\n");
	if (!ci->dr)
		return 0;

	mutex_lock(&ci->lock);
	read_reg(ci, 0x0f, &msb);
	read_reg(ci, 0x10, &lsb);
	len = (msb<<8)|lsb;
	read_block(ci, 0x12, ebuf, len);
	ci->dr = 0;
	mutex_unlock(&ci->lock);

	return len;
}

static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	printk(kern_INFO "write_data %d\n", ecount);
	write_reg(ci, 0x0d, ecount>>8);
	write_reg(ci, 0x0e, ecount&0xff);
	write_block(ci, 0x11, ebuf, ecount);
	mutex_unlock(&ci->lock);
	return ecount;
}
#endif

static struct dvb_ca_en50221 en_templ = {
	.read_attribute_mem  = read_attribute_mem,
	.write_attribute_mem = write_attribute_mem,
	.read_cam_control    = read_cam_control,
	.write_cam_control   = write_cam_control,
	.slot_reset          = slot_reset,
	.slot_shutdown       = slot_shutdown,
	.slot_ts_enable      = slot_ts_enable,
	.poll_slot_status    = poll_slot_status,
#ifdef BUFFER_MODE
	.read_data           = read_data,
	.write_data          = write_data,
#endif

};

struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
				      void *priv,
				      struct i2c_adapter *i2c)
{
	struct cxd *ci;
	u8 val;

	if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
		dev_info(&i2c->dev, "No CXD2099 detected at %02x\n", cfg->adr);
		return NULL;
	}

	ci = kzalloc(sizeof(struct cxd), GFP_KERNEL);
	if (!ci)
		return NULL;

	mutex_init(&ci->lock);
	ci->cfg = *cfg;
	ci->i2c = i2c;
	ci->lastaddress = 0xff;
	ci->clk_reg_b = 0x4a;
	ci->clk_reg_f = 0x1b;

	ci->en = en_templ;
	ci->en.data = ci;
	init(ci);
	dev_info(&i2c->dev, "Attached CXD2099AR at %02x\n", ci->cfg.adr);
	return &ci->en;
}
EXPORT_SYMBOL(cxd2099_attach);

MODULE_DESCRIPTION("cxd2099");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");
Commit	Line	Data
0f0b270f RM	1	/*
	2	* cxd2099.c: Driver for the CXD2099AR Common Interface Controller
	3	*
6eb94193	4	* Copyright (C) 2010-2011 Digital Devices GmbH
0f0b270f RM	5	*
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 only, as published by the Free Software Foundation.
	10	*
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	21	* 02110-1301, USA
	22	* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
	23	*/
	24
0f0b270f RM	25	#include <linux/slab.h>
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/moduleparam.h>
0f0b270f RM	29	#include <linux/i2c.h>
	30	#include <linux/wait.h>
	31	#include <linux/delay.h>
	32	#include <linux/mutex.h>
	33	#include <linux/io.h>
	34
	35	#include "cxd2099.h"
	36
	37	#define MAX_BUFFER_SIZE 248
	38
	39	struct cxd {
	40	struct dvb_ca_en50221 en;
	41
	42	struct i2c_adapter *i2c;
6eb94193 RM	43	struct cxd2099_cfg cfg;
6eb94193 RM	44
0f0b270f RM	45	u8 regs[0x23];
	46	u8 lastaddress;
	47	u8 clk_reg_f;
	48	u8 clk_reg_b;
	49	int mode;
0f0b270f RM	50	int ready;
	51	int dr;
	52	int slot_stat;
	53
	54	u8 amem[1024];
	55	int amem_read;
	56
	57	int cammode;
	58	struct mutex lock;
	59	};
	60
	61	static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
	62	u8 reg, u8 data)
	63	{
	64	u8 m[2] = {reg, data};
	65	struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
	66
	67	if (i2c_transfer(adapter, &msg, 1) != 1) {
011b2aad YT	68	dev_err(&adapter->dev,
	69	"Failed to write to I2C register %02x@%02x!\n",
	70	reg, adr);
0f0b270f RM	71	return -1;
	72	}
	73	return 0;
	74	}
	75
	76	static int i2c_write(struct i2c_adapter *adapter, u8 adr,
	77	u8 *data, u8 len)
	78	{
	79	struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};
	80
	81	if (i2c_transfer(adapter, &msg, 1) != 1) {
011b2aad	82	dev_err(&adapter->dev, "Failed to write to I2C!\n");
0f0b270f RM	83	return -1;
	84	}
	85	return 0;
	86	}
	87
	88	static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
	89	u8 reg, u8 *val)
	90	{
	91	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
6eb94193	92	.buf = &reg, .len = 1},
0f0b270f	93	{.addr = adr, .flags = I2C_M_RD,
9daf9bcc	94	.buf = val, .len = 1} };
0f0b270f RM	95
0f0b270f RM	96	if (i2c_transfer(adapter, msgs, 2) != 2) {
011b2aad	97	dev_err(&adapter->dev, "error in i2c_read_reg\n");
0f0b270f RM	98	return -1;
	99	}
	100	return 0;
	101	}
	102
	103	static int i2c_read(struct i2c_adapter *adapter, u8 adr,
	104	u8 reg, u8 *data, u8 n)
	105	{
	106	struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
6eb94193 RM	107	.buf = &reg, .len = 1},
6eb94193 RM	108	{.addr = adr, .flags = I2C_M_RD,
9daf9bcc	109	.buf = data, .len = n} };
0f0b270f RM	110
0f0b270f RM	111	if (i2c_transfer(adapter, msgs, 2) != 2) {
011b2aad	112	dev_err(&adapter->dev, "error in i2c_read\n");
0f0b270f RM	113	return -1;
	114	}
	115	return 0;
	116	}
	117
	118	static int read_block(struct cxd ci, u8 adr, u8 data, u8 n)
	119	{
	120	int status;
	121
6eb94193	122	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
0f0b270f RM	123	if (!status) {
0f0b270f RM	124	ci->lastaddress = adr;
6eb94193	125	status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n);
0f0b270f RM	126	}
	127	return status;
	128	}
	129
	130	static int read_reg(struct cxd ci, u8 reg, u8 val)
	131	{
	132	return read_block(ci, reg, val, 1);
	133	}
	134
	135
	136	static int read_pccard(struct cxd ci, u16 address, u8 data, u8 n)
	137	{
	138	int status;
6eb94193	139	u8 addr[3] = {2, address & 0xff, address >> 8};
0f0b270f	140
9daf9bcc	141	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
0f0b270f	142	if (!status)
6eb94193	143	status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
0f0b270f RM	144	return status;
	145	}
	146
	147	static int write_pccard(struct cxd ci, u16 address, u8 data, u8 n)
	148	{
	149	int status;
6eb94193	150	u8 addr[3] = {2, address & 0xff, address >> 8};
0f0b270f	151
9daf9bcc	152	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
0f0b270f RM	153	if (!status) {
	154	u8 buf[256] = {3};
	155	memcpy(buf+1, data, n);
6eb94193	156	status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1);
0f0b270f RM	157	}
	158	return status;
	159	}
	160
	161	static int read_io(struct cxd ci, u16 address, u8 val)
	162	{
	163	int status;
6eb94193	164	u8 addr[3] = {2, address & 0xff, address >> 8};
0f0b270f	165
6eb94193	166	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
0f0b270f	167	if (!status)
6eb94193	168	status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
0f0b270f RM	169	return status;
	170	}
	171
	172	static int write_io(struct cxd *ci, u16 address, u8 val)
	173	{
	174	int status;
6eb94193 RM	175	u8 addr[3] = {2, address & 0xff, address >> 8};
6eb94193 RM	176	u8 buf[2] = {3, val};
0f0b270f	177
6eb94193	178	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
0f0b270f	179	if (!status)
6eb94193	180	status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
0f0b270f RM	181	return status;
	182	}
	183
6eb94193 RM	184	#if 0
	185	static int read_io_data(struct cxd ci, u8 data, u8 n)
	186	{
	187	int status;
	188	u8 addr[3] = { 2, 0, 0 };
	189
	190	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	191	if (!status)
	192	status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
	193	return 0;
	194	}
	195
	196	static int write_io_data(struct cxd ci, u8 data, u8 n)
	197	{
	198	int status;
	199	u8 addr[3] = {2, 0, 0};
	200
	201	status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
	202	if (!status) {
	203	u8 buf[256] = {3};
	204	memcpy(buf+1, data, n);
	205	status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
	206	}
	207	return 0;
	208	}
	209	#endif
0f0b270f RM	210
	211	static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
	212	{
	213	int status;
	214
9daf9bcc	215	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
0f0b270f	216	if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
6eb94193 RM	217	status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
6eb94193 RM	218	ci->regs[reg] = (ci->regs[reg] & (~mask)) \| val;
0f0b270f RM	219	if (!status) {
0f0b270f RM	220	ci->lastaddress = reg;
6eb94193	221	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
0f0b270f RM	222	}
	223	if (reg == 0x20)
	224	ci->regs[reg] &= 0x7f;
	225	return status;
	226	}
	227
	228	static int write_reg(struct cxd *ci, u8 reg, u8 val)
	229	{
	230	return write_regm(ci, reg, val, 0xff);
	231	}
	232
	233	#ifdef BUFFER_MODE
	234	static int write_block(struct cxd ci, u8 adr, u8 data, int n)
	235	{
	236	int status;
	237	u8 buf[256] = {1};
	238
6eb94193	239	status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
0f0b270f RM	240	if (!status) {
0f0b270f RM	241	ci->lastaddress = adr;
6eb94193 RM	242	memcpy(buf + 1, data, n);
6eb94193 RM	243	status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
0f0b270f RM	244	}
	245	return status;
	246	}
	247	#endif
	248
	249	static void set_mode(struct cxd *ci, int mode)
	250	{
	251	if (mode == ci->mode)
	252	return;
	253
	254	switch (mode) {
	255	case 0x00: /* IO mem */
	256	write_regm(ci, 0x06, 0x00, 0x07);
	257	break;
	258	case 0x01: /* ATT mem */
	259	write_regm(ci, 0x06, 0x02, 0x07);
	260	break;
	261	default:
	262	break;
	263	}
	264	ci->mode = mode;
	265	}
	266
	267	static void cam_mode(struct cxd *ci, int mode)
	268	{
	269	if (mode == ci->cammode)
	270	return;
	271
	272	switch (mode) {
	273	case 0x00:
	274	write_regm(ci, 0x20, 0x80, 0x80);
	275	break;
	276	case 0x01:
6eb94193 RM	277	#ifdef BUFFER_MODE
	278	if (!ci->en.read_data)
	279	return;
011b2aad	280	dev_info(&ci->i2c->dev, "enable cam buffer mode\n");
0f0b270f RM	281	/* write_reg(ci, 0x0d, 0x00); */
	282	/* write_reg(ci, 0x0e, 0x01); */
	283	write_regm(ci, 0x08, 0x40, 0x40);
	284	/* read_reg(ci, 0x12, &dummy); */
	285	write_regm(ci, 0x08, 0x80, 0x80);
6eb94193	286	#endif
0f0b270f RM	287	break;
	288	default:
	289	break;
	290	}
	291	ci->cammode = mode;
	292	}
	293
	294
	295
0f0b270f RM	296	static int init(struct cxd *ci)
	297	{
	298	int status;
	299
	300	mutex_lock(&ci->lock);
	301	ci->mode = -1;
	302	do {
af070bd6 MCC	303	status = write_reg(ci, 0x00, 0x00);
	304	if (status < 0)
	305	break;
	306	status = write_reg(ci, 0x01, 0x00);
	307	if (status < 0)
	308	break;
	309	status = write_reg(ci, 0x02, 0x10);
	310	if (status < 0)
	311	break;
	312	status = write_reg(ci, 0x03, 0x00);
	313	if (status < 0)
	314	break;
	315	status = write_reg(ci, 0x05, 0xFF);
	316	if (status < 0)
	317	break;
	318	status = write_reg(ci, 0x06, 0x1F);
	319	if (status < 0)
	320	break;
	321	status = write_reg(ci, 0x07, 0x1F);
	322	if (status < 0)
	323	break;
	324	status = write_reg(ci, 0x08, 0x28);
	325	if (status < 0)
	326	break;
	327	status = write_reg(ci, 0x14, 0x20);
	328	if (status < 0)
	329	break;
	330
	331	#if 0
	332	status = write_reg(ci, 0x09, 0x4D); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
	333	if (status < 0)
	334	break;
	335	#endif
	336	status = write_reg(ci, 0x0A, 0xA7); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
	337	if (status < 0)
	338	break;
	339
	340	status = write_reg(ci, 0x0B, 0x33);
	341	if (status < 0)
	342	break;
	343	status = write_reg(ci, 0x0C, 0x33);
	344	if (status < 0)
	345	break;
	346
	347	status = write_regm(ci, 0x14, 0x00, 0x0F);
	348	if (status < 0)
	349	break;
	350	status = write_reg(ci, 0x15, ci->clk_reg_b);
	351	if (status < 0)
	352	break;
	353	status = write_regm(ci, 0x16, 0x00, 0x0F);
	354	if (status < 0)
	355	break;
	356	status = write_reg(ci, 0x17, ci->clk_reg_f);
	357	if (status < 0)
	358	break;
0f0b270f	359
6eb94193 RM	360	if (ci->cfg.clock_mode) {
6eb94193 RM	361	if (ci->cfg.polarity) {
af070bd6 MCC	362	status = write_reg(ci, 0x09, 0x6f);
	363	if (status < 0)
	364	break;
6eb94193	365	} else {
af070bd6 MCC	366	status = write_reg(ci, 0x09, 0x6d);
	367	if (status < 0)
	368	break;
6eb94193	369	}
af070bd6 MCC	370	status = write_reg(ci, 0x20, 0x68);
	371	if (status < 0)
	372	break;
	373	status = write_reg(ci, 0x21, 0x00);
	374	if (status < 0)
	375	break;
	376	status = write_reg(ci, 0x22, 0x02);
	377	if (status < 0)
	378	break;
6eb94193 RM	379	} else {
6eb94193 RM	380	if (ci->cfg.polarity) {
af070bd6 MCC	381	status = write_reg(ci, 0x09, 0x4f);
	382	if (status < 0)
	383	break;
6eb94193	384	} else {
af070bd6 MCC	385	status = write_reg(ci, 0x09, 0x4d);
	386	if (status < 0)
	387	break;
6eb94193	388	}
0f0b270f	389
af070bd6 MCC	390	status = write_reg(ci, 0x20, 0x28);
	391	if (status < 0)
	392	break;
	393	status = write_reg(ci, 0x21, 0x00);
	394	if (status < 0)
	395	break;
	396	status = write_reg(ci, 0x22, 0x07);
	397	if (status < 0)
	398	break;
6eb94193	399	}
0f0b270f	400
af070bd6 MCC	401	status = write_regm(ci, 0x20, 0x80, 0x80);
	402	if (status < 0)
	403	break;
	404	status = write_regm(ci, 0x03, 0x02, 0x02);
	405	if (status < 0)
	406	break;
	407	status = write_reg(ci, 0x01, 0x04);
	408	if (status < 0)
	409	break;
	410	status = write_reg(ci, 0x00, 0x31);
	411	if (status < 0)
	412	break;
0f0b270f	413
6eb94193	414	/* Put TS in bypass */
af070bd6 MCC	415	status = write_regm(ci, 0x09, 0x08, 0x08);
	416	if (status < 0)
	417	break;
0f0b270f	418	ci->cammode = -1;
0f0b270f	419	cam_mode(ci, 0);
0f0b270f RM	420	} while (0);
	421	mutex_unlock(&ci->lock);
	422
	423	return 0;
	424	}
	425
0f0b270f RM	426	static int read_attribute_mem(struct dvb_ca_en50221 *ca,
	427	int slot, int address)
	428	{
	429	struct cxd *ci = ca->data;
6eb94193 RM	430	#if 0
6eb94193 RM	431	if (ci->amem_read) {
9daf9bcc	432	if (address <= 0 \|\| address > 1024)
6eb94193 RM	433	return -EIO;
	434	return ci->amem[address];
	435	}
	436
	437	mutex_lock(&ci->lock);
	438	write_regm(ci, 0x06, 0x00, 0x05);
	439	read_pccard(ci, 0, &ci->amem[0], 128);
	440	read_pccard(ci, 128, &ci->amem[0], 128);
	441	read_pccard(ci, 256, &ci->amem[0], 128);
	442	read_pccard(ci, 384, &ci->amem[0], 128);
	443	write_regm(ci, 0x06, 0x05, 0x05);
	444	mutex_unlock(&ci->lock);
	445	return ci->amem[address];
	446	#else
0f0b270f RM	447	u8 val;
	448	mutex_lock(&ci->lock);
	449	set_mode(ci, 1);
	450	read_pccard(ci, address, &val, 1);
	451	mutex_unlock(&ci->lock);
9daf9bcc	452	/* printk(KERN_INFO "%02x:%02x\n", address,val); */
0f0b270f	453	return val;
6eb94193	454	#endif
0f0b270f RM	455	}
0f0b270f RM	456
0f0b270f RM	457	static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
	458	int address, u8 value)
	459	{
	460	struct cxd *ci = ca->data;
	461
	462	mutex_lock(&ci->lock);
	463	set_mode(ci, 1);
	464	write_pccard(ci, address, &value, 1);
	465	mutex_unlock(&ci->lock);
	466	return 0;
	467	}
	468
	469	static int read_cam_control(struct dvb_ca_en50221 *ca,
	470	int slot, u8 address)
	471	{
	472	struct cxd *ci = ca->data;
	473	u8 val;
	474
	475	mutex_lock(&ci->lock);
	476	set_mode(ci, 0);
	477	read_io(ci, address, &val);
	478	mutex_unlock(&ci->lock);
	479	return val;
	480	}
	481
	482	static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
	483	u8 address, u8 value)
	484	{
	485	struct cxd *ci = ca->data;
	486
	487	mutex_lock(&ci->lock);
	488	set_mode(ci, 0);
	489	write_io(ci, address, value);
	490	mutex_unlock(&ci->lock);
	491	return 0;
	492	}
	493
	494	static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
	495	{
	496	struct cxd *ci = ca->data;
	497
	498	mutex_lock(&ci->lock);
6eb94193 RM	499	#if 0
	500	write_reg(ci, 0x00, 0x21);
	501	write_reg(ci, 0x06, 0x1F);
	502	write_reg(ci, 0x00, 0x31);
	503	#else
	504	#if 0
	505	write_reg(ci, 0x06, 0x1F);
	506	write_reg(ci, 0x06, 0x2F);
	507	#else
0f0b270f RM	508	cam_mode(ci, 0);
	509	write_reg(ci, 0x00, 0x21);
	510	write_reg(ci, 0x06, 0x1F);
	511	write_reg(ci, 0x00, 0x31);
	512	write_regm(ci, 0x20, 0x80, 0x80);
	513	write_reg(ci, 0x03, 0x02);
	514	ci->ready = 0;
6eb94193 RM	515	#endif
6eb94193 RM	516	#endif
0f0b270f RM	517	ci->mode = -1;
	518	{
	519	int i;
6eb94193 RM	520	#if 0
	521	u8 val;
	522	#endif
0f0b270f RM	523	for (i = 0; i < 100; i++) {
0f0b270f RM	524	msleep(10);
6eb94193	525	#if 0
9daf9bcc	526	read_reg(ci, 0x06, &val);
011b2aad	527	dev_info(&ci->i2c->dev, "%d:%02x\n", i, val);
6eb94193 RM	528	if (!(val&0x10))
	529	break;
	530	#else
0f0b270f RM	531	if (ci->ready)
0f0b270f RM	532	break;
6eb94193	533	#endif
0f0b270f RM	534	}
	535	}
	536	mutex_unlock(&ci->lock);
	537	/* msleep(500); */
	538	return 0;
	539	}
	540
	541	static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
	542	{
	543	struct cxd *ci = ca->data;
	544
011b2aad	545	dev_info(&ci->i2c->dev, "slot_shutdown\n");
0f0b270f	546	mutex_lock(&ci->lock);
6eb94193 RM	547	write_regm(ci, 0x09, 0x08, 0x08);
	548	write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
	549	write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
0f0b270f RM	550	ci->mode = -1;
0f0b270f RM	551	mutex_unlock(&ci->lock);
6eb94193	552	return 0;
0f0b270f RM	553	}
	554
	555	static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
	556	{
	557	struct cxd *ci = ca->data;
	558
	559	mutex_lock(&ci->lock);
	560	write_regm(ci, 0x09, 0x00, 0x08);
	561	set_mode(ci, 0);
	562	#ifdef BUFFER_MODE
	563	cam_mode(ci, 1);
	564	#endif
	565	mutex_unlock(&ci->lock);
	566	return 0;
	567	}
	568
	569
	570	static int campoll(struct cxd *ci)
	571	{
	572	u8 istat;
	573
	574	read_reg(ci, 0x04, &istat);
	575	if (!istat)
	576	return 0;
	577	write_reg(ci, 0x05, istat);
	578
	579	if (istat&0x40) {
	580	ci->dr = 1;
011b2aad	581	dev_info(&ci->i2c->dev, "DR\n");
0f0b270f RM	582	}
0f0b270f RM	583	if (istat&0x20)
011b2aad	584	dev_info(&ci->i2c->dev, "WC\n");
0f0b270f RM	585
	586	if (istat&2) {
	587	u8 slotstat;
	588
	589	read_reg(ci, 0x01, &slotstat);
	590	if (!(2&slotstat)) {
	591	if (!ci->slot_stat) {
	592	ci->slot_stat \|= DVB_CA_EN50221_POLL_CAM_PRESENT;
	593	write_regm(ci, 0x03, 0x08, 0x08);
	594	}
	595
	596	} else {
	597	if (ci->slot_stat) {
	598	ci->slot_stat = 0;
	599	write_regm(ci, 0x03, 0x00, 0x08);
011b2aad	600	dev_info(&ci->i2c->dev, "NO CAM\n");
0f0b270f RM	601	ci->ready = 0;
	602	}
	603	}
	604	if (istat&8 && ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
	605	ci->ready = 1;
	606	ci->slot_stat \|= DVB_CA_EN50221_POLL_CAM_READY;
0f0b270f RM	607	}
	608	}
	609	return 0;
	610	}
	611
	612
	613	static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
	614	{
	615	struct cxd *ci = ca->data;
	616	u8 slotstat;
	617
	618	mutex_lock(&ci->lock);
	619	campoll(ci);
	620	read_reg(ci, 0x01, &slotstat);
	621	mutex_unlock(&ci->lock);
	622
	623	return ci->slot_stat;
	624	}
	625
	626	#ifdef BUFFER_MODE
	627	static int read_data(struct dvb_ca_en50221 ca, int slot, u8 ebuf, int ecount)
	628	{
	629	struct cxd *ci = ca->data;
	630	u8 msb, lsb;
	631	u16 len;
	632
	633	mutex_lock(&ci->lock);
	634	campoll(ci);
	635	mutex_unlock(&ci->lock);
	636
011b2aad	637	dev_info(&ci->i2c->dev, "read_data\n");
0f0b270f RM	638	if (!ci->dr)
	639	return 0;
	640
	641	mutex_lock(&ci->lock);
	642	read_reg(ci, 0x0f, &msb);
	643	read_reg(ci, 0x10, &lsb);
	644	len = (msb<<8)\|lsb;
	645	read_block(ci, 0x12, ebuf, len);
	646	ci->dr = 0;
	647	mutex_unlock(&ci->lock);
	648
	649	return len;
	650	}
	651
	652	static int write_data(struct dvb_ca_en50221 ca, int slot, u8 ebuf, int ecount)
	653	{
	654	struct cxd *ci = ca->data;
	655
	656	mutex_lock(&ci->lock);
9daf9bcc	657	printk(kern_INFO "write_data %d\n", ecount);
0f0b270f RM	658	write_reg(ci, 0x0d, ecount>>8);
	659	write_reg(ci, 0x0e, ecount&0xff);
	660	write_block(ci, 0x11, ebuf, ecount);
	661	mutex_unlock(&ci->lock);
	662	return ecount;
	663	}
	664	#endif
	665
	666	static struct dvb_ca_en50221 en_templ = {
	667	.read_attribute_mem = read_attribute_mem,
	668	.write_attribute_mem = write_attribute_mem,
	669	.read_cam_control = read_cam_control,
	670	.write_cam_control = write_cam_control,
	671	.slot_reset = slot_reset,
	672	.slot_shutdown = slot_shutdown,
	673	.slot_ts_enable = slot_ts_enable,
	674	.poll_slot_status = poll_slot_status,
	675	#ifdef BUFFER_MODE
	676	.read_data = read_data,
	677	.write_data = write_data,
	678	#endif
	679
	680	};
	681
6eb94193 RM	682	struct dvb_ca_en50221 cxd2099_attach(struct cxd2099_cfg cfg,
6eb94193 RM	683	void *priv,
0f0b270f RM	684	struct i2c_adapter *i2c)
0f0b270f RM	685	{
4aff355c	686	struct cxd *ci;
0f0b270f RM	687	u8 val;
0f0b270f RM	688
9daf9bcc	689	if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
011b2aad	690	dev_info(&i2c->dev, "No CXD2099 detected at %02x\n", cfg->adr);
4aff355c	691	return NULL;
0f0b270f RM	692	}
0f0b270f RM	693
ada3678c	694	ci = kzalloc(sizeof(struct cxd), GFP_KERNEL);
0f0b270f	695	if (!ci)
4aff355c	696	return NULL;
0f0b270f RM	697
0f0b270f RM	698	mutex_init(&ci->lock);
8d9b2584	699	ci->cfg = *cfg;
0f0b270f	700	ci->i2c = i2c;
0f0b270f RM	701	ci->lastaddress = 0xff;
	702	ci->clk_reg_b = 0x4a;
	703	ci->clk_reg_f = 0x1b;
0f0b270f	704
8d9b2584	705	ci->en = en_templ;
0f0b270f RM	706	ci->en.data = ci;
0f0b270f RM	707	init(ci);
011b2aad	708	dev_info(&i2c->dev, "Attached CXD2099AR at %02x\n", ci->cfg.adr);
0f0b270f RM	709	return &ci->en;
	710	}
	711	EXPORT_SYMBOL(cxd2099_attach);
	712
	713	MODULE_DESCRIPTION("cxd2099");
6eb94193	714	MODULE_AUTHOR("Ralph Metzler");
0f0b270f	715	MODULE_LICENSE("GPL");