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717f4a5f MM |
1 | /*************************************************************************** |
2 | * Copyright (C) 2006-2010 by Marin Mitov * | |
3 | * mitov@issp.bas.bg * | |
4 | * * | |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
15 | * You should have received a copy of the GNU General Public License * | |
16 | * along with this program; if not, write to the * | |
17 | * Free Software Foundation, Inc., * | |
18 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
19 | ***************************************************************************/ | |
20 | ||
99c97852 | 21 | #include <linux/module.h> |
d42bffb8 MM |
22 | #include <linux/version.h> |
23 | #include <linux/stringify.h> | |
7ec21181 | 24 | #include <linux/delay.h> |
d42bffb8 | 25 | #include <linux/kthread.h> |
dac95cb8 | 26 | #include <linux/slab.h> |
a57941c2 MM |
27 | #include <media/v4l2-dev.h> |
28 | #include <media/v4l2-ioctl.h> | |
8ded351a | 29 | #include <media/videobuf2-dma-contig.h> |
d42bffb8 MM |
30 | |
31 | #include "dt3155v4l.h" | |
d42bffb8 MM |
32 | |
33 | #define DT3155_VENDOR_ID 0x8086 | |
34 | #define DT3155_DEVICE_ID 0x1223 | |
35 | ||
a57941c2 MM |
36 | /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */ |
37 | #define DT3155_CHUNK_SIZE (1U << 22) | |
38 | ||
39 | #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN) | |
40 | ||
41 | #define DT3155_BUF_SIZE (768 * 576) | |
42 | ||
8ded351a MM |
43 | #ifdef CONFIG_DT3155_STREAMING |
44 | #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING | |
45 | #else | |
46 | #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE | |
47 | #endif | |
48 | ||
d42bffb8 MM |
49 | /* global initializers (for all boards) */ |
50 | #ifdef CONFIG_DT3155_CCIR | |
51 | static const u8 csr2_init = VT_50HZ; | |
52 | #define DT3155_CURRENT_NORM V4L2_STD_625_50 | |
53 | static const unsigned int img_width = 768; | |
54 | static const unsigned int img_height = 576; | |
55 | static const unsigned int frames_per_sec = 25; | |
56 | static const struct v4l2_fmtdesc frame_std[] = { | |
57 | { | |
58 | .index = 0, | |
59 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
60 | .flags = 0, | |
61 | .description = "CCIR/50Hz 8 bits gray", | |
62 | .pixelformat = V4L2_PIX_FMT_GREY, | |
63 | }, | |
64 | }; | |
65 | #else | |
66 | static const u8 csr2_init = VT_60HZ; | |
67 | #define DT3155_CURRENT_NORM V4L2_STD_525_60 | |
68 | static const unsigned int img_width = 640; | |
69 | static const unsigned int img_height = 480; | |
70 | static const unsigned int frames_per_sec = 30; | |
71 | static const struct v4l2_fmtdesc frame_std[] = { | |
72 | { | |
73 | .index = 0, | |
74 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
75 | .flags = 0, | |
76 | .description = "RS-170/60Hz 8 bits gray", | |
77 | .pixelformat = V4L2_PIX_FMT_GREY, | |
78 | }, | |
79 | }; | |
80 | #endif | |
81 | ||
82 | #define NUM_OF_FORMATS ARRAY_SIZE(frame_std) | |
83 | ||
84 | static u8 config_init = ACQ_MODE_EVEN; | |
85 | ||
86 | /** | |
87 | * read_i2c_reg - reads an internal i2c register | |
88 | * | |
89 | * @addr: dt3155 mmio base address | |
90 | * @index: index (internal address) of register to read | |
91 | * @data: pointer to byte the read data will be placed in | |
92 | * | |
93 | * returns: zero on success or error code | |
94 | * | |
95 | * This function starts reading the specified (by index) register | |
96 | * and busy waits for the process to finish. The result is placed | |
97 | * in a byte pointed by data. | |
98 | */ | |
99 | static int | |
2342df0e | 100 | read_i2c_reg(void __iomem *addr, u8 index, u8 *data) |
d42bffb8 MM |
101 | { |
102 | u32 tmp = index; | |
103 | ||
104 | iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2); | |
105 | mmiowb(); | |
106 | udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
107 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
108 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 MM |
109 | tmp = ioread32(addr + IIC_CSR1); |
110 | if (tmp & DIRECT_ABORT) { | |
d42bffb8 MM |
111 | /* reset DIRECT_ABORT bit */ |
112 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 113 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 MM |
114 | } |
115 | *data = tmp>>24; | |
116 | return 0; | |
117 | } | |
118 | ||
119 | /** | |
120 | * write_i2c_reg - writes to an internal i2c register | |
121 | * | |
122 | * @addr: dt3155 mmio base address | |
123 | * @index: index (internal address) of register to read | |
124 | * @data: data to be written | |
125 | * | |
126 | * returns: zero on success or error code | |
127 | * | |
128 | * This function starts writting the specified (by index) register | |
129 | * and busy waits for the process to finish. | |
130 | */ | |
131 | static int | |
2342df0e | 132 | write_i2c_reg(void __iomem *addr, u8 index, u8 data) |
d42bffb8 MM |
133 | { |
134 | u32 tmp = index; | |
135 | ||
136 | iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2); | |
137 | mmiowb(); | |
138 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
139 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
140 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 | 141 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { |
d42bffb8 MM |
142 | /* reset DIRECT_ABORT bit */ |
143 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 144 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 MM |
145 | } |
146 | return 0; | |
147 | } | |
148 | ||
149 | /** | |
150 | * write_i2c_reg_nowait - writes to an internal i2c register | |
151 | * | |
152 | * @addr: dt3155 mmio base address | |
153 | * @index: index (internal address) of register to read | |
154 | * @data: data to be written | |
155 | * | |
156 | * This function starts writting the specified (by index) register | |
157 | * and then returns. | |
158 | */ | |
2342df0e | 159 | static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data) |
d42bffb8 MM |
160 | { |
161 | u32 tmp = index; | |
162 | ||
163 | iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2); | |
164 | mmiowb(); | |
165 | } | |
166 | ||
167 | /** | |
168 | * wait_i2c_reg - waits the read/write to finish | |
169 | * | |
170 | * @addr: dt3155 mmio base address | |
171 | * | |
172 | * returns: zero on success or error code | |
173 | * | |
174 | * This function waits reading/writting to finish. | |
175 | */ | |
2342df0e | 176 | static int wait_i2c_reg(void __iomem *addr) |
d42bffb8 MM |
177 | { |
178 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) | |
179 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ | |
c94a2e47 HS |
180 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
181 | return -EIO; /* error: NEW_CYCLE not cleared */ | |
d42bffb8 | 182 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { |
d42bffb8 MM |
183 | /* reset DIRECT_ABORT bit */ |
184 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
c94a2e47 | 185 | return -EIO; /* error: DIRECT_ABORT set */ |
d42bffb8 MM |
186 | } |
187 | return 0; | |
188 | } | |
189 | ||
d42bffb8 MM |
190 | static int |
191 | dt3155_start_acq(struct dt3155_priv *pd) | |
192 | { | |
8ded351a | 193 | struct vb2_buffer *vb = pd->curr_buf; |
d42bffb8 MM |
194 | dma_addr_t dma_addr; |
195 | ||
1f28291c | 196 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); |
d42bffb8 | 197 | iowrite32(dma_addr, pd->regs + EVEN_DMA_START); |
8ded351a MM |
198 | iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START); |
199 | iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE); | |
200 | iowrite32(img_width, pd->regs + ODD_DMA_STRIDE); | |
d42bffb8 MM |
201 | /* enable interrupts, clear all irq flags */ |
202 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | | |
203 | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); | |
204 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | | |
205 | FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, | |
206 | pd->regs + CSR1); | |
207 | wait_i2c_reg(pd->regs); | |
208 | write_i2c_reg(pd->regs, CONFIG, pd->config); | |
209 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); | |
210 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); | |
211 | ||
212 | /* start the board */ | |
213 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); | |
214 | return 0; /* success */ | |
215 | } | |
216 | ||
8ded351a MM |
217 | /* |
218 | * driver-specific callbacks (vb2_ops) | |
219 | */ | |
d42bffb8 | 220 | static int |
527f18be DC |
221 | dt3155_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, |
222 | unsigned int *num_buffers, unsigned int *num_planes, | |
223 | unsigned int sizes[], void *alloc_ctxs[]) | |
224 | ||
8ded351a MM |
225 | { |
226 | struct dt3155_priv *pd = vb2_get_drv_priv(q); | |
227 | void *ret; | |
228 | ||
229 | if (*num_buffers == 0) | |
230 | *num_buffers = 1; | |
231 | *num_planes = 1; | |
232 | sizes[0] = img_width * img_height; | |
233 | if (pd->q->alloc_ctx[0]) | |
234 | return 0; | |
235 | ret = vb2_dma_contig_init_ctx(&pd->pdev->dev); | |
236 | if (IS_ERR(ret)) | |
237 | return PTR_ERR(ret); | |
238 | pd->q->alloc_ctx[0] = ret; | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static void | |
243 | dt3155_wait_prepare(struct vb2_queue *q) | |
d42bffb8 | 244 | { |
8ded351a | 245 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
d42bffb8 | 246 | |
8ded351a MM |
247 | mutex_unlock(pd->vdev->lock); |
248 | } | |
d42bffb8 | 249 | |
8ded351a MM |
250 | static void |
251 | dt3155_wait_finish(struct vb2_queue *q) | |
252 | { | |
253 | struct dt3155_priv *pd = vb2_get_drv_priv(q); | |
254 | ||
255 | mutex_lock(pd->vdev->lock); | |
d42bffb8 MM |
256 | } |
257 | ||
d42bffb8 | 258 | static int |
8ded351a | 259 | dt3155_buf_prepare(struct vb2_buffer *vb) |
d42bffb8 | 260 | { |
8ded351a | 261 | vb2_set_plane_payload(vb, 0, img_width * img_height); |
d42bffb8 MM |
262 | return 0; |
263 | } | |
264 | ||
8ded351a MM |
265 | static int |
266 | dt3155_stop_streaming(struct vb2_queue *q) | |
d42bffb8 | 267 | { |
8ded351a MM |
268 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
269 | struct vb2_buffer *vb; | |
270 | ||
271 | spin_lock_irq(&pd->lock); | |
272 | while (!list_empty(&pd->dmaq)) { | |
273 | vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry); | |
274 | list_del(&vb->done_entry); | |
275 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); | |
276 | } | |
277 | spin_unlock_irq(&pd->lock); | |
278 | msleep(45); /* irq hendler will stop the hardware */ | |
279 | return 0; | |
d42bffb8 MM |
280 | } |
281 | ||
d42bffb8 | 282 | static void |
8ded351a | 283 | dt3155_buf_queue(struct vb2_buffer *vb) |
d42bffb8 | 284 | { |
8ded351a MM |
285 | struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); |
286 | ||
287 | /* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */ | |
288 | spin_lock_irq(&pd->lock); | |
289 | if (pd->curr_buf) | |
290 | list_add_tail(&vb->done_entry, &pd->dmaq); | |
291 | else { | |
292 | pd->curr_buf = vb; | |
293 | dt3155_start_acq(pd); | |
294 | } | |
295 | spin_unlock_irq(&pd->lock); | |
d42bffb8 | 296 | } |
8ded351a MM |
297 | /* |
298 | * end driver-specific callbacks | |
299 | */ | |
d42bffb8 | 300 | |
8ded351a MM |
301 | const struct vb2_ops q_ops = { |
302 | .queue_setup = dt3155_queue_setup, | |
303 | .wait_prepare = dt3155_wait_prepare, | |
304 | .wait_finish = dt3155_wait_finish, | |
d42bffb8 | 305 | .buf_prepare = dt3155_buf_prepare, |
8ded351a | 306 | .stop_streaming = dt3155_stop_streaming, |
d42bffb8 | 307 | .buf_queue = dt3155_buf_queue, |
d42bffb8 MM |
308 | }; |
309 | ||
310 | static irqreturn_t | |
311 | dt3155_irq_handler_even(int irq, void *dev_id) | |
312 | { | |
313 | struct dt3155_priv *ipd = dev_id; | |
8ded351a | 314 | struct vb2_buffer *ivb; |
d42bffb8 MM |
315 | dma_addr_t dma_addr; |
316 | u32 tmp; | |
317 | ||
318 | tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD); | |
319 | if (!tmp) | |
320 | return IRQ_NONE; /* not our irq */ | |
321 | if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) { | |
322 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START, | |
323 | ipd->regs + INT_CSR); | |
324 | ipd->field_count++; | |
325 | return IRQ_HANDLED; /* start of field irq */ | |
326 | } | |
c94a2e47 | 327 | if ((tmp & FLD_START) && (tmp & FLD_END_ODD)) |
5ba321cf | 328 | ipd->stats.start_before_end++; |
d42bffb8 MM |
329 | /* check for corrupted fields */ |
330 | /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */ | |
331 | /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */ | |
332 | tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); | |
333 | if (tmp) { | |
c94a2e47 | 334 | ipd->stats.corrupted_fields++; |
d42bffb8 MM |
335 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
336 | FLD_DN_ODD | FLD_DN_EVEN | | |
337 | CAP_CONT_EVEN | CAP_CONT_ODD, | |
338 | ipd->regs + CSR1); | |
339 | mmiowb(); | |
340 | } | |
341 | ||
342 | spin_lock(&ipd->lock); | |
8ded351a MM |
343 | if (ipd->curr_buf) { |
344 | do_gettimeofday(&ipd->curr_buf->v4l2_buf.timestamp); | |
345 | ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1; | |
346 | vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE); | |
347 | } | |
348 | ||
349 | if (!ipd->q->streaming || list_empty(&ipd->dmaq)) | |
d42bffb8 | 350 | goto stop_dma; |
8ded351a MM |
351 | ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry); |
352 | list_del(&ivb->done_entry); | |
353 | ipd->curr_buf = ivb; | |
1f28291c | 354 | dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0); |
d42bffb8 | 355 | iowrite32(dma_addr, ipd->regs + EVEN_DMA_START); |
8ded351a MM |
356 | iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START); |
357 | iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE); | |
358 | iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE); | |
d42bffb8 MM |
359 | mmiowb(); |
360 | /* enable interrupts, clear all irq flags */ | |
361 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | | |
362 | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); | |
363 | spin_unlock(&ipd->lock); | |
364 | return IRQ_HANDLED; | |
365 | ||
366 | stop_dma: | |
367 | ipd->curr_buf = NULL; | |
368 | /* stop the board */ | |
369 | write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2); | |
8ded351a MM |
370 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
371 | FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1); | |
d42bffb8 MM |
372 | /* disable interrupts, clear all irq flags */ |
373 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); | |
374 | spin_unlock(&ipd->lock); | |
375 | return IRQ_HANDLED; | |
376 | } | |
377 | ||
d42bffb8 MM |
378 | static int |
379 | dt3155_open(struct file *filp) | |
380 | { | |
381 | int ret = 0; | |
382 | struct dt3155_priv *pd = video_drvdata(filp); | |
383 | ||
d42bffb8 | 384 | if (!pd->users) { |
8ded351a MM |
385 | pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL); |
386 | if (!pd->q) { | |
d42bffb8 MM |
387 | ret = -ENOMEM; |
388 | goto err_alloc_queue; | |
389 | } | |
8ded351a MM |
390 | pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
391 | pd->q->io_modes = VB2_READ | VB2_MMAP; | |
392 | pd->q->ops = &q_ops; | |
393 | pd->q->mem_ops = &vb2_dma_contig_memops; | |
394 | pd->q->drv_priv = pd; | |
395 | pd->curr_buf = NULL; | |
396 | pd->field_count = 0; | |
397 | vb2_queue_init(pd->q); /* cannot fail */ | |
398 | INIT_LIST_HEAD(&pd->dmaq); | |
399 | spin_lock_init(&pd->lock); | |
d42bffb8 MM |
400 | /* disable all irqs, clear all irq flags */ |
401 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, | |
402 | pd->regs + INT_CSR); | |
17078647 | 403 | ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even, |
d42bffb8 | 404 | IRQF_SHARED, DT3155_NAME, pd); |
c94a2e47 | 405 | if (ret) |
d42bffb8 | 406 | goto err_request_irq; |
d42bffb8 MM |
407 | } |
408 | pd->users++; | |
8ded351a | 409 | return 0; /* success */ |
d42bffb8 | 410 | err_request_irq: |
8ded351a MM |
411 | kfree(pd->q); |
412 | pd->q = NULL; | |
d42bffb8 | 413 | err_alloc_queue: |
d42bffb8 MM |
414 | return ret; |
415 | } | |
416 | ||
417 | static int | |
418 | dt3155_release(struct file *filp) | |
419 | { | |
420 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 421 | |
d42bffb8 MM |
422 | pd->users--; |
423 | BUG_ON(pd->users < 0); | |
d42bffb8 | 424 | if (!pd->users) { |
8ded351a | 425 | vb2_queue_release(pd->q); |
d42bffb8 | 426 | free_irq(pd->pdev->irq, pd); |
8ded351a MM |
427 | if (pd->q->alloc_ctx[0]) |
428 | vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]); | |
429 | kfree(pd->q); | |
430 | pd->q = NULL; | |
d42bffb8 | 431 | } |
8ded351a | 432 | return 0; |
d42bffb8 MM |
433 | } |
434 | ||
435 | static ssize_t | |
436 | dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff) | |
437 | { | |
438 | struct dt3155_priv *pd = video_drvdata(filp); | |
8ded351a MM |
439 | |
440 | return vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK); | |
d42bffb8 MM |
441 | } |
442 | ||
443 | static unsigned int | |
444 | dt3155_poll(struct file *filp, struct poll_table_struct *polltbl) | |
445 | { | |
446 | struct dt3155_priv *pd = video_drvdata(filp); | |
447 | ||
8ded351a | 448 | return vb2_poll(pd->q, filp, polltbl); |
d42bffb8 MM |
449 | } |
450 | ||
451 | static int | |
452 | dt3155_mmap(struct file *filp, struct vm_area_struct *vma) | |
453 | { | |
454 | struct dt3155_priv *pd = video_drvdata(filp); | |
455 | ||
8ded351a | 456 | return vb2_mmap(pd->q, vma); |
d42bffb8 MM |
457 | } |
458 | ||
459 | static const struct v4l2_file_operations dt3155_fops = { | |
460 | .owner = THIS_MODULE, | |
461 | .open = dt3155_open, | |
462 | .release = dt3155_release, | |
463 | .read = dt3155_read, | |
464 | .poll = dt3155_poll, | |
465 | .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ | |
466 | .mmap = dt3155_mmap, | |
467 | }; | |
468 | ||
469 | static int | |
470 | dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type) | |
471 | { | |
472 | struct dt3155_priv *pd = video_drvdata(filp); | |
8ded351a MM |
473 | |
474 | return vb2_streamon(pd->q, type); | |
d42bffb8 MM |
475 | } |
476 | ||
477 | static int | |
478 | dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type) | |
479 | { | |
480 | struct dt3155_priv *pd = video_drvdata(filp); | |
8ded351a MM |
481 | |
482 | return vb2_streamoff(pd->q, type); | |
d42bffb8 MM |
483 | } |
484 | ||
485 | static int | |
486 | dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap) | |
487 | { | |
488 | struct dt3155_priv *pd = video_drvdata(filp); | |
489 | ||
490 | strcpy(cap->driver, DT3155_NAME); | |
491 | strcpy(cap->card, DT3155_NAME " frame grabber"); | |
492 | sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev)); | |
493 | cap->version = | |
494 | KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT); | |
495 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | | |
8ded351a | 496 | DT3155_CAPTURE_METHOD; |
d42bffb8 MM |
497 | return 0; |
498 | } | |
499 | ||
500 | static int | |
501 | dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f) | |
502 | { | |
503 | if (f->index >= NUM_OF_FORMATS) | |
504 | return -EINVAL; | |
505 | *f = frame_std[f->index]; | |
506 | return 0; | |
507 | } | |
508 | ||
509 | static int | |
510 | dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
511 | { | |
512 | if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
513 | return -EINVAL; | |
514 | f->fmt.pix.width = img_width; | |
515 | f->fmt.pix.height = img_height; | |
516 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY; | |
517 | f->fmt.pix.field = V4L2_FIELD_NONE; | |
518 | f->fmt.pix.bytesperline = f->fmt.pix.width; | |
519 | f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height; | |
520 | f->fmt.pix.colorspace = 0; | |
521 | f->fmt.pix.priv = 0; | |
522 | return 0; | |
523 | } | |
524 | ||
525 | static int | |
526 | dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
527 | { | |
528 | if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
529 | return -EINVAL; | |
530 | if (f->fmt.pix.width == img_width && | |
531 | f->fmt.pix.height == img_height && | |
532 | f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY && | |
533 | f->fmt.pix.field == V4L2_FIELD_NONE && | |
534 | f->fmt.pix.bytesperline == f->fmt.pix.width && | |
535 | f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height) | |
536 | return 0; | |
537 | else | |
538 | return -EINVAL; | |
539 | } | |
540 | ||
541 | static int | |
542 | dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
543 | { | |
8ded351a | 544 | return dt3155_ioc_g_fmt_vid_cap(filp, p, f); |
d42bffb8 MM |
545 | } |
546 | ||
547 | static int | |
548 | dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b) | |
549 | { | |
550 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 551 | |
8ded351a | 552 | return vb2_reqbufs(pd->q, b); |
d42bffb8 MM |
553 | } |
554 | ||
555 | static int | |
556 | dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
557 | { | |
558 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 559 | |
8ded351a | 560 | return vb2_querybuf(pd->q, b); |
d42bffb8 MM |
561 | } |
562 | ||
563 | static int | |
564 | dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
565 | { | |
566 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 567 | |
8ded351a | 568 | return vb2_qbuf(pd->q, b); |
d42bffb8 MM |
569 | } |
570 | ||
571 | static int | |
572 | dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
573 | { | |
574 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 575 | |
8ded351a | 576 | return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK); |
d42bffb8 MM |
577 | } |
578 | ||
579 | static int | |
580 | dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm) | |
581 | { | |
582 | *norm = DT3155_CURRENT_NORM; | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static int | |
587 | dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm) | |
588 | { | |
589 | *norm = DT3155_CURRENT_NORM; | |
590 | return 0; | |
591 | } | |
592 | ||
593 | static int | |
594 | dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id *norm) | |
595 | { | |
596 | if (*norm & DT3155_CURRENT_NORM) | |
597 | return 0; | |
598 | return -EINVAL; | |
599 | } | |
600 | ||
601 | static int | |
602 | dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input) | |
603 | { | |
604 | if (input->index) | |
605 | return -EINVAL; | |
606 | strcpy(input->name, "Coax in"); | |
607 | input->type = V4L2_INPUT_TYPE_CAMERA; | |
fdd2d934 MM |
608 | /* |
609 | * FIXME: input->std = 0 according to v4l2 API | |
610 | * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD | |
611 | * should return -EINVAL | |
612 | */ | |
613 | input->std = DT3155_CURRENT_NORM; | |
d42bffb8 MM |
614 | input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */ |
615 | return 0; | |
616 | } | |
617 | ||
618 | static int | |
619 | dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i) | |
620 | { | |
621 | *i = 0; | |
622 | return 0; | |
623 | } | |
624 | ||
625 | static int | |
626 | dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i) | |
627 | { | |
628 | if (i) | |
629 | return -EINVAL; | |
630 | return 0; | |
631 | } | |
632 | ||
633 | static int | |
634 | dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms) | |
635 | { | |
636 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
637 | return -EINVAL; | |
638 | parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; | |
639 | parms->parm.capture.capturemode = 0; | |
640 | parms->parm.capture.timeperframe.numerator = 1001; | |
641 | parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000; | |
642 | parms->parm.capture.extendedmode = 0; | |
fdd2d934 | 643 | parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */ |
d42bffb8 MM |
644 | return 0; |
645 | } | |
646 | ||
647 | static int | |
648 | dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms) | |
649 | { | |
650 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
651 | return -EINVAL; | |
652 | parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; | |
653 | parms->parm.capture.capturemode = 0; | |
654 | parms->parm.capture.timeperframe.numerator = 1001; | |
655 | parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000; | |
656 | parms->parm.capture.extendedmode = 0; | |
fdd2d934 | 657 | parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */ |
d42bffb8 MM |
658 | return 0; |
659 | } | |
660 | ||
661 | static const struct v4l2_ioctl_ops dt3155_ioctl_ops = { | |
662 | .vidioc_streamon = dt3155_ioc_streamon, | |
663 | .vidioc_streamoff = dt3155_ioc_streamoff, | |
664 | .vidioc_querycap = dt3155_ioc_querycap, | |
665 | /* | |
666 | .vidioc_g_priority = dt3155_ioc_g_priority, | |
667 | .vidioc_s_priority = dt3155_ioc_s_priority, | |
668 | */ | |
669 | .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap, | |
670 | .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap, | |
671 | .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap, | |
672 | .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap, | |
673 | .vidioc_reqbufs = dt3155_ioc_reqbufs, | |
674 | .vidioc_querybuf = dt3155_ioc_querybuf, | |
675 | .vidioc_qbuf = dt3155_ioc_qbuf, | |
676 | .vidioc_dqbuf = dt3155_ioc_dqbuf, | |
677 | .vidioc_querystd = dt3155_ioc_querystd, | |
678 | .vidioc_g_std = dt3155_ioc_g_std, | |
679 | .vidioc_s_std = dt3155_ioc_s_std, | |
680 | .vidioc_enum_input = dt3155_ioc_enum_input, | |
681 | .vidioc_g_input = dt3155_ioc_g_input, | |
682 | .vidioc_s_input = dt3155_ioc_s_input, | |
683 | /* | |
684 | .vidioc_queryctrl = dt3155_ioc_queryctrl, | |
685 | .vidioc_g_ctrl = dt3155_ioc_g_ctrl, | |
686 | .vidioc_s_ctrl = dt3155_ioc_s_ctrl, | |
687 | .vidioc_querymenu = dt3155_ioc_querymenu, | |
688 | .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls, | |
689 | .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls, | |
690 | */ | |
691 | .vidioc_g_parm = dt3155_ioc_g_parm, | |
692 | .vidioc_s_parm = dt3155_ioc_s_parm, | |
693 | /* | |
694 | .vidioc_cropcap = dt3155_ioc_cropcap, | |
695 | .vidioc_g_crop = dt3155_ioc_g_crop, | |
696 | .vidioc_s_crop = dt3155_ioc_s_crop, | |
697 | .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes, | |
698 | .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals, | |
d42bffb8 MM |
699 | */ |
700 | }; | |
701 | ||
702 | static int __devinit | |
8ded351a | 703 | dt3155_init_board(struct pci_dev *pdev) |
d42bffb8 | 704 | { |
8ded351a | 705 | struct dt3155_priv *pd = pci_get_drvdata(pdev); |
a57941c2 MM |
706 | void *buf_cpu; |
707 | dma_addr_t buf_dma; | |
d42bffb8 MM |
708 | int i; |
709 | u8 tmp; | |
a57941c2 | 710 | |
8ded351a | 711 | pci_set_master(pdev); /* dt3155 needs it */ |
d42bffb8 MM |
712 | |
713 | /* resetting the adapter */ | |
714 | iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN, | |
715 | pd->regs + CSR1); | |
716 | mmiowb(); | |
8ded351a | 717 | msleep(20); |
d42bffb8 MM |
718 | |
719 | /* initializing adaper registers */ | |
720 | iowrite32(FIFO_EN | SRST, pd->regs + CSR1); | |
721 | mmiowb(); | |
722 | iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT); | |
723 | iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT); | |
724 | iowrite32(0x00000020, pd->regs + FIFO_TRIGER); | |
725 | iowrite32(0x00000103, pd->regs + XFER_MODE); | |
726 | iowrite32(0, pd->regs + RETRY_WAIT_CNT); | |
727 | iowrite32(0, pd->regs + INT_CSR); | |
728 | iowrite32(1, pd->regs + EVEN_FLD_MASK); | |
729 | iowrite32(1, pd->regs + ODD_FLD_MASK); | |
730 | iowrite32(0, pd->regs + MASK_LENGTH); | |
731 | iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT); | |
732 | iowrite32(0x01010101, pd->regs + IIC_CLK_DUR); | |
733 | mmiowb(); | |
734 | ||
735 | /* verifying that we have a DT3155 board (not just a SAA7116 chip) */ | |
736 | read_i2c_reg(pd->regs, DT_ID, &tmp); | |
737 | if (tmp != DT3155_ID) | |
738 | return -ENODEV; | |
739 | ||
740 | /* initialize AD LUT */ | |
741 | write_i2c_reg(pd->regs, AD_ADDR, 0); | |
742 | for (i = 0; i < 256; i++) | |
743 | write_i2c_reg(pd->regs, AD_LUT, i); | |
744 | ||
745 | /* initialize ADC references */ | |
746 | /* FIXME: pos_ref & neg_ref depend on VT_50HZ */ | |
747 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); | |
748 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); | |
749 | write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF); | |
750 | write_i2c_reg(pd->regs, AD_CMD, 34); | |
751 | write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF); | |
752 | write_i2c_reg(pd->regs, AD_CMD, 0); | |
753 | ||
754 | /* initialize PM LUT */ | |
755 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM); | |
756 | for (i = 0; i < 256; i++) { | |
757 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); | |
758 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); | |
759 | } | |
760 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL); | |
761 | for (i = 0; i < 256; i++) { | |
762 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); | |
763 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); | |
764 | } | |
765 | write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */ | |
766 | ||
767 | /* select chanel 1 for input and set sync level */ | |
768 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); | |
769 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); | |
770 | ||
a57941c2 | 771 | /* allocate memory, and initialize the DMA machine */ |
8ded351a | 772 | buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma, |
a57941c2 | 773 | GFP_KERNEL); |
c94a2e47 | 774 | if (!buf_cpu) |
d42bffb8 | 775 | return -ENOMEM; |
a57941c2 MM |
776 | iowrite32(buf_dma, pd->regs + EVEN_DMA_START); |
777 | iowrite32(buf_dma, pd->regs + ODD_DMA_START); | |
d42bffb8 MM |
778 | iowrite32(0, pd->regs + EVEN_DMA_STRIDE); |
779 | iowrite32(0, pd->regs + ODD_DMA_STRIDE); | |
780 | ||
781 | /* Perform a pseudo even field acquire */ | |
782 | iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1); | |
783 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL); | |
784 | write_i2c_reg(pd->regs, CONFIG, pd->config); | |
785 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL); | |
786 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL); | |
787 | msleep(100); | |
788 | read_i2c_reg(pd->regs, CSR2, &tmp); | |
789 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE); | |
790 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE); | |
791 | write_i2c_reg(pd->regs, CSR2, pd->csr2); | |
792 | iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1); | |
793 | ||
a57941c2 | 794 | /* deallocate memory */ |
8ded351a | 795 | dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma); |
c94a2e47 | 796 | if (tmp & BUSY_EVEN) |
d42bffb8 | 797 | return -EIO; |
d42bffb8 MM |
798 | return 0; |
799 | } | |
800 | ||
801 | static struct video_device dt3155_vdev = { | |
802 | .name = DT3155_NAME, | |
803 | .fops = &dt3155_fops, | |
804 | .ioctl_ops = &dt3155_ioctl_ops, | |
805 | .minor = -1, | |
806 | .release = video_device_release, | |
fdd2d934 | 807 | .tvnorms = DT3155_CURRENT_NORM, |
d42bffb8 MM |
808 | .current_norm = DT3155_CURRENT_NORM, |
809 | }; | |
810 | ||
a57941c2 MM |
811 | /* same as in drivers/base/dma-coherent.c */ |
812 | struct dma_coherent_mem { | |
813 | void *virt_base; | |
8ded351a | 814 | dma_addr_t device_base; |
a57941c2 MM |
815 | int size; |
816 | int flags; | |
817 | unsigned long *bitmap; | |
818 | }; | |
819 | ||
820 | static int __devinit | |
821 | dt3155_alloc_coherent(struct device *dev, size_t size, int flags) | |
822 | { | |
f932e3a3 MM |
823 | struct dma_coherent_mem *mem; |
824 | dma_addr_t dev_base; | |
a57941c2 MM |
825 | int pages = size >> PAGE_SHIFT; |
826 | int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); | |
827 | ||
828 | if ((flags & DMA_MEMORY_MAP) == 0) | |
829 | goto out; | |
830 | if (!size) | |
831 | goto out; | |
832 | if (dev->dma_mem) | |
833 | goto out; | |
834 | ||
f932e3a3 MM |
835 | mem = kzalloc(sizeof(*mem), GFP_KERNEL); |
836 | if (!mem) | |
a57941c2 | 837 | goto out; |
f932e3a3 MM |
838 | mem->virt_base = dma_alloc_coherent(dev, size, &dev_base, |
839 | DT3155_COH_FLAGS); | |
840 | if (!mem->virt_base) | |
841 | goto err_alloc_coherent; | |
842 | mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
843 | if (!mem->bitmap) | |
a57941c2 MM |
844 | goto err_bitmap; |
845 | ||
f932e3a3 MM |
846 | /* coherent_dma_mask is already set to 32 bits */ |
847 | mem->device_base = dev_base; | |
848 | mem->size = pages; | |
849 | mem->flags = flags; | |
850 | dev->dma_mem = mem; | |
a57941c2 MM |
851 | return DMA_MEMORY_MAP; |
852 | ||
a57941c2 | 853 | err_bitmap: |
f932e3a3 MM |
854 | dma_free_coherent(dev, size, mem->virt_base, dev_base); |
855 | err_alloc_coherent: | |
856 | kfree(mem); | |
a57941c2 MM |
857 | out: |
858 | return 0; | |
859 | } | |
860 | ||
861 | static void __devexit | |
862 | dt3155_free_coherent(struct device *dev) | |
863 | { | |
864 | struct dma_coherent_mem *mem = dev->dma_mem; | |
865 | ||
866 | if (!mem) | |
867 | return; | |
868 | dev->dma_mem = NULL; | |
869 | dma_free_coherent(dev, mem->size << PAGE_SHIFT, | |
870 | mem->virt_base, mem->device_base); | |
871 | kfree(mem->bitmap); | |
872 | kfree(mem); | |
873 | } | |
874 | ||
d42bffb8 | 875 | static int __devinit |
8ded351a | 876 | dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
d42bffb8 | 877 | { |
a57941c2 | 878 | int err; |
d42bffb8 MM |
879 | struct dt3155_priv *pd; |
880 | ||
8ded351a | 881 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
c94a2e47 | 882 | if (err) |
d42bffb8 | 883 | return -ENODEV; |
8ded351a | 884 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
c94a2e47 | 885 | if (err) |
a57941c2 | 886 | return -ENODEV; |
d42bffb8 | 887 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); |
c94a2e47 | 888 | if (!pd) |
d42bffb8 | 889 | return -ENOMEM; |
d42bffb8 | 890 | pd->vdev = video_device_alloc(); |
c94a2e47 | 891 | if (!pd->vdev) |
d42bffb8 | 892 | goto err_video_device_alloc; |
d42bffb8 | 893 | *pd->vdev = dt3155_vdev; |
8ded351a | 894 | pci_set_drvdata(pdev, pd); /* for use in dt3155_remove() */ |
a57941c2 | 895 | video_set_drvdata(pd->vdev, pd); /* for use in video_fops */ |
d42bffb8 | 896 | pd->users = 0; |
8ded351a | 897 | pd->pdev = pdev; |
d42bffb8 | 898 | INIT_LIST_HEAD(&pd->dmaq); |
d42bffb8 | 899 | mutex_init(&pd->mux); |
8ded351a MM |
900 | pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */ |
901 | spin_lock_init(&pd->lock); | |
d42bffb8 MM |
902 | pd->csr2 = csr2_init; |
903 | pd->config = config_init; | |
8ded351a | 904 | err = pci_enable_device(pdev); |
c94a2e47 | 905 | if (err) |
d42bffb8 | 906 | goto err_enable_dev; |
8ded351a | 907 | err = pci_request_region(pdev, 0, pci_name(pdev)); |
d42bffb8 MM |
908 | if (err) |
909 | goto err_req_region; | |
8ded351a | 910 | pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0)); |
aecf33db | 911 | if (!pd->regs) { |
d42bffb8 | 912 | err = -ENOMEM; |
d42bffb8 | 913 | goto err_pci_iomap; |
aecf33db | 914 | } |
8ded351a | 915 | err = dt3155_init_board(pdev); |
c94a2e47 | 916 | if (err) |
d42bffb8 | 917 | goto err_init_board; |
d42bffb8 | 918 | err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1); |
a57941c2 | 919 | if (err) |
c94a2e47 HS |
920 | goto err_init_board; |
921 | if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE, | |
922 | DMA_MEMORY_MAP)) | |
923 | dev_info(&pdev->dev, "preallocated 8 buffers\n"); | |
924 | dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev->minor); | |
d42bffb8 MM |
925 | return 0; /* success */ |
926 | ||
927 | err_init_board: | |
8ded351a | 928 | pci_iounmap(pdev, pd->regs); |
d42bffb8 | 929 | err_pci_iomap: |
8ded351a | 930 | pci_release_region(pdev, 0); |
d42bffb8 | 931 | err_req_region: |
8ded351a | 932 | pci_disable_device(pdev); |
d42bffb8 MM |
933 | err_enable_dev: |
934 | video_device_release(pd->vdev); | |
935 | err_video_device_alloc: | |
936 | kfree(pd); | |
937 | return err; | |
938 | } | |
939 | ||
940 | static void __devexit | |
8ded351a | 941 | dt3155_remove(struct pci_dev *pdev) |
d42bffb8 | 942 | { |
8ded351a | 943 | struct dt3155_priv *pd = pci_get_drvdata(pdev); |
d42bffb8 | 944 | |
8ded351a | 945 | dt3155_free_coherent(&pdev->dev); |
d42bffb8 | 946 | video_unregister_device(pd->vdev); |
8ded351a MM |
947 | pci_iounmap(pdev, pd->regs); |
948 | pci_release_region(pdev, 0); | |
949 | pci_disable_device(pdev); | |
d42bffb8 MM |
950 | /* |
951 | * video_device_release() is invoked automatically | |
952 | * see: struct video_device dt3155_vdev | |
953 | */ | |
954 | kfree(pd); | |
955 | } | |
956 | ||
957 | static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { | |
958 | { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) }, | |
959 | { 0, /* zero marks the end */ }, | |
960 | }; | |
961 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
962 | ||
963 | static struct pci_driver pci_driver = { | |
964 | .name = DT3155_NAME, | |
965 | .id_table = pci_ids, | |
966 | .probe = dt3155_probe, | |
967 | .remove = __devexit_p(dt3155_remove), | |
968 | }; | |
969 | ||
970 | static int __init | |
971 | dt3155_init_module(void) | |
972 | { | |
c94a2e47 | 973 | return pci_register_driver(&pci_driver); |
d42bffb8 MM |
974 | } |
975 | ||
976 | static void __exit | |
977 | dt3155_exit_module(void) | |
978 | { | |
979 | pci_unregister_driver(&pci_driver); | |
d42bffb8 MM |
980 | } |
981 | ||
982 | module_init(dt3155_init_module); | |
983 | module_exit(dt3155_exit_module); | |
984 | ||
985 | MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber"); | |
986 | MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>"); | |
987 | MODULE_VERSION(DT3155_VERSION); | |
988 | MODULE_LICENSE("GPL"); |