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59f0ad80 SA |
1 | /* |
2 | * TI OMAP4 ISS V4L2 Driver | |
3 | * | |
4 | * Copyright (C) 2012, Texas Instruments | |
5 | * | |
6 | * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/i2c.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/vmalloc.h> | |
25 | ||
26 | #include <media/v4l2-common.h> | |
27 | #include <media/v4l2-device.h> | |
28 | #include <media/v4l2-ctrls.h> | |
29 | ||
30 | #include "iss.h" | |
31 | #include "iss_regs.h" | |
32 | ||
33 | #define ISS_PRINT_REGISTER(iss, name)\ | |
34 | dev_dbg(iss->dev, "###ISS " #name "=0x%08x\n", \ | |
11abbfd3 | 35 | iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_##name)) |
59f0ad80 SA |
36 | |
37 | static void iss_print_status(struct iss_device *iss) | |
38 | { | |
39 | dev_dbg(iss->dev, "-------------ISS HL Register dump-------------\n"); | |
40 | ||
41 | ISS_PRINT_REGISTER(iss, HL_REVISION); | |
42 | ISS_PRINT_REGISTER(iss, HL_SYSCONFIG); | |
ade1ec37 LP |
43 | ISS_PRINT_REGISTER(iss, HL_IRQSTATUS(5)); |
44 | ISS_PRINT_REGISTER(iss, HL_IRQENABLE_SET(5)); | |
45 | ISS_PRINT_REGISTER(iss, HL_IRQENABLE_CLR(5)); | |
59f0ad80 SA |
46 | ISS_PRINT_REGISTER(iss, CTRL); |
47 | ISS_PRINT_REGISTER(iss, CLKCTRL); | |
48 | ISS_PRINT_REGISTER(iss, CLKSTAT); | |
49 | ||
50 | dev_dbg(iss->dev, "-----------------------------------------------\n"); | |
51 | } | |
52 | ||
53 | /* | |
54 | * omap4iss_flush - Post pending L3 bus writes by doing a register readback | |
55 | * @iss: OMAP4 ISS device | |
56 | * | |
57 | * In order to force posting of pending writes, we need to write and | |
58 | * readback the same register, in this case the revision register. | |
59 | * | |
60 | * See this link for reference: | |
61 | * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html | |
62 | */ | |
63 | void omap4iss_flush(struct iss_device *iss) | |
64 | { | |
11abbfd3 LP |
65 | iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION, 0); |
66 | iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION); | |
59f0ad80 SA |
67 | } |
68 | ||
69 | /* | |
af15d025 | 70 | * iss_isp_enable_interrupts - Enable ISS ISP interrupts. |
59f0ad80 SA |
71 | * @iss: OMAP4 ISS device |
72 | */ | |
af15d025 | 73 | static void omap4iss_isp_enable_interrupts(struct iss_device *iss) |
59f0ad80 | 74 | { |
af15d025 LP |
75 | static const u32 isp_irq = ISP5_IRQ_OCP_ERR | |
76 | ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR | | |
77 | ISP5_IRQ_RSZ_FIFO_OVF | | |
78 | ISP5_IRQ_RSZ_INT_DMA | | |
79 | ISP5_IRQ_ISIF_INT(0); | |
59f0ad80 | 80 | |
af15d025 LP |
81 | /* Enable ISP interrupts */ |
82 | iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQSTATUS(0), isp_irq); | |
83 | iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQENABLE_SET(0), | |
84 | isp_irq); | |
59f0ad80 SA |
85 | } |
86 | ||
87 | /* | |
af15d025 | 88 | * iss_isp_disable_interrupts - Disable ISS interrupts. |
59f0ad80 SA |
89 | * @iss: OMAP4 ISS device |
90 | */ | |
af15d025 | 91 | static void omap4iss_isp_disable_interrupts(struct iss_device *iss) |
59f0ad80 | 92 | { |
af15d025 | 93 | iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQENABLE_CLR(0), ~0); |
59f0ad80 SA |
94 | } |
95 | ||
96 | /* | |
af15d025 | 97 | * iss_enable_interrupts - Enable ISS interrupts. |
59f0ad80 SA |
98 | * @iss: OMAP4 ISS device |
99 | */ | |
af15d025 | 100 | static void iss_enable_interrupts(struct iss_device *iss) |
59f0ad80 | 101 | { |
af15d025 LP |
102 | static const u32 hl_irq = ISS_HL_IRQ_CSIA | ISS_HL_IRQ_CSIB |
103 | | ISS_HL_IRQ_ISP(0); | |
59f0ad80 | 104 | |
af15d025 LP |
105 | /* Enable HL interrupts */ |
106 | iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5), hl_irq); | |
107 | iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQENABLE_SET(5), hl_irq); | |
108 | ||
109 | if (iss->regs[OMAP4_ISS_MEM_ISP_SYS1]) | |
110 | omap4iss_isp_enable_interrupts(iss); | |
59f0ad80 SA |
111 | } |
112 | ||
113 | /* | |
af15d025 | 114 | * iss_disable_interrupts - Disable ISS interrupts. |
59f0ad80 SA |
115 | * @iss: OMAP4 ISS device |
116 | */ | |
af15d025 | 117 | static void iss_disable_interrupts(struct iss_device *iss) |
59f0ad80 | 118 | { |
af15d025 LP |
119 | if (iss->regs[OMAP4_ISS_MEM_ISP_SYS1]) |
120 | omap4iss_isp_disable_interrupts(iss); | |
121 | ||
122 | iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQENABLE_CLR(5), ~0); | |
59f0ad80 SA |
123 | } |
124 | ||
125 | int omap4iss_get_external_info(struct iss_pipeline *pipe, | |
126 | struct media_link *link) | |
127 | { | |
128 | struct iss_device *iss = | |
129 | container_of(pipe, struct iss_video, pipe)->iss; | |
130 | struct v4l2_subdev_format fmt; | |
ea72717e | 131 | struct v4l2_ctrl *ctrl; |
59f0ad80 SA |
132 | int ret; |
133 | ||
134 | if (!pipe->external) | |
135 | return 0; | |
136 | ||
137 | if (pipe->external_rate) | |
138 | return 0; | |
139 | ||
140 | memset(&fmt, 0, sizeof(fmt)); | |
141 | ||
142 | fmt.pad = link->source->index; | |
143 | fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; | |
144 | ret = v4l2_subdev_call(media_entity_to_v4l2_subdev(link->sink->entity), | |
145 | pad, get_fmt, NULL, &fmt); | |
146 | if (ret < 0) | |
147 | return -EPIPE; | |
148 | ||
149 | pipe->external_bpp = omap4iss_video_format_info(fmt.format.code)->bpp; | |
150 | ||
ea72717e LP |
151 | ctrl = v4l2_ctrl_find(pipe->external->ctrl_handler, |
152 | V4L2_CID_PIXEL_RATE); | |
153 | if (ctrl == NULL) { | |
59f0ad80 SA |
154 | dev_warn(iss->dev, "no pixel rate control in subdev %s\n", |
155 | pipe->external->name); | |
ea72717e | 156 | return -EPIPE; |
59f0ad80 SA |
157 | } |
158 | ||
ea72717e | 159 | pipe->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl); |
59f0ad80 SA |
160 | |
161 | return 0; | |
162 | } | |
163 | ||
164 | /* | |
165 | * Configure the bridge. Valid inputs are | |
166 | * | |
167 | * IPIPEIF_INPUT_CSI2A: CSI2a receiver | |
168 | * IPIPEIF_INPUT_CSI2B: CSI2b receiver | |
169 | * | |
170 | * The bridge and lane shifter are configured according to the selected input | |
171 | * and the ISP platform data. | |
172 | */ | |
173 | void omap4iss_configure_bridge(struct iss_device *iss, | |
174 | enum ipipeif_input_entity input) | |
175 | { | |
176 | u32 issctrl_val; | |
177 | u32 isp5ctrl_val; | |
178 | ||
11abbfd3 | 179 | issctrl_val = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_CTRL); |
59f0ad80 SA |
180 | issctrl_val &= ~ISS_CTRL_INPUT_SEL_MASK; |
181 | issctrl_val &= ~ISS_CTRL_CLK_DIV_MASK; | |
182 | ||
11abbfd3 | 183 | isp5ctrl_val = iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL); |
59f0ad80 SA |
184 | |
185 | switch (input) { | |
186 | case IPIPEIF_INPUT_CSI2A: | |
187 | issctrl_val |= ISS_CTRL_INPUT_SEL_CSI2A; | |
59f0ad80 SA |
188 | break; |
189 | ||
190 | case IPIPEIF_INPUT_CSI2B: | |
191 | issctrl_val |= ISS_CTRL_INPUT_SEL_CSI2B; | |
59f0ad80 SA |
192 | break; |
193 | ||
194 | default: | |
195 | return; | |
196 | } | |
197 | ||
198 | issctrl_val |= ISS_CTRL_SYNC_DETECT_VS_RAISING; | |
199 | ||
cce093ee LP |
200 | isp5ctrl_val |= ISP5_CTRL_VD_PULSE_EXT | ISP5_CTRL_PSYNC_CLK_SEL | |
201 | ISP5_CTRL_SYNC_ENABLE; | |
59f0ad80 | 202 | |
11abbfd3 LP |
203 | iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_CTRL, issctrl_val); |
204 | iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL, isp5ctrl_val); | |
59f0ad80 SA |
205 | } |
206 | ||
d14cb130 | 207 | #ifdef ISS_ISR_DEBUG |
380df42b | 208 | static void iss_isr_dbg(struct iss_device *iss, u32 irqstatus) |
59f0ad80 | 209 | { |
5122f6a2 LP |
210 | static const char * const name[] = { |
211 | "ISP_0", | |
212 | "ISP_1", | |
213 | "ISP_2", | |
214 | "ISP_3", | |
215 | "CSIA", | |
216 | "CSIB", | |
217 | "CCP2_0", | |
218 | "CCP2_1", | |
219 | "CCP2_2", | |
220 | "CCP2_3", | |
221 | "CBUFF", | |
222 | "BTE", | |
223 | "SIMCOP_0", | |
224 | "SIMCOP_1", | |
225 | "SIMCOP_2", | |
226 | "SIMCOP_3", | |
227 | "CCP2_8", | |
228 | "HS_VS", | |
229 | "18", | |
230 | "19", | |
231 | "20", | |
232 | "21", | |
233 | "22", | |
234 | "23", | |
235 | "24", | |
236 | "25", | |
237 | "26", | |
238 | "27", | |
239 | "28", | |
240 | "29", | |
241 | "30", | |
242 | "31", | |
59f0ad80 | 243 | }; |
5122f6a2 | 244 | unsigned int i; |
59f0ad80 SA |
245 | |
246 | dev_dbg(iss->dev, "ISS IRQ: "); | |
247 | ||
248 | for (i = 0; i < ARRAY_SIZE(name); i++) { | |
249 | if ((1 << i) & irqstatus) | |
250 | pr_cont("%s ", name[i]); | |
251 | } | |
252 | pr_cont("\n"); | |
253 | } | |
254 | ||
380df42b | 255 | static void iss_isp_isr_dbg(struct iss_device *iss, u32 irqstatus) |
5122f6a2 LP |
256 | { |
257 | static const char * const name[] = { | |
258 | "ISIF_0", | |
259 | "ISIF_1", | |
260 | "ISIF_2", | |
261 | "ISIF_3", | |
262 | "IPIPEREQ", | |
263 | "IPIPELAST_PIX", | |
264 | "IPIPEDMA", | |
265 | "IPIPEBSC", | |
266 | "IPIPEHST", | |
267 | "IPIPEIF", | |
268 | "AEW", | |
269 | "AF", | |
270 | "H3A", | |
271 | "RSZ_REG", | |
272 | "RSZ_LAST_PIX", | |
273 | "RSZ_DMA", | |
274 | "RSZ_CYC_RZA", | |
275 | "RSZ_CYC_RZB", | |
276 | "RSZ_FIFO_OVF", | |
277 | "RSZ_FIFO_IN_BLK_ERR", | |
278 | "20", | |
279 | "21", | |
280 | "RSZ_EOF0", | |
281 | "RSZ_EOF1", | |
282 | "H3A_EOF", | |
283 | "IPIPE_EOF", | |
284 | "26", | |
285 | "IPIPE_DPC_INI", | |
286 | "IPIPE_DPC_RNEW0", | |
287 | "IPIPE_DPC_RNEW1", | |
288 | "30", | |
289 | "OCP_ERR", | |
290 | }; | |
291 | unsigned int i; | |
292 | ||
293 | dev_dbg(iss->dev, "ISP IRQ: "); | |
294 | ||
295 | for (i = 0; i < ARRAY_SIZE(name); i++) { | |
296 | if ((1 << i) & irqstatus) | |
297 | pr_cont("%s ", name[i]); | |
298 | } | |
299 | pr_cont("\n"); | |
300 | } | |
301 | #endif | |
302 | ||
59f0ad80 SA |
303 | /* |
304 | * iss_isr - Interrupt Service Routine for ISS module. | |
305 | * @irq: Not used currently. | |
306 | * @_iss: Pointer to the OMAP4 ISS device | |
307 | * | |
308 | * Handles the corresponding callback if plugged in. | |
309 | * | |
310 | * Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the | |
311 | * IRQ wasn't handled. | |
312 | */ | |
313 | static irqreturn_t iss_isr(int irq, void *_iss) | |
314 | { | |
ade1ec37 LP |
315 | static const u32 ipipeif_events = ISP5_IRQ_IPIPEIF_IRQ | |
316 | ISP5_IRQ_ISIF_INT(0); | |
317 | static const u32 resizer_events = ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR | | |
59f0ad80 SA |
318 | ISP5_IRQ_RSZ_FIFO_OVF | |
319 | ISP5_IRQ_RSZ_INT_DMA; | |
320 | struct iss_device *iss = _iss; | |
321 | u32 irqstatus; | |
322 | ||
11abbfd3 LP |
323 | irqstatus = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5)); |
324 | iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5), irqstatus); | |
59f0ad80 SA |
325 | |
326 | if (irqstatus & ISS_HL_IRQ_CSIA) | |
327 | omap4iss_csi2_isr(&iss->csi2a); | |
328 | ||
329 | if (irqstatus & ISS_HL_IRQ_CSIB) | |
330 | omap4iss_csi2_isr(&iss->csi2b); | |
331 | ||
332 | if (irqstatus & ISS_HL_IRQ_ISP(0)) { | |
11abbfd3 LP |
333 | u32 isp_irqstatus = iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, |
334 | ISP5_IRQSTATUS(0)); | |
335 | iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQSTATUS(0), | |
336 | isp_irqstatus); | |
59f0ad80 SA |
337 | |
338 | if (isp_irqstatus & ISP5_IRQ_OCP_ERR) | |
339 | dev_dbg(iss->dev, "ISP5 OCP Error!\n"); | |
340 | ||
341 | if (isp_irqstatus & ipipeif_events) { | |
342 | omap4iss_ipipeif_isr(&iss->ipipeif, | |
343 | isp_irqstatus & ipipeif_events); | |
344 | } | |
345 | ||
346 | if (isp_irqstatus & resizer_events) | |
347 | omap4iss_resizer_isr(&iss->resizer, | |
348 | isp_irqstatus & resizer_events); | |
5122f6a2 | 349 | |
d14cb130 | 350 | #ifdef ISS_ISR_DEBUG |
5122f6a2 LP |
351 | iss_isp_isr_dbg(iss, isp_irqstatus); |
352 | #endif | |
59f0ad80 SA |
353 | } |
354 | ||
355 | omap4iss_flush(iss); | |
356 | ||
d14cb130 | 357 | #ifdef ISS_ISR_DEBUG |
59f0ad80 SA |
358 | iss_isr_dbg(iss, irqstatus); |
359 | #endif | |
360 | ||
361 | return IRQ_HANDLED; | |
362 | } | |
363 | ||
364 | /* ----------------------------------------------------------------------------- | |
365 | * Pipeline power management | |
366 | * | |
367 | * Entities must be powered up when part of a pipeline that contains at least | |
368 | * one open video device node. | |
369 | * | |
370 | * To achieve this use the entity use_count field to track the number of users. | |
371 | * For entities corresponding to video device nodes the use_count field stores | |
372 | * the users count of the node. For entities corresponding to subdevs the | |
373 | * use_count field stores the total number of users of all video device nodes | |
374 | * in the pipeline. | |
375 | * | |
376 | * The omap4iss_pipeline_pm_use() function must be called in the open() and | |
377 | * close() handlers of video device nodes. It increments or decrements the use | |
378 | * count of all subdev entities in the pipeline. | |
379 | * | |
380 | * To react to link management on powered pipelines, the link setup notification | |
381 | * callback updates the use count of all entities in the source and sink sides | |
382 | * of the link. | |
383 | */ | |
384 | ||
385 | /* | |
386 | * iss_pipeline_pm_use_count - Count the number of users of a pipeline | |
387 | * @entity: The entity | |
388 | * | |
389 | * Return the total number of users of all video device nodes in the pipeline. | |
390 | */ | |
391 | static int iss_pipeline_pm_use_count(struct media_entity *entity) | |
392 | { | |
393 | struct media_entity_graph graph; | |
394 | int use = 0; | |
395 | ||
396 | media_entity_graph_walk_start(&graph, entity); | |
397 | ||
398 | while ((entity = media_entity_graph_walk_next(&graph))) { | |
399 | if (media_entity_type(entity) == MEDIA_ENT_T_DEVNODE) | |
400 | use += entity->use_count; | |
401 | } | |
402 | ||
403 | return use; | |
404 | } | |
405 | ||
406 | /* | |
407 | * iss_pipeline_pm_power_one - Apply power change to an entity | |
408 | * @entity: The entity | |
409 | * @change: Use count change | |
410 | * | |
411 | * Change the entity use count by @change. If the entity is a subdev update its | |
412 | * power state by calling the core::s_power operation when the use count goes | |
413 | * from 0 to != 0 or from != 0 to 0. | |
414 | * | |
415 | * Return 0 on success or a negative error code on failure. | |
416 | */ | |
417 | static int iss_pipeline_pm_power_one(struct media_entity *entity, int change) | |
418 | { | |
419 | struct v4l2_subdev *subdev; | |
420 | ||
421 | subdev = media_entity_type(entity) == MEDIA_ENT_T_V4L2_SUBDEV | |
422 | ? media_entity_to_v4l2_subdev(entity) : NULL; | |
423 | ||
424 | if (entity->use_count == 0 && change > 0 && subdev != NULL) { | |
425 | int ret; | |
426 | ||
427 | ret = v4l2_subdev_call(subdev, core, s_power, 1); | |
428 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
429 | return ret; | |
430 | } | |
431 | ||
432 | entity->use_count += change; | |
433 | WARN_ON(entity->use_count < 0); | |
434 | ||
435 | if (entity->use_count == 0 && change < 0 && subdev != NULL) | |
436 | v4l2_subdev_call(subdev, core, s_power, 0); | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | /* | |
442 | * iss_pipeline_pm_power - Apply power change to all entities in a pipeline | |
443 | * @entity: The entity | |
444 | * @change: Use count change | |
445 | * | |
446 | * Walk the pipeline to update the use count and the power state of all non-node | |
447 | * entities. | |
448 | * | |
449 | * Return 0 on success or a negative error code on failure. | |
450 | */ | |
451 | static int iss_pipeline_pm_power(struct media_entity *entity, int change) | |
452 | { | |
453 | struct media_entity_graph graph; | |
454 | struct media_entity *first = entity; | |
455 | int ret = 0; | |
456 | ||
457 | if (!change) | |
458 | return 0; | |
459 | ||
460 | media_entity_graph_walk_start(&graph, entity); | |
461 | ||
462 | while (!ret && (entity = media_entity_graph_walk_next(&graph))) | |
463 | if (media_entity_type(entity) != MEDIA_ENT_T_DEVNODE) | |
464 | ret = iss_pipeline_pm_power_one(entity, change); | |
465 | ||
466 | if (!ret) | |
467 | return 0; | |
468 | ||
469 | media_entity_graph_walk_start(&graph, first); | |
470 | ||
471 | while ((first = media_entity_graph_walk_next(&graph)) | |
472 | && first != entity) | |
473 | if (media_entity_type(first) != MEDIA_ENT_T_DEVNODE) | |
474 | iss_pipeline_pm_power_one(first, -change); | |
475 | ||
476 | return ret; | |
477 | } | |
478 | ||
479 | /* | |
480 | * omap4iss_pipeline_pm_use - Update the use count of an entity | |
481 | * @entity: The entity | |
482 | * @use: Use (1) or stop using (0) the entity | |
483 | * | |
484 | * Update the use count of all entities in the pipeline and power entities on or | |
485 | * off accordingly. | |
486 | * | |
487 | * Return 0 on success or a negative error code on failure. Powering entities | |
488 | * off is assumed to never fail. No failure can occur when the use parameter is | |
489 | * set to 0. | |
490 | */ | |
491 | int omap4iss_pipeline_pm_use(struct media_entity *entity, int use) | |
492 | { | |
493 | int change = use ? 1 : -1; | |
494 | int ret; | |
495 | ||
496 | mutex_lock(&entity->parent->graph_mutex); | |
497 | ||
498 | /* Apply use count to node. */ | |
499 | entity->use_count += change; | |
500 | WARN_ON(entity->use_count < 0); | |
501 | ||
502 | /* Apply power change to connected non-nodes. */ | |
503 | ret = iss_pipeline_pm_power(entity, change); | |
504 | if (ret < 0) | |
505 | entity->use_count -= change; | |
506 | ||
507 | mutex_unlock(&entity->parent->graph_mutex); | |
508 | ||
509 | return ret; | |
510 | } | |
511 | ||
512 | /* | |
513 | * iss_pipeline_link_notify - Link management notification callback | |
514 | * @link: The link | |
515 | * @flags: New link flags that will be applied | |
516 | * | |
517 | * React to link management on powered pipelines by updating the use count of | |
518 | * all entities in the source and sink sides of the link. Entities are powered | |
519 | * on or off accordingly. | |
520 | * | |
521 | * Return 0 on success or a negative error code on failure. Powering entities | |
522 | * off is assumed to never fail. This function will not fail for disconnection | |
523 | * events. | |
524 | */ | |
525 | static int iss_pipeline_link_notify(struct media_link *link, u32 flags, | |
526 | unsigned int notification) | |
527 | { | |
528 | struct media_entity *source = link->source->entity; | |
529 | struct media_entity *sink = link->sink->entity; | |
530 | int source_use = iss_pipeline_pm_use_count(source); | |
531 | int sink_use = iss_pipeline_pm_use_count(sink); | |
532 | int ret; | |
533 | ||
534 | if (notification == MEDIA_DEV_NOTIFY_POST_LINK_CH && | |
535 | !(link->flags & MEDIA_LNK_FL_ENABLED)) { | |
536 | /* Powering off entities is assumed to never fail. */ | |
537 | iss_pipeline_pm_power(source, -sink_use); | |
538 | iss_pipeline_pm_power(sink, -source_use); | |
539 | return 0; | |
540 | } | |
541 | ||
542 | if (notification == MEDIA_DEV_NOTIFY_POST_LINK_CH && | |
543 | (flags & MEDIA_LNK_FL_ENABLED)) { | |
544 | ret = iss_pipeline_pm_power(source, sink_use); | |
545 | if (ret < 0) | |
546 | return ret; | |
547 | ||
548 | ret = iss_pipeline_pm_power(sink, source_use); | |
549 | if (ret < 0) | |
550 | iss_pipeline_pm_power(source, -sink_use); | |
551 | ||
552 | return ret; | |
553 | } | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | /* ----------------------------------------------------------------------------- | |
559 | * Pipeline stream management | |
560 | */ | |
561 | ||
9587a3fc LP |
562 | /* |
563 | * iss_pipeline_disable - Disable streaming on a pipeline | |
564 | * @pipe: ISS pipeline | |
565 | * @until: entity at which to stop pipeline walk | |
566 | * | |
567 | * Walk the entities chain starting at the pipeline output video node and stop | |
568 | * all modules in the chain. Wait synchronously for the modules to be stopped if | |
569 | * necessary. | |
570 | * | |
571 | * If the until argument isn't NULL, stop the pipeline walk when reaching the | |
572 | * until entity. This is used to disable a partially started pipeline due to a | |
573 | * subdev start error. | |
574 | */ | |
575 | static int iss_pipeline_disable(struct iss_pipeline *pipe, | |
576 | struct media_entity *until) | |
577 | { | |
578 | struct iss_device *iss = pipe->output->iss; | |
579 | struct media_entity *entity; | |
580 | struct media_pad *pad; | |
581 | struct v4l2_subdev *subdev; | |
582 | int failure = 0; | |
583 | int ret; | |
584 | ||
585 | entity = &pipe->output->video.entity; | |
586 | while (1) { | |
587 | pad = &entity->pads[0]; | |
588 | if (!(pad->flags & MEDIA_PAD_FL_SINK)) | |
589 | break; | |
590 | ||
591 | pad = media_entity_remote_pad(pad); | |
592 | if (pad == NULL || | |
593 | media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV) | |
594 | break; | |
595 | ||
596 | entity = pad->entity; | |
597 | if (entity == until) | |
598 | break; | |
599 | ||
600 | subdev = media_entity_to_v4l2_subdev(entity); | |
601 | ret = v4l2_subdev_call(subdev, video, s_stream, 0); | |
602 | if (ret < 0) { | |
603 | dev_dbg(iss->dev, "%s: module stop timeout.\n", | |
604 | subdev->name); | |
605 | /* If the entity failed to stopped, assume it has | |
606 | * crashed. Mark it as such, the ISS will be reset when | |
607 | * applications will release it. | |
608 | */ | |
609 | iss->crashed |= 1U << subdev->entity.id; | |
610 | failure = -ETIMEDOUT; | |
611 | } | |
612 | } | |
613 | ||
614 | return failure; | |
615 | } | |
616 | ||
59f0ad80 SA |
617 | /* |
618 | * iss_pipeline_enable - Enable streaming on a pipeline | |
619 | * @pipe: ISS pipeline | |
620 | * @mode: Stream mode (single shot or continuous) | |
621 | * | |
622 | * Walk the entities chain starting at the pipeline output video node and start | |
623 | * all modules in the chain in the given mode. | |
624 | * | |
625 | * Return 0 if successful, or the return value of the failed video::s_stream | |
626 | * operation otherwise. | |
627 | */ | |
628 | static int iss_pipeline_enable(struct iss_pipeline *pipe, | |
629 | enum iss_pipeline_stream_state mode) | |
630 | { | |
f3632ba8 | 631 | struct iss_device *iss = pipe->output->iss; |
59f0ad80 SA |
632 | struct media_entity *entity; |
633 | struct media_pad *pad; | |
634 | struct v4l2_subdev *subdev; | |
635 | unsigned long flags; | |
636 | int ret; | |
637 | ||
f3632ba8 LP |
638 | /* If one of the entities in the pipeline has crashed it will not work |
639 | * properly. Refuse to start streaming in that case. This check must be | |
640 | * performed before the loop below to avoid starting entities if the | |
641 | * pipeline won't start anyway (those entities would then likely fail to | |
642 | * stop, making the problem worse). | |
643 | */ | |
644 | if (pipe->entities & iss->crashed) | |
645 | return -EIO; | |
646 | ||
59f0ad80 SA |
647 | spin_lock_irqsave(&pipe->lock, flags); |
648 | pipe->state &= ~(ISS_PIPELINE_IDLE_INPUT | ISS_PIPELINE_IDLE_OUTPUT); | |
649 | spin_unlock_irqrestore(&pipe->lock, flags); | |
650 | ||
651 | pipe->do_propagation = false; | |
652 | ||
653 | entity = &pipe->output->video.entity; | |
654 | while (1) { | |
655 | pad = &entity->pads[0]; | |
656 | if (!(pad->flags & MEDIA_PAD_FL_SINK)) | |
657 | break; | |
658 | ||
659 | pad = media_entity_remote_pad(pad); | |
660 | if (pad == NULL || | |
661 | media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV) | |
662 | break; | |
663 | ||
664 | entity = pad->entity; | |
665 | subdev = media_entity_to_v4l2_subdev(entity); | |
666 | ||
667 | ret = v4l2_subdev_call(subdev, video, s_stream, mode); | |
9587a3fc LP |
668 | if (ret < 0 && ret != -ENOIOCTLCMD) { |
669 | iss_pipeline_disable(pipe, entity); | |
59f0ad80 | 670 | return ret; |
9587a3fc | 671 | } |
707acfc0 LP |
672 | |
673 | if (subdev == &iss->csi2a.subdev || | |
674 | subdev == &iss->csi2b.subdev) | |
675 | pipe->do_propagation = true; | |
59f0ad80 | 676 | } |
707acfc0 | 677 | |
59f0ad80 SA |
678 | iss_print_status(pipe->output->iss); |
679 | return 0; | |
680 | } | |
681 | ||
59f0ad80 SA |
682 | /* |
683 | * omap4iss_pipeline_set_stream - Enable/disable streaming on a pipeline | |
684 | * @pipe: ISS pipeline | |
685 | * @state: Stream state (stopped, single shot or continuous) | |
686 | * | |
687 | * Set the pipeline to the given stream state. Pipelines can be started in | |
688 | * single-shot or continuous mode. | |
689 | * | |
690 | * Return 0 if successful, or the return value of the failed video::s_stream | |
691 | * operation otherwise. The pipeline state is not updated when the operation | |
692 | * fails, except when stopping the pipeline. | |
693 | */ | |
694 | int omap4iss_pipeline_set_stream(struct iss_pipeline *pipe, | |
695 | enum iss_pipeline_stream_state state) | |
696 | { | |
697 | int ret; | |
698 | ||
699 | if (state == ISS_PIPELINE_STREAM_STOPPED) | |
9587a3fc | 700 | ret = iss_pipeline_disable(pipe, NULL); |
59f0ad80 SA |
701 | else |
702 | ret = iss_pipeline_enable(pipe, state); | |
703 | ||
704 | if (ret == 0 || state == ISS_PIPELINE_STREAM_STOPPED) | |
705 | pipe->stream_state = state; | |
706 | ||
707 | return ret; | |
708 | } | |
709 | ||
112da085 LP |
710 | /* |
711 | * omap4iss_pipeline_cancel_stream - Cancel stream on a pipeline | |
712 | * @pipe: ISS pipeline | |
713 | * | |
714 | * Cancelling a stream mark all buffers on all video nodes in the pipeline as | |
715 | * erroneous and makes sure no new buffer can be queued. This function is called | |
716 | * when a fatal error that prevents any further operation on the pipeline | |
717 | * occurs. | |
718 | */ | |
719 | void omap4iss_pipeline_cancel_stream(struct iss_pipeline *pipe) | |
720 | { | |
721 | if (pipe->input) | |
722 | omap4iss_video_cancel_stream(pipe->input); | |
723 | if (pipe->output) | |
724 | omap4iss_video_cancel_stream(pipe->output); | |
725 | } | |
726 | ||
59f0ad80 SA |
727 | /* |
728 | * iss_pipeline_is_last - Verify if entity has an enabled link to the output | |
729 | * video node | |
730 | * @me: ISS module's media entity | |
731 | * | |
732 | * Returns 1 if the entity has an enabled link to the output video node or 0 | |
733 | * otherwise. It's true only while pipeline can have no more than one output | |
734 | * node. | |
735 | */ | |
736 | static int iss_pipeline_is_last(struct media_entity *me) | |
737 | { | |
738 | struct iss_pipeline *pipe; | |
739 | struct media_pad *pad; | |
740 | ||
741 | if (!me->pipe) | |
742 | return 0; | |
743 | pipe = to_iss_pipeline(me); | |
744 | if (pipe->stream_state == ISS_PIPELINE_STREAM_STOPPED) | |
745 | return 0; | |
746 | pad = media_entity_remote_pad(&pipe->output->pad); | |
747 | return pad->entity == me; | |
748 | } | |
749 | ||
750 | static int iss_reset(struct iss_device *iss) | |
751 | { | |
05b1b986 | 752 | unsigned int timeout; |
59f0ad80 | 753 | |
11abbfd3 LP |
754 | iss_reg_set(iss, OMAP4_ISS_MEM_TOP, ISS_HL_SYSCONFIG, |
755 | ISS_HL_SYSCONFIG_SOFTRESET); | |
59f0ad80 | 756 | |
05b1b986 LP |
757 | timeout = iss_poll_condition_timeout( |
758 | !(iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_SYSCONFIG) & | |
fa7014f5 | 759 | ISS_HL_SYSCONFIG_SOFTRESET), 1000, 10, 100); |
05b1b986 LP |
760 | if (timeout) { |
761 | dev_err(iss->dev, "ISS reset timeout\n"); | |
762 | return -ETIMEDOUT; | |
59f0ad80 SA |
763 | } |
764 | ||
f3632ba8 | 765 | iss->crashed = 0; |
59f0ad80 SA |
766 | return 0; |
767 | } | |
768 | ||
769 | static int iss_isp_reset(struct iss_device *iss) | |
770 | { | |
05b1b986 | 771 | unsigned int timeout; |
59f0ad80 SA |
772 | |
773 | /* Fist, ensure that the ISP is IDLE (no transactions happening) */ | |
11abbfd3 LP |
774 | iss_reg_update(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG, |
775 | ISP5_SYSCONFIG_STANDBYMODE_MASK, | |
776 | ISP5_SYSCONFIG_STANDBYMODE_SMART); | |
59f0ad80 | 777 | |
11abbfd3 | 778 | iss_reg_set(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL, ISP5_CTRL_MSTANDBY); |
59f0ad80 | 779 | |
05b1b986 LP |
780 | timeout = iss_poll_condition_timeout( |
781 | iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL) & | |
782 | ISP5_CTRL_MSTANDBY_WAIT, 1000000, 1000, 1500); | |
783 | if (timeout) { | |
784 | dev_err(iss->dev, "ISP5 standby timeout\n"); | |
785 | return -ETIMEDOUT; | |
59f0ad80 SA |
786 | } |
787 | ||
788 | /* Now finally, do the reset */ | |
11abbfd3 LP |
789 | iss_reg_set(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG, |
790 | ISP5_SYSCONFIG_SOFTRESET); | |
59f0ad80 | 791 | |
05b1b986 LP |
792 | timeout = iss_poll_condition_timeout( |
793 | !(iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG) & | |
794 | ISP5_SYSCONFIG_SOFTRESET), 1000000, 1000, 1500); | |
795 | if (timeout) { | |
796 | dev_err(iss->dev, "ISP5 reset timeout\n"); | |
797 | return -ETIMEDOUT; | |
59f0ad80 SA |
798 | } |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
803 | /* | |
804 | * iss_module_sync_idle - Helper to sync module with its idle state | |
805 | * @me: ISS submodule's media entity | |
806 | * @wait: ISS submodule's wait queue for streamoff/interrupt synchronization | |
807 | * @stopping: flag which tells module wants to stop | |
808 | * | |
809 | * This function checks if ISS submodule needs to wait for next interrupt. If | |
810 | * yes, makes the caller to sleep while waiting for such event. | |
811 | */ | |
812 | int omap4iss_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, | |
813 | atomic_t *stopping) | |
814 | { | |
815 | struct iss_pipeline *pipe = to_iss_pipeline(me); | |
816 | struct iss_video *video = pipe->output; | |
817 | unsigned long flags; | |
818 | ||
819 | if (pipe->stream_state == ISS_PIPELINE_STREAM_STOPPED || | |
820 | (pipe->stream_state == ISS_PIPELINE_STREAM_SINGLESHOT && | |
821 | !iss_pipeline_ready(pipe))) | |
822 | return 0; | |
823 | ||
824 | /* | |
825 | * atomic_set() doesn't include memory barrier on ARM platform for SMP | |
826 | * scenario. We'll call it here to avoid race conditions. | |
827 | */ | |
828 | atomic_set(stopping, 1); | |
829 | smp_wmb(); | |
830 | ||
831 | /* | |
832 | * If module is the last one, it's writing to memory. In this case, | |
833 | * it's necessary to check if the module is already paused due to | |
834 | * DMA queue underrun or if it has to wait for next interrupt to be | |
835 | * idle. | |
836 | * If it isn't the last one, the function won't sleep but *stopping | |
837 | * will still be set to warn next submodule caller's interrupt the | |
838 | * module wants to be idle. | |
839 | */ | |
840 | if (!iss_pipeline_is_last(me)) | |
841 | return 0; | |
842 | ||
843 | spin_lock_irqsave(&video->qlock, flags); | |
844 | if (video->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_UNDERRUN) { | |
845 | spin_unlock_irqrestore(&video->qlock, flags); | |
846 | atomic_set(stopping, 0); | |
847 | smp_wmb(); | |
848 | return 0; | |
849 | } | |
850 | spin_unlock_irqrestore(&video->qlock, flags); | |
851 | if (!wait_event_timeout(*wait, !atomic_read(stopping), | |
852 | msecs_to_jiffies(1000))) { | |
853 | atomic_set(stopping, 0); | |
854 | smp_wmb(); | |
855 | return -ETIMEDOUT; | |
856 | } | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | /* | |
862 | * omap4iss_module_sync_is_stopped - Helper to verify if module was stopping | |
863 | * @wait: ISS submodule's wait queue for streamoff/interrupt synchronization | |
864 | * @stopping: flag which tells module wants to stop | |
865 | * | |
866 | * This function checks if ISS submodule was stopping. In case of yes, it | |
867 | * notices the caller by setting stopping to 0 and waking up the wait queue. | |
868 | * Returns 1 if it was stopping or 0 otherwise. | |
869 | */ | |
870 | int omap4iss_module_sync_is_stopping(wait_queue_head_t *wait, | |
871 | atomic_t *stopping) | |
872 | { | |
873 | if (atomic_cmpxchg(stopping, 1, 0)) { | |
874 | wake_up(wait); | |
875 | return 1; | |
876 | } | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | /* -------------------------------------------------------------------------- | |
882 | * Clock management | |
883 | */ | |
884 | ||
885 | #define ISS_CLKCTRL_MASK (ISS_CLKCTRL_CSI2_A |\ | |
886 | ISS_CLKCTRL_CSI2_B |\ | |
887 | ISS_CLKCTRL_ISP) | |
888 | ||
889 | static int __iss_subclk_update(struct iss_device *iss) | |
890 | { | |
891 | u32 clk = 0; | |
892 | int ret = 0, timeout = 1000; | |
893 | ||
894 | if (iss->subclk_resources & OMAP4_ISS_SUBCLK_CSI2_A) | |
895 | clk |= ISS_CLKCTRL_CSI2_A; | |
896 | ||
897 | if (iss->subclk_resources & OMAP4_ISS_SUBCLK_CSI2_B) | |
898 | clk |= ISS_CLKCTRL_CSI2_B; | |
899 | ||
900 | if (iss->subclk_resources & OMAP4_ISS_SUBCLK_ISP) | |
901 | clk |= ISS_CLKCTRL_ISP; | |
902 | ||
11abbfd3 LP |
903 | iss_reg_update(iss, OMAP4_ISS_MEM_TOP, ISS_CLKCTRL, |
904 | ISS_CLKCTRL_MASK, clk); | |
59f0ad80 SA |
905 | |
906 | /* Wait for HW assertion */ | |
907 | while (--timeout > 0) { | |
908 | udelay(1); | |
11abbfd3 LP |
909 | if ((iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_CLKSTAT) & |
910 | ISS_CLKCTRL_MASK) == clk) | |
59f0ad80 SA |
911 | break; |
912 | } | |
913 | ||
914 | if (!timeout) | |
915 | ret = -EBUSY; | |
916 | ||
917 | return ret; | |
918 | } | |
919 | ||
920 | int omap4iss_subclk_enable(struct iss_device *iss, | |
921 | enum iss_subclk_resource res) | |
922 | { | |
923 | iss->subclk_resources |= res; | |
924 | ||
925 | return __iss_subclk_update(iss); | |
926 | } | |
927 | ||
928 | int omap4iss_subclk_disable(struct iss_device *iss, | |
929 | enum iss_subclk_resource res) | |
930 | { | |
931 | iss->subclk_resources &= ~res; | |
932 | ||
933 | return __iss_subclk_update(iss); | |
934 | } | |
935 | ||
936 | #define ISS_ISP5_CLKCTRL_MASK (ISP5_CTRL_BL_CLK_ENABLE |\ | |
937 | ISP5_CTRL_ISIF_CLK_ENABLE |\ | |
938 | ISP5_CTRL_H3A_CLK_ENABLE |\ | |
939 | ISP5_CTRL_RSZ_CLK_ENABLE |\ | |
940 | ISP5_CTRL_IPIPE_CLK_ENABLE |\ | |
941 | ISP5_CTRL_IPIPEIF_CLK_ENABLE) | |
942 | ||
68c03a66 | 943 | static void __iss_isp_subclk_update(struct iss_device *iss) |
59f0ad80 SA |
944 | { |
945 | u32 clk = 0; | |
946 | ||
947 | if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_ISIF) | |
948 | clk |= ISP5_CTRL_ISIF_CLK_ENABLE; | |
949 | ||
950 | if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_H3A) | |
951 | clk |= ISP5_CTRL_H3A_CLK_ENABLE; | |
952 | ||
953 | if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_RSZ) | |
954 | clk |= ISP5_CTRL_RSZ_CLK_ENABLE; | |
955 | ||
956 | if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_IPIPE) | |
957 | clk |= ISP5_CTRL_IPIPE_CLK_ENABLE; | |
958 | ||
959 | if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_IPIPEIF) | |
960 | clk |= ISP5_CTRL_IPIPEIF_CLK_ENABLE; | |
961 | ||
962 | if (clk) | |
963 | clk |= ISP5_CTRL_BL_CLK_ENABLE; | |
964 | ||
11abbfd3 LP |
965 | iss_reg_update(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL, |
966 | ISS_ISP5_CLKCTRL_MASK, clk); | |
59f0ad80 SA |
967 | } |
968 | ||
68c03a66 | 969 | void omap4iss_isp_subclk_enable(struct iss_device *iss, |
59f0ad80 SA |
970 | enum iss_isp_subclk_resource res) |
971 | { | |
972 | iss->isp_subclk_resources |= res; | |
973 | ||
68c03a66 | 974 | __iss_isp_subclk_update(iss); |
59f0ad80 SA |
975 | } |
976 | ||
68c03a66 LP |
977 | void omap4iss_isp_subclk_disable(struct iss_device *iss, |
978 | enum iss_isp_subclk_resource res) | |
59f0ad80 SA |
979 | { |
980 | iss->isp_subclk_resources &= ~res; | |
981 | ||
68c03a66 | 982 | __iss_isp_subclk_update(iss); |
59f0ad80 SA |
983 | } |
984 | ||
985 | /* | |
986 | * iss_enable_clocks - Enable ISS clocks | |
987 | * @iss: OMAP4 ISS device | |
988 | * | |
989 | * Return 0 if successful, or clk_enable return value if any of tthem fails. | |
990 | */ | |
991 | static int iss_enable_clocks(struct iss_device *iss) | |
992 | { | |
2b16b44a | 993 | int ret; |
59f0ad80 | 994 | |
2b16b44a LP |
995 | ret = clk_enable(iss->iss_fck); |
996 | if (ret) { | |
59f0ad80 | 997 | dev_err(iss->dev, "clk_enable iss_fck failed\n"); |
2b16b44a | 998 | return ret; |
59f0ad80 SA |
999 | } |
1000 | ||
2b16b44a LP |
1001 | ret = clk_enable(iss->iss_ctrlclk); |
1002 | if (ret) { | |
59f0ad80 | 1003 | dev_err(iss->dev, "clk_enable iss_ctrlclk failed\n"); |
2b16b44a LP |
1004 | clk_disable(iss->iss_fck); |
1005 | return ret; | |
59f0ad80 | 1006 | } |
59f0ad80 | 1007 | |
2b16b44a | 1008 | return 0; |
59f0ad80 SA |
1009 | } |
1010 | ||
1011 | /* | |
1012 | * iss_disable_clocks - Disable ISS clocks | |
1013 | * @iss: OMAP4 ISS device | |
1014 | */ | |
1015 | static void iss_disable_clocks(struct iss_device *iss) | |
1016 | { | |
1017 | clk_disable(iss->iss_ctrlclk); | |
1018 | clk_disable(iss->iss_fck); | |
1019 | } | |
1020 | ||
59f0ad80 SA |
1021 | static int iss_get_clocks(struct iss_device *iss) |
1022 | { | |
1153be56 | 1023 | iss->iss_fck = devm_clk_get(iss->dev, "iss_fck"); |
59f0ad80 SA |
1024 | if (IS_ERR(iss->iss_fck)) { |
1025 | dev_err(iss->dev, "Unable to get iss_fck clock info\n"); | |
59f0ad80 SA |
1026 | return PTR_ERR(iss->iss_fck); |
1027 | } | |
1028 | ||
1153be56 | 1029 | iss->iss_ctrlclk = devm_clk_get(iss->dev, "iss_ctrlclk"); |
59f0ad80 SA |
1030 | if (IS_ERR(iss->iss_ctrlclk)) { |
1031 | dev_err(iss->dev, "Unable to get iss_ctrlclk clock info\n"); | |
057ef1e5 | 1032 | return PTR_ERR(iss->iss_ctrlclk); |
59f0ad80 SA |
1033 | } |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | /* | |
1039 | * omap4iss_get - Acquire the ISS resource. | |
1040 | * | |
1041 | * Initializes the clocks for the first acquire. | |
1042 | * | |
1043 | * Increment the reference count on the ISS. If the first reference is taken, | |
1044 | * enable clocks and power-up all submodules. | |
1045 | * | |
1046 | * Return a pointer to the ISS device structure, or NULL if an error occurred. | |
1047 | */ | |
1048 | struct iss_device *omap4iss_get(struct iss_device *iss) | |
1049 | { | |
1050 | struct iss_device *__iss = iss; | |
1051 | ||
1052 | if (iss == NULL) | |
1053 | return NULL; | |
1054 | ||
1055 | mutex_lock(&iss->iss_mutex); | |
1056 | if (iss->ref_count > 0) | |
1057 | goto out; | |
1058 | ||
1059 | if (iss_enable_clocks(iss) < 0) { | |
1060 | __iss = NULL; | |
1061 | goto out; | |
1062 | } | |
1063 | ||
1064 | iss_enable_interrupts(iss); | |
1065 | ||
1066 | out: | |
1067 | if (__iss != NULL) | |
1068 | iss->ref_count++; | |
1069 | mutex_unlock(&iss->iss_mutex); | |
1070 | ||
1071 | return __iss; | |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * omap4iss_put - Release the ISS | |
1076 | * | |
1077 | * Decrement the reference count on the ISS. If the last reference is released, | |
1078 | * power-down all submodules, disable clocks and free temporary buffers. | |
1079 | */ | |
1080 | void omap4iss_put(struct iss_device *iss) | |
1081 | { | |
1082 | if (iss == NULL) | |
1083 | return; | |
1084 | ||
1085 | mutex_lock(&iss->iss_mutex); | |
1086 | BUG_ON(iss->ref_count == 0); | |
1087 | if (--iss->ref_count == 0) { | |
1088 | iss_disable_interrupts(iss); | |
f3632ba8 LP |
1089 | /* Reset the ISS if an entity has failed to stop. This is the |
1090 | * only way to recover from such conditions, although it would | |
1091 | * be worth investigating whether resetting the ISP only can't | |
1092 | * fix the problem in some cases. | |
1093 | */ | |
1094 | if (iss->crashed) | |
1095 | iss_reset(iss); | |
59f0ad80 SA |
1096 | iss_disable_clocks(iss); |
1097 | } | |
1098 | mutex_unlock(&iss->iss_mutex); | |
1099 | } | |
1100 | ||
1101 | static int iss_map_mem_resource(struct platform_device *pdev, | |
1102 | struct iss_device *iss, | |
1103 | enum iss_mem_resources res) | |
1104 | { | |
1105 | struct resource *mem; | |
1106 | ||
59f0ad80 | 1107 | mem = platform_get_resource(pdev, IORESOURCE_MEM, res); |
59f0ad80 | 1108 | |
1153be56 | 1109 | iss->regs[res] = devm_ioremap_resource(iss->dev, mem); |
59f0ad80 | 1110 | |
1153be56 | 1111 | return PTR_ERR_OR_ZERO(iss->regs[res]); |
59f0ad80 SA |
1112 | } |
1113 | ||
1114 | static void iss_unregister_entities(struct iss_device *iss) | |
1115 | { | |
1116 | omap4iss_resizer_unregister_entities(&iss->resizer); | |
1117 | omap4iss_ipipe_unregister_entities(&iss->ipipe); | |
1118 | omap4iss_ipipeif_unregister_entities(&iss->ipipeif); | |
1119 | omap4iss_csi2_unregister_entities(&iss->csi2a); | |
1120 | omap4iss_csi2_unregister_entities(&iss->csi2b); | |
1121 | ||
1122 | v4l2_device_unregister(&iss->v4l2_dev); | |
1123 | media_device_unregister(&iss->media_dev); | |
1124 | } | |
1125 | ||
1126 | /* | |
1127 | * iss_register_subdev_group - Register a group of subdevices | |
1128 | * @iss: OMAP4 ISS device | |
1129 | * @board_info: I2C subdevs board information array | |
1130 | * | |
1131 | * Register all I2C subdevices in the board_info array. The array must be | |
1132 | * terminated by a NULL entry, and the first entry must be the sensor. | |
1133 | * | |
1134 | * Return a pointer to the sensor media entity if it has been successfully | |
1135 | * registered, or NULL otherwise. | |
1136 | */ | |
1137 | static struct v4l2_subdev * | |
1138 | iss_register_subdev_group(struct iss_device *iss, | |
1139 | struct iss_subdev_i2c_board_info *board_info) | |
1140 | { | |
1141 | struct v4l2_subdev *sensor = NULL; | |
1142 | unsigned int first; | |
1143 | ||
1144 | if (board_info->board_info == NULL) | |
1145 | return NULL; | |
1146 | ||
1147 | for (first = 1; board_info->board_info; ++board_info, first = 0) { | |
1148 | struct v4l2_subdev *subdev; | |
1149 | struct i2c_adapter *adapter; | |
1150 | ||
1151 | adapter = i2c_get_adapter(board_info->i2c_adapter_id); | |
1152 | if (adapter == NULL) { | |
499226fb LP |
1153 | dev_err(iss->dev, |
1154 | "%s: Unable to get I2C adapter %d for device %s\n", | |
1155 | __func__, board_info->i2c_adapter_id, | |
59f0ad80 SA |
1156 | board_info->board_info->type); |
1157 | continue; | |
1158 | } | |
1159 | ||
1160 | subdev = v4l2_i2c_new_subdev_board(&iss->v4l2_dev, adapter, | |
1161 | board_info->board_info, NULL); | |
1162 | if (subdev == NULL) { | |
1163 | dev_err(iss->dev, "%s: Unable to register subdev %s\n", | |
1164 | __func__, board_info->board_info->type); | |
1165 | continue; | |
1166 | } | |
1167 | ||
1168 | if (first) | |
1169 | sensor = subdev; | |
1170 | } | |
1171 | ||
1172 | return sensor; | |
1173 | } | |
1174 | ||
1175 | static int iss_register_entities(struct iss_device *iss) | |
1176 | { | |
1177 | struct iss_platform_data *pdata = iss->pdata; | |
1178 | struct iss_v4l2_subdevs_group *subdevs; | |
1179 | int ret; | |
1180 | ||
1181 | iss->media_dev.dev = iss->dev; | |
1182 | strlcpy(iss->media_dev.model, "TI OMAP4 ISS", | |
1183 | sizeof(iss->media_dev.model)); | |
1184 | iss->media_dev.hw_revision = iss->revision; | |
1185 | iss->media_dev.link_notify = iss_pipeline_link_notify; | |
1186 | ret = media_device_register(&iss->media_dev); | |
1187 | if (ret < 0) { | |
4cd89e91 | 1188 | dev_err(iss->dev, "%s: Media device registration failed (%d)\n", |
59f0ad80 SA |
1189 | __func__, ret); |
1190 | return ret; | |
1191 | } | |
1192 | ||
1193 | iss->v4l2_dev.mdev = &iss->media_dev; | |
1194 | ret = v4l2_device_register(iss->dev, &iss->v4l2_dev); | |
1195 | if (ret < 0) { | |
4cd89e91 | 1196 | dev_err(iss->dev, "%s: V4L2 device registration failed (%d)\n", |
59f0ad80 SA |
1197 | __func__, ret); |
1198 | goto done; | |
1199 | } | |
1200 | ||
1201 | /* Register internal entities */ | |
1202 | ret = omap4iss_csi2_register_entities(&iss->csi2a, &iss->v4l2_dev); | |
1203 | if (ret < 0) | |
1204 | goto done; | |
1205 | ||
1206 | ret = omap4iss_csi2_register_entities(&iss->csi2b, &iss->v4l2_dev); | |
1207 | if (ret < 0) | |
1208 | goto done; | |
1209 | ||
1210 | ret = omap4iss_ipipeif_register_entities(&iss->ipipeif, &iss->v4l2_dev); | |
1211 | if (ret < 0) | |
1212 | goto done; | |
1213 | ||
1214 | ret = omap4iss_ipipe_register_entities(&iss->ipipe, &iss->v4l2_dev); | |
1215 | if (ret < 0) | |
1216 | goto done; | |
1217 | ||
1218 | ret = omap4iss_resizer_register_entities(&iss->resizer, &iss->v4l2_dev); | |
1219 | if (ret < 0) | |
1220 | goto done; | |
1221 | ||
1222 | /* Register external entities */ | |
1223 | for (subdevs = pdata->subdevs; subdevs && subdevs->subdevs; ++subdevs) { | |
1224 | struct v4l2_subdev *sensor; | |
1225 | struct media_entity *input; | |
1226 | unsigned int flags; | |
1227 | unsigned int pad; | |
1228 | ||
1229 | sensor = iss_register_subdev_group(iss, subdevs->subdevs); | |
1230 | if (sensor == NULL) | |
1231 | continue; | |
1232 | ||
1233 | sensor->host_priv = subdevs; | |
1234 | ||
1235 | /* Connect the sensor to the correct interface module. | |
1236 | * CSI2a receiver through CSIPHY1, or | |
1237 | * CSI2b receiver through CSIPHY2 | |
1238 | */ | |
1239 | switch (subdevs->interface) { | |
1240 | case ISS_INTERFACE_CSI2A_PHY1: | |
1241 | input = &iss->csi2a.subdev.entity; | |
1242 | pad = CSI2_PAD_SINK; | |
1243 | flags = MEDIA_LNK_FL_IMMUTABLE | |
1244 | | MEDIA_LNK_FL_ENABLED; | |
1245 | break; | |
1246 | ||
1247 | case ISS_INTERFACE_CSI2B_PHY2: | |
1248 | input = &iss->csi2b.subdev.entity; | |
1249 | pad = CSI2_PAD_SINK; | |
1250 | flags = MEDIA_LNK_FL_IMMUTABLE | |
1251 | | MEDIA_LNK_FL_ENABLED; | |
1252 | break; | |
1253 | ||
1254 | default: | |
4cd89e91 LP |
1255 | dev_err(iss->dev, "%s: invalid interface type %u\n", |
1256 | __func__, subdevs->interface); | |
59f0ad80 SA |
1257 | ret = -EINVAL; |
1258 | goto done; | |
1259 | } | |
1260 | ||
1261 | ret = media_entity_create_link(&sensor->entity, 0, input, pad, | |
1262 | flags); | |
1263 | if (ret < 0) | |
1264 | goto done; | |
1265 | } | |
1266 | ||
1267 | ret = v4l2_device_register_subdev_nodes(&iss->v4l2_dev); | |
1268 | ||
1269 | done: | |
1270 | if (ret < 0) | |
1271 | iss_unregister_entities(iss); | |
1272 | ||
1273 | return ret; | |
1274 | } | |
1275 | ||
1276 | static void iss_cleanup_modules(struct iss_device *iss) | |
1277 | { | |
1278 | omap4iss_csi2_cleanup(iss); | |
1279 | omap4iss_ipipeif_cleanup(iss); | |
1280 | omap4iss_ipipe_cleanup(iss); | |
1281 | omap4iss_resizer_cleanup(iss); | |
1282 | } | |
1283 | ||
1284 | static int iss_initialize_modules(struct iss_device *iss) | |
1285 | { | |
1286 | int ret; | |
1287 | ||
1288 | ret = omap4iss_csiphy_init(iss); | |
1289 | if (ret < 0) { | |
1290 | dev_err(iss->dev, "CSI PHY initialization failed\n"); | |
1291 | goto error_csiphy; | |
1292 | } | |
1293 | ||
1294 | ret = omap4iss_csi2_init(iss); | |
1295 | if (ret < 0) { | |
1296 | dev_err(iss->dev, "CSI2 initialization failed\n"); | |
1297 | goto error_csi2; | |
1298 | } | |
1299 | ||
1300 | ret = omap4iss_ipipeif_init(iss); | |
1301 | if (ret < 0) { | |
1302 | dev_err(iss->dev, "ISP IPIPEIF initialization failed\n"); | |
1303 | goto error_ipipeif; | |
1304 | } | |
1305 | ||
1306 | ret = omap4iss_ipipe_init(iss); | |
1307 | if (ret < 0) { | |
1308 | dev_err(iss->dev, "ISP IPIPE initialization failed\n"); | |
1309 | goto error_ipipe; | |
1310 | } | |
1311 | ||
1312 | ret = omap4iss_resizer_init(iss); | |
1313 | if (ret < 0) { | |
1314 | dev_err(iss->dev, "ISP RESIZER initialization failed\n"); | |
1315 | goto error_resizer; | |
1316 | } | |
1317 | ||
1318 | /* Connect the submodules. */ | |
1319 | ret = media_entity_create_link( | |
1320 | &iss->csi2a.subdev.entity, CSI2_PAD_SOURCE, | |
1321 | &iss->ipipeif.subdev.entity, IPIPEIF_PAD_SINK, 0); | |
1322 | if (ret < 0) | |
1323 | goto error_link; | |
1324 | ||
1325 | ret = media_entity_create_link( | |
1326 | &iss->csi2b.subdev.entity, CSI2_PAD_SOURCE, | |
1327 | &iss->ipipeif.subdev.entity, IPIPEIF_PAD_SINK, 0); | |
1328 | if (ret < 0) | |
1329 | goto error_link; | |
1330 | ||
1331 | ret = media_entity_create_link( | |
1332 | &iss->ipipeif.subdev.entity, IPIPEIF_PAD_SOURCE_VP, | |
1333 | &iss->resizer.subdev.entity, RESIZER_PAD_SINK, 0); | |
1334 | if (ret < 0) | |
1335 | goto error_link; | |
1336 | ||
1337 | ret = media_entity_create_link( | |
1338 | &iss->ipipeif.subdev.entity, IPIPEIF_PAD_SOURCE_VP, | |
1339 | &iss->ipipe.subdev.entity, IPIPE_PAD_SINK, 0); | |
1340 | if (ret < 0) | |
1341 | goto error_link; | |
1342 | ||
1343 | ret = media_entity_create_link( | |
1344 | &iss->ipipe.subdev.entity, IPIPE_PAD_SOURCE_VP, | |
1345 | &iss->resizer.subdev.entity, RESIZER_PAD_SINK, 0); | |
1346 | if (ret < 0) | |
1347 | goto error_link; | |
1348 | ||
1349 | return 0; | |
1350 | ||
1351 | error_link: | |
1352 | omap4iss_resizer_cleanup(iss); | |
1353 | error_resizer: | |
1354 | omap4iss_ipipe_cleanup(iss); | |
1355 | error_ipipe: | |
1356 | omap4iss_ipipeif_cleanup(iss); | |
1357 | error_ipipeif: | |
1358 | omap4iss_csi2_cleanup(iss); | |
1359 | error_csi2: | |
1360 | error_csiphy: | |
1361 | return ret; | |
1362 | } | |
1363 | ||
1364 | static int iss_probe(struct platform_device *pdev) | |
1365 | { | |
1366 | struct iss_platform_data *pdata = pdev->dev.platform_data; | |
1367 | struct iss_device *iss; | |
4334fd18 LP |
1368 | unsigned int i; |
1369 | int ret; | |
59f0ad80 SA |
1370 | |
1371 | if (pdata == NULL) | |
1372 | return -EINVAL; | |
1373 | ||
1153be56 | 1374 | iss = devm_kzalloc(&pdev->dev, sizeof(*iss), GFP_KERNEL); |
b717a65a | 1375 | if (!iss) |
59f0ad80 | 1376 | return -ENOMEM; |
59f0ad80 SA |
1377 | |
1378 | mutex_init(&iss->iss_mutex); | |
1379 | ||
1380 | iss->dev = &pdev->dev; | |
1381 | iss->pdata = pdata; | |
59f0ad80 SA |
1382 | |
1383 | iss->raw_dmamask = DMA_BIT_MASK(32); | |
1384 | iss->dev->dma_mask = &iss->raw_dmamask; | |
1385 | iss->dev->coherent_dma_mask = DMA_BIT_MASK(32); | |
1386 | ||
1387 | platform_set_drvdata(pdev, iss); | |
1388 | ||
1389 | /* Clocks */ | |
1390 | ret = iss_map_mem_resource(pdev, iss, OMAP4_ISS_MEM_TOP); | |
1391 | if (ret < 0) | |
1392 | goto error; | |
1393 | ||
1394 | ret = iss_get_clocks(iss); | |
1395 | if (ret < 0) | |
1396 | goto error; | |
1397 | ||
1398 | if (omap4iss_get(iss) == NULL) | |
1399 | goto error; | |
1400 | ||
1401 | ret = iss_reset(iss); | |
1402 | if (ret < 0) | |
1403 | goto error_iss; | |
1404 | ||
11abbfd3 | 1405 | iss->revision = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION); |
59f0ad80 SA |
1406 | dev_info(iss->dev, "Revision %08x found\n", iss->revision); |
1407 | ||
1408 | for (i = 1; i < OMAP4_ISS_MEM_LAST; i++) { | |
1409 | ret = iss_map_mem_resource(pdev, iss, i); | |
1410 | if (ret) | |
1411 | goto error_iss; | |
1412 | } | |
1413 | ||
1414 | /* Configure BTE BW_LIMITER field to max recommended value (1 GB) */ | |
11abbfd3 LP |
1415 | iss_reg_update(iss, OMAP4_ISS_MEM_BTE, BTE_CTRL, |
1416 | BTE_CTRL_BW_LIMITER_MASK, | |
1417 | 18 << BTE_CTRL_BW_LIMITER_SHIFT); | |
59f0ad80 SA |
1418 | |
1419 | /* Perform ISP reset */ | |
1420 | ret = omap4iss_subclk_enable(iss, OMAP4_ISS_SUBCLK_ISP); | |
1421 | if (ret < 0) | |
1422 | goto error_iss; | |
1423 | ||
1424 | ret = iss_isp_reset(iss); | |
1425 | if (ret < 0) | |
1426 | goto error_iss; | |
1427 | ||
1428 | dev_info(iss->dev, "ISP Revision %08x found\n", | |
11abbfd3 | 1429 | iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_REVISION)); |
59f0ad80 SA |
1430 | |
1431 | /* Interrupt */ | |
1432 | iss->irq_num = platform_get_irq(pdev, 0); | |
1433 | if (iss->irq_num <= 0) { | |
1434 | dev_err(iss->dev, "No IRQ resource\n"); | |
1435 | ret = -ENODEV; | |
1436 | goto error_iss; | |
1437 | } | |
1438 | ||
1153be56 LP |
1439 | if (devm_request_irq(iss->dev, iss->irq_num, iss_isr, IRQF_SHARED, |
1440 | "OMAP4 ISS", iss)) { | |
59f0ad80 SA |
1441 | dev_err(iss->dev, "Unable to request IRQ\n"); |
1442 | ret = -EINVAL; | |
1443 | goto error_iss; | |
1444 | } | |
1445 | ||
1446 | /* Entities */ | |
1447 | ret = iss_initialize_modules(iss); | |
1448 | if (ret < 0) | |
1153be56 | 1449 | goto error_iss; |
59f0ad80 SA |
1450 | |
1451 | ret = iss_register_entities(iss); | |
1452 | if (ret < 0) | |
1453 | goto error_modules; | |
1454 | ||
1455 | omap4iss_put(iss); | |
1456 | ||
1457 | return 0; | |
1458 | ||
1459 | error_modules: | |
1460 | iss_cleanup_modules(iss); | |
59f0ad80 SA |
1461 | error_iss: |
1462 | omap4iss_put(iss); | |
1463 | error: | |
59f0ad80 SA |
1464 | platform_set_drvdata(pdev, NULL); |
1465 | ||
1466 | mutex_destroy(&iss->iss_mutex); | |
59f0ad80 SA |
1467 | |
1468 | return ret; | |
1469 | } | |
1470 | ||
1471 | static int iss_remove(struct platform_device *pdev) | |
1472 | { | |
1473 | struct iss_device *iss = platform_get_drvdata(pdev); | |
59f0ad80 SA |
1474 | |
1475 | iss_unregister_entities(iss); | |
1476 | iss_cleanup_modules(iss); | |
1477 | ||
59f0ad80 SA |
1478 | return 0; |
1479 | } | |
1480 | ||
1481 | static struct platform_device_id omap4iss_id_table[] = { | |
1482 | { "omap4iss", 0 }, | |
1483 | { }, | |
1484 | }; | |
1485 | MODULE_DEVICE_TABLE(platform, omap4iss_id_table); | |
1486 | ||
1487 | static struct platform_driver iss_driver = { | |
1488 | .probe = iss_probe, | |
1489 | .remove = iss_remove, | |
1490 | .id_table = omap4iss_id_table, | |
1491 | .driver = { | |
59f0ad80 SA |
1492 | .name = "omap4iss", |
1493 | }, | |
1494 | }; | |
1495 | ||
1496 | module_platform_driver(iss_driver); | |
1497 | ||
1498 | MODULE_DESCRIPTION("TI OMAP4 ISS driver"); | |
1499 | MODULE_AUTHOR("Sergio Aguirre <sergio.a.aguirre@gmail.com>"); | |
1500 | MODULE_LICENSE("GPL"); | |
1501 | MODULE_VERSION(ISS_VIDEO_DRIVER_VERSION); |