[deliverable/linux.git] / drivers / staging / media / solo6x10 / p2m.c

/*
 * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
 *
 * Original author:
 * Ben Collins <bcollins@ubuntu.com>
 *
 * Additional work by:
 * John Brooks <john.brooks@bluecherry.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>

#include "solo6x10.h"

static int multi_p2m;
module_param(multi_p2m, uint, 0644);
MODULE_PARM_DESC(multi_p2m,
		 "Use multiple P2M DMA channels (default: no, 6010-only)");

static int desc_mode;
module_param(desc_mode, uint, 0644);
MODULE_PARM_DESC(desc_mode,
		 "Allow use of descriptor mode DMA (default: no, 6010-only)");

int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
		 void *sys_addr, u32 ext_addr, u32 size,
		 int repeat, u32 ext_size)
{
	dma_addr_t dma_addr;
	int ret;

	if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
		return -EINVAL;
	if (WARN_ON_ONCE(!size))
		return -EINVAL;

	dma_addr = pci_map_single(solo_dev->pdev, sys_addr, size,
				  wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
	if (pci_dma_mapping_error(solo_dev->pdev, dma_addr))
		return -ENOMEM;

	ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
			     repeat, ext_size);

	pci_unmap_single(solo_dev->pdev, dma_addr, size,
			 wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);

	return ret;
}

/* Mutex must be held for p2m_id before calling this!! */
int solo_p2m_dma_desc(struct solo_dev *solo_dev,
		      struct solo_p2m_desc *desc, dma_addr_t desc_dma,
		      int desc_cnt)
{
	struct solo_p2m_dev *p2m_dev;
	unsigned int timeout;
	unsigned int config = 0;
	int ret = 0;
	int p2m_id = 0;

	/* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
	if (solo_dev->type != SOLO_DEV_6110 && multi_p2m) {
		p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;
		if (p2m_id < 0)
			p2m_id = -p2m_id;
	}

	p2m_dev = &solo_dev->p2m_dev[p2m_id];

	if (mutex_lock_interruptible(&p2m_dev->mutex))
		return -EINTR;

	INIT_COMPLETION(p2m_dev->completion);
	p2m_dev->error = 0;

	if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
		/* For 6010 with more than one desc, we can do a one-shot */
		p2m_dev->desc_count = p2m_dev->desc_idx = 0;
		config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));

		solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
		solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
		solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config |
			       SOLO_P2M_DESC_MODE);
	} else {
		/* For single descriptors and 6110, we need to run each desc */
		p2m_dev->desc_count = desc_cnt;
		p2m_dev->desc_idx = 1;
		p2m_dev->descs = desc;

		solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
			       desc[1].dma_addr);
		solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
			       desc[1].ext_addr);
		solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
			       desc[1].cfg);
		solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
			       desc[1].ctrl);
	}

	timeout = wait_for_completion_timeout(&p2m_dev->completion,
					      solo_dev->p2m_jiffies);

	if (WARN_ON_ONCE(p2m_dev->error))
		ret = -EIO;
	else if (timeout == 0) {
		solo_dev->p2m_timeouts++;
		ret = -EAGAIN;
	}

	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);

	/* Don't write here for the no_desc_mode case, because config is 0.
	 * We can't test no_desc_mode again, it might race. */
	if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
		solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);

	mutex_unlock(&p2m_dev->mutex);

	return ret;
}

void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
			dma_addr_t dma_addr, u32 ext_addr, u32 size,
			int repeat, u32 ext_size)
{
	WARN_ON_ONCE(dma_addr & 0x03);
	WARN_ON_ONCE(!size);

	desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
	desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) |
		(wr ? SOLO_P2M_WRITE : 0) | SOLO_P2M_TRANS_ON;

	if (repeat) {
		desc->cfg |= SOLO_P2M_EXT_INC(ext_size >> 2);
		desc->ctrl |=  SOLO_P2M_PCI_INC(size >> 2) |
			 SOLO_P2M_REPEAT(repeat);
	}

	desc->dma_addr = dma_addr;
	desc->ext_addr = ext_addr;
}

int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
		   dma_addr_t dma_addr, u32 ext_addr, u32 size,
		   int repeat, u32 ext_size)
{
	struct solo_p2m_desc desc[2];

	solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
			   ext_size);

	/* No need for desc_dma since we know it is a single-shot */
	return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
}

void solo_p2m_isr(struct solo_dev *solo_dev, int id)
{
	struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
	struct solo_p2m_desc *desc;

	if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
		complete(&p2m_dev->completion);
		return;
	}

	/* Setup next descriptor */
	p2m_dev->desc_idx++;
	desc = &p2m_dev->descs[p2m_dev->desc_idx];

	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
	solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
	solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
	solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
}

void solo_p2m_error_isr(struct solo_dev *solo_dev)
{
	unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
	struct solo_p2m_dev *p2m_dev;
	int i;

	if (!(err & (SOLO_PCI_ERR_P2M | SOLO_PCI_ERR_P2M_DESC)))
		return;

	for (i = 0; i < SOLO_NR_P2M; i++) {
		p2m_dev = &solo_dev->p2m_dev[i];
		p2m_dev->error = 1;
		solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
		complete(&p2m_dev->completion);
	}
}

void solo_p2m_exit(struct solo_dev *solo_dev)
{
	int i;

	for (i = 0; i < SOLO_NR_P2M; i++)
		solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
}

static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
{
	u32 *wr_buf;
	u32 *rd_buf;
	int i;
	int ret = -EIO;
	int order = get_order(size);

	wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
	if (wr_buf == NULL)
		return -1;

	rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
	if (rd_buf == NULL) {
		free_pages((unsigned long)wr_buf, order);
		return -1;
	}

	for (i = 0; i < (size >> 3); i++)
		*(wr_buf + i) = (i << 16) | (i + 1);

	for (i = (size >> 3); i < (size >> 2); i++)
		*(wr_buf + i) = ~((i << 16) | (i + 1));

	memset(rd_buf, 0x55, size);

	if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
		goto test_fail;

	if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
		goto test_fail;

	for (i = 0; i < (size >> 2); i++) {
		if (*(wr_buf + i) != *(rd_buf + i))
			goto test_fail;
	}

	ret = 0;

test_fail:
	free_pages((unsigned long)wr_buf, order);
	free_pages((unsigned long)rd_buf, order);

	return ret;
}

int solo_p2m_init(struct solo_dev *solo_dev)
{
	struct solo_p2m_dev *p2m_dev;
	int i;

	for (i = 0; i < SOLO_NR_P2M; i++) {
		p2m_dev = &solo_dev->p2m_dev[i];

		mutex_init(&p2m_dev->mutex);
		init_completion(&p2m_dev->completion);

		solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
		solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
			       SOLO_P2M_CSC_16BIT_565 |
			       SOLO_P2M_DESC_INTR_OPT |
			       SOLO_P2M_DMA_INTERVAL(0) |
			       SOLO_P2M_PCI_MASTER_MODE);
		solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
	}

	/* Find correct SDRAM size */
	for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
		solo_reg_write(solo_dev, SOLO_DMA_CTRL,
			       SOLO_DMA_CTRL_REFRESH_CYCLE(1) |
			       SOLO_DMA_CTRL_SDRAM_SIZE(i) |
			       SOLO_DMA_CTRL_SDRAM_CLK_INVERT |
			       SOLO_DMA_CTRL_READ_CLK_SELECT |
			       SOLO_DMA_CTRL_LATENCY(1));

		solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config |
			       SOLO_SYS_CFG_RESET);
		solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);

		switch (i) {
		case 2:
			if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) ||
			    solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
				continue;
			break;

		case 1:
			if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
				continue;
			break;

		default:
			if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
				continue;
		}

		solo_dev->sdram_size = (32 << 20) << i;
		break;
	}

	if (!solo_dev->sdram_size) {
		dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
		return -EIO;
	}

	if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
		dev_err(&solo_dev->pdev->dev,
			"SDRAM is not large enough (%u < %u)\n",
			solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
		return -EIO;
	}

	return 0;
}
Commit	Line	Data
faa4fd2a	1	/*
dcae5dac HV	2	* Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
	3	*
	4	* Original author:
	5	* Ben Collins <bcollins@ubuntu.com>
	6	*
	7	* Additional work by:
	8	* John Brooks <john.brooks@bluecherry.net>
faa4fd2a BC	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	23	*/
	24
	25	#include <linux/kernel.h>
dcae5dac	26	#include <linux/module.h>
7b4785f4	27	#include <linux/slab.h>
dcae5dac	28
ae69b22c	29	#include "solo6x10.h"
faa4fd2a	30
dcae5dac HV	31	static int multi_p2m;
	32	module_param(multi_p2m, uint, 0644);
	33	MODULE_PARM_DESC(multi_p2m,
	34	"Use multiple P2M DMA channels (default: no, 6010-only)");
faa4fd2a	35
dcae5dac HV	36	static int desc_mode;
	37	module_param(desc_mode, uint, 0644);
	38	MODULE_PARM_DESC(desc_mode,
	39	"Allow use of descriptor mode DMA (default: no, 6010-only)");
	40
	41	int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
	42	void *sys_addr, u32 ext_addr, u32 size,
	43	int repeat, u32 ext_size)
faa4fd2a BC	44	{
	45	dma_addr_t dma_addr;
	46	int ret;
	47
dcae5dac HV	48	if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
	49	return -EINVAL;
	50	if (WARN_ON_ONCE(!size))
faa4fd2a BC	51	return -EINVAL;
	52
	53	dma_addr = pci_map_single(solo_dev->pdev, sys_addr, size,
	54	wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
f43afb1e HV	55	if (pci_dma_mapping_error(solo_dev->pdev, dma_addr))
f43afb1e HV	56	return -ENOMEM;
faa4fd2a	57
dcae5dac HV	58	ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
dcae5dac HV	59	repeat, ext_size);
faa4fd2a BC	60
	61	pci_unmap_single(solo_dev->pdev, dma_addr, size,
	62	wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
	63
	64	return ret;
	65	}
	66
dcae5dac HV	67	/* Mutex must be held for p2m_id before calling this!! */
	68	int solo_p2m_dma_desc(struct solo_dev *solo_dev,
	69	struct solo_p2m_desc *desc, dma_addr_t desc_dma,
	70	int desc_cnt)
faa4fd2a BC	71	{
faa4fd2a BC	72	struct solo_p2m_dev *p2m_dev;
f62de9be	73	unsigned int timeout;
dcae5dac	74	unsigned int config = 0;
f62de9be	75	int ret = 0;
dcae5dac	76	int p2m_id = 0;
faa4fd2a	77
dcae5dac HV	78	/* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
	79	if (solo_dev->type != SOLO_DEV_6110 && multi_p2m) {
	80	p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;
	81	if (p2m_id < 0)
	82	p2m_id = -p2m_id;
	83	}
faa4fd2a	84
dcae5dac	85	p2m_dev = &solo_dev->p2m_dev[p2m_id];
faa4fd2a	86
dcae5dac HV	87	if (mutex_lock_interruptible(&p2m_dev->mutex))
dcae5dac HV	88	return -EINTR;
0e4de059	89
faa4fd2a BC	90	INIT_COMPLETION(p2m_dev->completion);
faa4fd2a BC	91	p2m_dev->error = 0;
faa4fd2a	92
dcae5dac HV	93	if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
	94	/* For 6010 with more than one desc, we can do a one-shot */
	95	p2m_dev->desc_count = p2m_dev->desc_idx = 0;
	96	config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));
	97
	98	solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
	99	solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
	100	solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config \|
	101	SOLO_P2M_DESC_MODE);
	102	} else {
	103	/* For single descriptors and 6110, we need to run each desc */
	104	p2m_dev->desc_count = desc_cnt;
	105	p2m_dev->desc_idx = 1;
	106	p2m_dev->descs = desc;
	107
	108	solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
	109	desc[1].dma_addr);
	110	solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
	111	desc[1].ext_addr);
	112	solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
	113	desc[1].cfg);
	114	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
	115	desc[1].ctrl);
	116	}
faa4fd2a	117
dcae5dac HV	118	timeout = wait_for_completion_timeout(&p2m_dev->completion,
dcae5dac HV	119	solo_dev->p2m_jiffies);
0e4de059	120
dcae5dac	121	if (WARN_ON_ONCE(p2m_dev->error))
f62de9be	122	ret = -EIO;
dcae5dac HV	123	else if (timeout == 0) {
dcae5dac HV	124	solo_dev->p2m_timeouts++;
f62de9be	125	ret = -EAGAIN;
f62de9be BC	126	}
f62de9be BC	127
dcae5dac	128	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);
f62de9be	129
dcae5dac HV	130	/* Don't write here for the no_desc_mode case, because config is 0.
	131	* We can't test no_desc_mode again, it might race. */
	132	if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
	133	solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);
faa4fd2a	134
dcae5dac	135	mutex_unlock(&p2m_dev->mutex);
faa4fd2a	136
dcae5dac HV	137	return ret;
dcae5dac HV	138	}
faa4fd2a	139
dcae5dac HV	140	void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
	141	dma_addr_t dma_addr, u32 ext_addr, u32 size,
	142	int repeat, u32 ext_size)
faa4fd2a	143	{
dcae5dac HV	144	WARN_ON_ONCE(dma_addr & 0x03);
dcae5dac HV	145	WARN_ON_ONCE(!size);
faa4fd2a	146
dcae5dac HV	147	desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
	148	desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) \|
	149	(wr ? SOLO_P2M_WRITE : 0) \| SOLO_P2M_TRANS_ON;
faa4fd2a	150
dcae5dac HV	151	if (repeat) {
	152	desc->cfg \|= SOLO_P2M_EXT_INC(ext_size >> 2);
	153	desc->ctrl \|= SOLO_P2M_PCI_INC(size >> 2) \|
	154	SOLO_P2M_REPEAT(repeat);
faa4fd2a BC	155	}
faa4fd2a BC	156
dcae5dac HV	157	desc->dma_addr = dma_addr;
dcae5dac HV	158	desc->ext_addr = ext_addr;
faa4fd2a BC	159	}
faa4fd2a BC	160
dcae5dac HV	161	int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
	162	dma_addr_t dma_addr, u32 ext_addr, u32 size,
	163	int repeat, u32 ext_size)
faa4fd2a	164	{
dcae5dac	165	struct solo_p2m_desc desc[2];
faa4fd2a	166
dcae5dac HV	167	solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
dcae5dac HV	168	ext_size);
faa4fd2a	169
dcae5dac HV	170	/* No need for desc_dma since we know it is a single-shot */
dcae5dac HV	171	return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
faa4fd2a	172	}
faa4fd2a	173
decebabf	174	void solo_p2m_isr(struct solo_dev *solo_dev, int id)
faa4fd2a	175	{
f62de9be	176	struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
dcae5dac HV	177	struct solo_p2m_desc *desc;
	178
	179	if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
	180	complete(&p2m_dev->completion);
	181	return;
	182	}
f62de9be	183
dcae5dac HV	184	/* Setup next descriptor */
	185	p2m_dev->desc_idx++;
	186	desc = &p2m_dev->descs[p2m_dev->desc_idx];
f62de9be	187
dcae5dac HV	188	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
	189	solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
	190	solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
	191	solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
	192	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
faa4fd2a BC	193	}
faa4fd2a BC	194
dcae5dac	195	void solo_p2m_error_isr(struct solo_dev *solo_dev)
faa4fd2a	196	{
dcae5dac	197	unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
faa4fd2a BC	198	struct solo_p2m_dev *p2m_dev;
	199	int i;
	200
4718892f	201	if (!(err & (SOLO_PCI_ERR_P2M \| SOLO_PCI_ERR_P2M_DESC)))
faa4fd2a BC	202	return;
	203
	204	for (i = 0; i < SOLO_NR_P2M; i++) {
	205	p2m_dev = &solo_dev->p2m_dev[i];
	206	p2m_dev->error = 1;
	207	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
	208	complete(&p2m_dev->completion);
	209	}
	210	}
	211
decebabf	212	void solo_p2m_exit(struct solo_dev *solo_dev)
faa4fd2a BC	213	{
	214	int i;
	215
	216	for (i = 0; i < SOLO_NR_P2M; i++)
decebabf	217	solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
faa4fd2a BC	218	}
faa4fd2a BC	219
dcae5dac HV	220	static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
	221	{
	222	u32 *wr_buf;
	223	u32 *rd_buf;
	224	int i;
	225	int ret = -EIO;
	226	int order = get_order(size);
	227
	228	wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
	229	if (wr_buf == NULL)
	230	return -1;
	231
	232	rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
	233	if (rd_buf == NULL) {
	234	free_pages((unsigned long)wr_buf, order);
	235	return -1;
	236	}
	237
	238	for (i = 0; i < (size >> 3); i++)
	239	*(wr_buf + i) = (i << 16) \| (i + 1);
	240
	241	for (i = (size >> 3); i < (size >> 2); i++)
	242	*(wr_buf + i) = ~((i << 16) \| (i + 1));
	243
	244	memset(rd_buf, 0x55, size);
	245
	246	if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
	247	goto test_fail;
	248
	249	if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
	250	goto test_fail;
	251
	252	for (i = 0; i < (size >> 2); i++) {
	253	if ((wr_buf + i) != (rd_buf + i))
	254	goto test_fail;
	255	}
	256
	257	ret = 0;
	258
	259	test_fail:
	260	free_pages((unsigned long)wr_buf, order);
	261	free_pages((unsigned long)rd_buf, order);
	262
	263	return ret;
	264	}
	265
decebabf	266	int solo_p2m_init(struct solo_dev *solo_dev)
faa4fd2a BC	267	{
	268	struct solo_p2m_dev *p2m_dev;
	269	int i;
	270
	271	for (i = 0; i < SOLO_NR_P2M; i++) {
	272	p2m_dev = &solo_dev->p2m_dev[i];
	273
f62de9be	274	mutex_init(&p2m_dev->mutex);
faa4fd2a BC	275	init_completion(&p2m_dev->completion);
faa4fd2a BC	276
faa4fd2a BC	277	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
	278	solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
	279	SOLO_P2M_CSC_16BIT_565 \|
0e4de059	280	SOLO_P2M_DESC_INTR_OPT \|
dcae5dac	281	SOLO_P2M_DMA_INTERVAL(0) \|
faa4fd2a	282	SOLO_P2M_PCI_MASTER_MODE);
decebabf	283	solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
faa4fd2a BC	284	}
faa4fd2a BC	285
dcae5dac HV	286	/* Find correct SDRAM size */
	287	for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
	288	solo_reg_write(solo_dev, SOLO_DMA_CTRL,
	289	SOLO_DMA_CTRL_REFRESH_CYCLE(1) \|
	290	SOLO_DMA_CTRL_SDRAM_SIZE(i) \|
	291	SOLO_DMA_CTRL_SDRAM_CLK_INVERT \|
	292	SOLO_DMA_CTRL_READ_CLK_SELECT \|
	293	SOLO_DMA_CTRL_LATENCY(1));
	294
	295	solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config \|
	296	SOLO_SYS_CFG_RESET);
	297	solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
	298
	299	switch (i) {
	300	case 2:
	301	if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) \|\|
	302	solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
	303	continue;
	304	break;
	305
	306	case 1:
	307	if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
	308	continue;
	309	break;
	310
	311	default:
	312	if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
	313	continue;
	314	}
	315
	316	solo_dev->sdram_size = (32 << 20) << i;
	317	break;
	318	}
	319
	320	if (!solo_dev->sdram_size) {
	321	dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
	322	return -EIO;
	323	}
	324
	325	if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
	326	dev_err(&solo_dev->pdev->dev,
	327	"SDRAM is not large enough (%u < %u)\n",
	328	solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
	329	return -EIO;
	330	}
faa4fd2a BC	331
	332	return 0;
	333	}