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ba3d7ddf CG |
1 | /* |
2 | * dim2_hal.h - DIM2 HAL interface | |
3 | * (MediaLB, Device Interface Macro IP, OS62420) | |
4 | * | |
5 | * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * This file is licensed under GPLv2. | |
13 | */ | |
14 | ||
15 | #ifndef _DIM2_HAL_H | |
16 | #define _DIM2_HAL_H | |
17 | ||
18 | #include <linux/types.h> | |
19 | ||
ba3d7ddf CG |
20 | #ifdef __cplusplus |
21 | extern "C" { | |
22 | #endif | |
23 | ||
24 | /* | |
25 | * The values below are specified in the hardware specification. | |
26 | * So, they should not be changed until the hardware specification changes. | |
27 | */ | |
28 | enum mlb_clk_speed { | |
29 | CLK_256FS = 0, | |
30 | CLK_512FS = 1, | |
31 | CLK_1024FS = 2, | |
32 | CLK_2048FS = 3, | |
33 | CLK_3072FS = 4, | |
34 | CLK_4096FS = 5, | |
35 | CLK_6144FS = 6, | |
36 | CLK_8192FS = 7, | |
37 | }; | |
38 | ||
39 | struct dim_ch_state_t { | |
40 | bool ready; /* Shows readiness to enqueue next buffer */ | |
41 | u16 done_buffers; /* Number of completed buffers */ | |
42 | }; | |
43 | ||
44 | typedef int atomic_counter_t; | |
45 | ||
46 | struct int_ch_state { | |
47 | /* changed only in interrupt context */ | |
48 | volatile atomic_counter_t request_counter; | |
49 | ||
50 | /* changed only in task context */ | |
51 | volatile atomic_counter_t service_counter; | |
52 | ||
53 | u8 idx1; | |
54 | u8 idx2; | |
55 | u8 level; /* [0..2], buffering level */ | |
56 | }; | |
57 | ||
58 | struct dim_channel { | |
59 | struct int_ch_state state; | |
60 | u8 addr; | |
61 | u16 dbr_addr; | |
62 | u16 dbr_size; | |
63 | u16 packet_length; /*< Isochronous packet length in bytes. */ | |
64 | u16 bytes_per_frame; /*< Synchronous bytes per frame. */ | |
65 | u16 done_sw_buffers_number; /*< Done software buffers number. */ | |
66 | }; | |
67 | ||
6417267f | 68 | u8 dim_startup(void *dim_base_address, u32 mlb_clock); |
ba3d7ddf | 69 | |
50a45b17 | 70 | void dim_shutdown(void); |
ba3d7ddf | 71 | |
b724207b | 72 | bool dim_get_lock_state(void); |
ba3d7ddf CG |
73 | |
74 | u16 DIM_NormCtrlAsyncBufferSize(u16 buf_size); | |
75 | ||
76 | u16 DIM_NormIsocBufferSize(u16 buf_size, u16 packet_length); | |
77 | ||
78 | u16 DIM_NormSyncBufferSize(u16 buf_size, u16 bytes_per_frame); | |
79 | ||
80 | u8 DIM_InitControl(struct dim_channel *ch, u8 is_tx, u16 ch_address, | |
81 | u16 max_buffer_size); | |
82 | ||
83 | u8 DIM_InitAsync(struct dim_channel *ch, u8 is_tx, u16 ch_address, | |
84 | u16 max_buffer_size); | |
85 | ||
86 | u8 DIM_InitIsoc(struct dim_channel *ch, u8 is_tx, u16 ch_address, | |
87 | u16 packet_length); | |
88 | ||
89 | u8 DIM_InitSync(struct dim_channel *ch, u8 is_tx, u16 ch_address, | |
90 | u16 bytes_per_frame); | |
91 | ||
92 | u8 DIM_DestroyChannel(struct dim_channel *ch); | |
93 | ||
94 | void DIM_ServiceIrq(struct dim_channel *const *channels); | |
95 | ||
96 | u8 DIM_ServiceChannel(struct dim_channel *ch); | |
97 | ||
98 | struct dim_ch_state_t *DIM_GetChannelState(struct dim_channel *ch, | |
99 | struct dim_ch_state_t *dim_ch_state_ptr); | |
100 | ||
101 | bool DIM_EnqueueBuffer(struct dim_channel *ch, u32 buffer_addr, | |
102 | u16 buffer_size); | |
103 | ||
38c38544 | 104 | bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number); |
ba3d7ddf | 105 | |
ddb98ce1 | 106 | u32 DIMCB_IoRead(u32 *ptr32); |
ba3d7ddf | 107 | |
ddb98ce1 | 108 | void DIMCB_IoWrite(u32 *ptr32, u32 value); |
ba3d7ddf | 109 | |
de668731 | 110 | void dimcb_on_error(u8 error_id, const char *error_message); |
ba3d7ddf | 111 | |
ba3d7ddf CG |
112 | #ifdef __cplusplus |
113 | } | |
114 | #endif | |
115 | ||
116 | #endif /* _DIM2_HAL_H */ |