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d974ce4f KP |
1 | /* |
2 | * Copyright (c) 2003-2013 Broadcom Corporation | |
3 | * | |
4 | * Copyright (c) 2009-2010 Micron Technology, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | #include <linux/mtd/nand.h> | |
22 | #include <linux/spi/spi.h> | |
23 | ||
24 | #include "mt29f_spinand.h" | |
25 | ||
26 | #define BUFSIZE (10 * 64 * 2048) | |
27 | #define CACHE_BUF 2112 | |
28 | /* | |
29 | * OOB area specification layout: Total 32 available free bytes. | |
30 | */ | |
d974ce4f KP |
31 | |
32 | static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd) | |
33 | { | |
34 | struct nand_chip *chip = (struct nand_chip *)mtd->priv; | |
35 | struct spinand_info *info = (struct spinand_info *)chip->priv; | |
36 | struct spinand_state *state = (struct spinand_state *)info->priv; | |
37 | ||
38 | return state; | |
39 | } | |
40 | ||
3685ebc4 RD |
41 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC |
42 | static int enable_hw_ecc; | |
43 | static int enable_read_hw_ecc; | |
44 | ||
d974ce4f KP |
45 | static struct nand_ecclayout spinand_oob_64 = { |
46 | .eccbytes = 24, | |
47 | .eccpos = { | |
48 | 1, 2, 3, 4, 5, 6, | |
49 | 17, 18, 19, 20, 21, 22, | |
50 | 33, 34, 35, 36, 37, 38, | |
51 | 49, 50, 51, 52, 53, 54, }, | |
52 | .oobavail = 32, | |
53 | .oobfree = { | |
54 | {.offset = 8, | |
55 | .length = 8}, | |
56 | {.offset = 24, | |
57 | .length = 8}, | |
58 | {.offset = 40, | |
59 | .length = 8}, | |
60 | {.offset = 56, | |
61 | .length = 8}, | |
62 | } | |
63 | }; | |
64 | #endif | |
65 | ||
66 | /* | |
67 | * spinand_cmd - to process a command to send to the SPI Nand | |
68 | * Description: | |
69 | * Set up the command buffer to send to the SPI controller. | |
70 | * The command buffer has to initialized to 0. | |
71 | */ | |
72 | ||
73 | static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd) | |
74 | { | |
75 | struct spi_message message; | |
76 | struct spi_transfer x[4]; | |
77 | u8 dummy = 0xff; | |
78 | ||
79 | spi_message_init(&message); | |
80 | memset(x, 0, sizeof(x)); | |
81 | ||
82 | x[0].len = 1; | |
83 | x[0].tx_buf = &cmd->cmd; | |
84 | spi_message_add_tail(&x[0], &message); | |
85 | ||
86 | if (cmd->n_addr) { | |
87 | x[1].len = cmd->n_addr; | |
88 | x[1].tx_buf = cmd->addr; | |
89 | spi_message_add_tail(&x[1], &message); | |
90 | } | |
91 | ||
92 | if (cmd->n_dummy) { | |
93 | x[2].len = cmd->n_dummy; | |
94 | x[2].tx_buf = &dummy; | |
95 | spi_message_add_tail(&x[2], &message); | |
96 | } | |
97 | ||
98 | if (cmd->n_tx) { | |
99 | x[3].len = cmd->n_tx; | |
100 | x[3].tx_buf = cmd->tx_buf; | |
101 | spi_message_add_tail(&x[3], &message); | |
102 | } | |
103 | ||
104 | if (cmd->n_rx) { | |
105 | x[3].len = cmd->n_rx; | |
106 | x[3].rx_buf = cmd->rx_buf; | |
107 | spi_message_add_tail(&x[3], &message); | |
108 | } | |
109 | ||
110 | return spi_sync(spi, &message); | |
111 | } | |
112 | ||
113 | /* | |
114 | * spinand_read_id- Read SPI Nand ID | |
115 | * Description: | |
116 | * Read ID: read two ID bytes from the SPI Nand device | |
117 | */ | |
118 | static int spinand_read_id(struct spi_device *spi_nand, u8 *id) | |
119 | { | |
120 | int retval; | |
121 | u8 nand_id[3]; | |
122 | struct spinand_cmd cmd = {0}; | |
123 | ||
124 | cmd.cmd = CMD_READ_ID; | |
125 | cmd.n_rx = 3; | |
126 | cmd.rx_buf = &nand_id[0]; | |
127 | ||
128 | retval = spinand_cmd(spi_nand, &cmd); | |
129 | if (retval < 0) { | |
130 | dev_err(&spi_nand->dev, "error %d reading id\n", retval); | |
131 | return retval; | |
132 | } | |
133 | id[0] = nand_id[1]; | |
134 | id[1] = nand_id[2]; | |
135 | return retval; | |
136 | } | |
137 | ||
138 | /* | |
139 | * spinand_read_status- send command 0xf to the SPI Nand status register | |
140 | * Description: | |
141 | * After read, write, or erase, the Nand device is expected to set the | |
142 | * busy status. | |
143 | * This function is to allow reading the status of the command: read, | |
144 | * write, and erase. | |
145 | * Once the status turns to be ready, the other status bits also are | |
146 | * valid status bits. | |
147 | */ | |
148 | static int spinand_read_status(struct spi_device *spi_nand, uint8_t *status) | |
149 | { | |
150 | struct spinand_cmd cmd = {0}; | |
151 | int ret; | |
152 | ||
153 | cmd.cmd = CMD_READ_REG; | |
154 | cmd.n_addr = 1; | |
155 | cmd.addr[0] = REG_STATUS; | |
156 | cmd.n_rx = 1; | |
157 | cmd.rx_buf = status; | |
158 | ||
159 | ret = spinand_cmd(spi_nand, &cmd); | |
160 | if (ret < 0) | |
161 | dev_err(&spi_nand->dev, "err: %d read status register\n", ret); | |
162 | ||
163 | return ret; | |
164 | } | |
165 | ||
166 | #define MAX_WAIT_JIFFIES (40 * HZ) | |
167 | static int wait_till_ready(struct spi_device *spi_nand) | |
168 | { | |
169 | unsigned long deadline; | |
170 | int retval; | |
171 | u8 stat = 0; | |
172 | ||
173 | deadline = jiffies + MAX_WAIT_JIFFIES; | |
174 | do { | |
175 | retval = spinand_read_status(spi_nand, &stat); | |
176 | if (retval < 0) | |
177 | return -1; | |
178 | else if (!(stat & 0x1)) | |
179 | break; | |
180 | ||
181 | cond_resched(); | |
182 | } while (!time_after_eq(jiffies, deadline)); | |
183 | ||
184 | if ((stat & 0x1) == 0) | |
185 | return 0; | |
186 | ||
187 | return -1; | |
188 | } | |
189 | /** | |
190 | * spinand_get_otp- send command 0xf to read the SPI Nand OTP register | |
191 | * Description: | |
192 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
193 | * Enable chip internal ECC, set the bit to 1 | |
194 | * Disable chip internal ECC, clear the bit to 0 | |
195 | */ | |
196 | static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp) | |
197 | { | |
198 | struct spinand_cmd cmd = {0}; | |
199 | int retval; | |
200 | ||
201 | cmd.cmd = CMD_READ_REG; | |
202 | cmd.n_addr = 1; | |
203 | cmd.addr[0] = REG_OTP; | |
204 | cmd.n_rx = 1; | |
205 | cmd.rx_buf = otp; | |
206 | ||
207 | retval = spinand_cmd(spi_nand, &cmd); | |
208 | if (retval < 0) | |
209 | dev_err(&spi_nand->dev, "error %d get otp\n", retval); | |
210 | return retval; | |
211 | } | |
212 | ||
213 | /** | |
214 | * spinand_set_otp- send command 0x1f to write the SPI Nand OTP register | |
215 | * Description: | |
216 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
217 | * Enable chip internal ECC, set the bit to 1 | |
218 | * Disable chip internal ECC, clear the bit to 0 | |
219 | */ | |
220 | static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp) | |
221 | { | |
222 | int retval; | |
223 | struct spinand_cmd cmd = {0}; | |
224 | ||
225 | cmd.cmd = CMD_WRITE_REG, | |
226 | cmd.n_addr = 1, | |
227 | cmd.addr[0] = REG_OTP, | |
228 | cmd.n_tx = 1, | |
229 | cmd.tx_buf = otp, | |
230 | ||
231 | retval = spinand_cmd(spi_nand, &cmd); | |
232 | if (retval < 0) | |
233 | dev_err(&spi_nand->dev, "error %d set otp\n", retval); | |
234 | ||
235 | return retval; | |
236 | } | |
237 | ||
238 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
239 | /** | |
240 | * spinand_enable_ecc- send command 0x1f to write the SPI Nand OTP register | |
241 | * Description: | |
242 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
243 | * Enable chip internal ECC, set the bit to 1 | |
244 | * Disable chip internal ECC, clear the bit to 0 | |
245 | */ | |
246 | static int spinand_enable_ecc(struct spi_device *spi_nand) | |
247 | { | |
248 | int retval; | |
249 | u8 otp = 0; | |
250 | ||
251 | retval = spinand_get_otp(spi_nand, &otp); | |
252 | if (retval < 0) | |
253 | return retval; | |
254 | ||
72267c27 | 255 | if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) |
d974ce4f | 256 | return 0; |
72267c27 | 257 | otp |= OTP_ECC_MASK; |
258 | retval = spinand_set_otp(spi_nand, &otp); | |
259 | if (retval < 0) | |
260 | return retval; | |
261 | return spinand_get_otp(spi_nand, &otp); | |
d974ce4f KP |
262 | } |
263 | #endif | |
264 | ||
265 | static int spinand_disable_ecc(struct spi_device *spi_nand) | |
266 | { | |
267 | int retval; | |
268 | u8 otp = 0; | |
269 | ||
270 | retval = spinand_get_otp(spi_nand, &otp); | |
271 | if (retval < 0) | |
272 | return retval; | |
273 | ||
274 | if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) { | |
275 | otp &= ~OTP_ECC_MASK; | |
276 | retval = spinand_set_otp(spi_nand, &otp); | |
277 | if (retval < 0) | |
278 | return retval; | |
279 | return spinand_get_otp(spi_nand, &otp); | |
72267c27 | 280 | } |
281 | return 0; | |
d974ce4f KP |
282 | } |
283 | ||
284 | /** | |
285 | * spinand_write_enable- send command 0x06 to enable write or erase the | |
286 | * Nand cells | |
287 | * Description: | |
288 | * Before write and erase the Nand cells, the write enable has to be set. | |
289 | * After the write or erase, the write enable bit is automatically | |
290 | * cleared (status register bit 2) | |
291 | * Set the bit 2 of the status register has the same effect | |
292 | */ | |
293 | static int spinand_write_enable(struct spi_device *spi_nand) | |
294 | { | |
295 | struct spinand_cmd cmd = {0}; | |
296 | ||
297 | cmd.cmd = CMD_WR_ENABLE; | |
298 | return spinand_cmd(spi_nand, &cmd); | |
299 | } | |
300 | ||
301 | static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id) | |
302 | { | |
303 | struct spinand_cmd cmd = {0}; | |
304 | u16 row; | |
305 | ||
306 | row = page_id; | |
307 | cmd.cmd = CMD_READ; | |
308 | cmd.n_addr = 3; | |
309 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
310 | cmd.addr[2] = (u8)(row & 0x00ff); | |
311 | ||
312 | return spinand_cmd(spi_nand, &cmd); | |
313 | } | |
314 | ||
315 | /* | |
316 | * spinand_read_from_cache- send command 0x03 to read out the data from the | |
317 | * cache register(2112 bytes max) | |
318 | * Description: | |
319 | * The read can specify 1 to 2112 bytes of data read at the corresponding | |
320 | * locations. | |
321 | * No tRd delay. | |
322 | */ | |
323 | static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id, | |
324 | u16 byte_id, u16 len, u8 *rbuf) | |
325 | { | |
326 | struct spinand_cmd cmd = {0}; | |
327 | u16 column; | |
328 | ||
329 | column = byte_id; | |
330 | cmd.cmd = CMD_READ_RDM; | |
331 | cmd.n_addr = 3; | |
332 | cmd.addr[0] = (u8)((column & 0xff00) >> 8); | |
333 | cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4); | |
334 | cmd.addr[1] = (u8)(column & 0x00ff); | |
335 | cmd.addr[2] = (u8)(0xff); | |
336 | cmd.n_dummy = 0; | |
337 | cmd.n_rx = len; | |
338 | cmd.rx_buf = rbuf; | |
339 | ||
340 | return spinand_cmd(spi_nand, &cmd); | |
341 | } | |
342 | ||
343 | /* | |
344 | * spinand_read_page-to read a page with: | |
345 | * @page_id: the physical page number | |
346 | * @offset: the location from 0 to 2111 | |
347 | * @len: number of bytes to read | |
348 | * @rbuf: read buffer to hold @len bytes | |
349 | * | |
350 | * Description: | |
351 | * The read includes two commands to the Nand: 0x13 and 0x03 commands | |
352 | * Poll to read status to wait for tRD time. | |
353 | */ | |
354 | static int spinand_read_page(struct spi_device *spi_nand, u16 page_id, | |
355 | u16 offset, u16 len, u8 *rbuf) | |
356 | { | |
357 | int ret; | |
358 | u8 status = 0; | |
359 | ||
360 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
361 | if (enable_read_hw_ecc) { | |
362 | if (spinand_enable_ecc(spi_nand) < 0) | |
363 | dev_err(&spi_nand->dev, "enable HW ECC failed!"); | |
364 | } | |
365 | #endif | |
366 | ret = spinand_read_page_to_cache(spi_nand, page_id); | |
367 | if (ret < 0) | |
368 | return ret; | |
369 | ||
370 | if (wait_till_ready(spi_nand)) | |
371 | dev_err(&spi_nand->dev, "WAIT timedout!!!\n"); | |
372 | ||
373 | while (1) { | |
374 | ret = spinand_read_status(spi_nand, &status); | |
375 | if (ret < 0) { | |
376 | dev_err(&spi_nand->dev, | |
377 | "err %d read status register\n", ret); | |
378 | return ret; | |
379 | } | |
380 | ||
381 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
382 | if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) { | |
383 | dev_err(&spi_nand->dev, "ecc error, page=%d\n", | |
384 | page_id); | |
385 | return 0; | |
386 | } | |
387 | break; | |
388 | } | |
389 | } | |
390 | ||
391 | ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf); | |
392 | if (ret < 0) { | |
393 | dev_err(&spi_nand->dev, "read from cache failed!!\n"); | |
394 | return ret; | |
395 | } | |
396 | ||
397 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
398 | if (enable_read_hw_ecc) { | |
399 | ret = spinand_disable_ecc(spi_nand); | |
400 | if (ret < 0) { | |
401 | dev_err(&spi_nand->dev, "disable ecc failed!!\n"); | |
402 | return ret; | |
403 | } | |
404 | enable_read_hw_ecc = 0; | |
405 | } | |
406 | #endif | |
407 | return ret; | |
408 | } | |
409 | ||
410 | /* | |
411 | * spinand_program_data_to_cache--to write a page to cache with: | |
412 | * @byte_id: the location to write to the cache | |
413 | * @len: number of bytes to write | |
414 | * @rbuf: read buffer to hold @len bytes | |
415 | * | |
416 | * Description: | |
417 | * The write command used here is 0x84--indicating that the cache is | |
418 | * not cleared first. | |
419 | * Since it is writing the data to cache, there is no tPROG time. | |
420 | */ | |
421 | static int spinand_program_data_to_cache(struct spi_device *spi_nand, | |
422 | u16 page_id, u16 byte_id, u16 len, u8 *wbuf) | |
423 | { | |
424 | struct spinand_cmd cmd = {0}; | |
425 | u16 column; | |
426 | ||
427 | column = byte_id; | |
428 | cmd.cmd = CMD_PROG_PAGE_CLRCACHE; | |
429 | cmd.n_addr = 2; | |
430 | cmd.addr[0] = (u8)((column & 0xff00) >> 8); | |
431 | cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4); | |
432 | cmd.addr[1] = (u8)(column & 0x00ff); | |
433 | cmd.n_tx = len; | |
434 | cmd.tx_buf = wbuf; | |
435 | ||
436 | return spinand_cmd(spi_nand, &cmd); | |
437 | } | |
438 | ||
439 | /** | |
440 | * spinand_program_execute--to write a page from cache to the Nand array with | |
441 | * @page_id: the physical page location to write the page. | |
442 | * | |
443 | * Description: | |
444 | * The write command used here is 0x10--indicating the cache is writing to | |
445 | * the Nand array. | |
446 | * Need to wait for tPROG time to finish the transaction. | |
447 | */ | |
448 | static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id) | |
449 | { | |
450 | struct spinand_cmd cmd = {0}; | |
451 | u16 row; | |
452 | ||
453 | row = page_id; | |
454 | cmd.cmd = CMD_PROG_PAGE_EXC; | |
455 | cmd.n_addr = 3; | |
456 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
457 | cmd.addr[2] = (u8)(row & 0x00ff); | |
458 | ||
459 | return spinand_cmd(spi_nand, &cmd); | |
460 | } | |
461 | ||
462 | /** | |
463 | * spinand_program_page--to write a page with: | |
464 | * @page_id: the physical page location to write the page. | |
465 | * @offset: the location from the cache starting from 0 to 2111 | |
466 | * @len: the number of bytes to write | |
467 | * @wbuf: the buffer to hold the number of bytes | |
468 | * | |
469 | * Description: | |
470 | * The commands used here are 0x06, 0x84, and 0x10--indicating that | |
471 | * the write enable is first sent, the write cache command, and the | |
472 | * write execute command. | |
473 | * Poll to wait for the tPROG time to finish the transaction. | |
474 | */ | |
475 | static int spinand_program_page(struct spi_device *spi_nand, | |
476 | u16 page_id, u16 offset, u16 len, u8 *buf) | |
477 | { | |
478 | int retval; | |
479 | u8 status = 0; | |
480 | uint8_t *wbuf; | |
481 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
482 | unsigned int i, j; | |
483 | ||
484 | enable_read_hw_ecc = 0; | |
485 | wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL); | |
486 | spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf); | |
487 | ||
488 | for (i = offset, j = 0; i < len; i++, j++) | |
489 | wbuf[i] &= buf[j]; | |
490 | ||
491 | if (enable_hw_ecc) { | |
492 | retval = spinand_enable_ecc(spi_nand); | |
493 | if (retval < 0) { | |
494 | dev_err(&spi_nand->dev, "enable ecc failed!!\n"); | |
495 | return retval; | |
496 | } | |
497 | } | |
498 | #else | |
499 | wbuf = buf; | |
500 | #endif | |
501 | retval = spinand_write_enable(spi_nand); | |
502 | if (retval < 0) { | |
503 | dev_err(&spi_nand->dev, "write enable failed!!\n"); | |
504 | return retval; | |
505 | } | |
506 | if (wait_till_ready(spi_nand)) | |
507 | dev_err(&spi_nand->dev, "wait timedout!!!\n"); | |
508 | ||
509 | retval = spinand_program_data_to_cache(spi_nand, page_id, | |
510 | offset, len, wbuf); | |
511 | if (retval < 0) | |
512 | return retval; | |
513 | retval = spinand_program_execute(spi_nand, page_id); | |
514 | if (retval < 0) | |
515 | return retval; | |
516 | while (1) { | |
517 | retval = spinand_read_status(spi_nand, &status); | |
518 | if (retval < 0) { | |
519 | dev_err(&spi_nand->dev, | |
520 | "error %d reading status register\n", | |
521 | retval); | |
522 | return retval; | |
523 | } | |
524 | ||
525 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
526 | if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) { | |
527 | dev_err(&spi_nand->dev, | |
528 | "program error, page %d\n", page_id); | |
529 | return -1; | |
72267c27 | 530 | } |
531 | break; | |
d974ce4f KP |
532 | } |
533 | } | |
534 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
535 | if (enable_hw_ecc) { | |
536 | retval = spinand_disable_ecc(spi_nand); | |
537 | if (retval < 0) { | |
538 | dev_err(&spi_nand->dev, "disable ecc failed!!\n"); | |
539 | return retval; | |
540 | } | |
541 | enable_hw_ecc = 0; | |
542 | } | |
543 | #endif | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | /** | |
549 | * spinand_erase_block_erase--to erase a page with: | |
550 | * @block_id: the physical block location to erase. | |
551 | * | |
552 | * Description: | |
553 | * The command used here is 0xd8--indicating an erase command to erase | |
554 | * one block--64 pages | |
555 | * Need to wait for tERS. | |
556 | */ | |
557 | static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id) | |
558 | { | |
559 | struct spinand_cmd cmd = {0}; | |
560 | u16 row; | |
561 | ||
562 | row = block_id; | |
563 | cmd.cmd = CMD_ERASE_BLK; | |
564 | cmd.n_addr = 3; | |
565 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
566 | cmd.addr[2] = (u8)(row & 0x00ff); | |
567 | ||
568 | return spinand_cmd(spi_nand, &cmd); | |
569 | } | |
570 | ||
571 | /** | |
572 | * spinand_erase_block--to erase a page with: | |
573 | * @block_id: the physical block location to erase. | |
574 | * | |
575 | * Description: | |
576 | * The commands used here are 0x06 and 0xd8--indicating an erase | |
577 | * command to erase one block--64 pages | |
578 | * It will first to enable the write enable bit (0x06 command), | |
579 | * and then send the 0xd8 erase command | |
580 | * Poll to wait for the tERS time to complete the tranaction. | |
581 | */ | |
582 | static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id) | |
583 | { | |
584 | int retval; | |
585 | u8 status = 0; | |
586 | ||
587 | retval = spinand_write_enable(spi_nand); | |
588 | if (wait_till_ready(spi_nand)) | |
589 | dev_err(&spi_nand->dev, "wait timedout!!!\n"); | |
590 | ||
591 | retval = spinand_erase_block_erase(spi_nand, block_id); | |
592 | while (1) { | |
593 | retval = spinand_read_status(spi_nand, &status); | |
594 | if (retval < 0) { | |
595 | dev_err(&spi_nand->dev, | |
596 | "error %d reading status register\n", | |
597 | (int) retval); | |
598 | return retval; | |
599 | } | |
600 | ||
601 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
602 | if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) { | |
603 | dev_err(&spi_nand->dev, | |
604 | "erase error, block %d\n", block_id); | |
605 | return -1; | |
72267c27 | 606 | } |
607 | break; | |
d974ce4f KP |
608 | } |
609 | } | |
610 | return 0; | |
611 | } | |
612 | ||
613 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
614 | static int spinand_write_page_hwecc(struct mtd_info *mtd, | |
45aaeff9 BB |
615 | struct nand_chip *chip, const uint8_t *buf, int oob_required, |
616 | int page) | |
d974ce4f KP |
617 | { |
618 | const uint8_t *p = buf; | |
619 | int eccsize = chip->ecc.size; | |
620 | int eccsteps = chip->ecc.steps; | |
621 | ||
622 | enable_hw_ecc = 1; | |
623 | chip->write_buf(mtd, p, eccsize * eccsteps); | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
628 | uint8_t *buf, int oob_required, int page) | |
629 | { | |
1f5cf802 DN |
630 | int retval; |
631 | u8 status; | |
d974ce4f KP |
632 | uint8_t *p = buf; |
633 | int eccsize = chip->ecc.size; | |
634 | int eccsteps = chip->ecc.steps; | |
635 | struct spinand_info *info = (struct spinand_info *)chip->priv; | |
636 | ||
637 | enable_read_hw_ecc = 1; | |
638 | ||
639 | chip->read_buf(mtd, p, eccsize * eccsteps); | |
640 | if (oob_required) | |
641 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
642 | ||
643 | while (1) { | |
644 | retval = spinand_read_status(info->spi, &status); | |
1f5cf802 DN |
645 | if (retval < 0) { |
646 | dev_err(&mtd->dev, | |
647 | "error %d reading status register\n", | |
648 | retval); | |
649 | return retval; | |
650 | } | |
651 | ||
d974ce4f KP |
652 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { |
653 | if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) { | |
654 | pr_info("spinand: ECC error\n"); | |
655 | mtd->ecc_stats.failed++; | |
656 | } else if ((status & STATUS_ECC_MASK) == | |
657 | STATUS_ECC_1BIT_CORRECTED) | |
658 | mtd->ecc_stats.corrected++; | |
659 | break; | |
660 | } | |
661 | } | |
662 | return 0; | |
663 | ||
664 | } | |
665 | #endif | |
666 | ||
667 | static void spinand_select_chip(struct mtd_info *mtd, int dev) | |
668 | { | |
669 | } | |
670 | ||
671 | static uint8_t spinand_read_byte(struct mtd_info *mtd) | |
672 | { | |
673 | struct spinand_state *state = mtd_to_state(mtd); | |
674 | u8 data; | |
675 | ||
676 | data = state->buf[state->buf_ptr]; | |
677 | state->buf_ptr++; | |
678 | return data; | |
679 | } | |
680 | ||
681 | ||
682 | static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
683 | { | |
684 | struct spinand_info *info = (struct spinand_info *)chip->priv; | |
685 | ||
686 | unsigned long timeo = jiffies; | |
687 | int retval, state = chip->state; | |
688 | u8 status; | |
689 | ||
690 | if (state == FL_ERASING) | |
691 | timeo += (HZ * 400) / 1000; | |
692 | else | |
693 | timeo += (HZ * 20) / 1000; | |
694 | ||
695 | while (time_before(jiffies, timeo)) { | |
696 | retval = spinand_read_status(info->spi, &status); | |
1f5cf802 DN |
697 | if (retval < 0) { |
698 | dev_err(&mtd->dev, | |
699 | "error %d reading status register\n", | |
700 | retval); | |
701 | return retval; | |
702 | } | |
703 | ||
d974ce4f KP |
704 | if ((status & STATUS_OIP_MASK) == STATUS_READY) |
705 | return 0; | |
706 | ||
707 | cond_resched(); | |
708 | } | |
709 | return 0; | |
710 | } | |
711 | ||
712 | static void spinand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
713 | { | |
714 | ||
715 | struct spinand_state *state = mtd_to_state(mtd); | |
aeb49155 | 716 | |
d974ce4f KP |
717 | memcpy(state->buf + state->buf_ptr, buf, len); |
718 | state->buf_ptr += len; | |
719 | } | |
720 | ||
721 | static void spinand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
722 | { | |
723 | struct spinand_state *state = mtd_to_state(mtd); | |
aeb49155 | 724 | |
d974ce4f KP |
725 | memcpy(buf, state->buf + state->buf_ptr, len); |
726 | state->buf_ptr += len; | |
727 | } | |
728 | ||
729 | /* | |
730 | * spinand_reset- send RESET command "0xff" to the Nand device. | |
731 | */ | |
732 | static void spinand_reset(struct spi_device *spi_nand) | |
733 | { | |
734 | struct spinand_cmd cmd = {0}; | |
735 | ||
736 | cmd.cmd = CMD_RESET; | |
737 | ||
738 | if (spinand_cmd(spi_nand, &cmd) < 0) | |
739 | pr_info("spinand reset failed!\n"); | |
740 | ||
741 | /* elapse 1ms before issuing any other command */ | |
742 | udelay(1000); | |
743 | ||
744 | if (wait_till_ready(spi_nand)) | |
745 | dev_err(&spi_nand->dev, "wait timedout!\n"); | |
746 | } | |
747 | ||
748 | static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
749 | int column, int page) | |
750 | { | |
751 | struct nand_chip *chip = (struct nand_chip *)mtd->priv; | |
752 | struct spinand_info *info = (struct spinand_info *)chip->priv; | |
753 | struct spinand_state *state = (struct spinand_state *)info->priv; | |
754 | ||
755 | switch (command) { | |
756 | /* | |
757 | * READ0 - read in first 0x800 bytes | |
758 | */ | |
759 | case NAND_CMD_READ1: | |
760 | case NAND_CMD_READ0: | |
761 | state->buf_ptr = 0; | |
762 | spinand_read_page(info->spi, page, 0x0, 0x840, state->buf); | |
763 | break; | |
764 | /* READOOB reads only the OOB because no ECC is performed. */ | |
765 | case NAND_CMD_READOOB: | |
766 | state->buf_ptr = 0; | |
767 | spinand_read_page(info->spi, page, 0x800, 0x40, state->buf); | |
768 | break; | |
769 | case NAND_CMD_RNDOUT: | |
770 | state->buf_ptr = column; | |
771 | break; | |
772 | case NAND_CMD_READID: | |
773 | state->buf_ptr = 0; | |
a511536f | 774 | spinand_read_id(info->spi, state->buf); |
d974ce4f KP |
775 | break; |
776 | case NAND_CMD_PARAM: | |
777 | state->buf_ptr = 0; | |
778 | break; | |
779 | /* ERASE1 stores the block and page address */ | |
780 | case NAND_CMD_ERASE1: | |
781 | spinand_erase_block(info->spi, page); | |
782 | break; | |
783 | /* ERASE2 uses the block and page address from ERASE1 */ | |
784 | case NAND_CMD_ERASE2: | |
785 | break; | |
786 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
787 | case NAND_CMD_SEQIN: | |
788 | state->col = column; | |
789 | state->row = page; | |
790 | state->buf_ptr = 0; | |
791 | break; | |
792 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
793 | case NAND_CMD_PAGEPROG: | |
794 | spinand_program_page(info->spi, state->row, state->col, | |
795 | state->buf_ptr, state->buf); | |
796 | break; | |
797 | case NAND_CMD_STATUS: | |
798 | spinand_get_otp(info->spi, state->buf); | |
799 | if (!(state->buf[0] & 0x80)) | |
800 | state->buf[0] = 0x80; | |
801 | state->buf_ptr = 0; | |
802 | break; | |
803 | /* RESET command */ | |
804 | case NAND_CMD_RESET: | |
805 | if (wait_till_ready(info->spi)) | |
806 | dev_err(&info->spi->dev, "WAIT timedout!!!\n"); | |
807 | /* a minimum of 250us must elapse before issuing RESET cmd*/ | |
808 | udelay(250); | |
809 | spinand_reset(info->spi); | |
810 | break; | |
811 | default: | |
812 | dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command); | |
813 | } | |
814 | } | |
815 | ||
816 | /** | |
817 | * spinand_lock_block- send write register 0x1f command to the Nand device | |
818 | * | |
819 | * Description: | |
820 | * After power up, all the Nand blocks are locked. This function allows | |
821 | * one to unlock the blocks, and so it can be written or erased. | |
822 | */ | |
823 | static int spinand_lock_block(struct spi_device *spi_nand, u8 lock) | |
824 | { | |
825 | struct spinand_cmd cmd = {0}; | |
826 | int ret; | |
827 | u8 otp = 0; | |
828 | ||
829 | ret = spinand_get_otp(spi_nand, &otp); | |
830 | ||
831 | cmd.cmd = CMD_WRITE_REG; | |
832 | cmd.n_addr = 1; | |
833 | cmd.addr[0] = REG_BLOCK_LOCK; | |
834 | cmd.n_tx = 1; | |
835 | cmd.tx_buf = &lock; | |
836 | ||
837 | ret = spinand_cmd(spi_nand, &cmd); | |
838 | if (ret < 0) | |
839 | dev_err(&spi_nand->dev, "error %d lock block\n", ret); | |
840 | ||
841 | return ret; | |
842 | } | |
843 | /* | |
844 | * spinand_probe - [spinand Interface] | |
845 | * @spi_nand: registered device driver. | |
846 | * | |
847 | * Description: | |
848 | * To set up the device driver parameters to make the device available. | |
849 | */ | |
850 | static int spinand_probe(struct spi_device *spi_nand) | |
851 | { | |
852 | struct mtd_info *mtd; | |
853 | struct nand_chip *chip; | |
854 | struct spinand_info *info; | |
855 | struct spinand_state *state; | |
856 | struct mtd_part_parser_data ppdata; | |
857 | ||
858 | info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info), | |
859 | GFP_KERNEL); | |
860 | if (!info) | |
861 | return -ENOMEM; | |
862 | ||
863 | info->spi = spi_nand; | |
864 | ||
865 | spinand_lock_block(spi_nand, BL_ALL_UNLOCKED); | |
866 | ||
867 | state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state), | |
868 | GFP_KERNEL); | |
869 | if (!state) | |
870 | return -ENOMEM; | |
871 | ||
872 | info->priv = state; | |
873 | state->buf_ptr = 0; | |
874 | state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL); | |
875 | if (!state->buf) | |
876 | return -ENOMEM; | |
877 | ||
878 | chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip), | |
879 | GFP_KERNEL); | |
880 | if (!chip) | |
881 | return -ENOMEM; | |
882 | ||
883 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
884 | chip->ecc.mode = NAND_ECC_HW; | |
885 | chip->ecc.size = 0x200; | |
886 | chip->ecc.bytes = 0x6; | |
887 | chip->ecc.steps = 0x4; | |
888 | ||
889 | chip->ecc.strength = 1; | |
890 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; | |
891 | chip->ecc.layout = &spinand_oob_64; | |
892 | chip->ecc.read_page = spinand_read_page_hwecc; | |
893 | chip->ecc.write_page = spinand_write_page_hwecc; | |
894 | #else | |
895 | chip->ecc.mode = NAND_ECC_SOFT; | |
896 | if (spinand_disable_ecc(spi_nand) < 0) | |
897 | pr_info("%s: disable ecc failed!\n", __func__); | |
898 | #endif | |
899 | ||
900 | chip->priv = info; | |
901 | chip->read_buf = spinand_read_buf; | |
902 | chip->write_buf = spinand_write_buf; | |
903 | chip->read_byte = spinand_read_byte; | |
904 | chip->cmdfunc = spinand_cmdfunc; | |
905 | chip->waitfunc = spinand_wait; | |
906 | chip->options |= NAND_CACHEPRG; | |
907 | chip->select_chip = spinand_select_chip; | |
908 | ||
909 | mtd = devm_kzalloc(&spi_nand->dev, sizeof(struct mtd_info), GFP_KERNEL); | |
910 | if (!mtd) | |
911 | return -ENOMEM; | |
912 | ||
913 | dev_set_drvdata(&spi_nand->dev, mtd); | |
914 | ||
915 | mtd->priv = chip; | |
efefcaee | 916 | mtd->dev.parent = &spi_nand->dev; |
d974ce4f KP |
917 | mtd->oobsize = 64; |
918 | ||
919 | if (nand_scan(mtd, 1)) | |
920 | return -ENXIO; | |
921 | ||
922 | ppdata.of_node = spi_nand->dev.of_node; | |
923 | return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); | |
924 | } | |
925 | ||
926 | /* | |
927 | * spinand_remove: Remove the device driver | |
928 | * @spi: the spi device. | |
929 | * | |
930 | * Description: | |
931 | * To remove the device driver parameters and free up allocated memories. | |
932 | */ | |
933 | static int spinand_remove(struct spi_device *spi) | |
934 | { | |
935 | mtd_device_unregister(dev_get_drvdata(&spi->dev)); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static const struct of_device_id spinand_dt[] = { | |
941 | { .compatible = "spinand,mt29f", }, | |
ffd07de6 | 942 | {} |
d974ce4f KP |
943 | }; |
944 | ||
945 | /* | |
946 | * Device name structure description | |
947 | */ | |
948 | static struct spi_driver spinand_driver = { | |
949 | .driver = { | |
950 | .name = "mt29f", | |
d974ce4f KP |
951 | .owner = THIS_MODULE, |
952 | .of_match_table = spinand_dt, | |
953 | }, | |
954 | .probe = spinand_probe, | |
955 | .remove = spinand_remove, | |
956 | }; | |
957 | ||
4a54b615 | 958 | module_spi_driver(spinand_driver); |
d974ce4f KP |
959 | |
960 | MODULE_DESCRIPTION("SPI NAND driver for Micron"); | |
961 | MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>"); | |
962 | MODULE_LICENSE("GPL v2"); |