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staging/olpc_dcon: fix kconfig to fix build errors
[deliverable/linux.git] / drivers / staging / netlogic / xlr_net.c
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6f98b1a2
GR		 1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#include <linux/phy.h>
35#include <linux/delay.h>
36#include <linux/netdevice.h>
37#include <linux/smp.h>
38#include <linux/ethtool.h>
39#include <linux/module.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/jiffies.h>
43#include <linux/interrupt.h>
44#include <linux/platform_device.h>
45
46#include <asm/mipsregs.h>
47
48/* fmn.h - For FMN credit configuration and registering fmn_handler.
49 * FMN is communication mechanism that allows processing agents within
50 * XLR/XLS to communicate each other.
51 */
52#include <asm/netlogic/xlr/fmn.h>
53
54#include "platform_net.h"
55#include "xlr_net.h"
56
57/*
58 * The readl/writel implementation byteswaps on XLR/XLS, so
59 * we need to use __raw_ IO to read the NAE registers
60 * because they are in the big-endian MMIO area on the SoC.
61 */
62static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
63{
64 __raw_writel(val, base + reg);
65}
66
67static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
68{
69 return __raw_readl(base + reg);
70}
71
72static inline void xlr_reg_update(u32 *base_addr,
73 u32 off, u32 val, u32 mask)
74{
75 u32 tmp;
76
77 tmp = xlr_nae_rdreg(base_addr, off);
78 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
79}
80
81/*
82 * Table of net_device pointers indexed by port, this will be used to
83 * lookup the net_device corresponding to a port by the message ring handler.
84 *
85 * Maximum ports in XLR/XLS is 8(8 GMAC on XLS, 4 GMAC + 2 XGMAC on XLR)
86 */
87static struct net_device *mac_to_ndev[8];
88
89static inline struct sk_buff *mac_get_skb_back_ptr(void *addr)
90{
91 struct sk_buff **back_ptr;
92
93 /* this function should be used only for newly allocated packets.
94 * It assumes the first cacheline is for the back pointer related
95 * book keeping info.
96 */
97 back_ptr = (struct sk_buff **)(addr - MAC_SKB_BACK_PTR_SIZE);
98 return *back_ptr;
99}
100
101static inline void mac_put_skb_back_ptr(struct sk_buff *skb)
102{
103 struct sk_buff **back_ptr = (struct sk_buff **)skb->data;
104
105 /* this function should be used only for newly allocated packets.
106 * It assumes the first cacheline is for the back pointer related
107 * book keeping info.
108 */
109 skb_reserve(skb, MAC_SKB_BACK_PTR_SIZE);
110 *back_ptr = skb;
111}
112
113static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
114{
115 struct nlm_fmn_msg msg;
116 int ret = 0, num_try = 0, stnid;
117 unsigned long paddr, mflags;
118
119 paddr = virt_to_bus(addr);
120 msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
121 msg.msg1 = 0;
122 msg.msg2 = 0;
123 msg.msg3 = 0;
124 stnid = priv->nd->rfr_station;
125 do {
126 mflags = nlm_cop2_enable();
127 ret = nlm_fmn_send(1, 0, stnid, &msg);
128 nlm_cop2_restore(mflags);
129 if (ret == 0)
130 return 0;
131 } while (++num_try < 10000);
132
133 pr_err("Send to RFR failed in RX path\n");
134 return ret;
135}
136
137static inline struct sk_buff *xlr_alloc_skb(void)
138{
139 struct sk_buff *skb;
140
141 /* skb->data is cache aligned */
142 skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
143 if (!skb) {
144 pr_err("SKB allocation failed\n");
145 return NULL;
146 }
147 mac_put_skb_back_ptr(skb);
148 return skb;
149}
150
151static void xlr_net_fmn_handler(int bkt, int src_stnid, int size,
152 int code, struct nlm_fmn_msg *msg, void *arg)
153{
154 struct sk_buff *skb, *skb_new = NULL;
155 struct net_device *ndev;
156 struct xlr_net_priv *priv;
157 u64 length, port;
158 void *addr;
159
160 length = (msg->msg0 >> 40) & 0x3fff;
161 if (length == 0) {
162 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
163 dev_kfree_skb_any(addr);
164 } else if (length) {
165 addr = bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
166 length = length - BYTE_OFFSET - MAC_CRC_LEN;
167 port = msg->msg0 & 0x0f;
168 if (src_stnid == FMN_STNID_GMAC1)
169 port = port + 4;
170 skb = mac_get_skb_back_ptr(addr);
171 skb->dev = mac_to_ndev[port];
172 ndev = skb->dev;
173 priv = netdev_priv(ndev);
174
175 /* 16 byte IP header align */
176 skb_reserve(skb, BYTE_OFFSET);
177 skb_put(skb, length);
178 skb->protocol = eth_type_trans(skb, skb->dev);
179 skb->dev->last_rx = jiffies;
180 netif_rx(skb);
181 /* Fill rx ring */
182 skb_new = xlr_alloc_skb();
183 if (skb_new)
184 send_to_rfr_fifo(priv, skb_new->data);
185 }
186 return;
187}
188
189/* Ethtool operation */
190static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
191{
192 struct xlr_net_priv *priv = netdev_priv(ndev);
193 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
194
195 if (!phydev)
196 return -ENODEV;
197 return phy_ethtool_gset(phydev, ecmd);
198}
199
200static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
201{
202 struct xlr_net_priv *priv = netdev_priv(ndev);
203 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
204
205 if (!phydev)
206 return -ENODEV;
207 return phy_ethtool_sset(phydev, ecmd);
208}
209
210static struct ethtool_ops xlr_ethtool_ops = {
211 .get_settings = xlr_get_settings,
212 .set_settings = xlr_set_settings,
213};
214
215/* Net operations */
216static int xlr_net_fill_rx_ring(struct net_device *ndev)
217{
218 struct sk_buff *skb;
219 struct xlr_net_priv *priv = netdev_priv(ndev);
220 int i;
221
222 for (i = 0; i < MAX_FRIN_SPILL/2; i++) {
223 skb = xlr_alloc_skb();
224 if (!skb)
225 return -ENOMEM;
226 send_to_rfr_fifo(priv, skb->data);
227 }
228 pr_info("Rx ring setup done\n");
229 return 0;
230}
231
232static int xlr_net_open(struct net_device *ndev)
233{
234 u32 err;
235 struct xlr_net_priv *priv = netdev_priv(ndev);
236 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
237
238 /* schedule a link state check */
239 phy_start(phydev);
240
241 err = phy_start_aneg(phydev);
242 if (err) {
243 pr_err("Autoneg failed\n");
244 return err;
245 }
246
247 /* Setup the speed from PHY to internal reg*/
248 xlr_set_gmac_speed(priv);
249 netif_tx_start_all_queues(ndev);
250 return 0;
251}
252
253static int xlr_net_stop(struct net_device *ndev)
254{
255 struct xlr_net_priv *priv = netdev_priv(ndev);
256 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
257
258 phy_stop(phydev);
259 netif_tx_stop_all_queues(ndev);
260 return 0;
261}
262
263static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
264 struct sk_buff *skb)
265{
266 unsigned long physkb = virt_to_phys(skb);
267 int cpu_core = nlm_core_id();
268 int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */
269 msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */
270 ((u64)127 << 54) | /* No Free back */
271 (u64)skb->len << 40 | /* Length of data */
272 ((u64)addr));
273 msg->msg1 = (((u64)1 << 63) |
274 ((u64)fr_stn_id << 54) | /* Free back id */
275 (u64)0 << 40 | /* Set len to 0 */
276 ((u64)physkb & 0xffffffff)); /* 32bit address */
277 msg->msg2 = msg->msg3 = 0;
278}
279
280static void __maybe_unused xlr_wakeup_queue(unsigned long dev)
281{
282 struct net_device *ndev = (struct net_device *) dev;
283 struct xlr_net_priv *priv = netdev_priv(ndev);
284 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
285
286 if (phydev->link)
287 netif_tx_wake_queue(netdev_get_tx_queue(ndev, priv->wakeup_q));
288}
289
290static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
291 struct net_device *ndev)
292{
293 struct nlm_fmn_msg msg;
294 struct xlr_net_priv *priv = netdev_priv(ndev);
295 int ret;
6f98b1a2
GR		 296 u32 flags;
297
6f98b1a2
GR		 298 xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
299 flags = nlm_cop2_enable();
300 ret = nlm_fmn_send(2, 0, priv->nd->tx_stnid, &msg);
301 nlm_cop2_restore(flags);
302 if (ret)
303 dev_kfree_skb_any(skb);
304 return NETDEV_TX_OK;
305}
306
307static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb)
308{
309 return (u16)smp_processor_id();
310}
311
312static void xlr_hw_set_mac_addr(struct net_device *ndev)
313{
314 struct xlr_net_priv *priv = netdev_priv(ndev);
315
316 /* set mac station address */
317 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
318 ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
319 (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
320 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
321 ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
322
323 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
324 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
325 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
326 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
327
328 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
329 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
330 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
331 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
332
333 if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
334 priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
335 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
336}
337
338static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
339{
340 int err;
341
342 err = eth_mac_addr(ndev, data);
343 if (err)
344 return err;
345 xlr_hw_set_mac_addr(ndev);
346 return 0;
347}
348
349static void xlr_set_rx_mode(struct net_device *ndev)
350{
351 struct xlr_net_priv *priv = netdev_priv(ndev);
352 u32 regval;
353
354 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
355
356 if (ndev->flags & IFF_PROMISC) {
357 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
358 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
359 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
360 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
361 } else {
362 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
363 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
364 }
365
366 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
367}
368
369static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
370{
371 struct xlr_net_priv *priv = netdev_priv(ndev);
372
373 stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
374 stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
375 stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
376 stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
377 stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
378 stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
379 RX_DROP_PACKET_COUNTER);
380 stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
381 TX_DROP_FRAME_COUNTER);
382
383 stats->multicast = xlr_nae_rdreg(priv->base_addr,
384 RX_MULTICAST_PACKET_COUNTER);
385 stats->collisions = xlr_nae_rdreg(priv->base_addr,
386 TX_TOTAL_COLLISION_COUNTER);
387
388 stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
389 RX_FRAME_LENGTH_ERROR_COUNTER);
390 stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
391 RX_DROP_PACKET_COUNTER);
392 stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
393 RX_FCS_ERROR_COUNTER);
394 stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
395 RX_ALIGNMENT_ERROR_COUNTER);
396
397 stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
398 RX_DROP_PACKET_COUNTER);
399 stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
400 RX_CARRIER_SENSE_ERROR_COUNTER);
401
402 stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
403 stats->rx_frame_errors + stats->rx_fifo_errors +
404 stats->rx_missed_errors);
405
406 stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
407 TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
408 stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
409 TX_DROP_FRAME_COUNTER);
410 stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
411 TX_DROP_FRAME_COUNTER);
412}
413
414static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
415 struct rtnl_link_stats64 *stats)
416{
417 xlr_stats(ndev, stats);
418 return stats;
419}
420
421static struct net_device_ops xlr_netdev_ops = {
422 .ndo_open = xlr_net_open,
423 .ndo_stop = xlr_net_stop,
424 .ndo_start_xmit = xlr_net_start_xmit,
425 .ndo_select_queue = xlr_net_select_queue,
426 .ndo_set_mac_address = xlr_net_set_mac_addr,
427 .ndo_set_rx_mode = xlr_set_rx_mode,
428 .ndo_get_stats64 = xlr_get_stats64,
429};
430
431/* Gmac init */
432static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
433 int reg_start_1, int reg_size, int size)
434{
435 void *spill;
436 u32 *base;
437 unsigned long phys_addr;
438 u32 spill_size;
439
440 base = priv->base_addr;
441 spill_size = size;
442 spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
443 if (!spill)
444 pr_err("Unable to allocate memory for spill area!\n");
445
446 spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
447 phys_addr = virt_to_phys(spill);
448 dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
449 size, phys_addr);
450 xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
451 xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
452 xlr_nae_wreg(base, reg_size, spill_size);
453
454 return spill;
455}
456
457/*
458 * Configure the 6 FIFO's that are used by the network accelarator to
459 * communicate with the rest of the XLx device. 4 of the FIFO's are for
460 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
461 * the NA with free descriptors.
462 */
463static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
464{
465 priv->frin_spill = xlr_config_spill(priv,
466 R_REG_FRIN_SPILL_MEM_START_0,
467 R_REG_FRIN_SPILL_MEM_START_1,
468 R_REG_FRIN_SPILL_MEM_SIZE,
469 MAX_FRIN_SPILL *
470 sizeof(u64));
471 priv->frout_spill = xlr_config_spill(priv,
472 R_FROUT_SPILL_MEM_START_0,
473 R_FROUT_SPILL_MEM_START_1,
474 R_FROUT_SPILL_MEM_SIZE,
475 MAX_FROUT_SPILL *
476 sizeof(u64));
477 priv->class_0_spill = xlr_config_spill(priv,
478 R_CLASS0_SPILL_MEM_START_0,
479 R_CLASS0_SPILL_MEM_START_1,
480 R_CLASS0_SPILL_MEM_SIZE,
481 MAX_CLASS_0_SPILL *
482 sizeof(u64));
483 priv->class_1_spill = xlr_config_spill(priv,
484 R_CLASS1_SPILL_MEM_START_0,
485 R_CLASS1_SPILL_MEM_START_1,
486 R_CLASS1_SPILL_MEM_SIZE,
487 MAX_CLASS_1_SPILL *
488 sizeof(u64));
489 priv->class_2_spill = xlr_config_spill(priv,
490 R_CLASS2_SPILL_MEM_START_0,
491 R_CLASS2_SPILL_MEM_START_1,
492 R_CLASS2_SPILL_MEM_SIZE,
493 MAX_CLASS_2_SPILL *
494 sizeof(u64));
495 priv->class_3_spill = xlr_config_spill(priv,
496 R_CLASS3_SPILL_MEM_START_0,
497 R_CLASS3_SPILL_MEM_START_1,
498 R_CLASS3_SPILL_MEM_SIZE,
499 MAX_CLASS_3_SPILL *
500 sizeof(u64));
501}
502
503/* Configure PDE to Round-Robin distribution of packets to the
504 * available cpu */
505static void xlr_config_pde(struct xlr_net_priv *priv)
506{
507 int i = 0;
508 u64 bkt_map = 0;
509
510 /* Each core has 8 buckets(station) */
511 for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
512 bkt_map |= (0xff << (i * 8));
513
514 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
515 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
516 ((bkt_map >> 32) & 0xffffffff));
517
518 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
519 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
520 ((bkt_map >> 32) & 0xffffffff));
521
522 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
523 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
524 ((bkt_map >> 32) & 0xffffffff));
525
526 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
527 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
528 ((bkt_map >> 32) & 0xffffffff));
529}
530
531/* Setup the Message ring credits, bucket size and other
532 * common configuration */
533static void xlr_config_common(struct xlr_net_priv *priv)
534{
535 struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
536 int start_stn_id = gmac->start_stn_id;
537 int end_stn_id = gmac->end_stn_id;
538 int *bucket_size = priv->nd->bucket_size;
539 int i, j;
540
541 /* Setting non-core MsgBktSize(0x321 - 0x325) */
542 for (i = start_stn_id; i <= end_stn_id; i++) {
543 xlr_nae_wreg(priv->base_addr,
544 R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
545 bucket_size[i]);
546 }
547
548 /* Setting non-core Credit counter register
549 * Distributing Gmac's credit to CPU's*/
550 for (i = 0; i < 8; i++) {
551 for (j = 0; j < 8; j++)
552 xlr_nae_wreg(priv->base_addr,
553 (R_CC_CPU0_0 + (i * 8)) + j,
554 gmac->credit_config[(i * 8) + j]);
555 }
556
557 xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
558 xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
559 xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
560 xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
561 xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
562 xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
563
564 xlr_net_fill_rx_ring(priv->ndev);
565 nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
566 NULL);
567}
568
569static void xlr_config_translate_table(struct xlr_net_priv *priv)
570{
571 u32 cpu_mask;
572 u32 val;
573 int bkts[32]; /* one bucket is assumed for each cpu */
574 int b1, b2, c1, c2, i, j, k;
575 int use_bkt;
576
577 use_bkt = 0;
578 cpu_mask = priv->nd->cpu_mask;
579
580 pr_info("Using %s-based distribution\n",
581 (use_bkt) ? "bucket" : "class");
582 j = 0;
583 for (i = 0; i < 32; i++) {
584 if ((1 << i) & cpu_mask) {
585 /* for each cpu, mark the 4+threadid bucket */
586 bkts[j] = ((i / 4) * 8) + (i % 4);
587 j++;
588 }
589 }
590
591 /*configure the 128 * 9 Translation table to send to available buckets*/
592 k = 0;
593 c1 = 3;
594 c2 = 0;
595 for (i = 0; i < 64; i++) {
596 /* On use_bkt set the b0, b1 are used, else
597 * the 4 classes are used, here implemented
598 * a logic to distribute the packets to the
599 * buckets equally or based on the class
600 */
601 c1 = (c1 + 1) & 3;
602 c2 = (c1 + 1) & 3;
603 b1 = bkts[k];
604 k = (k + 1) % j;
605 b2 = bkts[k];
606 k = (k + 1) % j;
607 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
608 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
609
610 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
611 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
612 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
613 i, b1, b2, c1, c2);
614 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
615 c1 = c2;
616 }
617}
618
619static void xlr_config_parser(struct xlr_net_priv *priv)
620{
621 u32 val;
622
623 /* Mark it as ETHERNET type */
624 xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
625
626 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
627 xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
628 ((0x7f << 8) | (1 << 1)));
629
630 /* configure the parser : L2 Type is configured in the bootloader */
631 /* extract IP: src, dest protocol */
632 xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
633 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
634 (0x0800 << 0));
635 xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
636 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
637 (16 << 4) | 4);
638
639 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
640 xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
641 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
642 val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
643 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
644 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
645
646 xlr_config_translate_table(priv);
647}
648
649static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
650{
651 unsigned long timeout, stoptime, checktime;
652 int timedout;
653
654 /* 100ms timeout*/
655 timeout = msecs_to_jiffies(100);
656 stoptime = jiffies + timeout;
657 timedout = 0;
658
659 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
660
661 /* Write the data which starts the write cycle */
662 xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32) val);
663
664 /* poll for the read cycle to complete */
665 while (!timedout) {
666 checktime = jiffies;
667 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
668 break;
669 timedout = time_after(checktime, stoptime);
670 }
671 if (timedout) {
672 pr_info("Phy device write err: device busy");
673 return -EBUSY;
674 }
675
676 return 0;
677}
678
679static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
680{
681 unsigned long timeout, stoptime, checktime;
682 int timedout;
683
684 /* 100ms timeout*/
685 timeout = msecs_to_jiffies(100);
686 stoptime = jiffies + timeout;
687 timedout = 0;
688
689 /* setup the phy reg to be used */
690 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
691 (phy_addr << 8) | (regnum << 0));
692
693 /* Issue the read command */
694 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
695 (1 << O_MII_MGMT_COMMAND__rstat));
696
697
698 /* poll for the read cycle to complete */
699 while (!timedout) {
700 checktime = jiffies;
701 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
702 break;
703 timedout = time_after(checktime, stoptime);
704 }
705 if (timedout) {
706 pr_info("Phy device read err: device busy");
707 return -EBUSY;
708 }
709
710 /* clear the read cycle */
711 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
712
713 /* Read the data */
714 return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
715}
716
717static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
718{
719 struct xlr_net_priv *priv = bus->priv;
720 int ret;
721
722 ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
723 dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
724 phy_addr, regnum, val, ret);
725 return ret;
726}
727
728static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
729{
730 struct xlr_net_priv *priv = bus->priv;
731 int ret;
732
733 ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum);
734 dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
735 phy_addr, regnum, ret);
736 return ret;
737}
738
739/* XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
740 * which can be configured either SGMII or RGMII, considered SGMII
741 * by default, if board setup to RGMII the port_type need to set
742 * accordingly.Serdes and PCS layer need to configured for SGMII
743 */
744static void xlr_sgmii_init(struct xlr_net_priv *priv)
745{
746 int phy;
747
748 xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
749 xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
750 xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
751 xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
752 xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
753 xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
754 xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
755 xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
756 xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
757 xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
758 xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
759
760 /* program GPIO values for serdes init parameters */
761 xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
762 xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
763
764 xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
765 xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
766
767 /* enable autoneg - more magic */
768 phy = priv->port_id % 4 + 27;
769 xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
770 xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
771}
772
773void xlr_set_gmac_speed(struct xlr_net_priv *priv)
774{
775 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
776 int speed;
777
778 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
779 xlr_sgmii_init(priv);
780
781 if (phydev->speed != priv->phy_speed) {
782 pr_info("change %d to %d\n", priv->phy_speed, phydev->speed);
783 speed = phydev->speed;
784 if (speed == SPEED_1000) {
785 /* Set interface to Byte mode */
786 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
787 priv->phy_speed = speed;
788 } else if (speed == SPEED_100 || speed == SPEED_10) {
789 /* Set interface to Nibble mode */
790 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
791 priv->phy_speed = speed;
792 }
793 /* Set SGMII speed in Interface controll reg */
794 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
795 if (speed == SPEED_10)
796 xlr_nae_wreg(priv->base_addr,
797 R_INTERFACE_CONTROL, SGMII_SPEED_10);
798 if (speed == SPEED_100)
799 xlr_nae_wreg(priv->base_addr,
800 R_INTERFACE_CONTROL, SGMII_SPEED_100);
801 if (speed == SPEED_1000)
802 xlr_nae_wreg(priv->base_addr,
803 R_INTERFACE_CONTROL, SGMII_SPEED_1000);
804 }
805 if (speed == SPEED_10)
806 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
807 if (speed == SPEED_100)
808 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
809 if (speed == SPEED_1000)
810 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
811 }
812 pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
813}
814
815static void xlr_gmac_link_adjust(struct net_device *ndev)
816{
817 struct xlr_net_priv *priv = netdev_priv(ndev);
818 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
819 u32 intreg;
820
821 intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
822 if (phydev->link) {
823 if (phydev->speed != priv->phy_speed) {
824 pr_info("gmac%d : Link up\n", priv->port_id);
825 xlr_set_gmac_speed(priv);
826 }
827 } else {
828 pr_info("gmac%d : Link down\n", priv->port_id);
829 xlr_set_gmac_speed(priv);
830 }
831}
832
833static int xlr_mii_probe(struct xlr_net_priv *priv)
834{
835 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
836
837 if (!phydev) {
838 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
839 return -ENODEV;
840 }
841
842 /* Attach MAC to PHY */
843 phydev = phy_connect(priv->ndev, dev_name(&phydev->dev),
844 &xlr_gmac_link_adjust, priv->nd->phy_interface);
845
846 if (IS_ERR(phydev)) {
847 pr_err("could not attach PHY\n");
848 return PTR_ERR(phydev);
849 }
850 phydev->supported &= (ADVERTISED_10baseT_Full
851 | ADVERTISED_10baseT_Half
852 | ADVERTISED_100baseT_Full
853 | ADVERTISED_100baseT_Half
854 | ADVERTISED_1000baseT_Full
855 | ADVERTISED_Autoneg
856 | ADVERTISED_MII);
857
858 phydev->advertising = phydev->supported;
859 pr_info("attached PHY driver [%s] (mii_bus:phy_addr=%s\n",
860 phydev->drv->name, dev_name(&phydev->dev));
861 return 0;
862}
863
864static int xlr_setup_mdio(struct xlr_net_priv *priv,
865 struct platform_device *pdev)
866{
867 int err;
868
869 priv->phy_addr = priv->nd->phy_addr;
870 priv->mii_bus = mdiobus_alloc();
871 if (!priv->mii_bus) {
872 pr_err("mdiobus alloc failed\n");
873 return -ENOMEM;
874 }
875
876 priv->mii_bus->priv = priv;
877 priv->mii_bus->name = "xlr-mdio";
878 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
879 priv->mii_bus->name, priv->port_id);
880 priv->mii_bus->read = xlr_mii_read;
881 priv->mii_bus->write = xlr_mii_write;
882 priv->mii_bus->parent = &pdev->dev;
883 priv->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
884 priv->mii_bus->irq[priv->phy_addr] = priv->ndev->irq;
885
886 /* Scan only the enabled address */
887 priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
888
889 /* setting clock divisor to 54 */
890 xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
891
892 err = mdiobus_register(priv->mii_bus);
893 if (err) {
894 mdiobus_free(priv->mii_bus);
895 pr_err("mdio bus registration failed\n");
896 return err;
897 }
898
9d2ea4de 899 pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
6f98b1a2
GR		 900 err = xlr_mii_probe(priv);
901 if (err) {
902 mdiobus_free(priv->mii_bus);
903 return err;
904 }
905 return 0;
906}
907
908static void xlr_port_enable(struct xlr_net_priv *priv)
909{
910 u32 prid = (read_c0_prid() & 0xf000);
911
912 /* Setup MAC_CONFIG reg if (xls & rgmii) */
913 if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
914 priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
915 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
916 (1 << O_RX_CONTROL__RGMII), (1 << O_RX_CONTROL__RGMII));
917
918 /* Rx Tx enable */
919 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
920 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
921 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
922 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
923 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)));
924
925 /* Setup tx control reg */
926 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
927 ((1 << O_TX_CONTROL__TxEnable) |
928 (512 << O_TX_CONTROL__TxThreshold)), 0x3fff);
929
930 /* Setup rx control reg */
931 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
932 1 << O_RX_CONTROL__RxEnable, 1 << O_RX_CONTROL__RxEnable);
933}
934
935static void xlr_port_disable(struct xlr_net_priv *priv)
936{
937 /* Setup MAC_CONFIG reg */
938 /* Rx Tx disable*/
939 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
940 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
941 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
942 0x0);
943
944 /* Setup tx control reg */
945 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
946 ((1 << O_TX_CONTROL__TxEnable) |
947 (512 << O_TX_CONTROL__TxThreshold)), 0);
948
949 /* Setup rx control reg */
950 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
951 1 << O_RX_CONTROL__RxEnable, 0);
952}
953
954/* Initialization of gmac */
955static int xlr_gmac_init(struct xlr_net_priv *priv,
956 struct platform_device *pdev)
957{
958 int ret;
959
960 pr_info("Initializing the gmac%d\n", priv->port_id);
961
962 xlr_port_disable(priv);
963 xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
964 (1 << O_DESC_PACK_CTRL__MaxEntry)
965 | (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset)
966 | (1600 << O_DESC_PACK_CTRL__RegularSize));
967
968 ret = xlr_setup_mdio(priv, pdev);
969 if (ret)
970 return ret;
971 xlr_port_enable(priv);
972
973 /* Enable Full-duplex/1000Mbps/CRC */
974 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
975 /* speed 2.5Mhz */
976 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
977 /* Setup Interrupt mask reg */
978 xlr_nae_wreg(priv->base_addr, R_INTMASK,
979 (1 << O_INTMASK__TxIllegal) |
980 (1 << O_INTMASK__MDInt) |
981 (1 << O_INTMASK__TxFetchError) |
982 (1 << O_INTMASK__P2PSpillEcc) |
983 (1 << O_INTMASK__TagFull) |
984 (1 << O_INTMASK__Underrun) |
985 (1 << O_INTMASK__Abort)
986 );
987
988 /* Clear all stats */
989 xlr_reg_update(priv->base_addr, R_STATCTRL,
990 0, 1 << O_STATCTRL__ClrCnt);
991 xlr_reg_update(priv->base_addr, R_STATCTRL,
992 1 << O_STATCTRL__ClrCnt, 1 << O_STATCTRL__ClrCnt);
993 return 0;
994}
995
996static int xlr_net_probe(struct platform_device *pdev)
997{
998 struct xlr_net_priv *priv = NULL;
999 struct net_device *ndev;
1000 struct resource *res;
1001 int mac, err;
1002
1003 mac = pdev->id;
1004 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1005 if (!ndev) {
1006 pr_err("Allocation of Ethernet device failed\n");
1007 return -ENOMEM;
1008 }
1009
1010 priv = netdev_priv(ndev);
1011 priv->pdev = pdev;
1012 priv->ndev = ndev;
1013 priv->port_id = mac;
1014 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1015
1016 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1017 if (res == NULL) {
1018 pr_err("No memory resource for MAC %d\n", mac);
1019 err = -ENODEV;
1020 goto err_gmac;
1021 }
1022
803c83fc 1023 ndev->base_addr = (unsigned long) devm_ioremap_resource
6f98b1a2 1024 (&pdev->dev, res);
803c83fc 1025 if (IS_ERR_VALUE(ndev->base_addr)) {
c639b9fb
WY		 1026 err = ndev->base_addr;
1027 goto err_gmac;
6f98b1a2
GR		 1028 }
1029
1030 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1031 if (res == NULL) {
1032 pr_err("No irq resource for MAC %d\n", mac);
1033 err = -ENODEV;
1034 goto err_gmac;
1035 }
1036 ndev->irq = res->start;
1037
1038 priv->mii_addr = priv->nd->mii_addr;
1039 priv->serdes_addr = priv->nd->serdes_addr;
1040 priv->pcs_addr = priv->nd->pcs_addr;
1041 priv->gpio_addr = priv->nd->gpio_addr;
1042 priv->base_addr = (u32 *) ndev->base_addr;
1043
1044 mac_to_ndev[mac] = ndev;
1045 ndev->netdev_ops = &xlr_netdev_ops;
1046 ndev->watchdog_timeo = HZ;
1047
1048 /* Setup Mac address and Rx mode */
1049 eth_hw_addr_random(ndev);
1050 xlr_hw_set_mac_addr(ndev);
1051 xlr_set_rx_mode(ndev);
1052
1053 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1054 SET_ETHTOOL_OPS(ndev, &xlr_ethtool_ops);
1055 SET_NETDEV_DEV(ndev, &pdev->dev);
1056
1057 /* Common registers, do one time initialization */
1058 if (mac == 0 || mac == 4) {
1059 xlr_config_fifo_spill_area(priv);
1060 /* Configure PDE to Round-Robin pkt distribution */
1061 xlr_config_pde(priv);
1062 xlr_config_parser(priv);
1063 }
1064 /* Call init with respect to port */
1065 if (strcmp(res->name, "gmac") == 0) {
1066 err = xlr_gmac_init(priv, pdev);
1067 if (err) {
1068 pr_err("gmac%d init failed\n", mac);
1069 goto err_gmac;
1070 }
1071 }
1072
1073 if (mac == 0 || mac == 4)
1074 xlr_config_common(priv);
1075
1076 err = register_netdev(ndev);
1077 if (err)
1078 goto err_netdev;
1079 platform_set_drvdata(pdev, priv);
1080 return 0;
1081
1082err_netdev:
1083 mdiobus_free(priv->mii_bus);
1084err_gmac:
1085 free_netdev(ndev);
1086 return err;
1087}
1088
1089static int xlr_net_remove(struct platform_device *pdev)
1090{
1091 struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1092 unregister_netdev(priv->ndev);
1093 mdiobus_unregister(priv->mii_bus);
1094 mdiobus_free(priv->mii_bus);
1095 free_netdev(priv->ndev);
1096 return 0;
1097}
1098
1099static struct platform_driver xlr_net_driver = {
1100 .probe = xlr_net_probe,
1101 .remove = xlr_net_remove,
1102 .driver = {
1103 .name = "xlr-net",
1104 .owner = THIS_MODULE,
1105 },
1106};
1107
1108module_platform_driver(xlr_net_driver);
1109
1110MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1111MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1112MODULE_LICENSE("Dual BSD/GPL");
1113MODULE_ALIAS("platform:xlr-net");
Linux kernel - Deliverables
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