Commit | Line | Data |
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162c7d8c MD |
1 | /* |
2 | * NVEC: NVIDIA compliant embedded controller interface | |
3 | * | |
4 | * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net> | |
5 | * | |
6 | * Authors: Pierre-Hugues Husson <phhusson@free.fr> | |
7 | * Ilya Petrov <ilya.muromec@gmail.com> | |
8 | * Marc Dietrich <marvin24@gmx.de> | |
791c4a64 | 9 | * Julian Andres Klode <jak@jak-linux.org> |
162c7d8c MD |
10 | * |
11 | * This file is subject to the terms and conditions of the GNU General Public | |
12 | * License. See the file "COPYING" in the main directory of this archive | |
13 | * for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | /* #define DEBUG */ | |
32890b98 | 18 | |
12b5a55d | 19 | #include <linux/kernel.h> |
3b769edd | 20 | #include <linux/module.h> |
0b1076c4 | 21 | #include <linux/atomic.h> |
12b5a55d | 22 | #include <linux/clk.h> |
32890b98 | 23 | #include <linux/completion.h> |
12b5a55d JAK |
24 | #include <linux/delay.h> |
25 | #include <linux/err.h> | |
26 | #include <linux/gpio.h> | |
32890b98 | 27 | #include <linux/interrupt.h> |
162c7d8c | 28 | #include <linux/io.h> |
32890b98 | 29 | #include <linux/irq.h> |
7990b0d7 MD |
30 | #include <linux/of.h> |
31 | #include <linux/of_gpio.h> | |
32890b98 | 32 | #include <linux/list.h> |
12b5a55d JAK |
33 | #include <linux/mfd/core.h> |
34 | #include <linux/mutex.h> | |
32890b98 | 35 | #include <linux/notifier.h> |
12b5a55d JAK |
36 | #include <linux/slab.h> |
37 | #include <linux/spinlock.h> | |
38 | #include <linux/workqueue.h> | |
162c7d8c | 39 | |
32890b98 MD |
40 | #include "nvec.h" |
41 | ||
391d2fa9 | 42 | #define I2C_CNFG 0x00 |
b4129f2f BA |
43 | #define I2C_CNFG_PACKET_MODE_EN (1 << 10) |
44 | #define I2C_CNFG_NEW_MASTER_SFM (1 << 11) | |
391d2fa9 JAK |
45 | #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 |
46 | ||
47 | #define I2C_SL_CNFG 0x20 | |
b4129f2f BA |
48 | #define I2C_SL_NEWSL (1 << 2) |
49 | #define I2C_SL_NACK (1 << 1) | |
50 | #define I2C_SL_RESP (1 << 0) | |
51 | #define I2C_SL_IRQ (1 << 3) | |
52 | #define END_TRANS (1 << 4) | |
53 | #define RCVD (1 << 2) | |
54 | #define RNW (1 << 1) | |
391d2fa9 JAK |
55 | |
56 | #define I2C_SL_RCVD 0x24 | |
57 | #define I2C_SL_STATUS 0x28 | |
58 | #define I2C_SL_ADDR1 0x2c | |
59 | #define I2C_SL_ADDR2 0x30 | |
60 | #define I2C_SL_DELAY_COUNT 0x3c | |
61 | ||
bb0590e2 JAK |
62 | /** |
63 | * enum nvec_msg_category - Message categories for nvec_msg_alloc() | |
64 | * @NVEC_MSG_RX: The message is an incoming message (from EC) | |
65 | * @NVEC_MSG_TX: The message is an outgoing message (to EC) | |
66 | */ | |
67 | enum nvec_msg_category { | |
68 | NVEC_MSG_RX, | |
69 | NVEC_MSG_TX, | |
70 | }; | |
71 | ||
518945fb MD |
72 | enum nvec_sleep_subcmds { |
73 | GLOBAL_EVENTS, | |
93eff83f MD |
74 | AP_PWR_DOWN, |
75 | AP_SUSPEND, | |
518945fb MD |
76 | }; |
77 | ||
93eff83f MD |
78 | #define CNF_EVENT_REPORTING 0x01 |
79 | #define GET_FIRMWARE_VERSION 0x15 | |
80 | #define LID_SWITCH BIT(1) | |
81 | #define PWR_BUTTON BIT(15) | |
32890b98 MD |
82 | |
83 | static struct nvec_chip *nvec_power_handle; | |
84 | ||
28397dc9 | 85 | static const struct mfd_cell nvec_devices[] = { |
f686e9af | 86 | { |
162c7d8c | 87 | .name = "nvec-kbd", |
f686e9af MD |
88 | }, |
89 | { | |
162c7d8c | 90 | .name = "nvec-mouse", |
f686e9af MD |
91 | }, |
92 | { | |
162c7d8c | 93 | .name = "nvec-power", |
3ec69881 | 94 | .id = 0, |
f686e9af MD |
95 | }, |
96 | { | |
162c7d8c | 97 | .name = "nvec-power", |
3ec69881 | 98 | .id = 1, |
f686e9af | 99 | }, |
97cc2657 | 100 | { |
ac562680 | 101 | .name = "nvec-paz00", |
97cc2657 | 102 | }, |
f686e9af MD |
103 | }; |
104 | ||
bdf034d9 JAK |
105 | /** |
106 | * nvec_register_notifier - Register a notifier with nvec | |
107 | * @nvec: A &struct nvec_chip | |
108 | * @nb: The notifier block to register | |
109 | * | |
110 | * Registers a notifier with @nvec. The notifier will be added to an atomic | |
111 | * notifier chain that is called for all received messages except those that | |
112 | * correspond to a request initiated by nvec_write_sync(). | |
113 | */ | |
32890b98 | 114 | int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb, |
162c7d8c | 115 | unsigned int events) |
32890b98 MD |
116 | { |
117 | return atomic_notifier_chain_register(&nvec->notifier_list, nb); | |
118 | } | |
119 | EXPORT_SYMBOL_GPL(nvec_register_notifier); | |
120 | ||
111c1587 MD |
121 | /** |
122 | * nvec_unregister_notifier - Unregister a notifier with nvec | |
123 | * @nvec: A &struct nvec_chip | |
124 | * @nb: The notifier block to unregister | |
125 | * | |
126 | * Unregisters a notifier with @nvec. The notifier will be removed from the | |
127 | * atomic notifier chain. | |
128 | */ | |
129 | int nvec_unregister_notifier(struct nvec_chip *nvec, struct notifier_block *nb) | |
130 | { | |
131 | return atomic_notifier_chain_unregister(&nvec->notifier_list, nb); | |
132 | } | |
133 | EXPORT_SYMBOL_GPL(nvec_unregister_notifier); | |
134 | ||
bdf034d9 JAK |
135 | /** |
136 | * nvec_status_notifier - The final notifier | |
137 | * | |
138 | * Prints a message about control events not handled in the notifier | |
139 | * chain. | |
140 | */ | |
162c7d8c MD |
141 | static int nvec_status_notifier(struct notifier_block *nb, |
142 | unsigned long event_type, void *data) | |
32890b98 | 143 | { |
50d4656a MD |
144 | struct nvec_chip *nvec = container_of(nb, struct nvec_chip, |
145 | nvec_status_notifier); | |
32890b98 | 146 | unsigned char *msg = (unsigned char *)data; |
32890b98 | 147 | |
162c7d8c | 148 | if (event_type != NVEC_CNTL) |
32890b98 MD |
149 | return NOTIFY_DONE; |
150 | ||
50d4656a | 151 | dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type); |
a3a9aa1a MD |
152 | print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1, |
153 | msg, msg[1] + 2, true); | |
32890b98 MD |
154 | |
155 | return NOTIFY_OK; | |
156 | } | |
157 | ||
bdf034d9 JAK |
158 | /** |
159 | * nvec_msg_alloc: | |
160 | * @nvec: A &struct nvec_chip | |
bb0590e2 | 161 | * @category: Pool category, see &enum nvec_msg_category |
bdf034d9 JAK |
162 | * |
163 | * Allocate a single &struct nvec_msg object from the message pool of | |
164 | * @nvec. The result shall be passed to nvec_msg_free() if no longer | |
165 | * used. | |
bb0590e2 JAK |
166 | * |
167 | * Outgoing messages are placed in the upper 75% of the pool, keeping the | |
168 | * lower 25% available for RX buffers only. The reason is to prevent a | |
169 | * situation where all buffers are full and a message is thus endlessly | |
170 | * retried because the response could never be processed. | |
bdf034d9 | 171 | */ |
bb0590e2 JAK |
172 | static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec, |
173 | enum nvec_msg_category category) | |
0b1076c4 | 174 | { |
bb0590e2 | 175 | int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0; |
0b1076c4 | 176 | |
bb0590e2 | 177 | for (; i < NVEC_POOL_SIZE; i++) { |
0b1076c4 JAK |
178 | if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) { |
179 | dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i); | |
180 | return &nvec->msg_pool[i]; | |
181 | } | |
182 | } | |
183 | ||
bb0590e2 JAK |
184 | dev_err(nvec->dev, "could not allocate %s buffer\n", |
185 | (category == NVEC_MSG_TX) ? "TX" : "RX"); | |
0b1076c4 JAK |
186 | |
187 | return NULL; | |
188 | } | |
189 | ||
bdf034d9 JAK |
190 | /** |
191 | * nvec_msg_free: | |
192 | * @nvec: A &struct nvec_chip | |
193 | * @msg: A message (must be allocated by nvec_msg_alloc() and belong to @nvec) | |
194 | * | |
195 | * Free the given message | |
196 | */ | |
705a4212 | 197 | void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg) |
0b1076c4 | 198 | { |
7b770657 JAK |
199 | if (msg != &nvec->tx_scratch) |
200 | dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool); | |
0b1076c4 JAK |
201 | atomic_set(&msg->used, 0); |
202 | } | |
198dd267 | 203 | EXPORT_SYMBOL_GPL(nvec_msg_free); |
0b1076c4 | 204 | |
8517e879 JAK |
205 | /** |
206 | * nvec_msg_is_event - Return %true if @msg is an event | |
207 | * @msg: A message | |
208 | */ | |
209 | static bool nvec_msg_is_event(struct nvec_msg *msg) | |
210 | { | |
211 | return msg->data[0] >> 7; | |
212 | } | |
213 | ||
214 | /** | |
215 | * nvec_msg_size - Get the size of a message | |
216 | * @msg: The message to get the size for | |
217 | * | |
218 | * This only works for received messages, not for outgoing messages. | |
219 | */ | |
220 | static size_t nvec_msg_size(struct nvec_msg *msg) | |
221 | { | |
222 | bool is_event = nvec_msg_is_event(msg); | |
223 | int event_length = (msg->data[0] & 0x60) >> 5; | |
224 | ||
225 | /* for variable size, payload size in byte 1 + count (1) + cmd (1) */ | |
226 | if (!is_event || event_length == NVEC_VAR_SIZE) | |
227 | return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0; | |
228 | else if (event_length == NVEC_2BYTES) | |
229 | return 2; | |
230 | else if (event_length == NVEC_3BYTES) | |
231 | return 3; | |
aea2cda3 | 232 | return 0; |
8517e879 JAK |
233 | } |
234 | ||
bdf034d9 JAK |
235 | /** |
236 | * nvec_gpio_set_value - Set the GPIO value | |
237 | * @nvec: A &struct nvec_chip | |
238 | * @value: The value to write (0 or 1) | |
239 | * | |
240 | * Like gpio_set_value(), but generating debugging information | |
241 | */ | |
e7c40851 JAK |
242 | static void nvec_gpio_set_value(struct nvec_chip *nvec, int value) |
243 | { | |
244 | dev_dbg(nvec->dev, "GPIO changed from %u to %u\n", | |
245 | gpio_get_value(nvec->gpio), value); | |
246 | gpio_set_value(nvec->gpio, value); | |
247 | } | |
248 | ||
bdf034d9 JAK |
249 | /** |
250 | * nvec_write_async - Asynchronously write a message to NVEC | |
251 | * @nvec: An nvec_chip instance | |
252 | * @data: The message data, starting with the request type | |
253 | * @size: The size of @data | |
254 | * | |
255 | * Queue a single message to be transferred to the embedded controller | |
256 | * and return immediately. | |
257 | * | |
258 | * Returns: 0 on success, a negative error code on failure. If a failure | |
9b872a74 | 259 | * occurred, the nvec driver may print an error. |
bdf034d9 | 260 | */ |
1b9bf629 | 261 | int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data, |
162c7d8c | 262 | short size) |
32890b98 | 263 | { |
0cab4cb8 JAK |
264 | struct nvec_msg *msg; |
265 | unsigned long flags; | |
32890b98 | 266 | |
bb0590e2 JAK |
267 | msg = nvec_msg_alloc(nvec, NVEC_MSG_TX); |
268 | ||
1b9bf629 JAK |
269 | if (msg == NULL) |
270 | return -ENOMEM; | |
271 | ||
32890b98 MD |
272 | msg->data[0] = size; |
273 | memcpy(msg->data + 1, data, size); | |
274 | msg->size = size + 1; | |
32890b98 | 275 | |
0cab4cb8 | 276 | spin_lock_irqsave(&nvec->tx_lock, flags); |
32890b98 | 277 | list_add_tail(&msg->node, &nvec->tx_data); |
0cab4cb8 | 278 | spin_unlock_irqrestore(&nvec->tx_lock, flags); |
32890b98 | 279 | |
033d9959 | 280 | schedule_work(&nvec->tx_work); |
1b9bf629 JAK |
281 | |
282 | return 0; | |
32890b98 MD |
283 | } |
284 | EXPORT_SYMBOL(nvec_write_async); | |
285 | ||
bdf034d9 JAK |
286 | /** |
287 | * nvec_write_sync - Write a message to nvec and read the response | |
288 | * @nvec: An &struct nvec_chip | |
289 | * @data: The data to write | |
290 | * @size: The size of @data | |
291 | * | |
292 | * This is similar to nvec_write_async(), but waits for the | |
293 | * request to be answered before returning. This function | |
294 | * uses a mutex and can thus not be called from e.g. | |
295 | * interrupt handlers. | |
296 | * | |
297 | * Returns: A pointer to the response message on success, | |
198dd267 JAK |
298 | * %NULL on failure. Free with nvec_msg_free() once no longer |
299 | * used. | |
bdf034d9 | 300 | */ |
0cab4cb8 JAK |
301 | struct nvec_msg *nvec_write_sync(struct nvec_chip *nvec, |
302 | const unsigned char *data, short size) | |
303 | { | |
304 | struct nvec_msg *msg; | |
305 | ||
306 | mutex_lock(&nvec->sync_write_mutex); | |
307 | ||
308 | nvec->sync_write_pending = (data[1] << 8) + data[0]; | |
1b9bf629 | 309 | |
4b8bf03d MD |
310 | if (nvec_write_async(nvec, data, size) < 0) { |
311 | mutex_unlock(&nvec->sync_write_mutex); | |
1b9bf629 | 312 | return NULL; |
4b8bf03d | 313 | } |
0cab4cb8 JAK |
314 | |
315 | dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n", | |
316 | nvec->sync_write_pending); | |
317 | if (!(wait_for_completion_timeout(&nvec->sync_write, | |
318 | msecs_to_jiffies(2000)))) { | |
319 | dev_warn(nvec->dev, "timeout waiting for sync write to complete\n"); | |
320 | mutex_unlock(&nvec->sync_write_mutex); | |
321 | return NULL; | |
322 | } | |
323 | ||
324 | dev_dbg(nvec->dev, "nvec_sync_write: pong!\n"); | |
325 | ||
326 | msg = nvec->last_sync_msg; | |
327 | ||
328 | mutex_unlock(&nvec->sync_write_mutex); | |
329 | ||
330 | return msg; | |
331 | } | |
332 | EXPORT_SYMBOL(nvec_write_sync); | |
333 | ||
518945fb MD |
334 | /** |
335 | * nvec_toggle_global_events - enables or disables global event reporting | |
336 | * @nvec: nvec handle | |
337 | * @state: true for enable, false for disable | |
338 | * | |
339 | * This switches on/off global event reports by the embedded controller. | |
340 | */ | |
341 | static void nvec_toggle_global_events(struct nvec_chip *nvec, bool state) | |
342 | { | |
343 | unsigned char global_events[] = { NVEC_SLEEP, GLOBAL_EVENTS, state }; | |
344 | ||
345 | nvec_write_async(nvec, global_events, 3); | |
346 | } | |
347 | ||
93eff83f MD |
348 | /** |
349 | * nvec_event_mask - fill the command string with event bitfield | |
350 | * ev: points to event command string | |
351 | * mask: bit to insert into the event mask | |
352 | * | |
353 | * Configure event command expects a 32 bit bitfield which describes | |
354 | * which events to enable. The bitfield has the following structure | |
355 | * (from highest byte to lowest): | |
356 | * system state bits 7-0 | |
357 | * system state bits 15-8 | |
358 | * oem system state bits 7-0 | |
359 | * oem system state bits 15-8 | |
360 | */ | |
361 | static void nvec_event_mask(char *ev, u32 mask) | |
362 | { | |
815fb010 WY |
363 | ev[3] = mask >> 16 & 0xff; |
364 | ev[4] = mask >> 24 & 0xff; | |
365 | ev[5] = mask >> 0 & 0xff; | |
366 | ev[6] = mask >> 8 & 0xff; | |
93eff83f MD |
367 | } |
368 | ||
bdf034d9 JAK |
369 | /** |
370 | * nvec_request_master - Process outgoing messages | |
371 | * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip) | |
372 | * | |
373 | * Processes all outgoing requests by sending the request and awaiting the | |
374 | * response, then continuing with the next request. Once a request has a | |
375 | * matching response, it will be freed and removed from the list. | |
376 | */ | |
32890b98 MD |
377 | static void nvec_request_master(struct work_struct *work) |
378 | { | |
379 | struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work); | |
0cab4cb8 JAK |
380 | unsigned long flags; |
381 | long err; | |
382 | struct nvec_msg *msg; | |
383 | ||
384 | spin_lock_irqsave(&nvec->tx_lock, flags); | |
385 | while (!list_empty(&nvec->tx_data)) { | |
386 | msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node); | |
387 | spin_unlock_irqrestore(&nvec->tx_lock, flags); | |
388 | nvec_gpio_set_value(nvec, 0); | |
389 | err = wait_for_completion_interruptible_timeout( | |
390 | &nvec->ec_transfer, msecs_to_jiffies(5000)); | |
391 | ||
392 | if (err == 0) { | |
393 | dev_warn(nvec->dev, "timeout waiting for ec transfer\n"); | |
394 | nvec_gpio_set_value(nvec, 1); | |
395 | msg->pos = 0; | |
396 | } | |
32890b98 | 397 | |
0cab4cb8 JAK |
398 | spin_lock_irqsave(&nvec->tx_lock, flags); |
399 | ||
400 | if (err > 0) { | |
401 | list_del_init(&msg->node); | |
402 | nvec_msg_free(nvec, msg); | |
403 | } | |
404 | } | |
405 | spin_unlock_irqrestore(&nvec->tx_lock, flags); | |
32890b98 MD |
406 | } |
407 | ||
bdf034d9 JAK |
408 | /** |
409 | * parse_msg - Print some information and call the notifiers on an RX message | |
410 | * @nvec: A &struct nvec_chip | |
411 | * @msg: A message received by @nvec | |
412 | * | |
413 | * Paarse some pieces of the message and then call the chain of notifiers | |
414 | * registered via nvec_register_notifier. | |
415 | */ | |
32890b98 MD |
416 | static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg) |
417 | { | |
162c7d8c | 418 | if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) { |
6a371978 | 419 | dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data); |
32890b98 MD |
420 | return -EINVAL; |
421 | } | |
422 | ||
a3a9aa1a MD |
423 | if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5) |
424 | print_hex_dump(KERN_WARNING, "ec system event ", | |
425 | DUMP_PREFIX_NONE, 16, 1, msg->data, | |
426 | msg->data[1] + 2, true); | |
32890b98 | 427 | |
162c7d8c MD |
428 | atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f, |
429 | msg->data); | |
32890b98 MD |
430 | |
431 | return 0; | |
432 | } | |
433 | ||
bdf034d9 JAK |
434 | /** |
435 | * nvec_dispatch - Process messages received from the EC | |
436 | * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip) | |
437 | * | |
438 | * Process messages previously received from the EC and put into the RX | |
439 | * queue of the &struct nvec_chip instance associated with @work. | |
440 | */ | |
32890b98 MD |
441 | static void nvec_dispatch(struct work_struct *work) |
442 | { | |
443 | struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work); | |
0cab4cb8 | 444 | unsigned long flags; |
32890b98 MD |
445 | struct nvec_msg *msg; |
446 | ||
0cab4cb8 | 447 | spin_lock_irqsave(&nvec->rx_lock, flags); |
162c7d8c | 448 | while (!list_empty(&nvec->rx_data)) { |
32890b98 MD |
449 | msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node); |
450 | list_del_init(&msg->node); | |
0cab4cb8 | 451 | spin_unlock_irqrestore(&nvec->rx_lock, flags); |
32890b98 | 452 | |
162c7d8c | 453 | if (nvec->sync_write_pending == |
0cab4cb8 | 454 | (msg->data[2] << 8) + msg->data[0]) { |
32890b98 MD |
455 | dev_dbg(nvec->dev, "sync write completed!\n"); |
456 | nvec->sync_write_pending = 0; | |
457 | nvec->last_sync_msg = msg; | |
458 | complete(&nvec->sync_write); | |
459 | } else { | |
460 | parse_msg(nvec, msg); | |
0cab4cb8 | 461 | nvec_msg_free(nvec, msg); |
32890b98 | 462 | } |
0cab4cb8 | 463 | spin_lock_irqsave(&nvec->rx_lock, flags); |
32890b98 | 464 | } |
0cab4cb8 | 465 | spin_unlock_irqrestore(&nvec->rx_lock, flags); |
32890b98 MD |
466 | } |
467 | ||
bdf034d9 JAK |
468 | /** |
469 | * nvec_tx_completed - Complete the current transfer | |
470 | * @nvec: A &struct nvec_chip | |
471 | * | |
472 | * This is called when we have received an END_TRANS on a TX transfer. | |
473 | */ | |
0cab4cb8 JAK |
474 | static void nvec_tx_completed(struct nvec_chip *nvec) |
475 | { | |
476 | /* We got an END_TRANS, let's skip this, maybe there's an event */ | |
477 | if (nvec->tx->pos != nvec->tx->size) { | |
478 | dev_err(nvec->dev, "premature END_TRANS, resending\n"); | |
479 | nvec->tx->pos = 0; | |
480 | nvec_gpio_set_value(nvec, 0); | |
481 | } else { | |
482 | nvec->state = 0; | |
483 | } | |
484 | } | |
485 | ||
bdf034d9 JAK |
486 | /** |
487 | * nvec_rx_completed - Complete the current transfer | |
488 | * @nvec: A &struct nvec_chip | |
489 | * | |
490 | * This is called when we have received an END_TRANS on a RX transfer. | |
491 | */ | |
0cab4cb8 JAK |
492 | static void nvec_rx_completed(struct nvec_chip *nvec) |
493 | { | |
210ceb4f | 494 | if (nvec->rx->pos != nvec_msg_size(nvec->rx)) { |
0cab4cb8 JAK |
495 | dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n", |
496 | (uint) nvec_msg_size(nvec->rx), | |
497 | (uint) nvec->rx->pos); | |
498 | ||
210ceb4f JAK |
499 | nvec_msg_free(nvec, nvec->rx); |
500 | nvec->state = 0; | |
d6bdcf2e JAK |
501 | |
502 | /* Battery quirk - Often incomplete, and likes to crash */ | |
503 | if (nvec->rx->data[0] == NVEC_BAT) | |
504 | complete(&nvec->ec_transfer); | |
505 | ||
210ceb4f JAK |
506 | return; |
507 | } | |
508 | ||
0cab4cb8 JAK |
509 | spin_lock(&nvec->rx_lock); |
510 | ||
511 | /* add the received data to the work list | |
512 | and move the ring buffer pointer to the next entry */ | |
513 | list_add_tail(&nvec->rx->node, &nvec->rx_data); | |
514 | ||
515 | spin_unlock(&nvec->rx_lock); | |
516 | ||
517 | nvec->state = 0; | |
518 | ||
519 | if (!nvec_msg_is_event(nvec->rx)) | |
520 | complete(&nvec->ec_transfer); | |
521 | ||
033d9959 | 522 | schedule_work(&nvec->rx_work); |
0cab4cb8 JAK |
523 | } |
524 | ||
525 | /** | |
526 | * nvec_invalid_flags - Send an error message about invalid flags and jump | |
527 | * @nvec: The nvec device | |
528 | * @status: The status flags | |
529 | * @reset: Whether we shall jump to state 0. | |
530 | */ | |
531 | static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status, | |
532 | bool reset) | |
533 | { | |
534 | dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n", | |
535 | status, nvec->state); | |
536 | if (reset) | |
537 | nvec->state = 0; | |
538 | } | |
539 | ||
540 | /** | |
541 | * nvec_tx_set - Set the message to transfer (nvec->tx) | |
bdf034d9 JAK |
542 | * @nvec: A &struct nvec_chip |
543 | * | |
544 | * Gets the first entry from the tx_data list of @nvec and sets the | |
545 | * tx member to it. If the tx_data list is empty, this uses the | |
546 | * tx_scratch message to send a no operation message. | |
0cab4cb8 JAK |
547 | */ |
548 | static void nvec_tx_set(struct nvec_chip *nvec) | |
549 | { | |
550 | spin_lock(&nvec->tx_lock); | |
551 | if (list_empty(&nvec->tx_data)) { | |
552 | dev_err(nvec->dev, "empty tx - sending no-op\n"); | |
553 | memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3); | |
554 | nvec->tx_scratch.size = 3; | |
555 | nvec->tx_scratch.pos = 0; | |
556 | nvec->tx = &nvec->tx_scratch; | |
557 | list_add_tail(&nvec->tx->node, &nvec->tx_data); | |
558 | } else { | |
559 | nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg, | |
560 | node); | |
561 | nvec->tx->pos = 0; | |
562 | } | |
563 | spin_unlock(&nvec->tx_lock); | |
564 | ||
565 | dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n", | |
566 | (uint)nvec->tx->size, nvec->tx->data[1]); | |
567 | } | |
568 | ||
569 | /** | |
570 | * nvec_interrupt - Interrupt handler | |
571 | * @irq: The IRQ | |
572 | * @dev: The nvec device | |
bdf034d9 JAK |
573 | * |
574 | * Interrupt handler that fills our RX buffers and empties our TX | |
575 | * buffers. This uses a finite state machine with ridiculous amounts | |
576 | * of error checking, in order to be fairly reliable. | |
0cab4cb8 | 577 | */ |
f686e9af | 578 | static irqreturn_t nvec_interrupt(int irq, void *dev) |
32890b98 MD |
579 | { |
580 | unsigned long status; | |
0cab4cb8 JAK |
581 | unsigned int received = 0; |
582 | unsigned char to_send = 0xff; | |
583 | const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW; | |
584 | struct nvec_chip *nvec = dev; | |
585 | unsigned int state = nvec->state; | |
32890b98 | 586 | |
0cab4cb8 | 587 | status = readl(nvec->base + I2C_SL_STATUS); |
32890b98 | 588 | |
0cab4cb8 JAK |
589 | /* Filter out some errors */ |
590 | if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) { | |
591 | dev_err(nvec->dev, "unexpected irq mask %lx\n", status); | |
592 | return IRQ_HANDLED; | |
32890b98 | 593 | } |
0cab4cb8 JAK |
594 | if ((status & I2C_SL_IRQ) == 0) { |
595 | dev_err(nvec->dev, "Spurious IRQ\n"); | |
32890b98 | 596 | return IRQ_HANDLED; |
0cab4cb8 | 597 | } |
32890b98 | 598 | |
0cab4cb8 JAK |
599 | /* The EC did not request a read, so it send us something, read it */ |
600 | if ((status & RNW) == 0) { | |
601 | received = readl(nvec->base + I2C_SL_RCVD); | |
162c7d8c | 602 | if (status & RCVD) |
0cab4cb8 JAK |
603 | writel(0, nvec->base + I2C_SL_RCVD); |
604 | } | |
162c7d8c | 605 | |
0cab4cb8 JAK |
606 | if (status == (I2C_SL_IRQ | RCVD)) |
607 | nvec->state = 0; | |
608 | ||
609 | switch (nvec->state) { | |
610 | case 0: /* Verify that its a transfer start, the rest later */ | |
611 | if (status != (I2C_SL_IRQ | RCVD)) | |
612 | nvec_invalid_flags(nvec, status, false); | |
613 | break; | |
614 | case 1: /* command byte */ | |
615 | if (status != I2C_SL_IRQ) { | |
616 | nvec_invalid_flags(nvec, status, true); | |
32890b98 | 617 | } else { |
bb0590e2 | 618 | nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX); |
8da79863 JAK |
619 | /* Should not happen in a normal world */ |
620 | if (unlikely(nvec->rx == NULL)) { | |
621 | nvec->state = 0; | |
622 | break; | |
623 | } | |
0cab4cb8 JAK |
624 | nvec->rx->data[0] = received; |
625 | nvec->rx->pos = 1; | |
626 | nvec->state = 2; | |
627 | } | |
628 | break; | |
629 | case 2: /* first byte after command */ | |
630 | if (status == (I2C_SL_IRQ | RNW | RCVD)) { | |
631 | udelay(33); | |
632 | if (nvec->rx->data[0] != 0x01) { | |
633 | dev_err(nvec->dev, | |
634 | "Read without prior read command\n"); | |
635 | nvec->state = 0; | |
636 | break; | |
32890b98 | 637 | } |
0cab4cb8 JAK |
638 | nvec_msg_free(nvec, nvec->rx); |
639 | nvec->state = 3; | |
640 | nvec_tx_set(nvec); | |
641 | BUG_ON(nvec->tx->size < 1); | |
642 | to_send = nvec->tx->data[0]; | |
643 | nvec->tx->pos = 1; | |
644 | } else if (status == (I2C_SL_IRQ)) { | |
645 | BUG_ON(nvec->rx == NULL); | |
646 | nvec->rx->data[1] = received; | |
647 | nvec->rx->pos = 2; | |
648 | nvec->state = 4; | |
649 | } else { | |
650 | nvec_invalid_flags(nvec, status, true); | |
32890b98 | 651 | } |
0cab4cb8 JAK |
652 | break; |
653 | case 3: /* EC does a block read, we transmit data */ | |
654 | if (status & END_TRANS) { | |
655 | nvec_tx_completed(nvec); | |
656 | } else if ((status & RNW) == 0 || (status & RCVD)) { | |
657 | nvec_invalid_flags(nvec, status, true); | |
658 | } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) { | |
659 | to_send = nvec->tx->data[nvec->tx->pos++]; | |
660 | } else { | |
661 | dev_err(nvec->dev, "tx buffer underflow on %p (%u > %u)\n", | |
662 | nvec->tx, | |
663 | (uint) (nvec->tx ? nvec->tx->pos : 0), | |
664 | (uint) (nvec->tx ? nvec->tx->size : 0)); | |
665 | nvec->state = 0; | |
32890b98 | 666 | } |
0cab4cb8 JAK |
667 | break; |
668 | case 4: /* EC does some write, we read the data */ | |
669 | if ((status & (END_TRANS | RNW)) == END_TRANS) | |
670 | nvec_rx_completed(nvec); | |
671 | else if (status & (RNW | RCVD)) | |
672 | nvec_invalid_flags(nvec, status, true); | |
673 | else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE) | |
674 | nvec->rx->data[nvec->rx->pos++] = received; | |
675 | else | |
676 | dev_err(nvec->dev, | |
b77f2767 | 677 | "RX buffer overflow on %p: Trying to write byte %u of %u\n", |
6330f9cf DC |
678 | nvec->rx, nvec->rx ? nvec->rx->pos : 0, |
679 | NVEC_MSG_SIZE); | |
0cab4cb8 JAK |
680 | break; |
681 | default: | |
682 | nvec->state = 0; | |
683 | } | |
32890b98 | 684 | |
0cab4cb8 JAK |
685 | /* If we are told that a new transfer starts, verify it */ |
686 | if ((status & (RCVD | RNW)) == RCVD) { | |
687 | if (received != nvec->i2c_addr) | |
688 | dev_err(nvec->dev, | |
689 | "received address 0x%02x, expected 0x%02x\n", | |
690 | received, nvec->i2c_addr); | |
691 | nvec->state = 1; | |
32890b98 | 692 | } |
0cab4cb8 JAK |
693 | |
694 | /* Send data if requested, but not on end of transmission */ | |
695 | if ((status & (RNW | END_TRANS)) == RNW) | |
696 | writel(to_send, nvec->base + I2C_SL_RCVD); | |
697 | ||
698 | /* If we have send the first byte */ | |
699 | if (status == (I2C_SL_IRQ | RNW | RCVD)) | |
700 | nvec_gpio_set_value(nvec, 1); | |
701 | ||
702 | dev_dbg(nvec->dev, | |
703 | "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n", | |
704 | (status & RNW) == 0 ? "received" : "R=", | |
705 | received, | |
706 | (status & (RNW | END_TRANS)) ? "sent" : "S=", | |
707 | to_send, | |
708 | state, | |
709 | status & END_TRANS ? " END_TRANS" : "", | |
710 | status & RCVD ? " RCVD" : "", | |
711 | status & RNW ? " RNW" : ""); | |
712 | ||
de839b8f JAK |
713 | /* |
714 | * TODO: A correct fix needs to be found for this. | |
715 | * | |
716 | * We experience less incomplete messages with this delay than without | |
717 | * it, but we don't know why. Help is appreciated. | |
718 | */ | |
719 | udelay(100); | |
720 | ||
32890b98 MD |
721 | return IRQ_HANDLED; |
722 | } | |
723 | ||
f686e9af | 724 | static void tegra_init_i2c_slave(struct nvec_chip *nvec) |
32890b98 MD |
725 | { |
726 | u32 val; | |
727 | ||
61c3b197 | 728 | clk_prepare_enable(nvec->i2c_clk); |
f686e9af | 729 | |
c0df5bf5 | 730 | reset_control_assert(nvec->rst); |
32890b98 | 731 | udelay(2); |
c0df5bf5 | 732 | reset_control_deassert(nvec->rst); |
32890b98 | 733 | |
32890b98 | 734 | val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN | |
ac810759 | 735 | (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); |
f686e9af | 736 | writel(val, nvec->base + I2C_CNFG); |
ac810759 MD |
737 | |
738 | clk_set_rate(nvec->i2c_clk, 8 * 80000); | |
739 | ||
d3f862ae | 740 | writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG); |
ac810759 MD |
741 | writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT); |
742 | ||
a9548c22 | 743 | writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1); |
ac810759 | 744 | writel(0, nvec->base + I2C_SL_ADDR2); |
32890b98 | 745 | |
ac810759 | 746 | enable_irq(nvec->irq); |
ac810759 MD |
747 | } |
748 | ||
ebefae28 | 749 | #ifdef CONFIG_PM_SLEEP |
ac810759 MD |
750 | static void nvec_disable_i2c_slave(struct nvec_chip *nvec) |
751 | { | |
752 | disable_irq(nvec->irq); | |
d3f862ae | 753 | writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG); |
61c3b197 | 754 | clk_disable_unprepare(nvec->i2c_clk); |
32890b98 | 755 | } |
ebefae28 | 756 | #endif |
32890b98 MD |
757 | |
758 | static void nvec_power_off(void) | |
759 | { | |
93eff83f MD |
760 | char ap_pwr_down[] = { NVEC_SLEEP, AP_PWR_DOWN }; |
761 | ||
518945fb | 762 | nvec_toggle_global_events(nvec_power_handle, false); |
93eff83f | 763 | nvec_write_async(nvec_power_handle, ap_pwr_down, 2); |
32890b98 MD |
764 | } |
765 | ||
95cd1860 MD |
766 | /* |
767 | * Parse common device tree data | |
768 | */ | |
769 | static int nvec_i2c_parse_dt_pdata(struct nvec_chip *nvec) | |
770 | { | |
771 | nvec->gpio = of_get_named_gpio(nvec->dev->of_node, "request-gpios", 0); | |
772 | ||
773 | if (nvec->gpio < 0) { | |
774 | dev_err(nvec->dev, "no gpio specified"); | |
775 | return -ENODEV; | |
776 | } | |
777 | ||
778 | if (of_property_read_u32(nvec->dev->of_node, "slave-addr", | |
779 | &nvec->i2c_addr)) { | |
780 | dev_err(nvec->dev, "no i2c address specified"); | |
781 | return -ENODEV; | |
782 | } | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
46620803 | 787 | static int tegra_nvec_probe(struct platform_device *pdev) |
32890b98 | 788 | { |
f686e9af | 789 | int err, ret; |
32890b98 | 790 | struct clk *i2c_clk; |
32890b98 MD |
791 | struct nvec_chip *nvec; |
792 | struct nvec_msg *msg; | |
f686e9af | 793 | struct resource *res; |
f686e9af | 794 | void __iomem *base; |
93eff83f MD |
795 | char get_firmware_version[] = { NVEC_CNTL, GET_FIRMWARE_VERSION }, |
796 | unmute_speakers[] = { NVEC_OEM0, 0x10, 0x59, 0x95 }, | |
797 | enable_event[7] = { NVEC_SYS, CNF_EVENT_REPORTING, true }; | |
32890b98 | 798 | |
15f1df57 | 799 | if (!pdev->dev.of_node) { |
2c6cbdd0 MD |
800 | dev_err(&pdev->dev, "must be instantiated using device tree\n"); |
801 | return -ENODEV; | |
802 | } | |
803 | ||
f5e3352e | 804 | nvec = devm_kzalloc(&pdev->dev, sizeof(struct nvec_chip), GFP_KERNEL); |
4c42d979 | 805 | if (!nvec) |
32890b98 | 806 | return -ENOMEM; |
5a9077a8 | 807 | |
32890b98 MD |
808 | platform_set_drvdata(pdev, nvec); |
809 | nvec->dev = &pdev->dev; | |
7990b0d7 | 810 | |
95cd1860 MD |
811 | err = nvec_i2c_parse_dt_pdata(nvec); |
812 | if (err < 0) | |
813 | return err; | |
f686e9af MD |
814 | |
815 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
97f4be60 TR |
816 | base = devm_ioremap_resource(&pdev->dev, res); |
817 | if (IS_ERR(base)) | |
818 | return PTR_ERR(base); | |
32890b98 | 819 | |
b5b628ba TR |
820 | nvec->irq = platform_get_irq(pdev, 0); |
821 | if (nvec->irq < 0) { | |
f686e9af | 822 | dev_err(&pdev->dev, "no irq resource?\n"); |
f5e3352e | 823 | return -ENODEV; |
f686e9af | 824 | } |
32890b98 | 825 | |
c2b62f60 | 826 | i2c_clk = devm_clk_get(&pdev->dev, "div-clk"); |
f686e9af MD |
827 | if (IS_ERR(i2c_clk)) { |
828 | dev_err(nvec->dev, "failed to get controller clock\n"); | |
f5e3352e | 829 | return -ENODEV; |
32890b98 MD |
830 | } |
831 | ||
c0df5bf5 SW |
832 | nvec->rst = devm_reset_control_get(&pdev->dev, "i2c"); |
833 | if (IS_ERR(nvec->rst)) { | |
834 | dev_err(nvec->dev, "failed to get controller reset\n"); | |
835 | return PTR_ERR(nvec->rst); | |
836 | } | |
837 | ||
f686e9af | 838 | nvec->base = base; |
f686e9af | 839 | nvec->i2c_clk = i2c_clk; |
0cab4cb8 | 840 | nvec->rx = &nvec->msg_pool[0]; |
f686e9af | 841 | |
32890b98 MD |
842 | ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list); |
843 | ||
844 | init_completion(&nvec->sync_write); | |
0cab4cb8 JAK |
845 | init_completion(&nvec->ec_transfer); |
846 | mutex_init(&nvec->sync_write_mutex); | |
847 | spin_lock_init(&nvec->tx_lock); | |
848 | spin_lock_init(&nvec->rx_lock); | |
32890b98 | 849 | INIT_LIST_HEAD(&nvec->rx_data); |
0cab4cb8 | 850 | INIT_LIST_HEAD(&nvec->tx_data); |
32890b98 MD |
851 | INIT_WORK(&nvec->rx_work, nvec_dispatch); |
852 | INIT_WORK(&nvec->tx_work, nvec_request_master); | |
853 | ||
f5e3352e MD |
854 | err = devm_gpio_request_one(&pdev->dev, nvec->gpio, GPIOF_OUT_INIT_HIGH, |
855 | "nvec gpio"); | |
aed92bbc JAK |
856 | if (err < 0) { |
857 | dev_err(nvec->dev, "couldn't request gpio\n"); | |
f5e3352e | 858 | return -ENODEV; |
aed92bbc JAK |
859 | } |
860 | ||
f5e3352e MD |
861 | err = devm_request_irq(&pdev->dev, nvec->irq, nvec_interrupt, 0, |
862 | "nvec", nvec); | |
f686e9af MD |
863 | if (err) { |
864 | dev_err(nvec->dev, "couldn't request irq\n"); | |
f5e3352e | 865 | return -ENODEV; |
f686e9af | 866 | } |
ac810759 | 867 | disable_irq(nvec->irq); |
f686e9af MD |
868 | |
869 | tegra_init_i2c_slave(nvec); | |
870 | ||
32890b98 | 871 | /* enable event reporting */ |
518945fb | 872 | nvec_toggle_global_events(nvec, true); |
32890b98 | 873 | |
32890b98 MD |
874 | nvec->nvec_status_notifier.notifier_call = nvec_status_notifier; |
875 | nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0); | |
876 | ||
877 | nvec_power_handle = nvec; | |
878 | pm_power_off = nvec_power_off; | |
879 | ||
880 | /* Get Firmware Version */ | |
93eff83f | 881 | msg = nvec_write_sync(nvec, get_firmware_version, 2); |
32890b98 | 882 | |
0cab4cb8 JAK |
883 | if (msg) { |
884 | dev_warn(nvec->dev, "ec firmware version %02x.%02x.%02x / %02x\n", | |
885 | msg->data[4], msg->data[5], msg->data[6], msg->data[7]); | |
32890b98 | 886 | |
0cab4cb8 JAK |
887 | nvec_msg_free(nvec, msg); |
888 | } | |
32890b98 | 889 | |
3ec69881 | 890 | ret = mfd_add_devices(nvec->dev, 0, nvec_devices, |
47e7b050 | 891 | ARRAY_SIZE(nvec_devices), NULL, 0, NULL); |
162c7d8c | 892 | if (ret) |
f686e9af MD |
893 | dev_err(nvec->dev, "error adding subdevices\n"); |
894 | ||
32890b98 | 895 | /* unmute speakers? */ |
93eff83f | 896 | nvec_write_async(nvec, unmute_speakers, 4); |
32890b98 MD |
897 | |
898 | /* enable lid switch event */ | |
93eff83f MD |
899 | nvec_event_mask(enable_event, LID_SWITCH); |
900 | nvec_write_async(nvec, enable_event, 7); | |
32890b98 MD |
901 | |
902 | /* enable power button event */ | |
93eff83f MD |
903 | nvec_event_mask(enable_event, PWR_BUTTON); |
904 | nvec_write_async(nvec, enable_event, 7); | |
32890b98 MD |
905 | |
906 | return 0; | |
32890b98 MD |
907 | } |
908 | ||
1a6a8a84 | 909 | static int tegra_nvec_remove(struct platform_device *pdev) |
32890b98 | 910 | { |
f686e9af MD |
911 | struct nvec_chip *nvec = platform_get_drvdata(pdev); |
912 | ||
518945fb | 913 | nvec_toggle_global_events(nvec, false); |
f686e9af | 914 | mfd_remove_devices(nvec->dev); |
c2b62f60 | 915 | nvec_unregister_notifier(nvec, &nvec->nvec_status_notifier); |
eb1e40a4 TH |
916 | cancel_work_sync(&nvec->rx_work); |
917 | cancel_work_sync(&nvec->tx_work); | |
fd90ae2c | 918 | /* FIXME: needs check whether nvec is responsible for power off */ |
c2b62f60 | 919 | pm_power_off = NULL; |
f686e9af | 920 | |
32890b98 MD |
921 | return 0; |
922 | } | |
923 | ||
ebefae28 MD |
924 | #ifdef CONFIG_PM_SLEEP |
925 | static int nvec_suspend(struct device *dev) | |
32890b98 | 926 | { |
ebefae28 | 927 | struct platform_device *pdev = to_platform_device(dev); |
32890b98 | 928 | struct nvec_chip *nvec = platform_get_drvdata(pdev); |
9feeb014 | 929 | struct nvec_msg *msg; |
93eff83f | 930 | char ap_suspend[] = { NVEC_SLEEP, AP_SUSPEND }; |
32890b98 MD |
931 | |
932 | dev_dbg(nvec->dev, "suspending\n"); | |
9feeb014 MD |
933 | |
934 | /* keep these sync or you'll break suspend */ | |
93eff83f MD |
935 | nvec_toggle_global_events(nvec, false); |
936 | ||
937 | msg = nvec_write_sync(nvec, ap_suspend, sizeof(ap_suspend)); | |
9feeb014 MD |
938 | nvec_msg_free(nvec, msg); |
939 | ||
ac810759 | 940 | nvec_disable_i2c_slave(nvec); |
32890b98 MD |
941 | |
942 | return 0; | |
943 | } | |
944 | ||
ebefae28 | 945 | static int nvec_resume(struct device *dev) |
162c7d8c | 946 | { |
ebefae28 | 947 | struct platform_device *pdev = to_platform_device(dev); |
32890b98 MD |
948 | struct nvec_chip *nvec = platform_get_drvdata(pdev); |
949 | ||
950 | dev_dbg(nvec->dev, "resuming\n"); | |
f686e9af | 951 | tegra_init_i2c_slave(nvec); |
518945fb | 952 | nvec_toggle_global_events(nvec, true); |
32890b98 MD |
953 | |
954 | return 0; | |
955 | } | |
32890b98 MD |
956 | #endif |
957 | ||
5d30566f | 958 | static SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume); |
ebefae28 | 959 | |
7990b0d7 | 960 | /* Match table for of_platform binding */ |
063f9f6a | 961 | static const struct of_device_id nvidia_nvec_of_match[] = { |
7990b0d7 MD |
962 | { .compatible = "nvidia,nvec", }, |
963 | {}, | |
964 | }; | |
965 | MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match); | |
966 | ||
162c7d8c MD |
967 | static struct platform_driver nvec_device_driver = { |
968 | .probe = tegra_nvec_probe, | |
44b90a3f | 969 | .remove = tegra_nvec_remove, |
162c7d8c | 970 | .driver = { |
32890b98 | 971 | .name = "nvec", |
ebefae28 | 972 | .pm = &nvec_pm_ops, |
7990b0d7 | 973 | .of_match_table = nvidia_nvec_of_match, |
32890b98 MD |
974 | } |
975 | }; | |
976 | ||
9891b1ce | 977 | module_platform_driver(nvec_device_driver); |
162c7d8c | 978 | |
32890b98 | 979 | MODULE_ALIAS("platform:nvec"); |
162c7d8c MD |
980 | MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface"); |
981 | MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>"); | |
982 | MODULE_LICENSE("GPL"); |