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b164935b AK |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Cavium Networks | |
6570b4a9 AK |
7 | * |
8 | * Some parts of the code were originally released under BSD license: | |
9 | * | |
10 | * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights | |
11 | * reserved. | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or without | |
14 | * modification, are permitted provided that the following conditions are | |
15 | * met: | |
16 | * | |
17 | * * Redistributions of source code must retain the above copyright | |
18 | * notice, this list of conditions and the following disclaimer. | |
19 | * | |
20 | * * Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials provided | |
23 | * with the distribution. | |
24 | * | |
25 | * * Neither the name of Cavium Networks nor the names of | |
26 | * its contributors may be used to endorse or promote products | |
27 | * derived from this software without specific prior written | |
28 | * permission. | |
29 | * | |
30 | * This Software, including technical data, may be subject to U.S. export | |
31 | * control laws, including the U.S. Export Administration Act and its associated | |
32 | * regulations, and may be subject to export or import regulations in other | |
33 | * countries. | |
34 | * | |
35 | * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" | |
36 | * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR | |
37 | * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO | |
38 | * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION | |
39 | * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM | |
40 | * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, | |
41 | * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF | |
42 | * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR | |
43 | * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR | |
44 | * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. | |
b164935b AK |
45 | */ |
46 | #include <linux/kernel.h> | |
47 | #include <linux/module.h> | |
48 | #include <linux/init.h> | |
49 | #include <linux/pci.h> | |
20f6b829 | 50 | #include <linux/prefetch.h> |
b164935b AK |
51 | #include <linux/interrupt.h> |
52 | #include <linux/platform_device.h> | |
b164935b AK |
53 | #include <linux/usb.h> |
54 | ||
2a81d2b0 AK |
55 | #include <linux/time.h> |
56 | #include <linux/delay.h> | |
b164935b AK |
57 | |
58 | #include <asm/octeon/cvmx.h> | |
b164935b AK |
59 | #include <asm/octeon/cvmx-iob-defs.h> |
60 | ||
61 | #include <linux/usb/hcd.h> | |
62 | ||
55fa328a DN |
63 | #include <linux/err.h> |
64 | ||
6570b4a9 AK |
65 | #include <asm/octeon/octeon.h> |
66 | #include <asm/octeon/cvmx-helper.h> | |
67 | #include <asm/octeon/cvmx-sysinfo.h> | |
68 | #include <asm/octeon/cvmx-helper-board.h> | |
69 | ||
f1219103 | 70 | #include "octeon-hcd.h" |
6570b4a9 AK |
71 | |
72 | /** | |
73 | * enum cvmx_usb_speed - the possible USB device speeds | |
74 | * | |
75 | * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps | |
76 | * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps | |
77 | * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps | |
78 | */ | |
79 | enum cvmx_usb_speed { | |
80 | CVMX_USB_SPEED_HIGH = 0, | |
81 | CVMX_USB_SPEED_FULL = 1, | |
82 | CVMX_USB_SPEED_LOW = 2, | |
83 | }; | |
84 | ||
85 | /** | |
86 | * enum cvmx_usb_transfer - the possible USB transfer types | |
87 | * | |
88 | * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status | |
89 | * transfers | |
90 | * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low | |
91 | * priority periodic transfers | |
92 | * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority | |
93 | * transfers | |
94 | * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority | |
95 | * periodic transfers | |
96 | */ | |
97 | enum cvmx_usb_transfer { | |
98 | CVMX_USB_TRANSFER_CONTROL = 0, | |
99 | CVMX_USB_TRANSFER_ISOCHRONOUS = 1, | |
100 | CVMX_USB_TRANSFER_BULK = 2, | |
101 | CVMX_USB_TRANSFER_INTERRUPT = 3, | |
102 | }; | |
103 | ||
104 | /** | |
105 | * enum cvmx_usb_direction - the transfer directions | |
106 | * | |
107 | * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host | |
108 | * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon | |
109 | */ | |
110 | enum cvmx_usb_direction { | |
111 | CVMX_USB_DIRECTION_OUT, | |
112 | CVMX_USB_DIRECTION_IN, | |
113 | }; | |
114 | ||
115 | /** | |
116 | * enum cvmx_usb_complete - possible callback function status codes | |
117 | * | |
118 | * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without | |
119 | * any errors | |
120 | * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented | |
121 | * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight | |
122 | * by a user call to cvmx_usb_cancel | |
123 | * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected | |
124 | * error status | |
125 | * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response | |
126 | * from the device | |
127 | * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the | |
128 | * device even after a number of retries | |
129 | * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle | |
130 | * error even after a number of retries | |
131 | * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error | |
132 | * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error | |
133 | * even after a number of retries | |
134 | */ | |
135 | enum cvmx_usb_complete { | |
136 | CVMX_USB_COMPLETE_SUCCESS, | |
137 | CVMX_USB_COMPLETE_SHORT, | |
138 | CVMX_USB_COMPLETE_CANCEL, | |
139 | CVMX_USB_COMPLETE_ERROR, | |
140 | CVMX_USB_COMPLETE_STALL, | |
141 | CVMX_USB_COMPLETE_XACTERR, | |
142 | CVMX_USB_COMPLETE_DATATGLERR, | |
143 | CVMX_USB_COMPLETE_BABBLEERR, | |
144 | CVMX_USB_COMPLETE_FRAMEERR, | |
145 | }; | |
146 | ||
147 | /** | |
148 | * struct cvmx_usb_port_status - the USB port status information | |
149 | * | |
150 | * @port_enabled: 1 = Usb port is enabled, 0 = disabled | |
151 | * @port_over_current: 1 = Over current detected, 0 = Over current not | |
152 | * detected. Octeon doesn't support over current detection. | |
153 | * @port_powered: 1 = Port power is being supplied to the device, 0 = | |
154 | * power is off. Octeon doesn't support turning port power | |
155 | * off. | |
156 | * @port_speed: Current port speed. | |
157 | * @connected: 1 = A device is connected to the port, 0 = No device is | |
158 | * connected. | |
159 | * @connect_change: 1 = Device connected state changed since the last set | |
160 | * status call. | |
161 | */ | |
162 | struct cvmx_usb_port_status { | |
163 | uint32_t reserved : 25; | |
164 | uint32_t port_enabled : 1; | |
165 | uint32_t port_over_current : 1; | |
166 | uint32_t port_powered : 1; | |
167 | enum cvmx_usb_speed port_speed : 2; | |
168 | uint32_t connected : 1; | |
169 | uint32_t connect_change : 1; | |
170 | }; | |
171 | ||
6570b4a9 AK |
172 | /** |
173 | * struct cvmx_usb_iso_packet - descriptor for Isochronous packets | |
174 | * | |
175 | * @offset: This is the offset in bytes into the main buffer where this data | |
176 | * is stored. | |
177 | * @length: This is the length in bytes of the data. | |
178 | * @status: This is the status of this individual packet transfer. | |
179 | */ | |
180 | struct cvmx_usb_iso_packet { | |
181 | int offset; | |
182 | int length; | |
183 | enum cvmx_usb_complete status; | |
184 | }; | |
185 | ||
6570b4a9 AK |
186 | /** |
187 | * enum cvmx_usb_initialize_flags - flags used by the initialization function | |
188 | * | |
189 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal | |
190 | * as clock source at USB_XO and | |
191 | * USB_XI. | |
192 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V | |
193 | * board clock source at USB_XO. | |
194 | * USB_XI should be tied to GND. | |
195 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field | |
196 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or | |
197 | * crystal | |
198 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock | |
199 | * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock | |
200 | * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for | |
201 | * data transfer use for the USB | |
202 | */ | |
203 | enum cvmx_usb_initialize_flags { | |
204 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0, | |
205 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1, | |
206 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3, | |
207 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3, | |
208 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3, | |
209 | CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3, | |
210 | /* Bits 3-4 used to encode the clock frequency */ | |
211 | CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5, | |
212 | }; | |
213 | ||
214 | /** | |
215 | * enum cvmx_usb_pipe_flags - internal flags for a pipe. | |
216 | * | |
6570b4a9 AK |
217 | * @__CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is |
218 | * actively using hardware. Do not use. | |
219 | * @__CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high | |
220 | * speed pipe is in the ping state. Do not | |
221 | * use. | |
222 | */ | |
223 | enum cvmx_usb_pipe_flags { | |
6570b4a9 AK |
224 | __CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17, |
225 | __CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18, | |
226 | }; | |
227 | ||
6570b4a9 AK |
228 | /* Maximum number of times to retry failed transactions */ |
229 | #define MAX_RETRIES 3 | |
230 | ||
6570b4a9 AK |
231 | /* Maximum number of hardware channels supported by the USB block */ |
232 | #define MAX_CHANNELS 8 | |
233 | ||
6570b4a9 AK |
234 | /* |
235 | * The low level hardware can transfer a maximum of this number of bytes in each | |
236 | * transfer. The field is 19 bits wide | |
237 | */ | |
238 | #define MAX_TRANSFER_BYTES ((1<<19)-1) | |
239 | ||
240 | /* | |
241 | * The low level hardware can transfer a maximum of this number of packets in | |
242 | * each transfer. The field is 10 bits wide | |
243 | */ | |
244 | #define MAX_TRANSFER_PACKETS ((1<<10)-1) | |
245 | ||
6570b4a9 AK |
246 | /** |
247 | * Logical transactions may take numerous low level | |
248 | * transactions, especially when splits are concerned. This | |
249 | * enum represents all of the possible stages a transaction can | |
250 | * be in. Note that split completes are always even. This is so | |
251 | * the NAK handler can backup to the previous low level | |
252 | * transaction with a simple clearing of bit 0. | |
253 | */ | |
254 | enum cvmx_usb_stage { | |
255 | CVMX_USB_STAGE_NON_CONTROL, | |
256 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE, | |
257 | CVMX_USB_STAGE_SETUP, | |
258 | CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE, | |
259 | CVMX_USB_STAGE_DATA, | |
260 | CVMX_USB_STAGE_DATA_SPLIT_COMPLETE, | |
261 | CVMX_USB_STAGE_STATUS, | |
262 | CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE, | |
263 | }; | |
264 | ||
265 | /** | |
266 | * struct cvmx_usb_transaction - describes each pending USB transaction | |
267 | * regardless of type. These are linked together | |
268 | * to form a list of pending requests for a pipe. | |
269 | * | |
5669601d | 270 | * @node: List node for transactions in the pipe. |
6570b4a9 AK |
271 | * @type: Type of transaction, duplicated of the pipe. |
272 | * @flags: State flags for this transaction. | |
273 | * @buffer: User's physical buffer address to read/write. | |
274 | * @buffer_length: Size of the user's buffer in bytes. | |
275 | * @control_header: For control transactions, physical address of the 8 | |
276 | * byte standard header. | |
277 | * @iso_start_frame: For ISO transactions, the starting frame number. | |
278 | * @iso_number_packets: For ISO transactions, the number of packets in the | |
279 | * request. | |
280 | * @iso_packets: For ISO transactions, the sub packets in the request. | |
281 | * @actual_bytes: Actual bytes transfer for this transaction. | |
282 | * @stage: For control transactions, the current stage. | |
0cce1004 | 283 | * @urb: URB. |
6570b4a9 AK |
284 | */ |
285 | struct cvmx_usb_transaction { | |
5669601d | 286 | struct list_head node; |
6570b4a9 | 287 | enum cvmx_usb_transfer type; |
6570b4a9 AK |
288 | uint64_t buffer; |
289 | int buffer_length; | |
290 | uint64_t control_header; | |
291 | int iso_start_frame; | |
292 | int iso_number_packets; | |
293 | struct cvmx_usb_iso_packet *iso_packets; | |
294 | int xfersize; | |
295 | int pktcnt; | |
296 | int retries; | |
297 | int actual_bytes; | |
298 | enum cvmx_usb_stage stage; | |
0cce1004 | 299 | struct urb *urb; |
6570b4a9 AK |
300 | }; |
301 | ||
302 | /** | |
303 | * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon | |
304 | * and some USB device. It contains a list of pending | |
305 | * request to the device. | |
306 | * | |
4a23ee1b | 307 | * @node: List node for pipe list |
6570b4a9 | 308 | * @next: Pipe after this one in the list |
5669601d | 309 | * @transactions: List of pending transactions |
6570b4a9 AK |
310 | * @interval: For periodic pipes, the interval between packets in |
311 | * frames | |
312 | * @next_tx_frame: The next frame this pipe is allowed to transmit on | |
313 | * @flags: State flags for this pipe | |
314 | * @device_speed: Speed of device connected to this pipe | |
315 | * @transfer_type: Type of transaction supported by this pipe | |
316 | * @transfer_dir: IN or OUT. Ignored for Control | |
317 | * @multi_count: Max packet in a row for the device | |
318 | * @max_packet: The device's maximum packet size in bytes | |
319 | * @device_addr: USB device address at other end of pipe | |
320 | * @endpoint_num: USB endpoint number at other end of pipe | |
321 | * @hub_device_addr: Hub address this device is connected to | |
322 | * @hub_port: Hub port this device is connected to | |
323 | * @pid_toggle: This toggles between 0/1 on every packet send to track | |
324 | * the data pid needed | |
325 | * @channel: Hardware DMA channel for this pipe | |
326 | * @split_sc_frame: The low order bits of the frame number the split | |
327 | * complete should be sent on | |
328 | */ | |
329 | struct cvmx_usb_pipe { | |
4a23ee1b | 330 | struct list_head node; |
5669601d | 331 | struct list_head transactions; |
6570b4a9 AK |
332 | uint64_t interval; |
333 | uint64_t next_tx_frame; | |
334 | enum cvmx_usb_pipe_flags flags; | |
335 | enum cvmx_usb_speed device_speed; | |
336 | enum cvmx_usb_transfer transfer_type; | |
337 | enum cvmx_usb_direction transfer_dir; | |
338 | int multi_count; | |
339 | uint16_t max_packet; | |
340 | uint8_t device_addr; | |
341 | uint8_t endpoint_num; | |
342 | uint8_t hub_device_addr; | |
343 | uint8_t hub_port; | |
344 | uint8_t pid_toggle; | |
345 | uint8_t channel; | |
346 | int8_t split_sc_frame; | |
347 | }; | |
348 | ||
6570b4a9 AK |
349 | struct cvmx_usb_tx_fifo { |
350 | struct { | |
351 | int channel; | |
352 | int size; | |
353 | uint64_t address; | |
354 | } entry[MAX_CHANNELS+1]; | |
355 | int head; | |
356 | int tail; | |
357 | }; | |
358 | ||
359 | /** | |
cb61c600 | 360 | * struct cvmx_usb_state - the state of the USB block |
6570b4a9 AK |
361 | * |
362 | * init_flags: Flags passed to initialize. | |
363 | * index: Which USB block this is for. | |
364 | * idle_hardware_channels: Bit set for every idle hardware channel. | |
365 | * usbcx_hprt: Stored port status so we don't need to read a CSR to | |
366 | * determine splits. | |
367 | * pipe_for_channel: Map channels to pipes. | |
6570b4a9 | 368 | * pipe: Storage for pipes. |
6570b4a9 AK |
369 | * indent: Used by debug output to indent functions. |
370 | * port_status: Last port status used for change notification. | |
6570b4a9 AK |
371 | * idle_pipes: List of open pipes that have no transactions. |
372 | * active_pipes: Active pipes indexed by transfer type. | |
373 | * frame_number: Increments every SOF interrupt for time keeping. | |
374 | * active_split: Points to the current active split, or NULL. | |
375 | */ | |
cb61c600 | 376 | struct cvmx_usb_state { |
6570b4a9 AK |
377 | int init_flags; |
378 | int index; | |
379 | int idle_hardware_channels; | |
380 | union cvmx_usbcx_hprt usbcx_hprt; | |
381 | struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS]; | |
6570b4a9 AK |
382 | int indent; |
383 | struct cvmx_usb_port_status port_status; | |
4a23ee1b AK |
384 | struct list_head idle_pipes; |
385 | struct list_head active_pipes[4]; | |
6570b4a9 AK |
386 | uint64_t frame_number; |
387 | struct cvmx_usb_transaction *active_split; | |
388 | struct cvmx_usb_tx_fifo periodic; | |
389 | struct cvmx_usb_tx_fifo nonperiodic; | |
390 | }; | |
391 | ||
b164935b | 392 | struct octeon_hcd { |
771378bb | 393 | spinlock_t lock; |
a24ed35a | 394 | struct cvmx_usb_state usb; |
b164935b AK |
395 | }; |
396 | ||
6570b4a9 AK |
397 | /* This macro spins on a field waiting for it to reach a value */ |
398 | #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\ | |
399 | ({int result; \ | |
400 | do { \ | |
401 | uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \ | |
402 | octeon_get_clock_rate() / 1000000; \ | |
403 | type c; \ | |
404 | while (1) { \ | |
68d435dd | 405 | c.u32 = cvmx_usb_read_csr32(usb, address); \ |
6570b4a9 AK |
406 | if (c.s.field op (value)) { \ |
407 | result = 0; \ | |
408 | break; \ | |
409 | } else if (cvmx_get_cycle() > done) { \ | |
410 | result = -1; \ | |
411 | break; \ | |
412 | } else \ | |
413 | cvmx_wait(100); \ | |
414 | } \ | |
415 | } while (0); \ | |
416 | result; }) | |
417 | ||
418 | /* | |
419 | * This macro logically sets a single field in a CSR. It does the sequence | |
420 | * read, modify, and write | |
421 | */ | |
422 | #define USB_SET_FIELD32(address, type, field, value) \ | |
423 | do { \ | |
424 | type c; \ | |
68d435dd | 425 | c.u32 = cvmx_usb_read_csr32(usb, address); \ |
6570b4a9 | 426 | c.s.field = value; \ |
68d435dd | 427 | cvmx_usb_write_csr32(usb, address, c.u32); \ |
6570b4a9 AK |
428 | } while (0) |
429 | ||
430 | /* Returns the IO address to push/pop stuff data from the FIFOs */ | |
e725cef3 PD |
431 | #define USB_FIFO_ADDRESS(channel, usb_index) \ |
432 | (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000) | |
6570b4a9 | 433 | |
120ee599 AK |
434 | /** |
435 | * struct octeon_temp_buffer - a bounce buffer for USB transfers | |
436 | * @temp_buffer: the newly allocated temporary buffer (including meta-data) | |
437 | * @orig_buffer: the original buffer passed by the USB stack | |
438 | * @data: the newly allocated temporary buffer (excluding meta-data) | |
439 | * | |
440 | * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If | |
441 | * the buffer is too short, we need to allocate a temporary one, and this struct | |
442 | * represents it. | |
443 | */ | |
444 | struct octeon_temp_buffer { | |
445 | void *temp_buffer; | |
446 | void *orig_buffer; | |
447 | u8 data[0]; | |
448 | }; | |
449 | ||
2e6ac45c AK |
450 | static inline struct octeon_hcd *cvmx_usb_to_octeon(struct cvmx_usb_state *p) |
451 | { | |
452 | return container_of(p, struct octeon_hcd, usb); | |
453 | } | |
454 | ||
455 | static inline struct usb_hcd *octeon_to_hcd(struct octeon_hcd *p) | |
456 | { | |
457 | return container_of((void *)p, struct usb_hcd, hcd_priv); | |
458 | } | |
459 | ||
120ee599 AK |
460 | /** |
461 | * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer | |
462 | * (if needed) | |
463 | * @urb: URB. | |
464 | * @mem_flags: Memory allocation flags. | |
465 | * | |
466 | * This function allocates a temporary bounce buffer whenever it's needed | |
467 | * due to HW limitations. | |
468 | */ | |
469 | static int octeon_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) | |
470 | { | |
471 | struct octeon_temp_buffer *temp; | |
472 | ||
473 | if (urb->num_sgs || urb->sg || | |
474 | (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) || | |
475 | !(urb->transfer_buffer_length % sizeof(u32))) | |
476 | return 0; | |
477 | ||
478 | temp = kmalloc(ALIGN(urb->transfer_buffer_length, sizeof(u32)) + | |
479 | sizeof(*temp), mem_flags); | |
480 | if (!temp) | |
481 | return -ENOMEM; | |
482 | ||
483 | temp->temp_buffer = temp; | |
484 | temp->orig_buffer = urb->transfer_buffer; | |
485 | if (usb_urb_dir_out(urb)) | |
486 | memcpy(temp->data, urb->transfer_buffer, | |
487 | urb->transfer_buffer_length); | |
488 | urb->transfer_buffer = temp->data; | |
489 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | /** | |
495 | * octeon_free_temp_buffer - free a temporary buffer used by USB transfers. | |
496 | * @urb: URB. | |
497 | * | |
498 | * Frees a buffer allocated by octeon_alloc_temp_buffer(). | |
499 | */ | |
500 | static void octeon_free_temp_buffer(struct urb *urb) | |
501 | { | |
502 | struct octeon_temp_buffer *temp; | |
503 | ||
504 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
505 | return; | |
506 | ||
507 | temp = container_of(urb->transfer_buffer, struct octeon_temp_buffer, | |
508 | data); | |
509 | if (usb_urb_dir_in(urb)) | |
510 | memcpy(temp->orig_buffer, urb->transfer_buffer, | |
511 | urb->actual_length); | |
512 | urb->transfer_buffer = temp->orig_buffer; | |
513 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
514 | kfree(temp->temp_buffer); | |
515 | } | |
516 | ||
517 | /** | |
518 | * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma(). | |
519 | * @hcd: USB HCD structure. | |
520 | * @urb: URB. | |
521 | * @mem_flags: Memory allocation flags. | |
522 | */ | |
523 | static int octeon_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
524 | gfp_t mem_flags) | |
525 | { | |
526 | int ret; | |
527 | ||
528 | ret = octeon_alloc_temp_buffer(urb, mem_flags); | |
529 | if (ret) | |
530 | return ret; | |
531 | ||
532 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
533 | if (ret) | |
534 | octeon_free_temp_buffer(urb); | |
535 | ||
536 | return ret; | |
537 | } | |
538 | ||
539 | /** | |
540 | * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma() | |
541 | * @hcd: USB HCD structure. | |
542 | * @urb: URB. | |
543 | */ | |
544 | static void octeon_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
545 | { | |
546 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
547 | octeon_free_temp_buffer(urb); | |
548 | } | |
549 | ||
6570b4a9 AK |
550 | /** |
551 | * Read a USB 32bit CSR. It performs the necessary address swizzle | |
552 | * for 32bit CSRs and logs the value in a readable format if | |
553 | * debugging is on. | |
554 | * | |
555 | * @usb: USB block this access is for | |
556 | * @address: 64bit address to read | |
557 | * | |
558 | * Returns: Result of the read | |
559 | */ | |
68d435dd AK |
560 | static inline uint32_t cvmx_usb_read_csr32(struct cvmx_usb_state *usb, |
561 | uint64_t address) | |
6570b4a9 AK |
562 | { |
563 | uint32_t result = cvmx_read64_uint32(address ^ 4); | |
564 | return result; | |
565 | } | |
566 | ||
567 | ||
568 | /** | |
569 | * Write a USB 32bit CSR. It performs the necessary address | |
570 | * swizzle for 32bit CSRs and logs the value in a readable format | |
571 | * if debugging is on. | |
572 | * | |
573 | * @usb: USB block this access is for | |
574 | * @address: 64bit address to write | |
575 | * @value: Value to write | |
576 | */ | |
68d435dd AK |
577 | static inline void cvmx_usb_write_csr32(struct cvmx_usb_state *usb, |
578 | uint64_t address, uint32_t value) | |
6570b4a9 AK |
579 | { |
580 | cvmx_write64_uint32(address ^ 4, value); | |
581 | cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index)); | |
582 | } | |
583 | ||
6570b4a9 AK |
584 | /** |
585 | * Return non zero if this pipe connects to a non HIGH speed | |
586 | * device through a high speed hub. | |
587 | * | |
588 | * @usb: USB block this access is for | |
589 | * @pipe: Pipe to check | |
590 | * | |
591 | * Returns: Non zero if we need to do split transactions | |
592 | */ | |
68d435dd AK |
593 | static inline int cvmx_usb_pipe_needs_split(struct cvmx_usb_state *usb, |
594 | struct cvmx_usb_pipe *pipe) | |
6570b4a9 | 595 | { |
aa87afe2 AK |
596 | return pipe->device_speed != CVMX_USB_SPEED_HIGH && |
597 | usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH; | |
6570b4a9 AK |
598 | } |
599 | ||
600 | ||
601 | /** | |
602 | * Trivial utility function to return the correct PID for a pipe | |
603 | * | |
604 | * @pipe: pipe to check | |
605 | * | |
606 | * Returns: PID for pipe | |
607 | */ | |
68d435dd | 608 | static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe) |
6570b4a9 AK |
609 | { |
610 | if (pipe->pid_toggle) | |
611 | return 2; /* Data1 */ | |
c9a114e7 | 612 | return 0; /* Data0 */ |
6570b4a9 AK |
613 | } |
614 | ||
6570b4a9 AK |
615 | /** |
616 | * Initialize a USB port for use. This must be called before any | |
617 | * other access to the Octeon USB port is made. The port starts | |
618 | * off in the disabled state. | |
619 | * | |
cb61c600 | 620 | * @usb: Pointer to an empty struct cvmx_usb_state |
6570b4a9 AK |
621 | * that will be populated by the initialize call. |
622 | * This structure is then passed to all other USB | |
623 | * functions. | |
624 | * @usb_port_number: | |
625 | * Which Octeon USB port to initialize. | |
626 | * | |
627 | * Returns: 0 or a negative error code. | |
628 | */ | |
cb61c600 | 629 | static int cvmx_usb_initialize(struct cvmx_usb_state *usb, |
b91619c2 DD |
630 | int usb_port_number, |
631 | enum cvmx_usb_initialize_flags flags) | |
6570b4a9 AK |
632 | { |
633 | union cvmx_usbnx_clk_ctl usbn_clk_ctl; | |
634 | union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status; | |
4a23ee1b | 635 | int i; |
6570b4a9 | 636 | |
6570b4a9 AK |
637 | memset(usb, 0, sizeof(*usb)); |
638 | usb->init_flags = flags; | |
639 | ||
640 | /* Initialize the USB state structure */ | |
d2695a8a | 641 | usb->index = usb_port_number; |
4a23ee1b AK |
642 | INIT_LIST_HEAD(&usb->idle_pipes); |
643 | for (i = 0; i < ARRAY_SIZE(usb->active_pipes); i++) | |
644 | INIT_LIST_HEAD(&usb->active_pipes[i]); | |
6570b4a9 AK |
645 | |
646 | /* | |
647 | * Power On Reset and PHY Initialization | |
648 | * | |
649 | * 1. Wait for DCOK to assert (nothing to do) | |
650 | * | |
651 | * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and | |
652 | * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0 | |
653 | */ | |
c4bdbdd9 | 654 | usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index)); |
6570b4a9 AK |
655 | usbn_clk_ctl.s.por = 1; |
656 | usbn_clk_ctl.s.hrst = 0; | |
657 | usbn_clk_ctl.s.prst = 0; | |
658 | usbn_clk_ctl.s.hclk_rst = 0; | |
659 | usbn_clk_ctl.s.enable = 0; | |
660 | /* | |
661 | * 2b. Select the USB reference clock/crystal parameters by writing | |
662 | * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON] | |
663 | */ | |
664 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) { | |
665 | /* | |
666 | * The USB port uses 12/24/48MHz 2.5V board clock | |
667 | * source at USB_XO. USB_XI should be tied to GND. | |
668 | * Most Octeon evaluation boards require this setting | |
669 | */ | |
7d7bc26b AK |
670 | if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || |
671 | OCTEON_IS_MODEL(OCTEON_CN56XX) || | |
672 | OCTEON_IS_MODEL(OCTEON_CN50XX)) | |
673 | /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */ | |
674 | usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */ | |
6570b4a9 AK |
675 | else |
676 | /* From CN52XX manual */ | |
34b70b9e | 677 | usbn_clk_ctl.s.p_rtype = 1; |
6570b4a9 AK |
678 | |
679 | switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) { | |
680 | case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: | |
681 | usbn_clk_ctl.s.p_c_sel = 0; | |
682 | break; | |
683 | case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: | |
684 | usbn_clk_ctl.s.p_c_sel = 1; | |
685 | break; | |
686 | case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: | |
687 | usbn_clk_ctl.s.p_c_sel = 2; | |
688 | break; | |
689 | } | |
690 | } else { | |
691 | /* | |
692 | * The USB port uses a 12MHz crystal as clock source | |
693 | * at USB_XO and USB_XI | |
694 | */ | |
7d7bc26b | 695 | if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) |
6570b4a9 | 696 | /* From CN31XX,CN30XX manual */ |
7d7bc26b | 697 | usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */ |
6570b4a9 | 698 | else |
7d7bc26b | 699 | /* From CN56XX,CN52XX,CN50XX manuals. */ |
34b70b9e | 700 | usbn_clk_ctl.s.p_rtype = 0; |
6570b4a9 AK |
701 | |
702 | usbn_clk_ctl.s.p_c_sel = 0; | |
703 | } | |
704 | /* | |
705 | * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and | |
706 | * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down | |
707 | * such that USB is as close as possible to 125Mhz | |
708 | */ | |
709 | { | |
dea7503a | 710 | int divisor = DIV_ROUND_UP(octeon_get_clock_rate(), 125000000); |
6570b4a9 AK |
711 | /* Lower than 4 doesn't seem to work properly */ |
712 | if (divisor < 4) | |
713 | divisor = 4; | |
714 | usbn_clk_ctl.s.divide = divisor; | |
715 | usbn_clk_ctl.s.divide2 = 0; | |
716 | } | |
c4bdbdd9 | 717 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
718 | /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */ |
719 | usbn_clk_ctl.s.hclk_rst = 1; | |
c4bdbdd9 | 720 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
721 | /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */ |
722 | cvmx_wait(64); | |
723 | /* | |
724 | * 3. Program the power-on reset field in the USBN clock-control | |
725 | * register: | |
726 | * USBN_CLK_CTL[POR] = 0 | |
727 | */ | |
728 | usbn_clk_ctl.s.por = 0; | |
c4bdbdd9 | 729 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
730 | /* 4. Wait 1 ms for PHY clock to start */ |
731 | mdelay(1); | |
732 | /* | |
733 | * 5. Program the Reset input from automatic test equipment field in the | |
734 | * USBP control and status register: | |
735 | * USBN_USBP_CTL_STATUS[ATE_RESET] = 1 | |
736 | */ | |
c4bdbdd9 AK |
737 | usbn_usbp_ctl_status.u64 = |
738 | cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index)); | |
6570b4a9 | 739 | usbn_usbp_ctl_status.s.ate_reset = 1; |
c4bdbdd9 AK |
740 | cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), |
741 | usbn_usbp_ctl_status.u64); | |
6570b4a9 AK |
742 | /* 6. Wait 10 cycles */ |
743 | cvmx_wait(10); | |
744 | /* | |
745 | * 7. Clear ATE_RESET field in the USBN clock-control register: | |
746 | * USBN_USBP_CTL_STATUS[ATE_RESET] = 0 | |
747 | */ | |
748 | usbn_usbp_ctl_status.s.ate_reset = 0; | |
c4bdbdd9 AK |
749 | cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), |
750 | usbn_usbp_ctl_status.u64); | |
6570b4a9 AK |
751 | /* |
752 | * 8. Program the PHY reset field in the USBN clock-control register: | |
753 | * USBN_CLK_CTL[PRST] = 1 | |
754 | */ | |
755 | usbn_clk_ctl.s.prst = 1; | |
c4bdbdd9 | 756 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
757 | /* |
758 | * 9. Program the USBP control and status register to select host or | |
759 | * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for | |
760 | * device | |
761 | */ | |
762 | usbn_usbp_ctl_status.s.hst_mode = 0; | |
c4bdbdd9 AK |
763 | cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), |
764 | usbn_usbp_ctl_status.u64); | |
6570b4a9 AK |
765 | /* 10. Wait 1 us */ |
766 | udelay(1); | |
767 | /* | |
768 | * 11. Program the hreset_n field in the USBN clock-control register: | |
769 | * USBN_CLK_CTL[HRST] = 1 | |
770 | */ | |
771 | usbn_clk_ctl.s.hrst = 1; | |
c4bdbdd9 | 772 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
773 | /* 12. Proceed to USB core initialization */ |
774 | usbn_clk_ctl.s.enable = 1; | |
c4bdbdd9 | 775 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
776 | udelay(1); |
777 | ||
778 | /* | |
779 | * USB Core Initialization | |
780 | * | |
781 | * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to | |
782 | * determine USB core configuration parameters. | |
783 | * | |
784 | * Nothing needed | |
785 | * | |
786 | * 2. Program the following fields in the global AHB configuration | |
787 | * register (USBC_GAHBCFG) | |
788 | * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode | |
789 | * Burst length, USBC_GAHBCFG[HBSTLEN] = 0 | |
790 | * Nonperiodic TxFIFO empty level (slave mode only), | |
791 | * USBC_GAHBCFG[NPTXFEMPLVL] | |
792 | * Periodic TxFIFO empty level (slave mode only), | |
793 | * USBC_GAHBCFG[PTXFEMPLVL] | |
794 | * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1 | |
795 | */ | |
796 | { | |
797 | union cvmx_usbcx_gahbcfg usbcx_gahbcfg; | |
798 | /* Due to an errata, CN31XX doesn't support DMA */ | |
799 | if (OCTEON_IS_MODEL(OCTEON_CN31XX)) | |
800 | usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA; | |
801 | usbcx_gahbcfg.u32 = 0; | |
1da69aa9 RO |
802 | usbcx_gahbcfg.s.dmaen = !(usb->init_flags & |
803 | CVMX_USB_INITIALIZE_FLAGS_NO_DMA); | |
6570b4a9 AK |
804 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) |
805 | /* Only use one channel with non DMA */ | |
806 | usb->idle_hardware_channels = 0x1; | |
807 | else if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) | |
808 | /* CN5XXX have an errata with channel 3 */ | |
809 | usb->idle_hardware_channels = 0xf7; | |
810 | else | |
811 | usb->idle_hardware_channels = 0xff; | |
812 | usbcx_gahbcfg.s.hbstlen = 0; | |
813 | usbcx_gahbcfg.s.nptxfemplvl = 1; | |
814 | usbcx_gahbcfg.s.ptxfemplvl = 1; | |
815 | usbcx_gahbcfg.s.glblintrmsk = 1; | |
68d435dd AK |
816 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index), |
817 | usbcx_gahbcfg.u32); | |
6570b4a9 AK |
818 | } |
819 | /* | |
820 | * 3. Program the following fields in USBC_GUSBCFG register. | |
821 | * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0 | |
822 | * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0 | |
823 | * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5 | |
824 | * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0 | |
825 | */ | |
826 | { | |
827 | union cvmx_usbcx_gusbcfg usbcx_gusbcfg; | |
f5106435 | 828 | |
68d435dd | 829 | usbcx_gusbcfg.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 830 | CVMX_USBCX_GUSBCFG(usb->index)); |
6570b4a9 AK |
831 | usbcx_gusbcfg.s.toutcal = 0; |
832 | usbcx_gusbcfg.s.ddrsel = 0; | |
833 | usbcx_gusbcfg.s.usbtrdtim = 0x5; | |
834 | usbcx_gusbcfg.s.phylpwrclksel = 0; | |
68d435dd AK |
835 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index), |
836 | usbcx_gusbcfg.u32); | |
6570b4a9 AK |
837 | } |
838 | /* | |
839 | * 4. The software must unmask the following bits in the USBC_GINTMSK | |
840 | * register. | |
841 | * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1 | |
842 | * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1 | |
843 | */ | |
844 | { | |
845 | union cvmx_usbcx_gintmsk usbcx_gintmsk; | |
846 | int channel; | |
847 | ||
68d435dd | 848 | usbcx_gintmsk.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 849 | CVMX_USBCX_GINTMSK(usb->index)); |
6570b4a9 AK |
850 | usbcx_gintmsk.s.otgintmsk = 1; |
851 | usbcx_gintmsk.s.modemismsk = 1; | |
852 | usbcx_gintmsk.s.hchintmsk = 1; | |
853 | usbcx_gintmsk.s.sofmsk = 0; | |
854 | /* We need RX FIFO interrupts if we don't have DMA */ | |
855 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) | |
856 | usbcx_gintmsk.s.rxflvlmsk = 1; | |
68d435dd AK |
857 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index), |
858 | usbcx_gintmsk.u32); | |
6570b4a9 AK |
859 | |
860 | /* | |
861 | * Disable all channel interrupts. We'll enable them per channel | |
862 | * later. | |
863 | */ | |
864 | for (channel = 0; channel < 8; channel++) | |
68d435dd | 865 | cvmx_usb_write_csr32(usb, |
1da69aa9 | 866 | CVMX_USBCX_HCINTMSKX(channel, usb->index), 0); |
6570b4a9 AK |
867 | } |
868 | ||
869 | { | |
870 | /* | |
871 | * Host Port Initialization | |
872 | * | |
873 | * 1. Program the host-port interrupt-mask field to unmask, | |
874 | * USBC_GINTMSK[PRTINT] = 1 | |
875 | */ | |
1da69aa9 RO |
876 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
877 | union cvmx_usbcx_gintmsk, prtintmsk, 1); | |
878 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), | |
879 | union cvmx_usbcx_gintmsk, disconnintmsk, 1); | |
6570b4a9 AK |
880 | /* |
881 | * 2. Program the USBC_HCFG register to select full-speed host | |
882 | * or high-speed host. | |
883 | */ | |
884 | { | |
885 | union cvmx_usbcx_hcfg usbcx_hcfg; | |
f5106435 | 886 | |
68d435dd | 887 | usbcx_hcfg.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 888 | CVMX_USBCX_HCFG(usb->index)); |
6570b4a9 AK |
889 | usbcx_hcfg.s.fslssupp = 0; |
890 | usbcx_hcfg.s.fslspclksel = 0; | |
68d435dd AK |
891 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), |
892 | usbcx_hcfg.u32); | |
6570b4a9 AK |
893 | } |
894 | /* | |
895 | * 3. Program the port power bit to drive VBUS on the USB, | |
896 | * USBC_HPRT[PRTPWR] = 1 | |
897 | */ | |
1da69aa9 RO |
898 | USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), |
899 | union cvmx_usbcx_hprt, prtpwr, 1); | |
6570b4a9 AK |
900 | |
901 | /* | |
902 | * Steps 4-15 from the manual are done later in the port enable | |
903 | */ | |
904 | } | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
909 | ||
910 | /** | |
911 | * Shutdown a USB port after a call to cvmx_usb_initialize(). | |
912 | * The port should be disabled with all pipes closed when this | |
913 | * function is called. | |
914 | * | |
cb61c600 | 915 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
916 | * |
917 | * Returns: 0 or a negative error code. | |
918 | */ | |
cb61c600 | 919 | static int cvmx_usb_shutdown(struct cvmx_usb_state *usb) |
6570b4a9 AK |
920 | { |
921 | union cvmx_usbnx_clk_ctl usbn_clk_ctl; | |
6570b4a9 AK |
922 | |
923 | /* Make sure all pipes are closed */ | |
4a23ee1b AK |
924 | if (!list_empty(&usb->idle_pipes) || |
925 | !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS]) || | |
926 | !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT]) || | |
927 | !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_CONTROL]) || | |
928 | !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_BULK])) | |
6570b4a9 AK |
929 | return -EBUSY; |
930 | ||
931 | /* Disable the clocks and put them in power on reset */ | |
c4bdbdd9 | 932 | usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index)); |
6570b4a9 AK |
933 | usbn_clk_ctl.s.enable = 1; |
934 | usbn_clk_ctl.s.por = 1; | |
935 | usbn_clk_ctl.s.hclk_rst = 1; | |
936 | usbn_clk_ctl.s.prst = 0; | |
937 | usbn_clk_ctl.s.hrst = 0; | |
c4bdbdd9 | 938 | cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); |
6570b4a9 AK |
939 | return 0; |
940 | } | |
941 | ||
942 | ||
943 | /** | |
944 | * Enable a USB port. After this call succeeds, the USB port is | |
945 | * online and servicing requests. | |
946 | * | |
cb61c600 | 947 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
948 | * |
949 | * Returns: 0 or a negative error code. | |
950 | */ | |
cb61c600 | 951 | static int cvmx_usb_enable(struct cvmx_usb_state *usb) |
6570b4a9 AK |
952 | { |
953 | union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3; | |
6570b4a9 | 954 | |
68d435dd AK |
955 | usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb, |
956 | CVMX_USBCX_HPRT(usb->index)); | |
6570b4a9 AK |
957 | |
958 | /* | |
959 | * If the port is already enabled the just return. We don't need to do | |
960 | * anything | |
961 | */ | |
962 | if (usb->usbcx_hprt.s.prtena) | |
963 | return 0; | |
964 | ||
965 | /* If there is nothing plugged into the port then fail immediately */ | |
b49f1133 | 966 | if (!usb->usbcx_hprt.s.prtconnsts) |
6570b4a9 | 967 | return -ETIMEDOUT; |
6570b4a9 AK |
968 | |
969 | /* Program the port reset bit to start the reset process */ | |
b49f1133 RO |
970 | USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, |
971 | prtrst, 1); | |
6570b4a9 AK |
972 | |
973 | /* | |
974 | * Wait at least 50ms (high speed), or 10ms (full speed) for the reset | |
975 | * process to complete. | |
976 | */ | |
977 | mdelay(50); | |
978 | ||
979 | /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */ | |
1da69aa9 RO |
980 | USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, |
981 | prtrst, 0); | |
6570b4a9 AK |
982 | |
983 | /* Wait for the USBC_HPRT[PRTENA]. */ | |
1da69aa9 RO |
984 | if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), |
985 | union cvmx_usbcx_hprt, prtena, ==, 1, 100000)) | |
6570b4a9 AK |
986 | return -ETIMEDOUT; |
987 | ||
988 | /* | |
989 | * Read the port speed field to get the enumerated speed, | |
990 | * USBC_HPRT[PRTSPD]. | |
991 | */ | |
68d435dd AK |
992 | usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb, |
993 | CVMX_USBCX_HPRT(usb->index)); | |
994 | usbcx_ghwcfg3.u32 = cvmx_usb_read_csr32(usb, | |
995 | CVMX_USBCX_GHWCFG3(usb->index)); | |
6570b4a9 AK |
996 | |
997 | /* | |
998 | * 13. Program the USBC_GRXFSIZ register to select the size of the | |
999 | * receive FIFO (25%). | |
1000 | */ | |
1da69aa9 RO |
1001 | USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), |
1002 | union cvmx_usbcx_grxfsiz, rxfdep, | |
1003 | usbcx_ghwcfg3.s.dfifodepth / 4); | |
6570b4a9 AK |
1004 | /* |
1005 | * 14. Program the USBC_GNPTXFSIZ register to select the size and the | |
1006 | * start address of the non- periodic transmit FIFO for nonperiodic | |
1007 | * transactions (50%). | |
1008 | */ | |
1009 | { | |
1010 | union cvmx_usbcx_gnptxfsiz siz; | |
f5106435 | 1011 | |
68d435dd AK |
1012 | siz.u32 = cvmx_usb_read_csr32(usb, |
1013 | CVMX_USBCX_GNPTXFSIZ(usb->index)); | |
6570b4a9 AK |
1014 | siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2; |
1015 | siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4; | |
68d435dd AK |
1016 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), |
1017 | siz.u32); | |
6570b4a9 AK |
1018 | } |
1019 | /* | |
1020 | * 15. Program the USBC_HPTXFSIZ register to select the size and start | |
1021 | * address of the periodic transmit FIFO for periodic transactions | |
1022 | * (25%). | |
1023 | */ | |
1024 | { | |
1025 | union cvmx_usbcx_hptxfsiz siz; | |
f5106435 | 1026 | |
68d435dd AK |
1027 | siz.u32 = cvmx_usb_read_csr32(usb, |
1028 | CVMX_USBCX_HPTXFSIZ(usb->index)); | |
6570b4a9 AK |
1029 | siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4; |
1030 | siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4; | |
68d435dd AK |
1031 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), |
1032 | siz.u32); | |
6570b4a9 AK |
1033 | } |
1034 | /* Flush all FIFOs */ | |
1da69aa9 RO |
1035 | USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), |
1036 | union cvmx_usbcx_grstctl, txfnum, 0x10); | |
1037 | USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), | |
1038 | union cvmx_usbcx_grstctl, txfflsh, 1); | |
1039 | CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), | |
1040 | union cvmx_usbcx_grstctl, | |
6570b4a9 | 1041 | txfflsh, ==, 0, 100); |
1da69aa9 RO |
1042 | USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), |
1043 | union cvmx_usbcx_grstctl, rxfflsh, 1); | |
1044 | CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), | |
1045 | union cvmx_usbcx_grstctl, | |
6570b4a9 AK |
1046 | rxfflsh, ==, 0, 100); |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | ||
1052 | /** | |
1053 | * Disable a USB port. After this call the USB port will not | |
1054 | * generate data transfers and will not generate events. | |
1055 | * Transactions in process will fail and call their | |
1056 | * associated callbacks. | |
1057 | * | |
cb61c600 | 1058 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1059 | * |
1060 | * Returns: 0 or a negative error code. | |
1061 | */ | |
cb61c600 | 1062 | static int cvmx_usb_disable(struct cvmx_usb_state *usb) |
6570b4a9 | 1063 | { |
6570b4a9 | 1064 | /* Disable the port */ |
1da69aa9 RO |
1065 | USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, |
1066 | prtena, 1); | |
6570b4a9 AK |
1067 | return 0; |
1068 | } | |
1069 | ||
1070 | ||
1071 | /** | |
1072 | * Get the current state of the USB port. Use this call to | |
1073 | * determine if the usb port has anything connected, is enabled, | |
1074 | * or has some sort of error condition. The return value of this | |
1075 | * call has "changed" bits to signal of the value of some fields | |
29a202fa | 1076 | * have changed between calls. |
6570b4a9 | 1077 | * |
cb61c600 | 1078 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1079 | * |
1080 | * Returns: Port status information | |
1081 | */ | |
1da69aa9 RO |
1082 | static struct cvmx_usb_port_status cvmx_usb_get_status( |
1083 | struct cvmx_usb_state *usb) | |
6570b4a9 AK |
1084 | { |
1085 | union cvmx_usbcx_hprt usbc_hprt; | |
1086 | struct cvmx_usb_port_status result; | |
6570b4a9 AK |
1087 | |
1088 | memset(&result, 0, sizeof(result)); | |
1089 | ||
68d435dd | 1090 | usbc_hprt.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index)); |
6570b4a9 AK |
1091 | result.port_enabled = usbc_hprt.s.prtena; |
1092 | result.port_over_current = usbc_hprt.s.prtovrcurract; | |
1093 | result.port_powered = usbc_hprt.s.prtpwr; | |
1094 | result.port_speed = usbc_hprt.s.prtspd; | |
1095 | result.connected = usbc_hprt.s.prtconnsts; | |
1da69aa9 RO |
1096 | result.connect_change = |
1097 | (result.connected != usb->port_status.connected); | |
6570b4a9 AK |
1098 | |
1099 | return result; | |
1100 | } | |
1101 | ||
6570b4a9 AK |
1102 | /** |
1103 | * Open a virtual pipe between the host and a USB device. A pipe | |
1104 | * must be opened before data can be transferred between a device | |
1105 | * and Octeon. | |
1106 | * | |
cb61c600 | 1107 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1108 | * @device_addr: |
1109 | * USB device address to open the pipe to | |
1110 | * (0-127). | |
1111 | * @endpoint_num: | |
1112 | * USB endpoint number to open the pipe to | |
1113 | * (0-15). | |
1114 | * @device_speed: | |
1115 | * The speed of the device the pipe is going | |
1116 | * to. This must match the device's speed, | |
1117 | * which may be different than the port speed. | |
1118 | * @max_packet: The maximum packet length the device can | |
1119 | * transmit/receive (low speed=0-8, full | |
1120 | * speed=0-1023, high speed=0-1024). This value | |
1121 | * comes from the standard endpoint descriptor | |
1122 | * field wMaxPacketSize bits <10:0>. | |
1123 | * @transfer_type: | |
1124 | * The type of transfer this pipe is for. | |
1125 | * @transfer_dir: | |
1126 | * The direction the pipe is in. This is not | |
1127 | * used for control pipes. | |
1128 | * @interval: For ISOCHRONOUS and INTERRUPT transfers, | |
1129 | * this is how often the transfer is scheduled | |
1130 | * for. All other transfers should specify | |
1131 | * zero. The units are in frames (8000/sec at | |
1132 | * high speed, 1000/sec for full speed). | |
1133 | * @multi_count: | |
1134 | * For high speed devices, this is the maximum | |
1135 | * allowed number of packet per microframe. | |
1136 | * Specify zero for non high speed devices. This | |
1137 | * value comes from the standard endpoint descriptor | |
1138 | * field wMaxPacketSize bits <12:11>. | |
1139 | * @hub_device_addr: | |
1140 | * Hub device address this device is connected | |
1141 | * to. Devices connected directly to Octeon | |
1142 | * use zero. This is only used when the device | |
1143 | * is full/low speed behind a high speed hub. | |
1144 | * The address will be of the high speed hub, | |
1145 | * not and full speed hubs after it. | |
1146 | * @hub_port: Which port on the hub the device is | |
1147 | * connected. Use zero for devices connected | |
1148 | * directly to Octeon. Like hub_device_addr, | |
1149 | * this is only used for full/low speed | |
1150 | * devices behind a high speed hub. | |
1151 | * | |
60f81507 | 1152 | * Returns: A non-NULL value is a pipe. NULL means an error. |
6570b4a9 | 1153 | */ |
60f81507 | 1154 | static struct cvmx_usb_pipe *cvmx_usb_open_pipe(struct cvmx_usb_state *usb, |
f5106435 PD |
1155 | int device_addr, |
1156 | int endpoint_num, | |
60f81507 AK |
1157 | enum cvmx_usb_speed |
1158 | device_speed, | |
1159 | int max_packet, | |
1160 | enum cvmx_usb_transfer | |
1161 | transfer_type, | |
1162 | enum cvmx_usb_direction | |
1163 | transfer_dir, | |
1164 | int interval, int multi_count, | |
1165 | int hub_device_addr, | |
1166 | int hub_port) | |
6570b4a9 AK |
1167 | { |
1168 | struct cvmx_usb_pipe *pipe; | |
6570b4a9 | 1169 | |
d2695a8a | 1170 | pipe = kzalloc(sizeof(*pipe), GFP_ATOMIC); |
6570b4a9 | 1171 | if (!pipe) |
60f81507 | 1172 | return NULL; |
6570b4a9 AK |
1173 | if ((device_speed == CVMX_USB_SPEED_HIGH) && |
1174 | (transfer_dir == CVMX_USB_DIRECTION_OUT) && | |
1175 | (transfer_type == CVMX_USB_TRANSFER_BULK)) | |
1176 | pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING; | |
1177 | pipe->device_addr = device_addr; | |
1178 | pipe->endpoint_num = endpoint_num; | |
1179 | pipe->device_speed = device_speed; | |
1180 | pipe->max_packet = max_packet; | |
1181 | pipe->transfer_type = transfer_type; | |
1182 | pipe->transfer_dir = transfer_dir; | |
5669601d AK |
1183 | INIT_LIST_HEAD(&pipe->transactions); |
1184 | ||
6570b4a9 AK |
1185 | /* |
1186 | * All pipes use interval to rate limit NAK processing. Force an | |
1187 | * interval if one wasn't supplied | |
1188 | */ | |
1189 | if (!interval) | |
1190 | interval = 1; | |
68d435dd | 1191 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
1192 | pipe->interval = interval*8; |
1193 | /* Force start splits to be schedule on uFrame 0 */ | |
e725cef3 PD |
1194 | pipe->next_tx_frame = ((usb->frame_number+7)&~7) + |
1195 | pipe->interval; | |
6570b4a9 AK |
1196 | } else { |
1197 | pipe->interval = interval; | |
1198 | pipe->next_tx_frame = usb->frame_number + pipe->interval; | |
1199 | } | |
1200 | pipe->multi_count = multi_count; | |
1201 | pipe->hub_device_addr = hub_device_addr; | |
1202 | pipe->hub_port = hub_port; | |
1203 | pipe->pid_toggle = 0; | |
1204 | pipe->split_sc_frame = -1; | |
4a23ee1b | 1205 | list_add_tail(&pipe->node, &usb->idle_pipes); |
6570b4a9 AK |
1206 | |
1207 | /* | |
1208 | * We don't need to tell the hardware about this pipe yet since | |
1209 | * it doesn't have any submitted requests | |
1210 | */ | |
1211 | ||
60f81507 | 1212 | return pipe; |
6570b4a9 AK |
1213 | } |
1214 | ||
1215 | ||
1216 | /** | |
1217 | * Poll the RX FIFOs and remove data as needed. This function is only used | |
1218 | * in non DMA mode. It is very important that this function be called quickly | |
1219 | * enough to prevent FIFO overflow. | |
1220 | * | |
cb61c600 | 1221 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 | 1222 | */ |
68d435dd | 1223 | static void cvmx_usb_poll_rx_fifo(struct cvmx_usb_state *usb) |
6570b4a9 AK |
1224 | { |
1225 | union cvmx_usbcx_grxstsph rx_status; | |
1226 | int channel; | |
1227 | int bytes; | |
1228 | uint64_t address; | |
1229 | uint32_t *ptr; | |
1230 | ||
68d435dd AK |
1231 | rx_status.u32 = cvmx_usb_read_csr32(usb, |
1232 | CVMX_USBCX_GRXSTSPH(usb->index)); | |
6570b4a9 AK |
1233 | /* Only read data if IN data is there */ |
1234 | if (rx_status.s.pktsts != 2) | |
1235 | return; | |
1236 | /* Check if no data is available */ | |
1237 | if (!rx_status.s.bcnt) | |
1238 | return; | |
1239 | ||
1240 | channel = rx_status.s.chnum; | |
1241 | bytes = rx_status.s.bcnt; | |
1242 | if (!bytes) | |
1243 | return; | |
1244 | ||
1245 | /* Get where the DMA engine would have written this data */ | |
c4bdbdd9 AK |
1246 | address = cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + |
1247 | channel * 8); | |
e725cef3 | 1248 | |
6570b4a9 | 1249 | ptr = cvmx_phys_to_ptr(address); |
c4bdbdd9 AK |
1250 | cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel * 8, |
1251 | address + bytes); | |
6570b4a9 AK |
1252 | |
1253 | /* Loop writing the FIFO data for this packet into memory */ | |
1254 | while (bytes > 0) { | |
68d435dd AK |
1255 | *ptr++ = cvmx_usb_read_csr32(usb, |
1256 | USB_FIFO_ADDRESS(channel, usb->index)); | |
6570b4a9 AK |
1257 | bytes -= 4; |
1258 | } | |
1259 | CVMX_SYNCW; | |
6570b4a9 AK |
1260 | } |
1261 | ||
1262 | ||
1263 | /** | |
1264 | * Fill the TX hardware fifo with data out of the software | |
1265 | * fifos | |
1266 | * | |
cb61c600 | 1267 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1268 | * @fifo: Software fifo to use |
1269 | * @available: Amount of space in the hardware fifo | |
1270 | * | |
1271 | * Returns: Non zero if the hardware fifo was too small and needs | |
1272 | * to be serviced again. | |
1273 | */ | |
68d435dd AK |
1274 | static int cvmx_usb_fill_tx_hw(struct cvmx_usb_state *usb, |
1275 | struct cvmx_usb_tx_fifo *fifo, int available) | |
6570b4a9 AK |
1276 | { |
1277 | /* | |
1278 | * We're done either when there isn't anymore space or the software FIFO | |
1279 | * is empty | |
1280 | */ | |
1281 | while (available && (fifo->head != fifo->tail)) { | |
1282 | int i = fifo->tail; | |
1283 | const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address); | |
1da69aa9 RO |
1284 | uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, |
1285 | usb->index) ^ 4; | |
6570b4a9 AK |
1286 | int words = available; |
1287 | ||
1288 | /* Limit the amount of data to waht the SW fifo has */ | |
1289 | if (fifo->entry[i].size <= available) { | |
1290 | words = fifo->entry[i].size; | |
1291 | fifo->tail++; | |
1292 | if (fifo->tail > MAX_CHANNELS) | |
1293 | fifo->tail = 0; | |
1294 | } | |
1295 | ||
1296 | /* Update the next locations and counts */ | |
1297 | available -= words; | |
1298 | fifo->entry[i].address += words * 4; | |
1299 | fifo->entry[i].size -= words; | |
1300 | ||
1301 | /* | |
1302 | * Write the HW fifo data. The read every three writes is due | |
1303 | * to an errata on CN3XXX chips | |
1304 | */ | |
1305 | while (words > 3) { | |
1306 | cvmx_write64_uint32(csr_address, *ptr++); | |
1307 | cvmx_write64_uint32(csr_address, *ptr++); | |
1308 | cvmx_write64_uint32(csr_address, *ptr++); | |
1da69aa9 RO |
1309 | cvmx_read64_uint64( |
1310 | CVMX_USBNX_DMA0_INB_CHN0(usb->index)); | |
6570b4a9 AK |
1311 | words -= 3; |
1312 | } | |
1313 | cvmx_write64_uint32(csr_address, *ptr++); | |
1314 | if (--words) { | |
1315 | cvmx_write64_uint32(csr_address, *ptr++); | |
1316 | if (--words) | |
1317 | cvmx_write64_uint32(csr_address, *ptr++); | |
1318 | } | |
1319 | cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index)); | |
1320 | } | |
1321 | return fifo->head != fifo->tail; | |
1322 | } | |
1323 | ||
1324 | ||
1325 | /** | |
1326 | * Check the hardware FIFOs and fill them as needed | |
1327 | * | |
cb61c600 | 1328 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 | 1329 | */ |
68d435dd | 1330 | static void cvmx_usb_poll_tx_fifo(struct cvmx_usb_state *usb) |
6570b4a9 AK |
1331 | { |
1332 | if (usb->periodic.head != usb->periodic.tail) { | |
1333 | union cvmx_usbcx_hptxsts tx_status; | |
f5106435 | 1334 | |
68d435dd AK |
1335 | tx_status.u32 = cvmx_usb_read_csr32(usb, |
1336 | CVMX_USBCX_HPTXSTS(usb->index)); | |
1337 | if (cvmx_usb_fill_tx_hw(usb, &usb->periodic, | |
1338 | tx_status.s.ptxfspcavail)) | |
1da69aa9 RO |
1339 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
1340 | union cvmx_usbcx_gintmsk, | |
1341 | ptxfempmsk, 1); | |
6570b4a9 | 1342 | else |
1da69aa9 RO |
1343 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
1344 | union cvmx_usbcx_gintmsk, | |
1345 | ptxfempmsk, 0); | |
6570b4a9 AK |
1346 | } |
1347 | ||
1348 | if (usb->nonperiodic.head != usb->nonperiodic.tail) { | |
1349 | union cvmx_usbcx_gnptxsts tx_status; | |
f5106435 | 1350 | |
68d435dd AK |
1351 | tx_status.u32 = cvmx_usb_read_csr32(usb, |
1352 | CVMX_USBCX_GNPTXSTS(usb->index)); | |
1353 | if (cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, | |
1354 | tx_status.s.nptxfspcavail)) | |
1da69aa9 RO |
1355 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
1356 | union cvmx_usbcx_gintmsk, | |
1357 | nptxfempmsk, 1); | |
6570b4a9 | 1358 | else |
1da69aa9 RO |
1359 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
1360 | union cvmx_usbcx_gintmsk, | |
1361 | nptxfempmsk, 0); | |
6570b4a9 | 1362 | } |
6570b4a9 AK |
1363 | } |
1364 | ||
1365 | ||
1366 | /** | |
1367 | * Fill the TX FIFO with an outgoing packet | |
1368 | * | |
cb61c600 | 1369 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1370 | * @channel: Channel number to get packet from |
1371 | */ | |
68d435dd | 1372 | static void cvmx_usb_fill_tx_fifo(struct cvmx_usb_state *usb, int channel) |
6570b4a9 AK |
1373 | { |
1374 | union cvmx_usbcx_hccharx hcchar; | |
1375 | union cvmx_usbcx_hcspltx usbc_hcsplt; | |
1376 | union cvmx_usbcx_hctsizx usbc_hctsiz; | |
1377 | struct cvmx_usb_tx_fifo *fifo; | |
1378 | ||
1379 | /* We only need to fill data on outbound channels */ | |
68d435dd | 1380 | hcchar.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 1381 | CVMX_USBCX_HCCHARX(channel, usb->index)); |
6570b4a9 AK |
1382 | if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT) |
1383 | return; | |
1384 | ||
1385 | /* OUT Splits only have data on the start and not the complete */ | |
68d435dd AK |
1386 | usbc_hcsplt.u32 = cvmx_usb_read_csr32(usb, |
1387 | CVMX_USBCX_HCSPLTX(channel, usb->index)); | |
6570b4a9 AK |
1388 | if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt) |
1389 | return; | |
1390 | ||
1391 | /* | |
1392 | * Find out how many bytes we need to fill and convert it into 32bit | |
1393 | * words. | |
1394 | */ | |
68d435dd AK |
1395 | usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, |
1396 | CVMX_USBCX_HCTSIZX(channel, usb->index)); | |
6570b4a9 AK |
1397 | if (!usbc_hctsiz.s.xfersize) |
1398 | return; | |
1399 | ||
1400 | if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) || | |
1401 | (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS)) | |
1402 | fifo = &usb->periodic; | |
1403 | else | |
1404 | fifo = &usb->nonperiodic; | |
1405 | ||
1406 | fifo->entry[fifo->head].channel = channel; | |
c4bdbdd9 AK |
1407 | fifo->entry[fifo->head].address = |
1408 | cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + | |
1409 | channel * 8); | |
6570b4a9 AK |
1410 | fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2; |
1411 | fifo->head++; | |
1412 | if (fifo->head > MAX_CHANNELS) | |
1413 | fifo->head = 0; | |
1414 | ||
68d435dd | 1415 | cvmx_usb_poll_tx_fifo(usb); |
6570b4a9 AK |
1416 | } |
1417 | ||
1418 | /** | |
1419 | * Perform channel specific setup for Control transactions. All | |
68d435dd | 1420 | * the generic stuff will already have been done in cvmx_usb_start_channel(). |
6570b4a9 | 1421 | * |
cb61c600 | 1422 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1423 | * @channel: Channel to setup |
1424 | * @pipe: Pipe for control transaction | |
1425 | */ | |
68d435dd AK |
1426 | static void cvmx_usb_start_channel_control(struct cvmx_usb_state *usb, |
1427 | int channel, | |
1428 | struct cvmx_usb_pipe *pipe) | |
6570b4a9 | 1429 | { |
ba0b8e42 AK |
1430 | struct octeon_hcd *priv = cvmx_usb_to_octeon(usb); |
1431 | struct usb_hcd *hcd = octeon_to_hcd(priv); | |
1432 | struct device *dev = hcd->self.controller; | |
5669601d AK |
1433 | struct cvmx_usb_transaction *transaction = |
1434 | list_first_entry(&pipe->transactions, typeof(*transaction), | |
1435 | node); | |
e301dfb2 | 1436 | struct usb_ctrlrequest *header = |
6570b4a9 | 1437 | cvmx_phys_to_ptr(transaction->control_header); |
1da69aa9 RO |
1438 | int bytes_to_transfer = transaction->buffer_length - |
1439 | transaction->actual_bytes; | |
6570b4a9 AK |
1440 | int packets_to_transfer; |
1441 | union cvmx_usbcx_hctsizx usbc_hctsiz; | |
1442 | ||
68d435dd AK |
1443 | usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, |
1444 | CVMX_USBCX_HCTSIZX(channel, usb->index)); | |
6570b4a9 AK |
1445 | |
1446 | switch (transaction->stage) { | |
1447 | case CVMX_USB_STAGE_NON_CONTROL: | |
1448 | case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE: | |
ba0b8e42 | 1449 | dev_err(dev, "%s: ERROR - Non control stage\n", __func__); |
6570b4a9 AK |
1450 | break; |
1451 | case CVMX_USB_STAGE_SETUP: | |
1452 | usbc_hctsiz.s.pid = 3; /* Setup */ | |
1453 | bytes_to_transfer = sizeof(*header); | |
1454 | /* All Control operations start with a setup going OUT */ | |
e725cef3 PD |
1455 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
1456 | union cvmx_usbcx_hccharx, epdir, | |
1457 | CVMX_USB_DIRECTION_OUT); | |
6570b4a9 AK |
1458 | /* |
1459 | * Setup send the control header instead of the buffer data. The | |
1460 | * buffer data will be used in the next stage | |
1461 | */ | |
c4bdbdd9 AK |
1462 | cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + |
1463 | channel * 8, | |
1464 | transaction->control_header); | |
6570b4a9 AK |
1465 | break; |
1466 | case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE: | |
1467 | usbc_hctsiz.s.pid = 3; /* Setup */ | |
1468 | bytes_to_transfer = 0; | |
1469 | /* All Control operations start with a setup going OUT */ | |
e725cef3 PD |
1470 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
1471 | union cvmx_usbcx_hccharx, epdir, | |
1472 | CVMX_USB_DIRECTION_OUT); | |
1473 | ||
1474 | USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), | |
1475 | union cvmx_usbcx_hcspltx, compsplt, 1); | |
6570b4a9 AK |
1476 | break; |
1477 | case CVMX_USB_STAGE_DATA: | |
68d435dd AK |
1478 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
1479 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { | |
96ee2cc8 | 1480 | if (header->bRequestType & USB_DIR_IN) |
6570b4a9 AK |
1481 | bytes_to_transfer = 0; |
1482 | else if (bytes_to_transfer > pipe->max_packet) | |
1483 | bytes_to_transfer = pipe->max_packet; | |
1484 | } | |
1485 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), | |
1486 | union cvmx_usbcx_hccharx, epdir, | |
96ee2cc8 | 1487 | ((header->bRequestType & USB_DIR_IN) ? |
6570b4a9 AK |
1488 | CVMX_USB_DIRECTION_IN : |
1489 | CVMX_USB_DIRECTION_OUT)); | |
1490 | break; | |
1491 | case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE: | |
68d435dd | 1492 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
96ee2cc8 | 1493 | if (!(header->bRequestType & USB_DIR_IN)) |
6570b4a9 AK |
1494 | bytes_to_transfer = 0; |
1495 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), | |
1496 | union cvmx_usbcx_hccharx, epdir, | |
96ee2cc8 | 1497 | ((header->bRequestType & USB_DIR_IN) ? |
6570b4a9 AK |
1498 | CVMX_USB_DIRECTION_IN : |
1499 | CVMX_USB_DIRECTION_OUT)); | |
1da69aa9 RO |
1500 | USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), |
1501 | union cvmx_usbcx_hcspltx, compsplt, 1); | |
6570b4a9 AK |
1502 | break; |
1503 | case CVMX_USB_STAGE_STATUS: | |
68d435dd | 1504 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
6570b4a9 | 1505 | bytes_to_transfer = 0; |
1da69aa9 RO |
1506 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
1507 | union cvmx_usbcx_hccharx, epdir, | |
96ee2cc8 | 1508 | ((header->bRequestType & USB_DIR_IN) ? |
6570b4a9 AK |
1509 | CVMX_USB_DIRECTION_OUT : |
1510 | CVMX_USB_DIRECTION_IN)); | |
1511 | break; | |
1512 | case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE: | |
68d435dd | 1513 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
6570b4a9 | 1514 | bytes_to_transfer = 0; |
1da69aa9 RO |
1515 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
1516 | union cvmx_usbcx_hccharx, epdir, | |
96ee2cc8 | 1517 | ((header->bRequestType & USB_DIR_IN) ? |
6570b4a9 AK |
1518 | CVMX_USB_DIRECTION_OUT : |
1519 | CVMX_USB_DIRECTION_IN)); | |
1da69aa9 RO |
1520 | USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), |
1521 | union cvmx_usbcx_hcspltx, compsplt, 1); | |
6570b4a9 AK |
1522 | break; |
1523 | } | |
1524 | ||
1525 | /* | |
1526 | * Make sure the transfer never exceeds the byte limit of the hardware. | |
1527 | * Further bytes will be sent as continued transactions | |
1528 | */ | |
1529 | if (bytes_to_transfer > MAX_TRANSFER_BYTES) { | |
1530 | /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */ | |
1531 | bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet; | |
1532 | bytes_to_transfer *= pipe->max_packet; | |
1533 | } | |
1534 | ||
1535 | /* | |
1536 | * Calculate the number of packets to transfer. If the length is zero | |
1537 | * we still need to transfer one packet | |
1538 | */ | |
dea7503a TP |
1539 | packets_to_transfer = DIV_ROUND_UP(bytes_to_transfer, |
1540 | pipe->max_packet); | |
6570b4a9 AK |
1541 | if (packets_to_transfer == 0) |
1542 | packets_to_transfer = 1; | |
1da69aa9 RO |
1543 | else if ((packets_to_transfer > 1) && |
1544 | (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) { | |
6570b4a9 AK |
1545 | /* |
1546 | * Limit to one packet when not using DMA. Channels must be | |
1547 | * restarted between every packet for IN transactions, so there | |
1548 | * is no reason to do multiple packets in a row | |
1549 | */ | |
1550 | packets_to_transfer = 1; | |
1551 | bytes_to_transfer = packets_to_transfer * pipe->max_packet; | |
1552 | } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) { | |
1553 | /* | |
1554 | * Limit the number of packet and data transferred to what the | |
1555 | * hardware can handle | |
1556 | */ | |
1557 | packets_to_transfer = MAX_TRANSFER_PACKETS; | |
1558 | bytes_to_transfer = packets_to_transfer * pipe->max_packet; | |
1559 | } | |
1560 | ||
1561 | usbc_hctsiz.s.xfersize = bytes_to_transfer; | |
1562 | usbc_hctsiz.s.pktcnt = packets_to_transfer; | |
1563 | ||
68d435dd AK |
1564 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), |
1565 | usbc_hctsiz.u32); | |
6570b4a9 AK |
1566 | } |
1567 | ||
1568 | ||
1569 | /** | |
1570 | * Start a channel to perform the pipe's head transaction | |
1571 | * | |
cb61c600 | 1572 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1573 | * @channel: Channel to setup |
1574 | * @pipe: Pipe to start | |
1575 | */ | |
68d435dd AK |
1576 | static void cvmx_usb_start_channel(struct cvmx_usb_state *usb, int channel, |
1577 | struct cvmx_usb_pipe *pipe) | |
6570b4a9 | 1578 | { |
5669601d AK |
1579 | struct cvmx_usb_transaction *transaction = |
1580 | list_first_entry(&pipe->transactions, typeof(*transaction), | |
1581 | node); | |
6570b4a9 AK |
1582 | |
1583 | /* Make sure all writes to the DMA region get flushed */ | |
1584 | CVMX_SYNCW; | |
1585 | ||
1586 | /* Attach the channel to the pipe */ | |
1587 | usb->pipe_for_channel[channel] = pipe; | |
1588 | pipe->channel = channel; | |
1589 | pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED; | |
1590 | ||
1591 | /* Mark this channel as in use */ | |
1592 | usb->idle_hardware_channels &= ~(1<<channel); | |
1593 | ||
1594 | /* Enable the channel interrupt bits */ | |
1595 | { | |
1596 | union cvmx_usbcx_hcintx usbc_hcint; | |
1597 | union cvmx_usbcx_hcintmskx usbc_hcintmsk; | |
1598 | union cvmx_usbcx_haintmsk usbc_haintmsk; | |
1599 | ||
1600 | /* Clear all channel status bits */ | |
68d435dd AK |
1601 | usbc_hcint.u32 = cvmx_usb_read_csr32(usb, |
1602 | CVMX_USBCX_HCINTX(channel, usb->index)); | |
e725cef3 | 1603 | |
68d435dd AK |
1604 | cvmx_usb_write_csr32(usb, |
1605 | CVMX_USBCX_HCINTX(channel, usb->index), | |
1606 | usbc_hcint.u32); | |
6570b4a9 AK |
1607 | |
1608 | usbc_hcintmsk.u32 = 0; | |
1609 | usbc_hcintmsk.s.chhltdmsk = 1; | |
1610 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { | |
1611 | /* | |
1612 | * Channels need these extra interrupts when we aren't | |
1613 | * in DMA mode. | |
1614 | */ | |
1615 | usbc_hcintmsk.s.datatglerrmsk = 1; | |
1616 | usbc_hcintmsk.s.frmovrunmsk = 1; | |
1617 | usbc_hcintmsk.s.bblerrmsk = 1; | |
1618 | usbc_hcintmsk.s.xacterrmsk = 1; | |
68d435dd | 1619 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
1620 | /* |
1621 | * Splits don't generate xfercompl, so we need | |
1622 | * ACK and NYET. | |
1623 | */ | |
1624 | usbc_hcintmsk.s.nyetmsk = 1; | |
1625 | usbc_hcintmsk.s.ackmsk = 1; | |
1626 | } | |
1627 | usbc_hcintmsk.s.nakmsk = 1; | |
1628 | usbc_hcintmsk.s.stallmsk = 1; | |
1629 | usbc_hcintmsk.s.xfercomplmsk = 1; | |
1630 | } | |
68d435dd | 1631 | cvmx_usb_write_csr32(usb, |
9109fcff AS |
1632 | CVMX_USBCX_HCINTMSKX(channel, usb->index), |
1633 | usbc_hcintmsk.u32); | |
6570b4a9 AK |
1634 | |
1635 | /* Enable the channel interrupt to propagate */ | |
68d435dd | 1636 | usbc_haintmsk.u32 = cvmx_usb_read_csr32(usb, |
e725cef3 | 1637 | CVMX_USBCX_HAINTMSK(usb->index)); |
6570b4a9 | 1638 | usbc_haintmsk.s.haintmsk |= 1<<channel; |
68d435dd AK |
1639 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), |
1640 | usbc_haintmsk.u32); | |
6570b4a9 AK |
1641 | } |
1642 | ||
1643 | /* Setup the locations the DMA engines use */ | |
1644 | { | |
e725cef3 PD |
1645 | uint64_t dma_address = transaction->buffer + |
1646 | transaction->actual_bytes; | |
f5106435 | 1647 | |
6570b4a9 | 1648 | if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) |
e725cef3 PD |
1649 | dma_address = transaction->buffer + |
1650 | transaction->iso_packets[0].offset + | |
1651 | transaction->actual_bytes; | |
1652 | ||
c4bdbdd9 AK |
1653 | cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + |
1654 | channel * 8, | |
1655 | dma_address); | |
1656 | cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + | |
1657 | channel * 8, | |
1658 | dma_address); | |
6570b4a9 AK |
1659 | } |
1660 | ||
1661 | /* Setup both the size of the transfer and the SPLIT characteristics */ | |
1662 | { | |
1663 | union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0}; | |
1664 | union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0}; | |
1665 | int packets_to_transfer; | |
1da69aa9 RO |
1666 | int bytes_to_transfer = transaction->buffer_length - |
1667 | transaction->actual_bytes; | |
6570b4a9 AK |
1668 | |
1669 | /* | |
1670 | * ISOCHRONOUS transactions store each individual transfer size | |
1671 | * in the packet structure, not the global buffer_length | |
1672 | */ | |
1673 | if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) | |
1da69aa9 RO |
1674 | bytes_to_transfer = |
1675 | transaction->iso_packets[0].length - | |
1676 | transaction->actual_bytes; | |
6570b4a9 AK |
1677 | |
1678 | /* | |
1679 | * We need to do split transactions when we are talking to non | |
1680 | * high speed devices that are behind a high speed hub | |
1681 | */ | |
68d435dd | 1682 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
1683 | /* |
1684 | * On the start split phase (stage is even) record the | |
1685 | * frame number we will need to send the split complete. | |
1686 | * We only store the lower two bits since the time ahead | |
1687 | * can only be two frames | |
1688 | */ | |
1689 | if ((transaction->stage&1) == 0) { | |
1690 | if (transaction->type == CVMX_USB_TRANSFER_BULK) | |
1da69aa9 RO |
1691 | pipe->split_sc_frame = |
1692 | (usb->frame_number + 1) & 0x7f; | |
6570b4a9 | 1693 | else |
1da69aa9 RO |
1694 | pipe->split_sc_frame = |
1695 | (usb->frame_number + 2) & 0x7f; | |
6570b4a9 AK |
1696 | } else |
1697 | pipe->split_sc_frame = -1; | |
1698 | ||
1699 | usbc_hcsplt.s.spltena = 1; | |
1700 | usbc_hcsplt.s.hubaddr = pipe->hub_device_addr; | |
1701 | usbc_hcsplt.s.prtaddr = pipe->hub_port; | |
1da69aa9 RO |
1702 | usbc_hcsplt.s.compsplt = (transaction->stage == |
1703 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE); | |
6570b4a9 AK |
1704 | |
1705 | /* | |
1706 | * SPLIT transactions can only ever transmit one data | |
1707 | * packet so limit the transfer size to the max packet | |
1708 | * size | |
1709 | */ | |
1710 | if (bytes_to_transfer > pipe->max_packet) | |
1711 | bytes_to_transfer = pipe->max_packet; | |
1712 | ||
1713 | /* | |
1714 | * ISOCHRONOUS OUT splits are unique in that they limit | |
1715 | * data transfers to 188 byte chunks representing the | |
1716 | * begin/middle/end of the data or all | |
1717 | */ | |
1718 | if (!usbc_hcsplt.s.compsplt && | |
1da69aa9 RO |
1719 | (pipe->transfer_dir == |
1720 | CVMX_USB_DIRECTION_OUT) && | |
1721 | (pipe->transfer_type == | |
1722 | CVMX_USB_TRANSFER_ISOCHRONOUS)) { | |
6570b4a9 AK |
1723 | /* |
1724 | * Clear the split complete frame number as | |
1725 | * there isn't going to be a split complete | |
1726 | */ | |
1727 | pipe->split_sc_frame = -1; | |
1728 | /* | |
1729 | * See if we've started this transfer and sent | |
1730 | * data | |
1731 | */ | |
1732 | if (transaction->actual_bytes == 0) { | |
1733 | /* | |
1734 | * Nothing sent yet, this is either a | |
1735 | * begin or the entire payload | |
1736 | */ | |
1737 | if (bytes_to_transfer <= 188) | |
1738 | /* Entire payload in one go */ | |
1739 | usbc_hcsplt.s.xactpos = 3; | |
1740 | else | |
1741 | /* First part of payload */ | |
1742 | usbc_hcsplt.s.xactpos = 2; | |
1743 | } else { | |
1744 | /* | |
1745 | * Continuing the previous data, we must | |
1746 | * either be in the middle or at the end | |
1747 | */ | |
1748 | if (bytes_to_transfer <= 188) | |
1749 | /* End of payload */ | |
1750 | usbc_hcsplt.s.xactpos = 1; | |
1751 | else | |
1752 | /* Middle of payload */ | |
1753 | usbc_hcsplt.s.xactpos = 0; | |
1754 | } | |
1755 | /* | |
1756 | * Again, the transfer size is limited to 188 | |
1757 | * bytes | |
1758 | */ | |
1759 | if (bytes_to_transfer > 188) | |
1760 | bytes_to_transfer = 188; | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | /* | |
1765 | * Make sure the transfer never exceeds the byte limit of the | |
1766 | * hardware. Further bytes will be sent as continued | |
1767 | * transactions | |
1768 | */ | |
1769 | if (bytes_to_transfer > MAX_TRANSFER_BYTES) { | |
1770 | /* | |
1771 | * Round MAX_TRANSFER_BYTES to a multiple of out packet | |
1772 | * size | |
1773 | */ | |
1da69aa9 RO |
1774 | bytes_to_transfer = MAX_TRANSFER_BYTES / |
1775 | pipe->max_packet; | |
6570b4a9 AK |
1776 | bytes_to_transfer *= pipe->max_packet; |
1777 | } | |
1778 | ||
1779 | /* | |
1780 | * Calculate the number of packets to transfer. If the length is | |
1781 | * zero we still need to transfer one packet | |
1782 | */ | |
1da69aa9 | 1783 | packets_to_transfer = |
dea7503a | 1784 | DIV_ROUND_UP(bytes_to_transfer, pipe->max_packet); |
6570b4a9 AK |
1785 | if (packets_to_transfer == 0) |
1786 | packets_to_transfer = 1; | |
1da69aa9 RO |
1787 | else if ((packets_to_transfer > 1) && |
1788 | (usb->init_flags & | |
1789 | CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) { | |
6570b4a9 AK |
1790 | /* |
1791 | * Limit to one packet when not using DMA. Channels must | |
1792 | * be restarted between every packet for IN | |
1793 | * transactions, so there is no reason to do multiple | |
1794 | * packets in a row | |
1795 | */ | |
1796 | packets_to_transfer = 1; | |
1da69aa9 RO |
1797 | bytes_to_transfer = packets_to_transfer * |
1798 | pipe->max_packet; | |
6570b4a9 AK |
1799 | } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) { |
1800 | /* | |
1801 | * Limit the number of packet and data transferred to | |
1802 | * what the hardware can handle | |
1803 | */ | |
1804 | packets_to_transfer = MAX_TRANSFER_PACKETS; | |
1da69aa9 RO |
1805 | bytes_to_transfer = packets_to_transfer * |
1806 | pipe->max_packet; | |
6570b4a9 AK |
1807 | } |
1808 | ||
1809 | usbc_hctsiz.s.xfersize = bytes_to_transfer; | |
1810 | usbc_hctsiz.s.pktcnt = packets_to_transfer; | |
1811 | ||
1812 | /* Update the DATA0/DATA1 toggle */ | |
68d435dd | 1813 | usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); |
6570b4a9 AK |
1814 | /* |
1815 | * High speed pipes may need a hardware ping before they start | |
1816 | */ | |
1817 | if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING) | |
1818 | usbc_hctsiz.s.dopng = 1; | |
1819 | ||
68d435dd AK |
1820 | cvmx_usb_write_csr32(usb, |
1821 | CVMX_USBCX_HCSPLTX(channel, usb->index), | |
1822 | usbc_hcsplt.u32); | |
1823 | cvmx_usb_write_csr32(usb, | |
1824 | CVMX_USBCX_HCTSIZX(channel, usb->index), | |
1825 | usbc_hctsiz.u32); | |
6570b4a9 AK |
1826 | } |
1827 | ||
1828 | /* Setup the Host Channel Characteristics Register */ | |
1829 | { | |
1830 | union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0}; | |
1831 | ||
1832 | /* | |
1833 | * Set the startframe odd/even properly. This is only used for | |
1834 | * periodic | |
1835 | */ | |
1836 | usbc_hcchar.s.oddfrm = usb->frame_number&1; | |
1837 | ||
1838 | /* | |
1839 | * Set the number of back to back packets allowed by this | |
1840 | * endpoint. Split transactions interpret "ec" as the number of | |
1841 | * immediate retries of failure. These retries happen too | |
1842 | * quickly, so we disable these entirely for splits | |
1843 | */ | |
68d435dd | 1844 | if (cvmx_usb_pipe_needs_split(usb, pipe)) |
6570b4a9 AK |
1845 | usbc_hcchar.s.ec = 1; |
1846 | else if (pipe->multi_count < 1) | |
1847 | usbc_hcchar.s.ec = 1; | |
1848 | else if (pipe->multi_count > 3) | |
1849 | usbc_hcchar.s.ec = 3; | |
1850 | else | |
1851 | usbc_hcchar.s.ec = pipe->multi_count; | |
1852 | ||
1853 | /* Set the rest of the endpoint specific settings */ | |
1854 | usbc_hcchar.s.devaddr = pipe->device_addr; | |
1855 | usbc_hcchar.s.eptype = transaction->type; | |
1da69aa9 RO |
1856 | usbc_hcchar.s.lspddev = |
1857 | (pipe->device_speed == CVMX_USB_SPEED_LOW); | |
6570b4a9 AK |
1858 | usbc_hcchar.s.epdir = pipe->transfer_dir; |
1859 | usbc_hcchar.s.epnum = pipe->endpoint_num; | |
1860 | usbc_hcchar.s.mps = pipe->max_packet; | |
68d435dd AK |
1861 | cvmx_usb_write_csr32(usb, |
1862 | CVMX_USBCX_HCCHARX(channel, usb->index), | |
1863 | usbc_hcchar.u32); | |
6570b4a9 AK |
1864 | } |
1865 | ||
1866 | /* Do transaction type specific fixups as needed */ | |
1867 | switch (transaction->type) { | |
1868 | case CVMX_USB_TRANSFER_CONTROL: | |
68d435dd | 1869 | cvmx_usb_start_channel_control(usb, channel, pipe); |
6570b4a9 AK |
1870 | break; |
1871 | case CVMX_USB_TRANSFER_BULK: | |
1872 | case CVMX_USB_TRANSFER_INTERRUPT: | |
1873 | break; | |
1874 | case CVMX_USB_TRANSFER_ISOCHRONOUS: | |
68d435dd | 1875 | if (!cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
1876 | /* |
1877 | * ISO transactions require different PIDs depending on | |
1878 | * direction and how many packets are needed | |
1879 | */ | |
1880 | if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) { | |
1881 | if (pipe->multi_count < 2) /* Need DATA0 */ | |
1da69aa9 RO |
1882 | USB_SET_FIELD32( |
1883 | CVMX_USBCX_HCTSIZX(channel, | |
1884 | usb->index), | |
1885 | union cvmx_usbcx_hctsizx, | |
1886 | pid, 0); | |
6570b4a9 | 1887 | else /* Need MDATA */ |
1da69aa9 RO |
1888 | USB_SET_FIELD32( |
1889 | CVMX_USBCX_HCTSIZX(channel, | |
1890 | usb->index), | |
1891 | union cvmx_usbcx_hctsizx, | |
1892 | pid, 3); | |
6570b4a9 AK |
1893 | } |
1894 | } | |
1895 | break; | |
1896 | } | |
1897 | { | |
1da69aa9 | 1898 | union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = |
68d435dd | 1899 | cvmx_usb_read_csr32(usb, |
1da69aa9 | 1900 | CVMX_USBCX_HCTSIZX(channel, usb->index))}; |
6570b4a9 AK |
1901 | transaction->xfersize = usbc_hctsiz.s.xfersize; |
1902 | transaction->pktcnt = usbc_hctsiz.s.pktcnt; | |
1903 | } | |
1904 | /* Remeber when we start a split transaction */ | |
68d435dd | 1905 | if (cvmx_usb_pipe_needs_split(usb, pipe)) |
6570b4a9 | 1906 | usb->active_split = transaction; |
1da69aa9 RO |
1907 | USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), |
1908 | union cvmx_usbcx_hccharx, chena, 1); | |
6570b4a9 | 1909 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) |
68d435dd | 1910 | cvmx_usb_fill_tx_fifo(usb, channel); |
6570b4a9 AK |
1911 | } |
1912 | ||
1913 | ||
1914 | /** | |
1915 | * Find a pipe that is ready to be scheduled to hardware. | |
cb61c600 | 1916 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1917 | * @list: Pipe list to search |
1918 | * @current_frame: | |
1919 | * Frame counter to use as a time reference. | |
1920 | * | |
1921 | * Returns: Pipe or NULL if none are ready | |
1922 | */ | |
68d435dd | 1923 | static struct cvmx_usb_pipe *cvmx_usb_find_ready_pipe( |
1da69aa9 RO |
1924 | struct cvmx_usb_state *usb, |
1925 | struct list_head *list, | |
1926 | uint64_t current_frame) | |
6570b4a9 | 1927 | { |
4a23ee1b AK |
1928 | struct cvmx_usb_pipe *pipe; |
1929 | ||
1930 | list_for_each_entry(pipe, list, node) { | |
5669601d | 1931 | struct cvmx_usb_transaction *t = |
1da69aa9 RO |
1932 | list_first_entry(&pipe->transactions, typeof(*t), |
1933 | node); | |
5669601d | 1934 | if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && t && |
6570b4a9 | 1935 | (pipe->next_tx_frame <= current_frame) && |
1da69aa9 RO |
1936 | ((pipe->split_sc_frame == -1) || |
1937 | ((((int)current_frame - (int)pipe->split_sc_frame) | |
1938 | & 0x7f) < 0x40)) && | |
5669601d | 1939 | (!usb->active_split || (usb->active_split == t))) { |
20f6b829 | 1940 | prefetch(t); |
6570b4a9 AK |
1941 | return pipe; |
1942 | } | |
6570b4a9 AK |
1943 | } |
1944 | return NULL; | |
1945 | } | |
1946 | ||
1947 | ||
1948 | /** | |
1949 | * Called whenever a pipe might need to be scheduled to the | |
1950 | * hardware. | |
1951 | * | |
cb61c600 | 1952 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
1953 | * @is_sof: True if this schedule was called on a SOF interrupt. |
1954 | */ | |
68d435dd | 1955 | static void cvmx_usb_schedule(struct cvmx_usb_state *usb, int is_sof) |
6570b4a9 AK |
1956 | { |
1957 | int channel; | |
1958 | struct cvmx_usb_pipe *pipe; | |
1959 | int need_sof; | |
1960 | enum cvmx_usb_transfer ttype; | |
1961 | ||
1962 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { | |
1963 | /* | |
1964 | * Without DMA we need to be careful to not schedule something | |
1965 | * at the end of a frame and cause an overrun. | |
1966 | */ | |
e725cef3 | 1967 | union cvmx_usbcx_hfnum hfnum = { |
68d435dd | 1968 | .u32 = cvmx_usb_read_csr32(usb, |
e725cef3 PD |
1969 | CVMX_USBCX_HFNUM(usb->index)) |
1970 | }; | |
1971 | ||
1972 | union cvmx_usbcx_hfir hfir = { | |
68d435dd | 1973 | .u32 = cvmx_usb_read_csr32(usb, |
e725cef3 PD |
1974 | CVMX_USBCX_HFIR(usb->index)) |
1975 | }; | |
f5106435 | 1976 | |
6570b4a9 AK |
1977 | if (hfnum.s.frrem < hfir.s.frint/4) |
1978 | goto done; | |
1979 | } | |
1980 | ||
1981 | while (usb->idle_hardware_channels) { | |
1982 | /* Find an idle channel */ | |
1983 | channel = __fls(usb->idle_hardware_channels); | |
1984 | if (unlikely(channel > 7)) | |
1985 | break; | |
1986 | ||
1987 | /* Find a pipe needing service */ | |
1988 | pipe = NULL; | |
1989 | if (is_sof) { | |
1990 | /* | |
1991 | * Only process periodic pipes on SOF interrupts. This | |
1992 | * way we are sure that the periodic data is sent in the | |
1993 | * beginning of the frame | |
1994 | */ | |
68d435dd | 1995 | pipe = cvmx_usb_find_ready_pipe(usb, |
1da69aa9 RO |
1996 | usb->active_pipes + |
1997 | CVMX_USB_TRANSFER_ISOCHRONOUS, | |
1998 | usb->frame_number); | |
6570b4a9 | 1999 | if (likely(!pipe)) |
68d435dd | 2000 | pipe = cvmx_usb_find_ready_pipe(usb, |
1da69aa9 RO |
2001 | usb->active_pipes + |
2002 | CVMX_USB_TRANSFER_INTERRUPT, | |
2003 | usb->frame_number); | |
6570b4a9 AK |
2004 | } |
2005 | if (likely(!pipe)) { | |
68d435dd | 2006 | pipe = cvmx_usb_find_ready_pipe(usb, |
1da69aa9 RO |
2007 | usb->active_pipes + |
2008 | CVMX_USB_TRANSFER_CONTROL, | |
2009 | usb->frame_number); | |
6570b4a9 | 2010 | if (likely(!pipe)) |
68d435dd | 2011 | pipe = cvmx_usb_find_ready_pipe(usb, |
1da69aa9 RO |
2012 | usb->active_pipes + |
2013 | CVMX_USB_TRANSFER_BULK, | |
2014 | usb->frame_number); | |
6570b4a9 AK |
2015 | } |
2016 | if (!pipe) | |
2017 | break; | |
2018 | ||
68d435dd | 2019 | cvmx_usb_start_channel(usb, channel, pipe); |
6570b4a9 AK |
2020 | } |
2021 | ||
2022 | done: | |
2023 | /* | |
2024 | * Only enable SOF interrupts when we have transactions pending in the | |
2025 | * future that might need to be scheduled | |
2026 | */ | |
2027 | need_sof = 0; | |
1da69aa9 RO |
2028 | for (ttype = CVMX_USB_TRANSFER_CONTROL; |
2029 | ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) { | |
4a23ee1b | 2030 | list_for_each_entry(pipe, &usb->active_pipes[ttype], node) { |
6570b4a9 AK |
2031 | if (pipe->next_tx_frame > usb->frame_number) { |
2032 | need_sof = 1; | |
2033 | break; | |
2034 | } | |
6570b4a9 AK |
2035 | } |
2036 | } | |
1da69aa9 RO |
2037 | USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), |
2038 | union cvmx_usbcx_gintmsk, sofmsk, need_sof); | |
6570b4a9 AK |
2039 | } |
2040 | ||
75ee5124 AK |
2041 | static void octeon_usb_urb_complete_callback(struct cvmx_usb_state *usb, |
2042 | enum cvmx_usb_complete status, | |
60f81507 | 2043 | struct cvmx_usb_pipe *pipe, |
3e1674c0 AK |
2044 | struct cvmx_usb_transaction |
2045 | *transaction, | |
75ee5124 | 2046 | int bytes_transferred, |
0cce1004 | 2047 | struct urb *urb) |
75ee5124 AK |
2048 | { |
2049 | struct octeon_hcd *priv = cvmx_usb_to_octeon(usb); | |
2050 | struct usb_hcd *hcd = octeon_to_hcd(priv); | |
2051 | struct device *dev = hcd->self.controller; | |
75ee5124 | 2052 | |
8dcf4ece AK |
2053 | if (likely(status == CVMX_USB_COMPLETE_SUCCESS)) |
2054 | urb->actual_length = bytes_transferred; | |
2055 | else | |
2056 | urb->actual_length = 0; | |
2057 | ||
75ee5124 AK |
2058 | urb->hcpriv = NULL; |
2059 | ||
75ee5124 AK |
2060 | /* For Isochronous transactions we need to update the URB packet status |
2061 | list from data in our private copy */ | |
2062 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
2063 | int i; | |
2064 | /* | |
2065 | * The pointer to the private list is stored in the setup_packet | |
2066 | * field. | |
2067 | */ | |
2068 | struct cvmx_usb_iso_packet *iso_packet = | |
2069 | (struct cvmx_usb_iso_packet *) urb->setup_packet; | |
2070 | /* Recalculate the transfer size by adding up each packet */ | |
2071 | urb->actual_length = 0; | |
2072 | for (i = 0; i < urb->number_of_packets; i++) { | |
1da69aa9 RO |
2073 | if (iso_packet[i].status == |
2074 | CVMX_USB_COMPLETE_SUCCESS) { | |
75ee5124 | 2075 | urb->iso_frame_desc[i].status = 0; |
1da69aa9 RO |
2076 | urb->iso_frame_desc[i].actual_length = |
2077 | iso_packet[i].length; | |
2078 | urb->actual_length += | |
2079 | urb->iso_frame_desc[i].actual_length; | |
75ee5124 | 2080 | } else { |
3e1674c0 | 2081 | dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n", |
75ee5124 | 2082 | i, urb->number_of_packets, |
60f81507 | 2083 | iso_packet[i].status, pipe, |
3e1674c0 | 2084 | transaction, iso_packet[i].length); |
75ee5124 AK |
2085 | urb->iso_frame_desc[i].status = -EREMOTEIO; |
2086 | } | |
2087 | } | |
2088 | /* Free the private list now that we don't need it anymore */ | |
2089 | kfree(iso_packet); | |
2090 | urb->setup_packet = NULL; | |
2091 | } | |
6570b4a9 | 2092 | |
75ee5124 AK |
2093 | switch (status) { |
2094 | case CVMX_USB_COMPLETE_SUCCESS: | |
2095 | urb->status = 0; | |
2096 | break; | |
2097 | case CVMX_USB_COMPLETE_CANCEL: | |
2098 | if (urb->status == 0) | |
2099 | urb->status = -ENOENT; | |
2100 | break; | |
2101 | case CVMX_USB_COMPLETE_STALL: | |
3e1674c0 AK |
2102 | dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n", |
2103 | pipe, transaction, bytes_transferred); | |
75ee5124 AK |
2104 | urb->status = -EPIPE; |
2105 | break; | |
2106 | case CVMX_USB_COMPLETE_BABBLEERR: | |
3e1674c0 AK |
2107 | dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n", |
2108 | pipe, transaction, bytes_transferred); | |
75ee5124 AK |
2109 | urb->status = -EPIPE; |
2110 | break; | |
2111 | case CVMX_USB_COMPLETE_SHORT: | |
3e1674c0 AK |
2112 | dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n", |
2113 | pipe, transaction, bytes_transferred); | |
75ee5124 AK |
2114 | urb->status = -EREMOTEIO; |
2115 | break; | |
2116 | case CVMX_USB_COMPLETE_ERROR: | |
2117 | case CVMX_USB_COMPLETE_XACTERR: | |
2118 | case CVMX_USB_COMPLETE_DATATGLERR: | |
2119 | case CVMX_USB_COMPLETE_FRAMEERR: | |
3e1674c0 AK |
2120 | dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n", |
2121 | status, pipe, transaction, bytes_transferred); | |
75ee5124 AK |
2122 | urb->status = -EPROTO; |
2123 | break; | |
2124 | } | |
e5b90898 | 2125 | usb_hcd_unlink_urb_from_ep(octeon_to_hcd(priv), urb); |
75ee5124 AK |
2126 | spin_unlock(&priv->lock); |
2127 | usb_hcd_giveback_urb(octeon_to_hcd(priv), urb, urb->status); | |
2128 | spin_lock(&priv->lock); | |
6570b4a9 AK |
2129 | } |
2130 | ||
6570b4a9 AK |
2131 | /** |
2132 | * Signal the completion of a transaction and free it. The | |
2133 | * transaction will be removed from the pipe transaction list. | |
2134 | * | |
cb61c600 | 2135 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
2136 | * @pipe: Pipe the transaction is on |
2137 | * @transaction: | |
2138 | * Transaction that completed | |
2139 | * @complete_code: | |
2140 | * Completion code | |
2141 | */ | |
68d435dd AK |
2142 | static void cvmx_usb_perform_complete(struct cvmx_usb_state *usb, |
2143 | struct cvmx_usb_pipe *pipe, | |
2144 | struct cvmx_usb_transaction *transaction, | |
2145 | enum cvmx_usb_complete complete_code) | |
6570b4a9 AK |
2146 | { |
2147 | /* If this was a split then clear our split in progress marker */ | |
2148 | if (usb->active_split == transaction) | |
2149 | usb->active_split = NULL; | |
2150 | ||
2151 | /* | |
2152 | * Isochronous transactions need extra processing as they might not be | |
2153 | * done after a single data transfer | |
2154 | */ | |
2155 | if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) { | |
2156 | /* Update the number of bytes transferred in this ISO packet */ | |
2157 | transaction->iso_packets[0].length = transaction->actual_bytes; | |
2158 | transaction->iso_packets[0].status = complete_code; | |
2159 | ||
2160 | /* | |
2161 | * If there are more ISOs pending and we succeeded, schedule the | |
2162 | * next one | |
2163 | */ | |
1da69aa9 RO |
2164 | if ((transaction->iso_number_packets > 1) && |
2165 | (complete_code == CVMX_USB_COMPLETE_SUCCESS)) { | |
6570b4a9 AK |
2166 | /* No bytes transferred for this packet as of yet */ |
2167 | transaction->actual_bytes = 0; | |
2168 | /* One less ISO waiting to transfer */ | |
2169 | transaction->iso_number_packets--; | |
2170 | /* Increment to the next location in our packet array */ | |
2171 | transaction->iso_packets++; | |
2172 | transaction->stage = CVMX_USB_STAGE_NON_CONTROL; | |
15ef0cc1 | 2173 | return; |
6570b4a9 AK |
2174 | } |
2175 | } | |
2176 | ||
2177 | /* Remove the transaction from the pipe list */ | |
5669601d AK |
2178 | list_del(&transaction->node); |
2179 | if (list_empty(&pipe->transactions)) | |
4a23ee1b | 2180 | list_move_tail(&pipe->node, &usb->idle_pipes); |
60f81507 | 2181 | octeon_usb_urb_complete_callback(usb, complete_code, pipe, |
3e1674c0 | 2182 | transaction, |
75ee5124 | 2183 | transaction->actual_bytes, |
0cce1004 | 2184 | transaction->urb); |
a2dfef06 | 2185 | kfree(transaction); |
6570b4a9 AK |
2186 | } |
2187 | ||
2188 | ||
2189 | /** | |
2190 | * Submit a usb transaction to a pipe. Called for all types | |
2191 | * of transactions. | |
2192 | * | |
2193 | * @usb: | |
60f81507 | 2194 | * @pipe: Which pipe to submit to. |
6570b4a9 AK |
2195 | * @type: Transaction type |
2196 | * @buffer: User buffer for the transaction | |
2197 | * @buffer_length: | |
2198 | * User buffer's length in bytes | |
2199 | * @control_header: | |
2200 | * For control transactions, the 8 byte standard header | |
2201 | * @iso_start_frame: | |
2202 | * For ISO transactions, the start frame | |
2203 | * @iso_number_packets: | |
2204 | * For ISO, the number of packet in the transaction. | |
2205 | * @iso_packets: | |
2206 | * A description of each ISO packet | |
0cce1004 | 2207 | * @urb: URB for the callback |
6570b4a9 | 2208 | * |
3e1674c0 | 2209 | * Returns: Transaction or NULL on failure. |
6570b4a9 | 2210 | */ |
68d435dd | 2211 | static struct cvmx_usb_transaction *cvmx_usb_submit_transaction( |
1da69aa9 RO |
2212 | struct cvmx_usb_state *usb, |
2213 | struct cvmx_usb_pipe *pipe, | |
2214 | enum cvmx_usb_transfer type, | |
2215 | uint64_t buffer, | |
2216 | int buffer_length, | |
2217 | uint64_t control_header, | |
2218 | int iso_start_frame, | |
2219 | int iso_number_packets, | |
2220 | struct cvmx_usb_iso_packet *iso_packets, | |
2221 | struct urb *urb) | |
6570b4a9 | 2222 | { |
6570b4a9 | 2223 | struct cvmx_usb_transaction *transaction; |
6570b4a9 | 2224 | |
6570b4a9 | 2225 | if (unlikely(pipe->transfer_type != type)) |
3e1674c0 | 2226 | return NULL; |
6570b4a9 | 2227 | |
a2dfef06 | 2228 | transaction = kzalloc(sizeof(*transaction), GFP_ATOMIC); |
6570b4a9 | 2229 | if (unlikely(!transaction)) |
3e1674c0 | 2230 | return NULL; |
6570b4a9 AK |
2231 | |
2232 | transaction->type = type; | |
2233 | transaction->buffer = buffer; | |
2234 | transaction->buffer_length = buffer_length; | |
2235 | transaction->control_header = control_header; | |
2236 | /* FIXME: This is not used, implement it. */ | |
2237 | transaction->iso_start_frame = iso_start_frame; | |
2238 | transaction->iso_number_packets = iso_number_packets; | |
2239 | transaction->iso_packets = iso_packets; | |
0cce1004 | 2240 | transaction->urb = urb; |
6570b4a9 AK |
2241 | if (transaction->type == CVMX_USB_TRANSFER_CONTROL) |
2242 | transaction->stage = CVMX_USB_STAGE_SETUP; | |
2243 | else | |
2244 | transaction->stage = CVMX_USB_STAGE_NON_CONTROL; | |
2245 | ||
5669601d AK |
2246 | if (!list_empty(&pipe->transactions)) { |
2247 | list_add_tail(&transaction->node, &pipe->transactions); | |
6570b4a9 | 2248 | } else { |
5669601d | 2249 | list_add_tail(&transaction->node, &pipe->transactions); |
4a23ee1b AK |
2250 | list_move_tail(&pipe->node, |
2251 | &usb->active_pipes[pipe->transfer_type]); | |
6570b4a9 | 2252 | |
5669601d AK |
2253 | /* |
2254 | * We may need to schedule the pipe if this was the head of the | |
2255 | * pipe. | |
2256 | */ | |
68d435dd | 2257 | cvmx_usb_schedule(usb, 0); |
5669601d | 2258 | } |
6570b4a9 | 2259 | |
3e1674c0 | 2260 | return transaction; |
6570b4a9 AK |
2261 | } |
2262 | ||
2263 | ||
2264 | /** | |
2265 | * Call to submit a USB Bulk transfer to a pipe. | |
2266 | * | |
cb61c600 | 2267 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2268 | * @pipe: Handle to the pipe for the transfer. |
9ccca707 | 2269 | * @urb: URB. |
6570b4a9 | 2270 | * |
3e1674c0 | 2271 | * Returns: A submitted transaction or NULL on failure. |
6570b4a9 | 2272 | */ |
1da69aa9 RO |
2273 | static struct cvmx_usb_transaction *cvmx_usb_submit_bulk( |
2274 | struct cvmx_usb_state *usb, | |
2275 | struct cvmx_usb_pipe *pipe, | |
2276 | struct urb *urb) | |
6570b4a9 | 2277 | { |
68d435dd AK |
2278 | return cvmx_usb_submit_transaction(usb, pipe, CVMX_USB_TRANSFER_BULK, |
2279 | urb->transfer_dma, | |
2280 | urb->transfer_buffer_length, | |
2281 | 0, /* control_header */ | |
2282 | 0, /* iso_start_frame */ | |
2283 | 0, /* iso_number_packets */ | |
2284 | NULL, /* iso_packets */ | |
2285 | urb); | |
6570b4a9 AK |
2286 | } |
2287 | ||
2288 | ||
2289 | /** | |
2290 | * Call to submit a USB Interrupt transfer to a pipe. | |
2291 | * | |
cb61c600 | 2292 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2293 | * @pipe: Handle to the pipe for the transfer. |
0cce1004 | 2294 | * @urb: URB returned when the callback is called. |
6570b4a9 | 2295 | * |
3e1674c0 | 2296 | * Returns: A submitted transaction or NULL on failure. |
6570b4a9 | 2297 | */ |
1da69aa9 RO |
2298 | static struct cvmx_usb_transaction *cvmx_usb_submit_interrupt( |
2299 | struct cvmx_usb_state *usb, | |
2300 | struct cvmx_usb_pipe *pipe, | |
2301 | struct urb *urb) | |
6570b4a9 | 2302 | { |
68d435dd AK |
2303 | return cvmx_usb_submit_transaction(usb, pipe, |
2304 | CVMX_USB_TRANSFER_INTERRUPT, | |
2305 | urb->transfer_dma, | |
2306 | urb->transfer_buffer_length, | |
2307 | 0, /* control_header */ | |
2308 | 0, /* iso_start_frame */ | |
2309 | 0, /* iso_number_packets */ | |
2310 | NULL, /* iso_packets */ | |
2311 | urb); | |
6570b4a9 AK |
2312 | } |
2313 | ||
2314 | ||
2315 | /** | |
2316 | * Call to submit a USB Control transfer to a pipe. | |
2317 | * | |
cb61c600 | 2318 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2319 | * @pipe: Handle to the pipe for the transfer. |
2ae09e87 | 2320 | * @urb: URB. |
6570b4a9 | 2321 | * |
3e1674c0 | 2322 | * Returns: A submitted transaction or NULL on failure. |
6570b4a9 | 2323 | */ |
1da69aa9 RO |
2324 | static struct cvmx_usb_transaction *cvmx_usb_submit_control( |
2325 | struct cvmx_usb_state *usb, | |
2326 | struct cvmx_usb_pipe *pipe, | |
2327 | struct urb *urb) | |
6570b4a9 | 2328 | { |
2ae09e87 AK |
2329 | int buffer_length = urb->transfer_buffer_length; |
2330 | uint64_t control_header = urb->setup_dma; | |
e301dfb2 | 2331 | struct usb_ctrlrequest *header = cvmx_phys_to_ptr(control_header); |
6570b4a9 | 2332 | |
96ee2cc8 | 2333 | if ((header->bRequestType & USB_DIR_IN) == 0) |
e301dfb2 | 2334 | buffer_length = le16_to_cpu(header->wLength); |
6570b4a9 | 2335 | |
68d435dd AK |
2336 | return cvmx_usb_submit_transaction(usb, pipe, |
2337 | CVMX_USB_TRANSFER_CONTROL, | |
2338 | urb->transfer_dma, buffer_length, | |
2339 | control_header, | |
2340 | 0, /* iso_start_frame */ | |
2341 | 0, /* iso_number_packets */ | |
2342 | NULL, /* iso_packets */ | |
2343 | urb); | |
6570b4a9 AK |
2344 | } |
2345 | ||
2346 | ||
2347 | /** | |
2348 | * Call to submit a USB Isochronous transfer to a pipe. | |
2349 | * | |
cb61c600 | 2350 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2351 | * @pipe: Handle to the pipe for the transfer. |
0cce1004 | 2352 | * @urb: URB returned when the callback is called. |
6570b4a9 | 2353 | * |
3e1674c0 | 2354 | * Returns: A submitted transaction or NULL on failure. |
6570b4a9 | 2355 | */ |
1da69aa9 RO |
2356 | static struct cvmx_usb_transaction *cvmx_usb_submit_isochronous( |
2357 | struct cvmx_usb_state *usb, | |
2358 | struct cvmx_usb_pipe *pipe, | |
2359 | struct urb *urb) | |
6570b4a9 | 2360 | { |
e16b5e3f | 2361 | struct cvmx_usb_iso_packet *packets; |
6570b4a9 | 2362 | |
e16b5e3f | 2363 | packets = (struct cvmx_usb_iso_packet *) urb->setup_packet; |
68d435dd AK |
2364 | return cvmx_usb_submit_transaction(usb, pipe, |
2365 | CVMX_USB_TRANSFER_ISOCHRONOUS, | |
2366 | urb->transfer_dma, | |
2367 | urb->transfer_buffer_length, | |
2368 | 0, /* control_header */ | |
2369 | urb->start_frame, | |
2370 | urb->number_of_packets, | |
2371 | packets, urb); | |
6570b4a9 AK |
2372 | } |
2373 | ||
2374 | ||
2375 | /** | |
2376 | * Cancel one outstanding request in a pipe. Canceling a request | |
2377 | * can fail if the transaction has already completed before cancel | |
2378 | * is called. Even after a successful cancel call, it may take | |
2379 | * a frame or two for the cvmx_usb_poll() function to call the | |
2380 | * associated callback. | |
2381 | * | |
cb61c600 | 2382 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2383 | * @pipe: Pipe to cancel requests in. |
3e1674c0 | 2384 | * @transaction: Transaction to cancel, returned by the submit function. |
6570b4a9 AK |
2385 | * |
2386 | * Returns: 0 or a negative error code. | |
2387 | */ | |
60f81507 AK |
2388 | static int cvmx_usb_cancel(struct cvmx_usb_state *usb, |
2389 | struct cvmx_usb_pipe *pipe, | |
3e1674c0 | 2390 | struct cvmx_usb_transaction *transaction) |
6570b4a9 | 2391 | { |
6570b4a9 AK |
2392 | /* |
2393 | * If the transaction is the HEAD of the queue and scheduled. We need to | |
2394 | * treat it special | |
2395 | */ | |
5669601d AK |
2396 | if (list_first_entry(&pipe->transactions, typeof(*transaction), node) == |
2397 | transaction && (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) { | |
6570b4a9 AK |
2398 | union cvmx_usbcx_hccharx usbc_hcchar; |
2399 | ||
2400 | usb->pipe_for_channel[pipe->channel] = NULL; | |
2401 | pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED; | |
2402 | ||
2403 | CVMX_SYNCW; | |
2404 | ||
68d435dd | 2405 | usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 2406 | CVMX_USBCX_HCCHARX(pipe->channel, usb->index)); |
6570b4a9 AK |
2407 | /* |
2408 | * If the channel isn't enabled then the transaction already | |
2409 | * completed. | |
2410 | */ | |
2411 | if (usbc_hcchar.s.chena) { | |
2412 | usbc_hcchar.s.chdis = 1; | |
68d435dd | 2413 | cvmx_usb_write_csr32(usb, |
1da69aa9 RO |
2414 | CVMX_USBCX_HCCHARX(pipe->channel, |
2415 | usb->index), | |
2416 | usbc_hcchar.u32); | |
6570b4a9 AK |
2417 | } |
2418 | } | |
68d435dd AK |
2419 | cvmx_usb_perform_complete(usb, pipe, transaction, |
2420 | CVMX_USB_COMPLETE_CANCEL); | |
6570b4a9 AK |
2421 | return 0; |
2422 | } | |
2423 | ||
2424 | ||
2425 | /** | |
2426 | * Cancel all outstanding requests in a pipe. Logically all this | |
2427 | * does is call cvmx_usb_cancel() in a loop. | |
2428 | * | |
cb61c600 | 2429 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2430 | * @pipe: Pipe to cancel requests in. |
6570b4a9 AK |
2431 | * |
2432 | * Returns: 0 or a negative error code. | |
2433 | */ | |
60f81507 AK |
2434 | static int cvmx_usb_cancel_all(struct cvmx_usb_state *usb, |
2435 | struct cvmx_usb_pipe *pipe) | |
6570b4a9 | 2436 | { |
5669601d AK |
2437 | struct cvmx_usb_transaction *transaction, *next; |
2438 | ||
6570b4a9 | 2439 | /* Simply loop through and attempt to cancel each transaction */ |
5669601d AK |
2440 | list_for_each_entry_safe(transaction, next, &pipe->transactions, node) { |
2441 | int result = cvmx_usb_cancel(usb, pipe, transaction); | |
f5106435 | 2442 | |
6570b4a9 AK |
2443 | if (unlikely(result != 0)) |
2444 | return result; | |
2445 | } | |
2446 | return 0; | |
2447 | } | |
2448 | ||
2449 | ||
2450 | /** | |
2451 | * Close a pipe created with cvmx_usb_open_pipe(). | |
2452 | * | |
cb61c600 | 2453 | * @usb: USB device state populated by cvmx_usb_initialize(). |
60f81507 | 2454 | * @pipe: Pipe to close. |
6570b4a9 AK |
2455 | * |
2456 | * Returns: 0 or a negative error code. EBUSY is returned if the pipe has | |
2457 | * outstanding transfers. | |
2458 | */ | |
60f81507 AK |
2459 | static int cvmx_usb_close_pipe(struct cvmx_usb_state *usb, |
2460 | struct cvmx_usb_pipe *pipe) | |
6570b4a9 | 2461 | { |
6570b4a9 | 2462 | /* Fail if the pipe has pending transactions */ |
5669601d | 2463 | if (!list_empty(&pipe->transactions)) |
6570b4a9 AK |
2464 | return -EBUSY; |
2465 | ||
4a23ee1b | 2466 | list_del(&pipe->node); |
d2695a8a | 2467 | kfree(pipe); |
6570b4a9 AK |
2468 | |
2469 | return 0; | |
2470 | } | |
2471 | ||
6570b4a9 AK |
2472 | /** |
2473 | * Get the current USB protocol level frame number. The frame | |
2474 | * number is always in the range of 0-0x7ff. | |
2475 | * | |
cb61c600 | 2476 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
2477 | * |
2478 | * Returns: USB frame number | |
2479 | */ | |
cb61c600 | 2480 | static int cvmx_usb_get_frame_number(struct cvmx_usb_state *usb) |
6570b4a9 AK |
2481 | { |
2482 | int frame_number; | |
6570b4a9 AK |
2483 | union cvmx_usbcx_hfnum usbc_hfnum; |
2484 | ||
68d435dd | 2485 | usbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index)); |
6570b4a9 AK |
2486 | frame_number = usbc_hfnum.s.frnum; |
2487 | ||
2488 | return frame_number; | |
2489 | } | |
2490 | ||
2491 | ||
2492 | /** | |
2493 | * Poll a channel for status | |
2494 | * | |
2495 | * @usb: USB device | |
2496 | * @channel: Channel to poll | |
2497 | * | |
2498 | * Returns: Zero on success | |
2499 | */ | |
68d435dd | 2500 | static int cvmx_usb_poll_channel(struct cvmx_usb_state *usb, int channel) |
6570b4a9 | 2501 | { |
ba0b8e42 AK |
2502 | struct octeon_hcd *priv = cvmx_usb_to_octeon(usb); |
2503 | struct usb_hcd *hcd = octeon_to_hcd(priv); | |
2504 | struct device *dev = hcd->self.controller; | |
6570b4a9 AK |
2505 | union cvmx_usbcx_hcintx usbc_hcint; |
2506 | union cvmx_usbcx_hctsizx usbc_hctsiz; | |
2507 | union cvmx_usbcx_hccharx usbc_hcchar; | |
2508 | struct cvmx_usb_pipe *pipe; | |
2509 | struct cvmx_usb_transaction *transaction; | |
2510 | int bytes_this_transfer; | |
2511 | int bytes_in_last_packet; | |
2512 | int packets_processed; | |
2513 | int buffer_space_left; | |
2514 | ||
2515 | /* Read the interrupt status bits for the channel */ | |
68d435dd AK |
2516 | usbc_hcint.u32 = cvmx_usb_read_csr32(usb, |
2517 | CVMX_USBCX_HCINTX(channel, usb->index)); | |
6570b4a9 AK |
2518 | |
2519 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { | |
68d435dd | 2520 | usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 2521 | CVMX_USBCX_HCCHARX(channel, usb->index)); |
6570b4a9 AK |
2522 | |
2523 | if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) { | |
2524 | /* | |
2525 | * There seems to be a bug in CN31XX which can cause | |
2526 | * interrupt IN transfers to get stuck until we do a | |
2527 | * write of HCCHARX without changing things | |
2528 | */ | |
68d435dd | 2529 | cvmx_usb_write_csr32(usb, |
1da69aa9 RO |
2530 | CVMX_USBCX_HCCHARX(channel, |
2531 | usb->index), | |
2532 | usbc_hcchar.u32); | |
6570b4a9 AK |
2533 | return 0; |
2534 | } | |
2535 | ||
2536 | /* | |
2537 | * In non DMA mode the channels don't halt themselves. We need | |
2538 | * to manually disable channels that are left running | |
2539 | */ | |
2540 | if (!usbc_hcint.s.chhltd) { | |
2541 | if (usbc_hcchar.s.chena) { | |
2542 | union cvmx_usbcx_hcintmskx hcintmsk; | |
2543 | /* Disable all interrupts except CHHLTD */ | |
2544 | hcintmsk.u32 = 0; | |
2545 | hcintmsk.s.chhltdmsk = 1; | |
68d435dd | 2546 | cvmx_usb_write_csr32(usb, |
1da69aa9 RO |
2547 | CVMX_USBCX_HCINTMSKX(channel, |
2548 | usb->index), | |
2549 | hcintmsk.u32); | |
6570b4a9 | 2550 | usbc_hcchar.s.chdis = 1; |
68d435dd | 2551 | cvmx_usb_write_csr32(usb, |
1da69aa9 RO |
2552 | CVMX_USBCX_HCCHARX(channel, |
2553 | usb->index), | |
2554 | usbc_hcchar.u32); | |
6570b4a9 AK |
2555 | return 0; |
2556 | } else if (usbc_hcint.s.xfercompl) { | |
2557 | /* | |
2558 | * Successful IN/OUT with transfer complete. | |
2559 | * Channel halt isn't needed. | |
2560 | */ | |
2561 | } else { | |
ba0b8e42 AK |
2562 | dev_err(dev, "USB%d: Channel %d interrupt without halt\n", |
2563 | usb->index, channel); | |
6570b4a9 AK |
2564 | return 0; |
2565 | } | |
2566 | } | |
2567 | } else { | |
2568 | /* | |
2569 | * There is are no interrupts that we need to process when the | |
2570 | * channel is still running | |
2571 | */ | |
2572 | if (!usbc_hcint.s.chhltd) | |
2573 | return 0; | |
2574 | } | |
2575 | ||
2576 | /* Disable the channel interrupts now that it is done */ | |
68d435dd | 2577 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0); |
6570b4a9 AK |
2578 | usb->idle_hardware_channels |= (1<<channel); |
2579 | ||
2580 | /* Make sure this channel is tied to a valid pipe */ | |
2581 | pipe = usb->pipe_for_channel[channel]; | |
20f6b829 | 2582 | prefetch(pipe); |
6570b4a9 AK |
2583 | if (!pipe) |
2584 | return 0; | |
1da69aa9 RO |
2585 | transaction = list_first_entry(&pipe->transactions, |
2586 | typeof(*transaction), | |
5669601d | 2587 | node); |
20f6b829 | 2588 | prefetch(transaction); |
6570b4a9 AK |
2589 | |
2590 | /* | |
2591 | * Disconnect this pipe from the HW channel. Later the schedule | |
2592 | * function will figure out which pipe needs to go | |
2593 | */ | |
2594 | usb->pipe_for_channel[channel] = NULL; | |
2595 | pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED; | |
2596 | ||
2597 | /* | |
2598 | * Read the channel config info so we can figure out how much data | |
1cf3273d | 2599 | * transferred |
6570b4a9 | 2600 | */ |
68d435dd | 2601 | usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 2602 | CVMX_USBCX_HCCHARX(channel, usb->index)); |
68d435dd | 2603 | usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, |
1da69aa9 | 2604 | CVMX_USBCX_HCTSIZX(channel, usb->index)); |
6570b4a9 AK |
2605 | |
2606 | /* | |
2607 | * Calculating the number of bytes successfully transferred is dependent | |
2608 | * on the transfer direction | |
2609 | */ | |
2610 | packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt; | |
2611 | if (usbc_hcchar.s.epdir) { | |
2612 | /* | |
2613 | * IN transactions are easy. For every byte received the | |
2614 | * hardware decrements xfersize. All we need to do is subtract | |
2615 | * the current value of xfersize from its starting value and we | |
2616 | * know how many bytes were written to the buffer | |
2617 | */ | |
1da69aa9 RO |
2618 | bytes_this_transfer = transaction->xfersize - |
2619 | usbc_hctsiz.s.xfersize; | |
6570b4a9 AK |
2620 | } else { |
2621 | /* | |
2622 | * OUT transaction don't decrement xfersize. Instead pktcnt is | |
2623 | * decremented on every successful packet send. The hardware | |
2624 | * does this when it receives an ACK, or NYET. If it doesn't | |
2625 | * receive one of these responses pktcnt doesn't change | |
2626 | */ | |
2627 | bytes_this_transfer = packets_processed * usbc_hcchar.s.mps; | |
2628 | /* | |
2629 | * The last packet may not be a full transfer if we didn't have | |
2630 | * enough data | |
2631 | */ | |
2632 | if (bytes_this_transfer > transaction->xfersize) | |
2633 | bytes_this_transfer = transaction->xfersize; | |
2634 | } | |
2635 | /* Figure out how many bytes were in the last packet of the transfer */ | |
2636 | if (packets_processed) | |
1da69aa9 RO |
2637 | bytes_in_last_packet = bytes_this_transfer - |
2638 | (packets_processed - 1) * usbc_hcchar.s.mps; | |
6570b4a9 AK |
2639 | else |
2640 | bytes_in_last_packet = bytes_this_transfer; | |
2641 | ||
2642 | /* | |
2643 | * As a special case, setup transactions output the setup header, not | |
2644 | * the user's data. For this reason we don't count setup data as bytes | |
2645 | * transferred | |
2646 | */ | |
2647 | if ((transaction->stage == CVMX_USB_STAGE_SETUP) || | |
2648 | (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE)) | |
2649 | bytes_this_transfer = 0; | |
2650 | ||
2651 | /* | |
2652 | * Add the bytes transferred to the running total. It is important that | |
2653 | * bytes_this_transfer doesn't count any data that needs to be | |
2654 | * retransmitted | |
2655 | */ | |
2656 | transaction->actual_bytes += bytes_this_transfer; | |
2657 | if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) | |
1da69aa9 RO |
2658 | buffer_space_left = transaction->iso_packets[0].length - |
2659 | transaction->actual_bytes; | |
6570b4a9 | 2660 | else |
1da69aa9 RO |
2661 | buffer_space_left = transaction->buffer_length - |
2662 | transaction->actual_bytes; | |
6570b4a9 AK |
2663 | |
2664 | /* | |
2665 | * We need to remember the PID toggle state for the next transaction. | |
2666 | * The hardware already updated it for the next transaction | |
2667 | */ | |
2668 | pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0); | |
2669 | ||
2670 | /* | |
2671 | * For high speed bulk out, assume the next transaction will need to do | |
2672 | * a ping before proceeding. If this isn't true the ACK processing below | |
2673 | * will clear this flag | |
2674 | */ | |
2675 | if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) && | |
2676 | (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) && | |
2677 | (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT)) | |
2678 | pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING; | |
2679 | ||
2680 | if (usbc_hcint.s.stall) { | |
2681 | /* | |
2682 | * STALL as a response means this transaction cannot be | |
2683 | * completed because the device can't process transactions. Tell | |
2684 | * the user. Any data that was transferred will be counted on | |
2685 | * the actual bytes transferred | |
2686 | */ | |
2687 | pipe->pid_toggle = 0; | |
68d435dd AK |
2688 | cvmx_usb_perform_complete(usb, pipe, transaction, |
2689 | CVMX_USB_COMPLETE_STALL); | |
6570b4a9 AK |
2690 | } else if (usbc_hcint.s.xacterr) { |
2691 | /* | |
2692 | * We know at least one packet worked if we get a ACK or NAK. | |
2693 | * Reset the retry counter | |
2694 | */ | |
2695 | if (usbc_hcint.s.nak || usbc_hcint.s.ack) | |
2696 | transaction->retries = 0; | |
2697 | transaction->retries++; | |
2698 | if (transaction->retries > MAX_RETRIES) { | |
2699 | /* | |
2700 | * XactErr as a response means the device signaled | |
2701 | * something wrong with the transfer. For example, PID | |
2702 | * toggle errors cause these | |
2703 | */ | |
68d435dd AK |
2704 | cvmx_usb_perform_complete(usb, pipe, transaction, |
2705 | CVMX_USB_COMPLETE_XACTERR); | |
6570b4a9 AK |
2706 | } else { |
2707 | /* | |
2708 | * If this was a split then clear our split in progress | |
2709 | * marker | |
2710 | */ | |
2711 | if (usb->active_split == transaction) | |
2712 | usb->active_split = NULL; | |
2713 | /* | |
2714 | * Rewind to the beginning of the transaction by anding | |
2715 | * off the split complete bit | |
2716 | */ | |
2717 | transaction->stage &= ~1; | |
2718 | pipe->split_sc_frame = -1; | |
2719 | pipe->next_tx_frame += pipe->interval; | |
2720 | if (pipe->next_tx_frame < usb->frame_number) | |
1da69aa9 RO |
2721 | pipe->next_tx_frame = |
2722 | usb->frame_number + pipe->interval - | |
2723 | (usb->frame_number - | |
2724 | pipe->next_tx_frame) % pipe->interval; | |
6570b4a9 AK |
2725 | } |
2726 | } else if (usbc_hcint.s.bblerr) { | |
2727 | /* Babble Error (BblErr) */ | |
68d435dd AK |
2728 | cvmx_usb_perform_complete(usb, pipe, transaction, |
2729 | CVMX_USB_COMPLETE_BABBLEERR); | |
6570b4a9 | 2730 | } else if (usbc_hcint.s.datatglerr) { |
d8c39d3f | 2731 | /* Data toggle error */ |
68d435dd AK |
2732 | cvmx_usb_perform_complete(usb, pipe, transaction, |
2733 | CVMX_USB_COMPLETE_DATATGLERR); | |
6570b4a9 AK |
2734 | } else if (usbc_hcint.s.nyet) { |
2735 | /* | |
2736 | * NYET as a response is only allowed in three cases: as a | |
2737 | * response to a ping, as a response to a split transaction, and | |
2738 | * as a response to a bulk out. The ping case is handled by | |
2739 | * hardware, so we only have splits and bulk out | |
2740 | */ | |
68d435dd | 2741 | if (!cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
2742 | transaction->retries = 0; |
2743 | /* | |
2744 | * If there is more data to go then we need to try | |
2745 | * again. Otherwise this transaction is complete | |
2746 | */ | |
1da69aa9 RO |
2747 | if ((buffer_space_left == 0) || |
2748 | (bytes_in_last_packet < pipe->max_packet)) | |
68d435dd | 2749 | cvmx_usb_perform_complete(usb, pipe, |
1da69aa9 RO |
2750 | transaction, |
2751 | CVMX_USB_COMPLETE_SUCCESS); | |
6570b4a9 AK |
2752 | } else { |
2753 | /* | |
2754 | * Split transactions retry the split complete 4 times | |
2755 | * then rewind to the start split and do the entire | |
2756 | * transactions again | |
2757 | */ | |
2758 | transaction->retries++; | |
2759 | if ((transaction->retries & 0x3) == 0) { | |
2760 | /* | |
2761 | * Rewind to the beginning of the transaction by | |
2762 | * anding off the split complete bit | |
2763 | */ | |
2764 | transaction->stage &= ~1; | |
2765 | pipe->split_sc_frame = -1; | |
2766 | } | |
2767 | } | |
2768 | } else if (usbc_hcint.s.ack) { | |
2769 | transaction->retries = 0; | |
2770 | /* | |
2771 | * The ACK bit can only be checked after the other error bits. | |
2772 | * This is because a multi packet transfer may succeed in a | |
2773 | * number of packets and then get a different response on the | |
2774 | * last packet. In this case both ACK and the last response bit | |
2775 | * will be set. If none of the other response bits is set, then | |
2776 | * the last packet must have been an ACK | |
2777 | * | |
2778 | * Since we got an ACK, we know we don't need to do a ping on | |
2779 | * this pipe | |
2780 | */ | |
2781 | pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING; | |
2782 | ||
2783 | switch (transaction->type) { | |
2784 | case CVMX_USB_TRANSFER_CONTROL: | |
2785 | switch (transaction->stage) { | |
2786 | case CVMX_USB_STAGE_NON_CONTROL: | |
2787 | case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE: | |
2788 | /* This should be impossible */ | |
68d435dd | 2789 | cvmx_usb_perform_complete(usb, pipe, |
1da69aa9 | 2790 | transaction, CVMX_USB_COMPLETE_ERROR); |
6570b4a9 AK |
2791 | break; |
2792 | case CVMX_USB_STAGE_SETUP: | |
2793 | pipe->pid_toggle = 1; | |
68d435dd | 2794 | if (cvmx_usb_pipe_needs_split(usb, pipe)) |
1da69aa9 RO |
2795 | transaction->stage = |
2796 | CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE; | |
6570b4a9 | 2797 | else { |
e301dfb2 | 2798 | struct usb_ctrlrequest *header = |
6570b4a9 | 2799 | cvmx_phys_to_ptr(transaction->control_header); |
e301dfb2 | 2800 | if (header->wLength) |
9109fcff AS |
2801 | transaction->stage = |
2802 | CVMX_USB_STAGE_DATA; | |
6570b4a9 | 2803 | else |
9109fcff AS |
2804 | transaction->stage = |
2805 | CVMX_USB_STAGE_STATUS; | |
6570b4a9 AK |
2806 | } |
2807 | break; | |
2808 | case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE: | |
2809 | { | |
e301dfb2 | 2810 | struct usb_ctrlrequest *header = |
6570b4a9 | 2811 | cvmx_phys_to_ptr(transaction->control_header); |
e301dfb2 | 2812 | if (header->wLength) |
9109fcff AS |
2813 | transaction->stage = |
2814 | CVMX_USB_STAGE_DATA; | |
6570b4a9 | 2815 | else |
9109fcff AS |
2816 | transaction->stage = |
2817 | CVMX_USB_STAGE_STATUS; | |
6570b4a9 AK |
2818 | } |
2819 | break; | |
2820 | case CVMX_USB_STAGE_DATA: | |
68d435dd | 2821 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
1da69aa9 RO |
2822 | transaction->stage = |
2823 | CVMX_USB_STAGE_DATA_SPLIT_COMPLETE; | |
6570b4a9 AK |
2824 | /* |
2825 | * For setup OUT data that are splits, | |
2826 | * the hardware doesn't appear to count | |
2827 | * transferred data. Here we manually | |
2828 | * update the data transferred | |
2829 | */ | |
2830 | if (!usbc_hcchar.s.epdir) { | |
2831 | if (buffer_space_left < pipe->max_packet) | |
1da69aa9 RO |
2832 | transaction->actual_bytes += |
2833 | buffer_space_left; | |
6570b4a9 | 2834 | else |
1da69aa9 RO |
2835 | transaction->actual_bytes += |
2836 | pipe->max_packet; | |
6570b4a9 | 2837 | } |
1da69aa9 RO |
2838 | } else if ((buffer_space_left == 0) || |
2839 | (bytes_in_last_packet < | |
2840 | pipe->max_packet)) { | |
6570b4a9 | 2841 | pipe->pid_toggle = 1; |
1da69aa9 RO |
2842 | transaction->stage = |
2843 | CVMX_USB_STAGE_STATUS; | |
6570b4a9 AK |
2844 | } |
2845 | break; | |
2846 | case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE: | |
1da69aa9 RO |
2847 | if ((buffer_space_left == 0) || |
2848 | (bytes_in_last_packet < | |
2849 | pipe->max_packet)) { | |
6570b4a9 | 2850 | pipe->pid_toggle = 1; |
1da69aa9 RO |
2851 | transaction->stage = |
2852 | CVMX_USB_STAGE_STATUS; | |
6570b4a9 | 2853 | } else { |
1da69aa9 RO |
2854 | transaction->stage = |
2855 | CVMX_USB_STAGE_DATA; | |
6570b4a9 AK |
2856 | } |
2857 | break; | |
2858 | case CVMX_USB_STAGE_STATUS: | |
68d435dd | 2859 | if (cvmx_usb_pipe_needs_split(usb, pipe)) |
1da69aa9 RO |
2860 | transaction->stage = |
2861 | CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE; | |
6570b4a9 | 2862 | else |
68d435dd | 2863 | cvmx_usb_perform_complete(usb, pipe, |
1da69aa9 RO |
2864 | transaction, |
2865 | CVMX_USB_COMPLETE_SUCCESS); | |
6570b4a9 AK |
2866 | break; |
2867 | case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE: | |
68d435dd | 2868 | cvmx_usb_perform_complete(usb, pipe, |
1da69aa9 RO |
2869 | transaction, |
2870 | CVMX_USB_COMPLETE_SUCCESS); | |
6570b4a9 AK |
2871 | break; |
2872 | } | |
2873 | break; | |
2874 | case CVMX_USB_TRANSFER_BULK: | |
2875 | case CVMX_USB_TRANSFER_INTERRUPT: | |
2876 | /* | |
2877 | * The only time a bulk transfer isn't complete when it | |
2878 | * finishes with an ACK is during a split transaction. | |
2879 | * For splits we need to continue the transfer if more | |
2880 | * data is needed | |
2881 | */ | |
68d435dd | 2882 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
1da69aa9 RO |
2883 | if (transaction->stage == |
2884 | CVMX_USB_STAGE_NON_CONTROL) | |
2885 | transaction->stage = | |
2886 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE; | |
6570b4a9 | 2887 | else { |
1da69aa9 RO |
2888 | if (buffer_space_left && |
2889 | (bytes_in_last_packet == | |
2890 | pipe->max_packet)) | |
2891 | transaction->stage = | |
2892 | CVMX_USB_STAGE_NON_CONTROL; | |
6570b4a9 | 2893 | else { |
1da69aa9 RO |
2894 | if (transaction->type == |
2895 | CVMX_USB_TRANSFER_INTERRUPT) | |
2896 | pipe->next_tx_frame += | |
2897 | pipe->interval; | |
68d435dd | 2898 | cvmx_usb_perform_complete( |
1da69aa9 RO |
2899 | usb, |
2900 | pipe, | |
2901 | transaction, | |
2902 | CVMX_USB_COMPLETE_SUCCESS); | |
6570b4a9 AK |
2903 | } |
2904 | } | |
2905 | } else { | |
1da69aa9 RO |
2906 | if ((pipe->device_speed == |
2907 | CVMX_USB_SPEED_HIGH) && | |
2908 | (pipe->transfer_type == | |
2909 | CVMX_USB_TRANSFER_BULK) && | |
2910 | (pipe->transfer_dir == | |
2911 | CVMX_USB_DIRECTION_OUT) && | |
6570b4a9 | 2912 | (usbc_hcint.s.nak)) |
1da69aa9 RO |
2913 | pipe->flags |= |
2914 | __CVMX_USB_PIPE_FLAGS_NEED_PING; | |
2915 | if (!buffer_space_left || | |
2916 | (bytes_in_last_packet < | |
2917 | pipe->max_packet)) { | |
2918 | if (transaction->type == | |
2919 | CVMX_USB_TRANSFER_INTERRUPT) | |
2920 | pipe->next_tx_frame += | |
2921 | pipe->interval; | |
68d435dd | 2922 | cvmx_usb_perform_complete(usb, pipe, |
1da69aa9 RO |
2923 | transaction, |
2924 | CVMX_USB_COMPLETE_SUCCESS); | |
6570b4a9 AK |
2925 | } |
2926 | } | |
2927 | break; | |
2928 | case CVMX_USB_TRANSFER_ISOCHRONOUS: | |
68d435dd | 2929 | if (cvmx_usb_pipe_needs_split(usb, pipe)) { |
6570b4a9 AK |
2930 | /* |
2931 | * ISOCHRONOUS OUT splits don't require a | |
2932 | * complete split stage. Instead they use a | |
2933 | * sequence of begin OUT splits to transfer the | |
2934 | * data 188 bytes at a time. Once the transfer | |
2935 | * is complete, the pipe sleeps until the next | |
2936 | * schedule interval | |
2937 | */ | |
9109fcff AS |
2938 | if (pipe->transfer_dir == |
2939 | CVMX_USB_DIRECTION_OUT) { | |
6570b4a9 AK |
2940 | /* |
2941 | * If no space left or this wasn't a max | |
2942 | * size packet then this transfer is | |
2943 | * complete. Otherwise start it again to | |
2944 | * send the next 188 bytes | |
2945 | */ | |
1da69aa9 RO |
2946 | if (!buffer_space_left || |
2947 | (bytes_this_transfer < 188)) { | |
e725cef3 PD |
2948 | pipe->next_tx_frame += |
2949 | pipe->interval; | |
68d435dd AK |
2950 | cvmx_usb_perform_complete(usb, |
2951 | pipe, transaction, | |
1da69aa9 | 2952 | CVMX_USB_COMPLETE_SUCCESS); |
6570b4a9 AK |
2953 | } |
2954 | } else { | |
1da69aa9 RO |
2955 | if (transaction->stage == |
2956 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) { | |
6570b4a9 AK |
2957 | /* |
2958 | * We are in the incoming data | |
2959 | * phase. Keep getting data | |
2960 | * until we run out of space or | |
2961 | * get a small packet | |
2962 | */ | |
1da69aa9 RO |
2963 | if ((buffer_space_left == 0) || |
2964 | (bytes_in_last_packet < | |
2965 | pipe->max_packet)) { | |
2966 | pipe->next_tx_frame += | |
2967 | pipe->interval; | |
68d435dd | 2968 | cvmx_usb_perform_complete( |
1da69aa9 RO |
2969 | usb, |
2970 | pipe, | |
2971 | transaction, | |
2972 | CVMX_USB_COMPLETE_SUCCESS); | |
6570b4a9 AK |
2973 | } |
2974 | } else | |
1da69aa9 RO |
2975 | transaction->stage = |
2976 | CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE; | |
6570b4a9 AK |
2977 | } |
2978 | } else { | |
2979 | pipe->next_tx_frame += pipe->interval; | |
68d435dd | 2980 | cvmx_usb_perform_complete(usb, pipe, |
1da69aa9 RO |
2981 | transaction, |
2982 | CVMX_USB_COMPLETE_SUCCESS); | |
6570b4a9 AK |
2983 | } |
2984 | break; | |
2985 | } | |
2986 | } else if (usbc_hcint.s.nak) { | |
2987 | /* | |
2988 | * If this was a split then clear our split in progress marker. | |
2989 | */ | |
2990 | if (usb->active_split == transaction) | |
2991 | usb->active_split = NULL; | |
2992 | /* | |
2993 | * NAK as a response means the device couldn't accept the | |
2994 | * transaction, but it should be retried in the future. Rewind | |
2995 | * to the beginning of the transaction by anding off the split | |
2996 | * complete bit. Retry in the next interval | |
2997 | */ | |
2998 | transaction->retries = 0; | |
2999 | transaction->stage &= ~1; | |
3000 | pipe->next_tx_frame += pipe->interval; | |
3001 | if (pipe->next_tx_frame < usb->frame_number) | |
1da69aa9 RO |
3002 | pipe->next_tx_frame = usb->frame_number + |
3003 | pipe->interval - | |
3004 | (usb->frame_number - pipe->next_tx_frame) % | |
3005 | pipe->interval; | |
6570b4a9 AK |
3006 | } else { |
3007 | struct cvmx_usb_port_status port; | |
f5106435 | 3008 | |
cb61c600 | 3009 | port = cvmx_usb_get_status(usb); |
6570b4a9 AK |
3010 | if (port.port_enabled) { |
3011 | /* We'll retry the exact same transaction again */ | |
3012 | transaction->retries++; | |
3013 | } else { | |
3014 | /* | |
3015 | * We get channel halted interrupts with no result bits | |
3016 | * sets when the cable is unplugged | |
3017 | */ | |
68d435dd | 3018 | cvmx_usb_perform_complete(usb, pipe, transaction, |
1da69aa9 | 3019 | CVMX_USB_COMPLETE_ERROR); |
6570b4a9 AK |
3020 | } |
3021 | } | |
3022 | return 0; | |
3023 | } | |
3024 | ||
393e2146 AK |
3025 | static void octeon_usb_port_callback(struct cvmx_usb_state *usb) |
3026 | { | |
3027 | struct octeon_hcd *priv = cvmx_usb_to_octeon(usb); | |
3028 | ||
3029 | spin_unlock(&priv->lock); | |
3030 | usb_hcd_poll_rh_status(octeon_to_hcd(priv)); | |
3031 | spin_lock(&priv->lock); | |
3032 | } | |
6570b4a9 AK |
3033 | |
3034 | /** | |
3035 | * Poll the USB block for status and call all needed callback | |
3036 | * handlers. This function is meant to be called in the interrupt | |
3037 | * handler for the USB controller. It can also be called | |
3038 | * periodically in a loop for non-interrupt based operation. | |
3039 | * | |
cb61c600 | 3040 | * @usb: USB device state populated by cvmx_usb_initialize(). |
6570b4a9 AK |
3041 | * |
3042 | * Returns: 0 or a negative error code. | |
3043 | */ | |
cb61c600 | 3044 | static int cvmx_usb_poll(struct cvmx_usb_state *usb) |
6570b4a9 AK |
3045 | { |
3046 | union cvmx_usbcx_hfnum usbc_hfnum; | |
3047 | union cvmx_usbcx_gintsts usbc_gintsts; | |
6570b4a9 | 3048 | |
20f6b829 | 3049 | prefetch_range(usb, sizeof(*usb)); |
6570b4a9 AK |
3050 | |
3051 | /* Update the frame counter */ | |
68d435dd | 3052 | usbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index)); |
6570b4a9 AK |
3053 | if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum) |
3054 | usb->frame_number += 0x4000; | |
3055 | usb->frame_number &= ~0x3fffull; | |
3056 | usb->frame_number |= usbc_hfnum.s.frnum; | |
3057 | ||
3058 | /* Read the pending interrupts */ | |
68d435dd AK |
3059 | usbc_gintsts.u32 = cvmx_usb_read_csr32(usb, |
3060 | CVMX_USBCX_GINTSTS(usb->index)); | |
6570b4a9 AK |
3061 | |
3062 | /* Clear the interrupts now that we know about them */ | |
68d435dd AK |
3063 | cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), |
3064 | usbc_gintsts.u32); | |
6570b4a9 AK |
3065 | |
3066 | if (usbc_gintsts.s.rxflvl) { | |
3067 | /* | |
3068 | * RxFIFO Non-Empty (RxFLvl) | |
3069 | * Indicates that there is at least one packet pending to be | |
3070 | * read from the RxFIFO. | |
3071 | * | |
3072 | * In DMA mode this is handled by hardware | |
3073 | */ | |
3074 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) | |
68d435dd | 3075 | cvmx_usb_poll_rx_fifo(usb); |
6570b4a9 AK |
3076 | } |
3077 | if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) { | |
3078 | /* Fill the Tx FIFOs when not in DMA mode */ | |
3079 | if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) | |
68d435dd | 3080 | cvmx_usb_poll_tx_fifo(usb); |
6570b4a9 AK |
3081 | } |
3082 | if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) { | |
3083 | union cvmx_usbcx_hprt usbc_hprt; | |
3084 | /* | |
3085 | * Disconnect Detected Interrupt (DisconnInt) | |
3086 | * Asserted when a device disconnect is detected. | |
3087 | * | |
3088 | * Host Port Interrupt (PrtInt) | |
3089 | * The core sets this bit to indicate a change in port status of | |
3090 | * one of the O2P USB core ports in Host mode. The application | |
3091 | * must read the Host Port Control and Status (HPRT) register to | |
3092 | * determine the exact event that caused this interrupt. The | |
3093 | * application must clear the appropriate status bit in the Host | |
3094 | * Port Control and Status register to clear this bit. | |
3095 | * | |
3096 | * Call the user's port callback | |
3097 | */ | |
393e2146 | 3098 | octeon_usb_port_callback(usb); |
6570b4a9 | 3099 | /* Clear the port change bits */ |
68d435dd AK |
3100 | usbc_hprt.u32 = cvmx_usb_read_csr32(usb, |
3101 | CVMX_USBCX_HPRT(usb->index)); | |
6570b4a9 | 3102 | usbc_hprt.s.prtena = 0; |
68d435dd AK |
3103 | cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), |
3104 | usbc_hprt.u32); | |
6570b4a9 AK |
3105 | } |
3106 | if (usbc_gintsts.s.hchint) { | |
3107 | /* | |
3108 | * Host Channels Interrupt (HChInt) | |
3109 | * The core sets this bit to indicate that an interrupt is | |
3110 | * pending on one of the channels of the core (in Host mode). | |
3111 | * The application must read the Host All Channels Interrupt | |
3112 | * (HAINT) register to determine the exact number of the channel | |
3113 | * on which the interrupt occurred, and then read the | |
3114 | * corresponding Host Channel-n Interrupt (HCINTn) register to | |
3115 | * determine the exact cause of the interrupt. The application | |
3116 | * must clear the appropriate status bit in the HCINTn register | |
3117 | * to clear this bit. | |
3118 | */ | |
3119 | union cvmx_usbcx_haint usbc_haint; | |
f5106435 | 3120 | |
68d435dd | 3121 | usbc_haint.u32 = cvmx_usb_read_csr32(usb, |
e725cef3 | 3122 | CVMX_USBCX_HAINT(usb->index)); |
6570b4a9 AK |
3123 | while (usbc_haint.u32) { |
3124 | int channel; | |
3125 | ||
3126 | channel = __fls(usbc_haint.u32); | |
68d435dd | 3127 | cvmx_usb_poll_channel(usb, channel); |
6570b4a9 AK |
3128 | usbc_haint.u32 ^= 1<<channel; |
3129 | } | |
3130 | } | |
3131 | ||
68d435dd | 3132 | cvmx_usb_schedule(usb, usbc_gintsts.s.sof); |
6570b4a9 AK |
3133 | |
3134 | return 0; | |
3135 | } | |
3136 | ||
b164935b AK |
3137 | /* convert between an HCD pointer and the corresponding struct octeon_hcd */ |
3138 | static inline struct octeon_hcd *hcd_to_octeon(struct usb_hcd *hcd) | |
3139 | { | |
3140 | return (struct octeon_hcd *)(hcd->hcd_priv); | |
3141 | } | |
3142 | ||
b164935b AK |
3143 | static irqreturn_t octeon_usb_irq(struct usb_hcd *hcd) |
3144 | { | |
771378bb AK |
3145 | struct octeon_hcd *priv = hcd_to_octeon(hcd); |
3146 | unsigned long flags; | |
71e06db3 | 3147 | |
771378bb AK |
3148 | spin_lock_irqsave(&priv->lock, flags); |
3149 | cvmx_usb_poll(&priv->usb); | |
3150 | spin_unlock_irqrestore(&priv->lock, flags); | |
3151 | return IRQ_HANDLED; | |
b164935b AK |
3152 | } |
3153 | ||
b164935b AK |
3154 | static int octeon_usb_start(struct usb_hcd *hcd) |
3155 | { | |
771378bb | 3156 | hcd->state = HC_STATE_RUNNING; |
771378bb | 3157 | return 0; |
b164935b AK |
3158 | } |
3159 | ||
3160 | static void octeon_usb_stop(struct usb_hcd *hcd) | |
3161 | { | |
771378bb | 3162 | hcd->state = HC_STATE_HALT; |
b164935b AK |
3163 | } |
3164 | ||
3165 | static int octeon_usb_get_frame_number(struct usb_hcd *hcd) | |
3166 | { | |
771378bb | 3167 | struct octeon_hcd *priv = hcd_to_octeon(hcd); |
71e06db3 | 3168 | |
771378bb | 3169 | return cvmx_usb_get_frame_number(&priv->usb); |
b164935b AK |
3170 | } |
3171 | ||
b164935b | 3172 | static int octeon_usb_urb_enqueue(struct usb_hcd *hcd, |
771378bb AK |
3173 | struct urb *urb, |
3174 | gfp_t mem_flags) | |
b164935b | 3175 | { |
771378bb | 3176 | struct octeon_hcd *priv = hcd_to_octeon(hcd); |
71e06db3 | 3177 | struct device *dev = hcd->self.controller; |
3e1674c0 | 3178 | struct cvmx_usb_transaction *transaction = NULL; |
60f81507 | 3179 | struct cvmx_usb_pipe *pipe; |
771378bb | 3180 | unsigned long flags; |
6e0e1b00 | 3181 | struct cvmx_usb_iso_packet *iso_packet; |
771378bb | 3182 | struct usb_host_endpoint *ep = urb->ep; |
e5b90898 | 3183 | int rc; |
771378bb | 3184 | |
771378bb | 3185 | urb->status = 0; |
771378bb AK |
3186 | spin_lock_irqsave(&priv->lock, flags); |
3187 | ||
e5b90898 AK |
3188 | rc = usb_hcd_link_urb_to_ep(hcd, urb); |
3189 | if (rc) { | |
3190 | spin_unlock_irqrestore(&priv->lock, flags); | |
3191 | return rc; | |
3192 | } | |
3193 | ||
771378bb | 3194 | if (!ep->hcpriv) { |
394d4e08 | 3195 | enum cvmx_usb_transfer transfer_type; |
4918072e | 3196 | enum cvmx_usb_speed speed; |
771378bb AK |
3197 | int split_device = 0; |
3198 | int split_port = 0; | |
f5106435 | 3199 | |
771378bb AK |
3200 | switch (usb_pipetype(urb->pipe)) { |
3201 | case PIPE_ISOCHRONOUS: | |
3202 | transfer_type = CVMX_USB_TRANSFER_ISOCHRONOUS; | |
3203 | break; | |
3204 | case PIPE_INTERRUPT: | |
3205 | transfer_type = CVMX_USB_TRANSFER_INTERRUPT; | |
3206 | break; | |
3207 | case PIPE_CONTROL: | |
3208 | transfer_type = CVMX_USB_TRANSFER_CONTROL; | |
3209 | break; | |
3210 | default: | |
3211 | transfer_type = CVMX_USB_TRANSFER_BULK; | |
3212 | break; | |
3213 | } | |
3214 | switch (urb->dev->speed) { | |
3215 | case USB_SPEED_LOW: | |
3216 | speed = CVMX_USB_SPEED_LOW; | |
3217 | break; | |
3218 | case USB_SPEED_FULL: | |
3219 | speed = CVMX_USB_SPEED_FULL; | |
3220 | break; | |
3221 | default: | |
3222 | speed = CVMX_USB_SPEED_HIGH; | |
3223 | break; | |
3224 | } | |
87e7e57a AK |
3225 | /* |
3226 | * For slow devices on high speed ports we need to find the hub | |
3227 | * that does the speed translation so we know where to send the | |
3228 | * split transactions. | |
3229 | */ | |
771378bb | 3230 | if (speed != CVMX_USB_SPEED_HIGH) { |
87e7e57a AK |
3231 | /* |
3232 | * Start at this device and work our way up the usb | |
3233 | * tree. | |
3234 | */ | |
771378bb | 3235 | struct usb_device *dev = urb->dev; |
f5106435 | 3236 | |
771378bb | 3237 | while (dev->parent) { |
87e7e57a AK |
3238 | /* |
3239 | * If our parent is high speed then he'll | |
3240 | * receive the splits. | |
3241 | */ | |
771378bb AK |
3242 | if (dev->parent->speed == USB_SPEED_HIGH) { |
3243 | split_device = dev->parent->devnum; | |
3244 | split_port = dev->portnum; | |
3245 | break; | |
3246 | } | |
87e7e57a AK |
3247 | /* |
3248 | * Move up the tree one level. If we make it all | |
3249 | * the way up the tree, then the port must not | |
3250 | * be in high speed mode and we don't need a | |
3251 | * split. | |
3252 | */ | |
771378bb AK |
3253 | dev = dev->parent; |
3254 | } | |
3255 | } | |
60f81507 AK |
3256 | pipe = cvmx_usb_open_pipe(&priv->usb, usb_pipedevice(urb->pipe), |
3257 | usb_pipeendpoint(urb->pipe), speed, | |
1da69aa9 RO |
3258 | le16_to_cpu(ep->desc.wMaxPacketSize) |
3259 | & 0x7ff, | |
60f81507 AK |
3260 | transfer_type, |
3261 | usb_pipein(urb->pipe) ? | |
3262 | CVMX_USB_DIRECTION_IN : | |
3263 | CVMX_USB_DIRECTION_OUT, | |
3264 | urb->interval, | |
1da69aa9 RO |
3265 | (le16_to_cpu(ep->desc.wMaxPacketSize) |
3266 | >> 11) & 0x3, | |
60f81507 AK |
3267 | split_device, split_port); |
3268 | if (!pipe) { | |
e5b90898 | 3269 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
771378bb | 3270 | spin_unlock_irqrestore(&priv->lock, flags); |
71e06db3 | 3271 | dev_dbg(dev, "Failed to create pipe\n"); |
771378bb AK |
3272 | return -ENOMEM; |
3273 | } | |
60f81507 | 3274 | ep->hcpriv = pipe; |
c7609eac | 3275 | } else { |
60f81507 | 3276 | pipe = ep->hcpriv; |
c7609eac | 3277 | } |
771378bb AK |
3278 | |
3279 | switch (usb_pipetype(urb->pipe)) { | |
3280 | case PIPE_ISOCHRONOUS: | |
71e06db3 | 3281 | dev_dbg(dev, "Submit isochronous to %d.%d\n", |
1da69aa9 RO |
3282 | usb_pipedevice(urb->pipe), |
3283 | usb_pipeendpoint(urb->pipe)); | |
87e7e57a AK |
3284 | /* |
3285 | * Allocate a structure to use for our private list of | |
3286 | * isochronous packets. | |
3287 | */ | |
6e0e1b00 AK |
3288 | iso_packet = kmalloc(urb->number_of_packets * |
3289 | sizeof(struct cvmx_usb_iso_packet), | |
3290 | GFP_ATOMIC); | |
771378bb AK |
3291 | if (iso_packet) { |
3292 | int i; | |
3293 | /* Fill the list with the data from the URB */ | |
3294 | for (i = 0; i < urb->number_of_packets; i++) { | |
1da69aa9 RO |
3295 | iso_packet[i].offset = |
3296 | urb->iso_frame_desc[i].offset; | |
3297 | iso_packet[i].length = | |
3298 | urb->iso_frame_desc[i].length; | |
3299 | iso_packet[i].status = | |
3300 | CVMX_USB_COMPLETE_ERROR; | |
771378bb | 3301 | } |
87e7e57a AK |
3302 | /* |
3303 | * Store a pointer to the list in the URB setup_packet | |
3304 | * field. We know this currently isn't being used and | |
3305 | * this saves us a bunch of logic. | |
3306 | */ | |
771378bb | 3307 | urb->setup_packet = (char *)iso_packet; |
3e1674c0 AK |
3308 | transaction = cvmx_usb_submit_isochronous(&priv->usb, |
3309 | pipe, urb); | |
87e7e57a AK |
3310 | /* |
3311 | * If submit failed we need to free our private packet | |
3312 | * list. | |
3313 | */ | |
3e1674c0 | 3314 | if (!transaction) { |
771378bb AK |
3315 | urb->setup_packet = NULL; |
3316 | kfree(iso_packet); | |
3317 | } | |
3318 | } | |
3319 | break; | |
3320 | case PIPE_INTERRUPT: | |
71e06db3 | 3321 | dev_dbg(dev, "Submit interrupt to %d.%d\n", |
1da69aa9 RO |
3322 | usb_pipedevice(urb->pipe), |
3323 | usb_pipeendpoint(urb->pipe)); | |
3e1674c0 | 3324 | transaction = cvmx_usb_submit_interrupt(&priv->usb, pipe, urb); |
771378bb AK |
3325 | break; |
3326 | case PIPE_CONTROL: | |
71e06db3 | 3327 | dev_dbg(dev, "Submit control to %d.%d\n", |
1da69aa9 RO |
3328 | usb_pipedevice(urb->pipe), |
3329 | usb_pipeendpoint(urb->pipe)); | |
3e1674c0 | 3330 | transaction = cvmx_usb_submit_control(&priv->usb, pipe, urb); |
771378bb AK |
3331 | break; |
3332 | case PIPE_BULK: | |
71e06db3 | 3333 | dev_dbg(dev, "Submit bulk to %d.%d\n", |
1da69aa9 RO |
3334 | usb_pipedevice(urb->pipe), |
3335 | usb_pipeendpoint(urb->pipe)); | |
3e1674c0 | 3336 | transaction = cvmx_usb_submit_bulk(&priv->usb, pipe, urb); |
771378bb AK |
3337 | break; |
3338 | } | |
3e1674c0 | 3339 | if (!transaction) { |
e5b90898 | 3340 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
771378bb | 3341 | spin_unlock_irqrestore(&priv->lock, flags); |
71e06db3 | 3342 | dev_dbg(dev, "Failed to submit\n"); |
771378bb AK |
3343 | return -ENOMEM; |
3344 | } | |
3e1674c0 | 3345 | urb->hcpriv = transaction; |
771378bb AK |
3346 | spin_unlock_irqrestore(&priv->lock, flags); |
3347 | return 0; | |
b164935b AK |
3348 | } |
3349 | ||
1da69aa9 RO |
3350 | static int octeon_usb_urb_dequeue(struct usb_hcd *hcd, |
3351 | struct urb *urb, | |
3352 | int status) | |
b164935b | 3353 | { |
771378bb AK |
3354 | struct octeon_hcd *priv = hcd_to_octeon(hcd); |
3355 | unsigned long flags; | |
e5b90898 | 3356 | int rc; |
b164935b | 3357 | |
771378bb AK |
3358 | if (!urb->dev) |
3359 | return -EINVAL; | |
b164935b | 3360 | |
771378bb | 3361 | spin_lock_irqsave(&priv->lock, flags); |
b164935b | 3362 | |
e5b90898 AK |
3363 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
3364 | if (rc) | |
3365 | goto out; | |
3366 | ||
771378bb | 3367 | urb->status = status; |
cdd15d89 | 3368 | cvmx_usb_cancel(&priv->usb, urb->ep->hcpriv, urb->hcpriv); |
b164935b | 3369 | |
e5b90898 | 3370 | out: |
771378bb | 3371 | spin_unlock_irqrestore(&priv->lock, flags); |
b164935b | 3372 | |
e5b90898 | 3373 | return rc; |
b164935b AK |
3374 | } |
3375 | ||
1da69aa9 RO |
3376 | static void octeon_usb_endpoint_disable(struct usb_hcd *hcd, |
3377 | struct usb_host_endpoint *ep) | |
b164935b | 3378 | { |
71e06db3 AK |
3379 | struct device *dev = hcd->self.controller; |
3380 | ||
771378bb AK |
3381 | if (ep->hcpriv) { |
3382 | struct octeon_hcd *priv = hcd_to_octeon(hcd); | |
60f81507 | 3383 | struct cvmx_usb_pipe *pipe = ep->hcpriv; |
771378bb | 3384 | unsigned long flags; |
f5106435 | 3385 | |
771378bb | 3386 | spin_lock_irqsave(&priv->lock, flags); |
60f81507 AK |
3387 | cvmx_usb_cancel_all(&priv->usb, pipe); |
3388 | if (cvmx_usb_close_pipe(&priv->usb, pipe)) | |
3389 | dev_dbg(dev, "Closing pipe %p failed\n", pipe); | |
771378bb AK |
3390 | spin_unlock_irqrestore(&priv->lock, flags); |
3391 | ep->hcpriv = NULL; | |
3392 | } | |
b164935b AK |
3393 | } |
3394 | ||
3395 | static int octeon_usb_hub_status_data(struct usb_hcd *hcd, char *buf) | |
3396 | { | |
771378bb | 3397 | struct octeon_hcd *priv = hcd_to_octeon(hcd); |
51a19621 | 3398 | struct cvmx_usb_port_status port_status; |
771378bb | 3399 | unsigned long flags; |
b164935b | 3400 | |
771378bb AK |
3401 | spin_lock_irqsave(&priv->lock, flags); |
3402 | port_status = cvmx_usb_get_status(&priv->usb); | |
3403 | spin_unlock_irqrestore(&priv->lock, flags); | |
3404 | buf[0] = 0; | |
3405 | buf[0] = port_status.connect_change << 1; | |
b164935b | 3406 | |
8522851e | 3407 | return buf[0] != 0; |
b164935b AK |
3408 | } |
3409 | ||
e725cef3 PD |
3410 | static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
3411 | u16 wIndex, char *buf, u16 wLength) | |
b164935b | 3412 | { |
771378bb | 3413 | struct octeon_hcd *priv = hcd_to_octeon(hcd); |
71e06db3 | 3414 | struct device *dev = hcd->self.controller; |
51a19621 | 3415 | struct cvmx_usb_port_status usb_port_status; |
771378bb AK |
3416 | int port_status; |
3417 | struct usb_hub_descriptor *desc; | |
3418 | unsigned long flags; | |
3419 | ||
3420 | switch (typeReq) { | |
3421 | case ClearHubFeature: | |
71e06db3 | 3422 | dev_dbg(dev, "ClearHubFeature\n"); |
771378bb AK |
3423 | switch (wValue) { |
3424 | case C_HUB_LOCAL_POWER: | |
3425 | case C_HUB_OVER_CURRENT: | |
3426 | /* Nothing required here */ | |
3427 | break; | |
3428 | default: | |
3429 | return -EINVAL; | |
3430 | } | |
3431 | break; | |
3432 | case ClearPortFeature: | |
71e06db3 | 3433 | dev_dbg(dev, "ClearPortFeature\n"); |
771378bb | 3434 | if (wIndex != 1) { |
71e06db3 | 3435 | dev_dbg(dev, " INVALID\n"); |
771378bb AK |
3436 | return -EINVAL; |
3437 | } | |
3438 | ||
3439 | switch (wValue) { | |
3440 | case USB_PORT_FEAT_ENABLE: | |
71e06db3 | 3441 | dev_dbg(dev, " ENABLE\n"); |
771378bb AK |
3442 | spin_lock_irqsave(&priv->lock, flags); |
3443 | cvmx_usb_disable(&priv->usb); | |
3444 | spin_unlock_irqrestore(&priv->lock, flags); | |
3445 | break; | |
3446 | case USB_PORT_FEAT_SUSPEND: | |
71e06db3 | 3447 | dev_dbg(dev, " SUSPEND\n"); |
771378bb AK |
3448 | /* Not supported on Octeon */ |
3449 | break; | |
3450 | case USB_PORT_FEAT_POWER: | |
71e06db3 | 3451 | dev_dbg(dev, " POWER\n"); |
771378bb AK |
3452 | /* Not supported on Octeon */ |
3453 | break; | |
3454 | case USB_PORT_FEAT_INDICATOR: | |
71e06db3 | 3455 | dev_dbg(dev, " INDICATOR\n"); |
771378bb AK |
3456 | /* Port inidicator not supported */ |
3457 | break; | |
3458 | case USB_PORT_FEAT_C_CONNECTION: | |
71e06db3 | 3459 | dev_dbg(dev, " C_CONNECTION\n"); |
771378bb AK |
3460 | /* Clears drivers internal connect status change flag */ |
3461 | spin_lock_irqsave(&priv->lock, flags); | |
1da69aa9 RO |
3462 | priv->usb.port_status = |
3463 | cvmx_usb_get_status(&priv->usb); | |
771378bb AK |
3464 | spin_unlock_irqrestore(&priv->lock, flags); |
3465 | break; | |
3466 | case USB_PORT_FEAT_C_RESET: | |
71e06db3 | 3467 | dev_dbg(dev, " C_RESET\n"); |
87e7e57a AK |
3468 | /* |
3469 | * Clears the driver's internal Port Reset Change flag. | |
3470 | */ | |
771378bb | 3471 | spin_lock_irqsave(&priv->lock, flags); |
1da69aa9 RO |
3472 | priv->usb.port_status = |
3473 | cvmx_usb_get_status(&priv->usb); | |
771378bb AK |
3474 | spin_unlock_irqrestore(&priv->lock, flags); |
3475 | break; | |
3476 | case USB_PORT_FEAT_C_ENABLE: | |
71e06db3 | 3477 | dev_dbg(dev, " C_ENABLE\n"); |
87e7e57a AK |
3478 | /* |
3479 | * Clears the driver's internal Port Enable/Disable | |
3480 | * Change flag. | |
3481 | */ | |
771378bb | 3482 | spin_lock_irqsave(&priv->lock, flags); |
1da69aa9 RO |
3483 | priv->usb.port_status = |
3484 | cvmx_usb_get_status(&priv->usb); | |
771378bb AK |
3485 | spin_unlock_irqrestore(&priv->lock, flags); |
3486 | break; | |
3487 | case USB_PORT_FEAT_C_SUSPEND: | |
71e06db3 | 3488 | dev_dbg(dev, " C_SUSPEND\n"); |
87e7e57a AK |
3489 | /* |
3490 | * Clears the driver's internal Port Suspend Change | |
3491 | * flag, which is set when resume signaling on the host | |
3492 | * port is complete. | |
3493 | */ | |
771378bb AK |
3494 | break; |
3495 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
71e06db3 | 3496 | dev_dbg(dev, " C_OVER_CURRENT\n"); |
771378bb AK |
3497 | /* Clears the driver's overcurrent Change flag */ |
3498 | spin_lock_irqsave(&priv->lock, flags); | |
1da69aa9 RO |
3499 | priv->usb.port_status = |
3500 | cvmx_usb_get_status(&priv->usb); | |
771378bb AK |
3501 | spin_unlock_irqrestore(&priv->lock, flags); |
3502 | break; | |
3503 | default: | |
71e06db3 | 3504 | dev_dbg(dev, " UNKNOWN\n"); |
771378bb AK |
3505 | return -EINVAL; |
3506 | } | |
771378bb AK |
3507 | break; |
3508 | case GetHubDescriptor: | |
71e06db3 | 3509 | dev_dbg(dev, "GetHubDescriptor\n"); |
771378bb AK |
3510 | desc = (struct usb_hub_descriptor *)buf; |
3511 | desc->bDescLength = 9; | |
3512 | desc->bDescriptorType = 0x29; | |
3513 | desc->bNbrPorts = 1; | |
e5873388 | 3514 | desc->wHubCharacteristics = cpu_to_le16(0x08); |
771378bb AK |
3515 | desc->bPwrOn2PwrGood = 1; |
3516 | desc->bHubContrCurrent = 0; | |
3517 | desc->u.hs.DeviceRemovable[0] = 0; | |
3518 | desc->u.hs.DeviceRemovable[1] = 0xff; | |
3519 | break; | |
3520 | case GetHubStatus: | |
71e06db3 | 3521 | dev_dbg(dev, "GetHubStatus\n"); |
771378bb AK |
3522 | *(__le32 *) buf = 0; |
3523 | break; | |
3524 | case GetPortStatus: | |
71e06db3 | 3525 | dev_dbg(dev, "GetPortStatus\n"); |
771378bb | 3526 | if (wIndex != 1) { |
71e06db3 | 3527 | dev_dbg(dev, " INVALID\n"); |
771378bb AK |
3528 | return -EINVAL; |
3529 | } | |
3530 | ||
3531 | spin_lock_irqsave(&priv->lock, flags); | |
3532 | usb_port_status = cvmx_usb_get_status(&priv->usb); | |
3533 | spin_unlock_irqrestore(&priv->lock, flags); | |
3534 | port_status = 0; | |
3535 | ||
3536 | if (usb_port_status.connect_change) { | |
3537 | port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); | |
71e06db3 | 3538 | dev_dbg(dev, " C_CONNECTION\n"); |
771378bb AK |
3539 | } |
3540 | ||
3541 | if (usb_port_status.port_enabled) { | |
3542 | port_status |= (1 << USB_PORT_FEAT_C_ENABLE); | |
71e06db3 | 3543 | dev_dbg(dev, " C_ENABLE\n"); |
771378bb AK |
3544 | } |
3545 | ||
3546 | if (usb_port_status.connected) { | |
3547 | port_status |= (1 << USB_PORT_FEAT_CONNECTION); | |
71e06db3 | 3548 | dev_dbg(dev, " CONNECTION\n"); |
771378bb AK |
3549 | } |
3550 | ||
3551 | if (usb_port_status.port_enabled) { | |
3552 | port_status |= (1 << USB_PORT_FEAT_ENABLE); | |
71e06db3 | 3553 | dev_dbg(dev, " ENABLE\n"); |
771378bb AK |
3554 | } |
3555 | ||
3556 | if (usb_port_status.port_over_current) { | |
3557 | port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); | |
71e06db3 | 3558 | dev_dbg(dev, " OVER_CURRENT\n"); |
771378bb AK |
3559 | } |
3560 | ||
3561 | if (usb_port_status.port_powered) { | |
3562 | port_status |= (1 << USB_PORT_FEAT_POWER); | |
71e06db3 | 3563 | dev_dbg(dev, " POWER\n"); |
771378bb AK |
3564 | } |
3565 | ||
3566 | if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH) { | |
3567 | port_status |= USB_PORT_STAT_HIGH_SPEED; | |
71e06db3 | 3568 | dev_dbg(dev, " HIGHSPEED\n"); |
771378bb AK |
3569 | } else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW) { |
3570 | port_status |= (1 << USB_PORT_FEAT_LOWSPEED); | |
71e06db3 | 3571 | dev_dbg(dev, " LOWSPEED\n"); |
771378bb AK |
3572 | } |
3573 | ||
3574 | *((__le32 *) buf) = cpu_to_le32(port_status); | |
771378bb AK |
3575 | break; |
3576 | case SetHubFeature: | |
71e06db3 | 3577 | dev_dbg(dev, "SetHubFeature\n"); |
771378bb AK |
3578 | /* No HUB features supported */ |
3579 | break; | |
3580 | case SetPortFeature: | |
71e06db3 | 3581 | dev_dbg(dev, "SetPortFeature\n"); |
771378bb | 3582 | if (wIndex != 1) { |
71e06db3 | 3583 | dev_dbg(dev, " INVALID\n"); |
771378bb AK |
3584 | return -EINVAL; |
3585 | } | |
3586 | ||
3587 | switch (wValue) { | |
3588 | case USB_PORT_FEAT_SUSPEND: | |
71e06db3 | 3589 | dev_dbg(dev, " SUSPEND\n"); |
771378bb AK |
3590 | return -EINVAL; |
3591 | case USB_PORT_FEAT_POWER: | |
71e06db3 | 3592 | dev_dbg(dev, " POWER\n"); |
771378bb AK |
3593 | return -EINVAL; |
3594 | case USB_PORT_FEAT_RESET: | |
71e06db3 | 3595 | dev_dbg(dev, " RESET\n"); |
771378bb AK |
3596 | spin_lock_irqsave(&priv->lock, flags); |
3597 | cvmx_usb_disable(&priv->usb); | |
3598 | if (cvmx_usb_enable(&priv->usb)) | |
71e06db3 | 3599 | dev_dbg(dev, "Failed to enable the port\n"); |
771378bb AK |
3600 | spin_unlock_irqrestore(&priv->lock, flags); |
3601 | return 0; | |
3602 | case USB_PORT_FEAT_INDICATOR: | |
71e06db3 | 3603 | dev_dbg(dev, " INDICATOR\n"); |
771378bb AK |
3604 | /* Not supported */ |
3605 | break; | |
3606 | default: | |
71e06db3 | 3607 | dev_dbg(dev, " UNKNOWN\n"); |
771378bb AK |
3608 | return -EINVAL; |
3609 | } | |
3610 | break; | |
3611 | default: | |
71e06db3 | 3612 | dev_dbg(dev, "Unknown root hub request\n"); |
771378bb AK |
3613 | return -EINVAL; |
3614 | } | |
3615 | return 0; | |
b164935b AK |
3616 | } |
3617 | ||
b164935b | 3618 | static const struct hc_driver octeon_hc_driver = { |
771378bb AK |
3619 | .description = "Octeon USB", |
3620 | .product_desc = "Octeon Host Controller", | |
3621 | .hcd_priv_size = sizeof(struct octeon_hcd), | |
3622 | .irq = octeon_usb_irq, | |
3623 | .flags = HCD_MEMORY | HCD_USB2, | |
3624 | .start = octeon_usb_start, | |
3625 | .stop = octeon_usb_stop, | |
3626 | .urb_enqueue = octeon_usb_urb_enqueue, | |
3627 | .urb_dequeue = octeon_usb_urb_dequeue, | |
3628 | .endpoint_disable = octeon_usb_endpoint_disable, | |
3629 | .get_frame_number = octeon_usb_get_frame_number, | |
3630 | .hub_status_data = octeon_usb_hub_status_data, | |
3631 | .hub_control = octeon_usb_hub_control, | |
120ee599 AK |
3632 | .map_urb_for_dma = octeon_map_urb_for_dma, |
3633 | .unmap_urb_for_dma = octeon_unmap_urb_for_dma, | |
b164935b AK |
3634 | }; |
3635 | ||
b91619c2 | 3636 | static int octeon_usb_probe(struct platform_device *pdev) |
b164935b | 3637 | { |
771378bb | 3638 | int status; |
b91619c2 DD |
3639 | int initialize_flags; |
3640 | int usb_num; | |
3641 | struct resource *res_mem; | |
3642 | struct device_node *usbn_node; | |
3643 | int irq = platform_get_irq(pdev, 0); | |
3644 | struct device *dev = &pdev->dev; | |
771378bb AK |
3645 | struct octeon_hcd *priv; |
3646 | struct usb_hcd *hcd; | |
3647 | unsigned long flags; | |
b91619c2 DD |
3648 | u32 clock_rate = 48000000; |
3649 | bool is_crystal_clock = false; | |
3650 | const char *clock_type; | |
3651 | int i; | |
3652 | ||
3653 | if (dev->of_node == NULL) { | |
3654 | dev_err(dev, "Error: empty of_node\n"); | |
3655 | return -ENXIO; | |
3656 | } | |
3657 | usbn_node = dev->of_node->parent; | |
3658 | ||
3659 | i = of_property_read_u32(usbn_node, | |
3660 | "refclk-frequency", &clock_rate); | |
3661 | if (i) { | |
3662 | dev_err(dev, "No USBN \"refclk-frequency\"\n"); | |
3663 | return -ENXIO; | |
3664 | } | |
3665 | switch (clock_rate) { | |
3666 | case 12000000: | |
3667 | initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ; | |
3668 | break; | |
3669 | case 24000000: | |
3670 | initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ; | |
3671 | break; | |
3672 | case 48000000: | |
3673 | initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ; | |
3674 | break; | |
3675 | default: | |
1da69aa9 RO |
3676 | dev_err(dev, "Illebal USBN \"refclk-frequency\" %u\n", |
3677 | clock_rate); | |
b91619c2 DD |
3678 | return -ENXIO; |
3679 | ||
3680 | } | |
3681 | ||
3682 | i = of_property_read_string(usbn_node, | |
3683 | "refclk-type", &clock_type); | |
3684 | ||
3685 | if (!i && strcmp("crystal", clock_type) == 0) | |
3686 | is_crystal_clock = true; | |
3687 | ||
3688 | if (is_crystal_clock) | |
3689 | initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI; | |
3690 | else | |
3691 | initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND; | |
3692 | ||
3693 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
3694 | if (res_mem == NULL) { | |
3695 | dev_err(dev, "found no memory resource\n"); | |
3696 | return -ENXIO; | |
3697 | } | |
3698 | usb_num = (res_mem->start >> 44) & 1; | |
3699 | ||
3700 | if (irq < 0) { | |
3701 | /* Defective device tree, but we know how to fix it. */ | |
3702 | irq_hw_number_t hwirq = usb_num ? (1 << 6) + 17 : 56; | |
f5106435 | 3703 | |
b91619c2 DD |
3704 | irq = irq_create_mapping(NULL, hwirq); |
3705 | } | |
771378bb | 3706 | |
87e7e57a AK |
3707 | /* |
3708 | * Set the DMA mask to 64bits so we get buffers already translated for | |
3709 | * DMA. | |
3710 | */ | |
771378bb AK |
3711 | dev->coherent_dma_mask = ~0; |
3712 | dev->dma_mask = &dev->coherent_dma_mask; | |
3713 | ||
b91619c2 DD |
3714 | /* |
3715 | * Only cn52XX and cn56XX have DWC_OTG USB hardware and the | |
3716 | * IOB priority registers. Under heavy network load USB | |
3717 | * hardware can be starved by the IOB causing a crash. Give | |
3718 | * it a priority boost if it has been waiting more than 400 | |
3719 | * cycles to avoid this situation. | |
3720 | * | |
3721 | * Testing indicates that a cnt_val of 8192 is not sufficient, | |
3722 | * but no failures are seen with 4096. We choose a value of | |
3723 | * 400 to give a safety factor of 10. | |
3724 | */ | |
3725 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) { | |
3726 | union cvmx_iob_n2c_l2c_pri_cnt pri_cnt; | |
3727 | ||
3728 | pri_cnt.u64 = 0; | |
3729 | pri_cnt.s.cnt_enb = 1; | |
3730 | pri_cnt.s.cnt_val = 400; | |
3731 | cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64); | |
3732 | } | |
3733 | ||
771378bb AK |
3734 | hcd = usb_create_hcd(&octeon_hc_driver, dev, dev_name(dev)); |
3735 | if (!hcd) { | |
71e06db3 | 3736 | dev_dbg(dev, "Failed to allocate memory for HCD\n"); |
771378bb AK |
3737 | return -1; |
3738 | } | |
3739 | hcd->uses_new_polling = 1; | |
3740 | priv = (struct octeon_hcd *)hcd->hcd_priv; | |
3741 | ||
3742 | spin_lock_init(&priv->lock); | |
3743 | ||
b91619c2 | 3744 | status = cvmx_usb_initialize(&priv->usb, usb_num, initialize_flags); |
771378bb | 3745 | if (status) { |
71e06db3 | 3746 | dev_dbg(dev, "USB initialization failed with %d\n", status); |
771378bb AK |
3747 | kfree(hcd); |
3748 | return -1; | |
3749 | } | |
3750 | ||
3751 | /* This delay is needed for CN3010, but I don't know why... */ | |
3752 | mdelay(10); | |
3753 | ||
3754 | spin_lock_irqsave(&priv->lock, flags); | |
3755 | cvmx_usb_poll(&priv->usb); | |
3756 | spin_unlock_irqrestore(&priv->lock, flags); | |
3757 | ||
b91619c2 | 3758 | status = usb_add_hcd(hcd, irq, 0); |
771378bb | 3759 | if (status) { |
71e06db3 | 3760 | dev_dbg(dev, "USB add HCD failed with %d\n", status); |
771378bb AK |
3761 | kfree(hcd); |
3762 | return -1; | |
3763 | } | |
3c9740a1 | 3764 | device_wakeup_enable(hcd->self.controller); |
771378bb | 3765 | |
b91619c2 | 3766 | dev_info(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq); |
771378bb AK |
3767 | |
3768 | return 0; | |
b164935b AK |
3769 | } |
3770 | ||
b91619c2 | 3771 | static int octeon_usb_remove(struct platform_device *pdev) |
b164935b | 3772 | { |
771378bb | 3773 | int status; |
b91619c2 | 3774 | struct device *dev = &pdev->dev; |
771378bb AK |
3775 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
3776 | struct octeon_hcd *priv = hcd_to_octeon(hcd); | |
3777 | unsigned long flags; | |
b164935b | 3778 | |
771378bb | 3779 | usb_remove_hcd(hcd); |
771378bb AK |
3780 | spin_lock_irqsave(&priv->lock, flags); |
3781 | status = cvmx_usb_shutdown(&priv->usb); | |
3782 | spin_unlock_irqrestore(&priv->lock, flags); | |
3783 | if (status) | |
71e06db3 | 3784 | dev_dbg(dev, "USB shutdown failed with %d\n", status); |
b164935b | 3785 | |
771378bb | 3786 | kfree(hcd); |
b164935b | 3787 | |
771378bb | 3788 | return 0; |
b164935b AK |
3789 | } |
3790 | ||
87794575 | 3791 | static const struct of_device_id octeon_usb_match[] = { |
b91619c2 DD |
3792 | { |
3793 | .compatible = "cavium,octeon-5750-usbc", | |
3794 | }, | |
3795 | {}, | |
b164935b AK |
3796 | }; |
3797 | ||
b91619c2 DD |
3798 | static struct platform_driver octeon_usb_driver = { |
3799 | .driver = { | |
3800 | .name = "OcteonUSB", | |
b91619c2 DD |
3801 | .of_match_table = octeon_usb_match, |
3802 | }, | |
3803 | .probe = octeon_usb_probe, | |
3804 | .remove = octeon_usb_remove, | |
3805 | }; | |
b164935b | 3806 | |
b91619c2 | 3807 | static int __init octeon_usb_driver_init(void) |
b164935b | 3808 | { |
b91619c2 DD |
3809 | if (usb_disabled()) |
3810 | return 0; | |
771378bb | 3811 | |
b91619c2 | 3812 | return platform_driver_register(&octeon_usb_driver); |
b164935b | 3813 | } |
b91619c2 | 3814 | module_init(octeon_usb_driver_init); |
b164935b | 3815 | |
b91619c2 | 3816 | static void __exit octeon_usb_driver_exit(void) |
b164935b | 3817 | { |
b91619c2 DD |
3818 | if (usb_disabled()) |
3819 | return; | |
71e06db3 | 3820 | |
b91619c2 | 3821 | platform_driver_unregister(&octeon_usb_driver); |
b164935b | 3822 | } |
b91619c2 | 3823 | module_exit(octeon_usb_driver_exit); |
b164935b AK |
3824 | |
3825 | MODULE_LICENSE("GPL"); | |
b91619c2 DD |
3826 | MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>"); |
3827 | MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver."); |