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cd5351f4 RC |
1 | /* |
2 | * drivers/staging/omapdrm/omap_drv.c | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "omap_drv.h" | |
21 | ||
22 | #include "drm_crtc_helper.h" | |
23 | #include "drm_fb_helper.h" | |
5c137797 | 24 | #include "omap_dmm_tiler.h" |
cd5351f4 RC |
25 | |
26 | #define DRIVER_NAME MODULE_NAME | |
27 | #define DRIVER_DESC "OMAP DRM" | |
28 | #define DRIVER_DATE "20110917" | |
29 | #define DRIVER_MAJOR 1 | |
30 | #define DRIVER_MINOR 0 | |
31 | #define DRIVER_PATCHLEVEL 0 | |
32 | ||
cd5351f4 RC |
33 | static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS; |
34 | ||
35 | MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs"); | |
36 | module_param(num_crtc, int, 0600); | |
37 | ||
38 | /* | |
39 | * mode config funcs | |
40 | */ | |
41 | ||
42 | /* Notes about mapping DSS and DRM entities: | |
43 | * CRTC: overlay | |
44 | * encoder: manager.. with some extension to allow one primary CRTC | |
45 | * and zero or more video CRTC's to be mapped to one encoder? | |
46 | * connector: dssdev.. manager can be attached/detached from different | |
47 | * devices | |
48 | */ | |
49 | ||
50 | static void omap_fb_output_poll_changed(struct drm_device *dev) | |
51 | { | |
52 | struct omap_drm_private *priv = dev->dev_private; | |
53 | DBG("dev=%p", dev); | |
54 | if (priv->fbdev) { | |
55 | drm_fb_helper_hotplug_event(priv->fbdev); | |
56 | } | |
57 | } | |
58 | ||
e6ecefaa | 59 | static const struct drm_mode_config_funcs omap_mode_config_funcs = { |
cd5351f4 RC |
60 | .fb_create = omap_framebuffer_create, |
61 | .output_poll_changed = omap_fb_output_poll_changed, | |
62 | }; | |
63 | ||
64 | static int get_connector_type(struct omap_dss_device *dssdev) | |
65 | { | |
66 | switch (dssdev->type) { | |
67 | case OMAP_DISPLAY_TYPE_HDMI: | |
68 | return DRM_MODE_CONNECTOR_HDMIA; | |
69 | case OMAP_DISPLAY_TYPE_DPI: | |
70 | if (!strcmp(dssdev->name, "dvi")) | |
71 | return DRM_MODE_CONNECTOR_DVID; | |
72 | /* fallthrough */ | |
73 | default: | |
74 | return DRM_MODE_CONNECTOR_Unknown; | |
75 | } | |
76 | } | |
77 | ||
78 | #if 0 /* enable when dss2 supports hotplug */ | |
79 | static int omap_drm_notifier(struct notifier_block *nb, | |
80 | unsigned long evt, void *arg) | |
81 | { | |
82 | switch (evt) { | |
83 | case OMAP_DSS_SIZE_CHANGE: | |
84 | case OMAP_DSS_HOTPLUG_CONNECT: | |
85 | case OMAP_DSS_HOTPLUG_DISCONNECT: { | |
86 | struct drm_device *dev = drm_device; | |
87 | DBG("hotplug event: evt=%d, dev=%p", evt, dev); | |
88 | if (dev) { | |
89 | drm_sysfs_hotplug_event(dev); | |
90 | } | |
91 | return NOTIFY_OK; | |
92 | } | |
93 | default: /* don't care about other events for now */ | |
94 | return NOTIFY_DONE; | |
95 | } | |
96 | } | |
97 | #endif | |
98 | ||
99 | static void dump_video_chains(void) | |
100 | { | |
101 | int i; | |
102 | ||
103 | DBG("dumping video chains: "); | |
104 | for (i = 0; i < omap_dss_get_num_overlays(); i++) { | |
105 | struct omap_overlay *ovl = omap_dss_get_overlay(i); | |
106 | struct omap_overlay_manager *mgr = ovl->manager; | |
23e2aa64 AT |
107 | struct omap_dss_device *dssdev = mgr ? |
108 | mgr->get_device(mgr) : NULL; | |
cd5351f4 RC |
109 | if (dssdev) { |
110 | DBG("%d: %s -> %s -> %s", i, ovl->name, mgr->name, | |
111 | dssdev->name); | |
112 | } else if (mgr) { | |
113 | DBG("%d: %s -> %s", i, ovl->name, mgr->name); | |
114 | } else { | |
115 | DBG("%d: %s", i, ovl->name); | |
116 | } | |
117 | } | |
118 | } | |
119 | ||
120 | /* create encoders for each manager */ | |
121 | static int create_encoder(struct drm_device *dev, | |
122 | struct omap_overlay_manager *mgr) | |
123 | { | |
124 | struct omap_drm_private *priv = dev->dev_private; | |
125 | struct drm_encoder *encoder = omap_encoder_init(dev, mgr); | |
126 | ||
127 | if (!encoder) { | |
128 | dev_err(dev->dev, "could not create encoder: %s\n", | |
129 | mgr->name); | |
130 | return -ENOMEM; | |
131 | } | |
132 | ||
133 | BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders)); | |
134 | ||
135 | priv->encoders[priv->num_encoders++] = encoder; | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
140 | /* create connectors for each display device */ | |
141 | static int create_connector(struct drm_device *dev, | |
142 | struct omap_dss_device *dssdev) | |
143 | { | |
144 | struct omap_drm_private *priv = dev->dev_private; | |
145 | static struct notifier_block *notifier; | |
146 | struct drm_connector *connector; | |
147 | int j; | |
148 | ||
149 | if (!dssdev->driver) { | |
150 | dev_warn(dev->dev, "%s has no driver.. skipping it\n", | |
151 | dssdev->name); | |
152 | return 0; | |
153 | } | |
154 | ||
155 | if (!(dssdev->driver->get_timings || | |
156 | dssdev->driver->read_edid)) { | |
157 | dev_warn(dev->dev, "%s driver does not support " | |
158 | "get_timings or read_edid.. skipping it!\n", | |
159 | dssdev->name); | |
160 | return 0; | |
161 | } | |
162 | ||
163 | connector = omap_connector_init(dev, | |
164 | get_connector_type(dssdev), dssdev); | |
165 | ||
166 | if (!connector) { | |
167 | dev_err(dev->dev, "could not create connector: %s\n", | |
168 | dssdev->name); | |
169 | return -ENOMEM; | |
170 | } | |
171 | ||
172 | BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors)); | |
173 | ||
174 | priv->connectors[priv->num_connectors++] = connector; | |
175 | ||
176 | #if 0 /* enable when dss2 supports hotplug */ | |
177 | notifier = kzalloc(sizeof(struct notifier_block), GFP_KERNEL); | |
178 | notifier->notifier_call = omap_drm_notifier; | |
179 | omap_dss_add_notify(dssdev, notifier); | |
180 | #else | |
181 | notifier = NULL; | |
182 | #endif | |
183 | ||
184 | for (j = 0; j < priv->num_encoders; j++) { | |
185 | struct omap_overlay_manager *mgr = | |
186 | omap_encoder_get_manager(priv->encoders[j]); | |
23e2aa64 | 187 | if (mgr->get_device(mgr) == dssdev) { |
cd5351f4 RC |
188 | drm_mode_connector_attach_encoder(connector, |
189 | priv->encoders[j]); | |
190 | } | |
191 | } | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | /* create up to max_overlays CRTCs mapping to overlays.. by default, | |
197 | * connect the overlays to different managers/encoders, giving priority | |
198 | * to encoders connected to connectors with a detected connection | |
199 | */ | |
200 | static int create_crtc(struct drm_device *dev, struct omap_overlay *ovl, | |
201 | int *j, unsigned int connected_connectors) | |
202 | { | |
203 | struct omap_drm_private *priv = dev->dev_private; | |
204 | struct omap_overlay_manager *mgr = NULL; | |
205 | struct drm_crtc *crtc; | |
206 | ||
cd5351f4 RC |
207 | /* find next best connector, ones with detected connection first |
208 | */ | |
209 | while (*j < priv->num_connectors && !mgr) { | |
210 | if (connected_connectors & (1 << *j)) { | |
211 | struct drm_encoder *encoder = | |
212 | omap_connector_attached_encoder( | |
213 | priv->connectors[*j]); | |
214 | if (encoder) { | |
215 | mgr = omap_encoder_get_manager(encoder); | |
216 | } | |
217 | } | |
218 | (*j)++; | |
219 | } | |
220 | ||
221 | /* if we couldn't find another connected connector, lets start | |
222 | * looking at the unconnected connectors: | |
223 | * | |
224 | * note: it might not be immediately apparent, but thanks to | |
225 | * the !mgr check in both this loop and the one above, the only | |
226 | * way to enter this loop is with *j == priv->num_connectors, | |
227 | * so idx can never go negative. | |
228 | */ | |
229 | while (*j < 2 * priv->num_connectors && !mgr) { | |
230 | int idx = *j - priv->num_connectors; | |
231 | if (!(connected_connectors & (1 << idx))) { | |
232 | struct drm_encoder *encoder = | |
233 | omap_connector_attached_encoder( | |
234 | priv->connectors[idx]); | |
235 | if (encoder) { | |
236 | mgr = omap_encoder_get_manager(encoder); | |
237 | } | |
238 | } | |
239 | (*j)++; | |
240 | } | |
241 | ||
cd5351f4 RC |
242 | crtc = omap_crtc_init(dev, ovl, priv->num_crtcs); |
243 | ||
244 | if (!crtc) { | |
245 | dev_err(dev->dev, "could not create CRTC: %s\n", | |
246 | ovl->name); | |
247 | return -ENOMEM; | |
248 | } | |
249 | ||
250 | BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs)); | |
251 | ||
252 | priv->crtcs[priv->num_crtcs++] = crtc; | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
bb5c2d9a RC |
257 | static int create_plane(struct drm_device *dev, struct omap_overlay *ovl, |
258 | unsigned int possible_crtcs) | |
259 | { | |
260 | struct omap_drm_private *priv = dev->dev_private; | |
261 | struct drm_plane *plane = | |
262 | omap_plane_init(dev, ovl, possible_crtcs, false); | |
263 | ||
264 | if (!plane) { | |
265 | dev_err(dev->dev, "could not create plane: %s\n", | |
266 | ovl->name); | |
267 | return -ENOMEM; | |
268 | } | |
269 | ||
270 | BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)); | |
271 | ||
272 | priv->planes[priv->num_planes++] = plane; | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
cd5351f4 RC |
277 | static int match_dev_name(struct omap_dss_device *dssdev, void *data) |
278 | { | |
279 | return !strcmp(dssdev->name, data); | |
280 | } | |
281 | ||
282 | static unsigned int detect_connectors(struct drm_device *dev) | |
283 | { | |
284 | struct omap_drm_private *priv = dev->dev_private; | |
285 | unsigned int connected_connectors = 0; | |
286 | int i; | |
287 | ||
288 | for (i = 0; i < priv->num_connectors; i++) { | |
289 | struct drm_connector *connector = priv->connectors[i]; | |
290 | if (omap_connector_detect(connector, true) == | |
291 | connector_status_connected) { | |
292 | connected_connectors |= (1 << i); | |
293 | } | |
294 | } | |
295 | ||
296 | return connected_connectors; | |
297 | } | |
298 | ||
299 | static int omap_modeset_init(struct drm_device *dev) | |
300 | { | |
301 | const struct omap_drm_platform_data *pdata = dev->dev->platform_data; | |
71e8831f | 302 | struct omap_kms_platform_data *kms_pdata = NULL; |
cd5351f4 RC |
303 | struct omap_drm_private *priv = dev->dev_private; |
304 | struct omap_dss_device *dssdev = NULL; | |
305 | int i, j; | |
306 | unsigned int connected_connectors = 0; | |
307 | ||
308 | drm_mode_config_init(dev); | |
309 | ||
71e8831f AG |
310 | if (pdata && pdata->kms_pdata) { |
311 | kms_pdata = pdata->kms_pdata; | |
312 | ||
cd5351f4 RC |
313 | /* if platform data is provided by the board file, use it to |
314 | * control which overlays, managers, and devices we own. | |
315 | */ | |
71e8831f | 316 | for (i = 0; i < kms_pdata->mgr_cnt; i++) { |
cd5351f4 | 317 | struct omap_overlay_manager *mgr = |
71e8831f AG |
318 | omap_dss_get_overlay_manager( |
319 | kms_pdata->mgr_ids[i]); | |
cd5351f4 RC |
320 | create_encoder(dev, mgr); |
321 | } | |
322 | ||
71e8831f | 323 | for (i = 0; i < kms_pdata->dev_cnt; i++) { |
cd5351f4 RC |
324 | struct omap_dss_device *dssdev = |
325 | omap_dss_find_device( | |
71e8831f AG |
326 | (void *)kms_pdata->dev_names[i], |
327 | match_dev_name); | |
cd5351f4 RC |
328 | if (!dssdev) { |
329 | dev_warn(dev->dev, "no such dssdev: %s\n", | |
71e8831f | 330 | kms_pdata->dev_names[i]); |
cd5351f4 RC |
331 | continue; |
332 | } | |
333 | create_connector(dev, dssdev); | |
334 | } | |
335 | ||
336 | connected_connectors = detect_connectors(dev); | |
337 | ||
338 | j = 0; | |
71e8831f | 339 | for (i = 0; i < kms_pdata->ovl_cnt; i++) { |
cd5351f4 | 340 | struct omap_overlay *ovl = |
71e8831f | 341 | omap_dss_get_overlay(kms_pdata->ovl_ids[i]); |
cd5351f4 RC |
342 | create_crtc(dev, ovl, &j, connected_connectors); |
343 | } | |
bb5c2d9a RC |
344 | |
345 | for (i = 0; i < kms_pdata->pln_cnt; i++) { | |
346 | struct omap_overlay *ovl = | |
347 | omap_dss_get_overlay(kms_pdata->pln_ids[i]); | |
348 | create_plane(dev, ovl, (1 << priv->num_crtcs) - 1); | |
349 | } | |
cd5351f4 RC |
350 | } else { |
351 | /* otherwise just grab up to CONFIG_DRM_OMAP_NUM_CRTCS and try | |
352 | * to make educated guesses about everything else | |
353 | */ | |
354 | int max_overlays = min(omap_dss_get_num_overlays(), num_crtc); | |
355 | ||
356 | for (i = 0; i < omap_dss_get_num_overlay_managers(); i++) { | |
357 | create_encoder(dev, omap_dss_get_overlay_manager(i)); | |
358 | } | |
359 | ||
360 | for_each_dss_dev(dssdev) { | |
361 | create_connector(dev, dssdev); | |
362 | } | |
363 | ||
364 | connected_connectors = detect_connectors(dev); | |
365 | ||
366 | j = 0; | |
367 | for (i = 0; i < max_overlays; i++) { | |
368 | create_crtc(dev, omap_dss_get_overlay(i), | |
369 | &j, connected_connectors); | |
370 | } | |
bb5c2d9a RC |
371 | |
372 | /* use any remaining overlays as drm planes */ | |
373 | for (; i < omap_dss_get_num_overlays(); i++) { | |
374 | struct omap_overlay *ovl = omap_dss_get_overlay(i); | |
375 | create_plane(dev, ovl, (1 << priv->num_crtcs) - 1); | |
376 | } | |
cd5351f4 RC |
377 | } |
378 | ||
379 | /* for now keep the mapping of CRTCs and encoders static.. */ | |
380 | for (i = 0; i < priv->num_encoders; i++) { | |
381 | struct drm_encoder *encoder = priv->encoders[i]; | |
382 | struct omap_overlay_manager *mgr = | |
383 | omap_encoder_get_manager(encoder); | |
384 | ||
bb5c2d9a | 385 | encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; |
cd5351f4 RC |
386 | |
387 | DBG("%s: possible_crtcs=%08x", mgr->name, | |
388 | encoder->possible_crtcs); | |
389 | } | |
390 | ||
391 | dump_video_chains(); | |
392 | ||
6b8ca4cf RC |
393 | dev->mode_config.min_width = 32; |
394 | dev->mode_config.min_height = 32; | |
cd5351f4 RC |
395 | |
396 | /* note: eventually will need some cpu_is_omapXYZ() type stuff here | |
397 | * to fill in these limits properly on different OMAP generations.. | |
398 | */ | |
399 | dev->mode_config.max_width = 2048; | |
400 | dev->mode_config.max_height = 2048; | |
401 | ||
402 | dev->mode_config.funcs = &omap_mode_config_funcs; | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | static void omap_modeset_free(struct drm_device *dev) | |
408 | { | |
409 | drm_mode_config_cleanup(dev); | |
410 | } | |
411 | ||
412 | /* | |
413 | * drm ioctl funcs | |
414 | */ | |
415 | ||
416 | ||
417 | static int ioctl_get_param(struct drm_device *dev, void *data, | |
418 | struct drm_file *file_priv) | |
419 | { | |
420 | struct drm_omap_param *args = data; | |
421 | ||
422 | DBG("%p: param=%llu", dev, args->param); | |
423 | ||
424 | switch (args->param) { | |
425 | case OMAP_PARAM_CHIPSET_ID: | |
426 | args->value = GET_OMAP_TYPE; | |
427 | break; | |
428 | default: | |
429 | DBG("unknown parameter %lld", args->param); | |
430 | return -EINVAL; | |
431 | } | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
436 | static int ioctl_set_param(struct drm_device *dev, void *data, | |
437 | struct drm_file *file_priv) | |
438 | { | |
439 | struct drm_omap_param *args = data; | |
440 | ||
441 | switch (args->param) { | |
442 | default: | |
443 | DBG("unknown parameter %lld", args->param); | |
444 | return -EINVAL; | |
445 | } | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | static int ioctl_gem_new(struct drm_device *dev, void *data, | |
451 | struct drm_file *file_priv) | |
452 | { | |
453 | struct drm_omap_gem_new *args = data; | |
454 | DBG("%p:%p: size=0x%08x, flags=%08x", dev, file_priv, | |
455 | args->size.bytes, args->flags); | |
456 | return omap_gem_new_handle(dev, file_priv, args->size, | |
457 | args->flags, &args->handle); | |
458 | } | |
459 | ||
460 | static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
461 | struct drm_file *file_priv) | |
462 | { | |
463 | struct drm_omap_gem_cpu_prep *args = data; | |
464 | struct drm_gem_object *obj; | |
465 | int ret; | |
466 | ||
467 | VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op); | |
468 | ||
469 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
470 | if (!obj) { | |
471 | return -ENOENT; | |
472 | } | |
473 | ||
474 | ret = omap_gem_op_sync(obj, args->op); | |
475 | ||
476 | if (!ret) { | |
477 | ret = omap_gem_op_start(obj, args->op); | |
478 | } | |
479 | ||
480 | drm_gem_object_unreference_unlocked(obj); | |
481 | ||
482 | return ret; | |
483 | } | |
484 | ||
485 | static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
486 | struct drm_file *file_priv) | |
487 | { | |
488 | struct drm_omap_gem_cpu_fini *args = data; | |
489 | struct drm_gem_object *obj; | |
490 | int ret; | |
491 | ||
492 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); | |
493 | ||
494 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
495 | if (!obj) { | |
496 | return -ENOENT; | |
497 | } | |
498 | ||
499 | /* XXX flushy, flushy */ | |
500 | ret = 0; | |
501 | ||
502 | if (!ret) { | |
503 | ret = omap_gem_op_finish(obj, args->op); | |
504 | } | |
505 | ||
506 | drm_gem_object_unreference_unlocked(obj); | |
507 | ||
508 | return ret; | |
509 | } | |
510 | ||
511 | static int ioctl_gem_info(struct drm_device *dev, void *data, | |
512 | struct drm_file *file_priv) | |
513 | { | |
514 | struct drm_omap_gem_info *args = data; | |
515 | struct drm_gem_object *obj; | |
516 | int ret = 0; | |
517 | ||
518 | DBG("%p:%p: handle=%d", dev, file_priv, args->handle); | |
519 | ||
520 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
521 | if (!obj) { | |
522 | return -ENOENT; | |
523 | } | |
524 | ||
f7f9f453 | 525 | args->size = omap_gem_mmap_size(obj); |
cd5351f4 RC |
526 | args->offset = omap_gem_mmap_offset(obj); |
527 | ||
528 | drm_gem_object_unreference_unlocked(obj); | |
529 | ||
530 | return ret; | |
531 | } | |
532 | ||
533 | struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { | |
534 | DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_UNLOCKED|DRM_AUTH), | |
535 | DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
536 | DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH), | |
537 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH), | |
538 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH), | |
539 | DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH), | |
540 | }; | |
541 | ||
542 | /* | |
543 | * drm driver funcs | |
544 | */ | |
545 | ||
546 | /** | |
547 | * load - setup chip and create an initial config | |
548 | * @dev: DRM device | |
549 | * @flags: startup flags | |
550 | * | |
551 | * The driver load routine has to do several things: | |
552 | * - initialize the memory manager | |
553 | * - allocate initial config memory | |
554 | * - setup the DRM framebuffer with the allocated memory | |
555 | */ | |
556 | static int dev_load(struct drm_device *dev, unsigned long flags) | |
557 | { | |
558 | struct omap_drm_private *priv; | |
559 | int ret; | |
560 | ||
561 | DBG("load: dev=%p", dev); | |
562 | ||
cd5351f4 RC |
563 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
564 | if (!priv) { | |
565 | dev_err(dev->dev, "could not allocate priv\n"); | |
566 | return -ENOMEM; | |
567 | } | |
568 | ||
569 | dev->dev_private = priv; | |
570 | ||
4619cdbc | 571 | priv->wq = alloc_ordered_workqueue("omapdrm", 0); |
5609f7fe | 572 | |
f6b6036e RC |
573 | INIT_LIST_HEAD(&priv->obj_list); |
574 | ||
f7f9f453 RC |
575 | omap_gem_init(dev); |
576 | ||
cd5351f4 RC |
577 | ret = omap_modeset_init(dev); |
578 | if (ret) { | |
579 | dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret); | |
580 | dev->dev_private = NULL; | |
581 | kfree(priv); | |
582 | return ret; | |
583 | } | |
584 | ||
585 | priv->fbdev = omap_fbdev_init(dev); | |
586 | if (!priv->fbdev) { | |
587 | dev_warn(dev->dev, "omap_fbdev_init failed\n"); | |
588 | /* well, limp along without an fbdev.. maybe X11 will work? */ | |
589 | } | |
590 | ||
591 | drm_kms_helper_poll_init(dev); | |
592 | ||
593 | ret = drm_vblank_init(dev, priv->num_crtcs); | |
594 | if (ret) { | |
595 | dev_warn(dev->dev, "could not init vblank\n"); | |
596 | } | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | static int dev_unload(struct drm_device *dev) | |
602 | { | |
5609f7fe RC |
603 | struct omap_drm_private *priv = dev->dev_private; |
604 | ||
cd5351f4 RC |
605 | DBG("unload: dev=%p", dev); |
606 | ||
607 | drm_vblank_cleanup(dev); | |
608 | drm_kms_helper_poll_fini(dev); | |
609 | ||
610 | omap_fbdev_free(dev); | |
cd5351f4 | 611 | omap_modeset_free(dev); |
f7f9f453 | 612 | omap_gem_deinit(dev); |
cd5351f4 | 613 | |
5609f7fe RC |
614 | flush_workqueue(priv->wq); |
615 | destroy_workqueue(priv->wq); | |
616 | ||
cd5351f4 RC |
617 | kfree(dev->dev_private); |
618 | dev->dev_private = NULL; | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
623 | static int dev_open(struct drm_device *dev, struct drm_file *file) | |
624 | { | |
625 | file->driver_priv = NULL; | |
626 | ||
627 | DBG("open: dev=%p, file=%p", dev, file); | |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
632 | static int dev_firstopen(struct drm_device *dev) | |
633 | { | |
634 | DBG("firstopen: dev=%p", dev); | |
635 | return 0; | |
636 | } | |
637 | ||
638 | /** | |
639 | * lastclose - clean up after all DRM clients have exited | |
640 | * @dev: DRM device | |
641 | * | |
642 | * Take care of cleaning up after all DRM clients have exited. In the | |
643 | * mode setting case, we want to restore the kernel's initial mode (just | |
644 | * in case the last client left us in a bad state). | |
645 | */ | |
646 | static void dev_lastclose(struct drm_device *dev) | |
647 | { | |
3c810c61 RC |
648 | int i; |
649 | ||
cd5351f4 RC |
650 | /* we don't support vga-switcheroo.. so just make sure the fbdev |
651 | * mode is active | |
652 | */ | |
653 | struct omap_drm_private *priv = dev->dev_private; | |
654 | int ret; | |
655 | ||
656 | DBG("lastclose: dev=%p", dev); | |
657 | ||
c2a6a552 RC |
658 | if (priv->rotation_prop) { |
659 | /* need to restore default rotation state.. not sure | |
660 | * if there is a cleaner way to restore properties to | |
661 | * default state? Maybe a flag that properties should | |
662 | * automatically be restored to default state on | |
663 | * lastclose? | |
664 | */ | |
665 | for (i = 0; i < priv->num_crtcs; i++) { | |
666 | drm_object_property_set_value(&priv->crtcs[i]->base, | |
667 | priv->rotation_prop, 0); | |
668 | } | |
3c810c61 | 669 | |
c2a6a552 RC |
670 | for (i = 0; i < priv->num_planes; i++) { |
671 | drm_object_property_set_value(&priv->planes[i]->base, | |
672 | priv->rotation_prop, 0); | |
673 | } | |
3c810c61 RC |
674 | } |
675 | ||
cd5351f4 RC |
676 | ret = drm_fb_helper_restore_fbdev_mode(priv->fbdev); |
677 | if (ret) | |
678 | DBG("failed to restore crtc mode"); | |
679 | } | |
680 | ||
681 | static void dev_preclose(struct drm_device *dev, struct drm_file *file) | |
682 | { | |
683 | DBG("preclose: dev=%p", dev); | |
684 | } | |
685 | ||
686 | static void dev_postclose(struct drm_device *dev, struct drm_file *file) | |
687 | { | |
688 | DBG("postclose: dev=%p, file=%p", dev, file); | |
689 | } | |
690 | ||
691 | /** | |
692 | * enable_vblank - enable vblank interrupt events | |
693 | * @dev: DRM device | |
694 | * @crtc: which irq to enable | |
695 | * | |
696 | * Enable vblank interrupts for @crtc. If the device doesn't have | |
697 | * a hardware vblank counter, this routine should be a no-op, since | |
698 | * interrupts will have to stay on to keep the count accurate. | |
699 | * | |
700 | * RETURNS | |
701 | * Zero on success, appropriate errno if the given @crtc's vblank | |
702 | * interrupt cannot be enabled. | |
703 | */ | |
704 | static int dev_enable_vblank(struct drm_device *dev, int crtc) | |
705 | { | |
706 | DBG("enable_vblank: dev=%p, crtc=%d", dev, crtc); | |
707 | return 0; | |
708 | } | |
709 | ||
710 | /** | |
711 | * disable_vblank - disable vblank interrupt events | |
712 | * @dev: DRM device | |
713 | * @crtc: which irq to enable | |
714 | * | |
715 | * Disable vblank interrupts for @crtc. If the device doesn't have | |
716 | * a hardware vblank counter, this routine should be a no-op, since | |
717 | * interrupts will have to stay on to keep the count accurate. | |
718 | */ | |
719 | static void dev_disable_vblank(struct drm_device *dev, int crtc) | |
720 | { | |
721 | DBG("disable_vblank: dev=%p, crtc=%d", dev, crtc); | |
722 | } | |
723 | ||
724 | static irqreturn_t dev_irq_handler(DRM_IRQ_ARGS) | |
725 | { | |
726 | return IRQ_HANDLED; | |
727 | } | |
728 | ||
729 | static void dev_irq_preinstall(struct drm_device *dev) | |
730 | { | |
731 | DBG("irq_preinstall: dev=%p", dev); | |
732 | } | |
733 | ||
734 | static int dev_irq_postinstall(struct drm_device *dev) | |
735 | { | |
736 | DBG("irq_postinstall: dev=%p", dev); | |
737 | return 0; | |
738 | } | |
739 | ||
740 | static void dev_irq_uninstall(struct drm_device *dev) | |
741 | { | |
742 | DBG("irq_uninstall: dev=%p", dev); | |
743 | } | |
744 | ||
78b68556 | 745 | static const struct vm_operations_struct omap_gem_vm_ops = { |
cd5351f4 RC |
746 | .fault = omap_gem_fault, |
747 | .open = drm_gem_vm_open, | |
748 | .close = drm_gem_vm_close, | |
749 | }; | |
750 | ||
ff4f3876 RC |
751 | static const struct file_operations omapdriver_fops = { |
752 | .owner = THIS_MODULE, | |
753 | .open = drm_open, | |
754 | .unlocked_ioctl = drm_ioctl, | |
755 | .release = drm_release, | |
756 | .mmap = omap_gem_mmap, | |
757 | .poll = drm_poll, | |
758 | .fasync = drm_fasync, | |
759 | .read = drm_read, | |
760 | .llseek = noop_llseek, | |
761 | }; | |
762 | ||
cd5351f4 RC |
763 | static struct drm_driver omap_drm_driver = { |
764 | .driver_features = | |
6ad11bc3 | 765 | DRIVER_HAVE_IRQ | DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, |
cd5351f4 RC |
766 | .load = dev_load, |
767 | .unload = dev_unload, | |
768 | .open = dev_open, | |
769 | .firstopen = dev_firstopen, | |
770 | .lastclose = dev_lastclose, | |
771 | .preclose = dev_preclose, | |
772 | .postclose = dev_postclose, | |
773 | .get_vblank_counter = drm_vblank_count, | |
774 | .enable_vblank = dev_enable_vblank, | |
775 | .disable_vblank = dev_disable_vblank, | |
776 | .irq_preinstall = dev_irq_preinstall, | |
777 | .irq_postinstall = dev_irq_postinstall, | |
778 | .irq_uninstall = dev_irq_uninstall, | |
779 | .irq_handler = dev_irq_handler, | |
6169a148 AG |
780 | #ifdef CONFIG_DEBUG_FS |
781 | .debugfs_init = omap_debugfs_init, | |
782 | .debugfs_cleanup = omap_debugfs_cleanup, | |
783 | #endif | |
6ad11bc3 | 784 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
3080b838 | 785 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
6ad11bc3 | 786 | .gem_prime_export = omap_gem_prime_export, |
3080b838 | 787 | .gem_prime_import = omap_gem_prime_import, |
cd5351f4 RC |
788 | .gem_init_object = omap_gem_init_object, |
789 | .gem_free_object = omap_gem_free_object, | |
790 | .gem_vm_ops = &omap_gem_vm_ops, | |
791 | .dumb_create = omap_gem_dumb_create, | |
792 | .dumb_map_offset = omap_gem_dumb_map_offset, | |
793 | .dumb_destroy = omap_gem_dumb_destroy, | |
794 | .ioctls = ioctls, | |
795 | .num_ioctls = DRM_OMAP_NUM_IOCTLS, | |
ff4f3876 | 796 | .fops = &omapdriver_fops, |
cd5351f4 RC |
797 | .name = DRIVER_NAME, |
798 | .desc = DRIVER_DESC, | |
799 | .date = DRIVER_DATE, | |
800 | .major = DRIVER_MAJOR, | |
801 | .minor = DRIVER_MINOR, | |
802 | .patchlevel = DRIVER_PATCHLEVEL, | |
803 | }; | |
804 | ||
805 | static int pdev_suspend(struct platform_device *pDevice, pm_message_t state) | |
806 | { | |
807 | DBG(""); | |
808 | return 0; | |
809 | } | |
810 | ||
811 | static int pdev_resume(struct platform_device *device) | |
812 | { | |
813 | DBG(""); | |
814 | return 0; | |
815 | } | |
816 | ||
817 | static void pdev_shutdown(struct platform_device *device) | |
818 | { | |
819 | DBG(""); | |
820 | } | |
821 | ||
822 | static int pdev_probe(struct platform_device *device) | |
823 | { | |
824 | DBG("%s", device->name); | |
825 | return drm_platform_init(&omap_drm_driver, device); | |
826 | } | |
827 | ||
828 | static int pdev_remove(struct platform_device *device) | |
829 | { | |
830 | DBG(""); | |
831 | drm_platform_exit(&omap_drm_driver, device); | |
5c137797 AG |
832 | |
833 | platform_driver_unregister(&omap_dmm_driver); | |
cd5351f4 RC |
834 | return 0; |
835 | } | |
836 | ||
837 | struct platform_driver pdev = { | |
838 | .driver = { | |
839 | .name = DRIVER_NAME, | |
840 | .owner = THIS_MODULE, | |
841 | }, | |
842 | .probe = pdev_probe, | |
843 | .remove = pdev_remove, | |
844 | .suspend = pdev_suspend, | |
845 | .resume = pdev_resume, | |
846 | .shutdown = pdev_shutdown, | |
847 | }; | |
848 | ||
849 | static int __init omap_drm_init(void) | |
850 | { | |
851 | DBG("init"); | |
be0775ac RC |
852 | if (platform_driver_register(&omap_dmm_driver)) { |
853 | /* we can continue on without DMM.. so not fatal */ | |
854 | dev_err(NULL, "DMM registration failed\n"); | |
855 | } | |
cd5351f4 RC |
856 | return platform_driver_register(&pdev); |
857 | } | |
858 | ||
859 | static void __exit omap_drm_fini(void) | |
860 | { | |
861 | DBG("fini"); | |
862 | platform_driver_unregister(&pdev); | |
863 | } | |
864 | ||
865 | /* need late_initcall() so we load after dss_driver's are loaded */ | |
866 | late_initcall(omap_drm_init); | |
867 | module_exit(omap_drm_fini); | |
868 | ||
869 | MODULE_AUTHOR("Rob Clark <rob@ti.com>"); | |
870 | MODULE_DESCRIPTION("OMAP DRM Display Driver"); | |
871 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
872 | MODULE_LICENSE("GPL v2"); |