[deliverable/linux.git] / drivers / staging / rdma / hfi1 / common.h

/*
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2015 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * BSD LICENSE
 *
 * Copyright(c) 2015 Intel Corporation.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  - Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  - Neither the name of Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef _COMMON_H
#define _COMMON_H

#include <rdma/hfi/hfi1_user.h>

/*
 * This file contains defines, structures, etc. that are used
 * to communicate between kernel and user code.
 */

/* version of protocol header (known to chip also). In the long run,
 * we should be able to generate and accept a range of version numbers;
 * for now we only accept one, and it's compiled in.
 */
#define IPS_PROTO_VERSION 2

/*
 * These are compile time constants that you may want to enable or disable
 * if you are trying to debug problems with code or performance.
 * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
 * fast path code
 * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
 * traced in fast path code
 * _HFI1_TRACING define as 0 if you want to remove all tracing in a
 * compilation unit
 */

/*
 * If a packet's QP[23:16] bits match this value, then it is
 * a PSM packet and the hardware will expect a KDETH header
 * following the BTH.
 */
#define DEFAULT_KDETH_QP 0x80

/* driver/hw feature set bitmask */
#define HFI1_CAP_USER_SHIFT      24
#define HFI1_CAP_MASK            ((1UL << HFI1_CAP_USER_SHIFT) - 1)
/* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
#define HFI1_CAP_LOCKED_SHIFT    63
#define HFI1_CAP_LOCKED_MASK     0x1ULL
#define HFI1_CAP_LOCKED_SMASK    (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
/* extra bits used between kernel and user processes */
#define HFI1_CAP_MISC_SHIFT      (HFI1_CAP_USER_SHIFT * 2)
#define HFI1_CAP_MISC_MASK       ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
					   HFI1_CAP_MISC_SHIFT)) - 1)

#define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
#define HFI1_CAP_KCLEAR(cap)						\
	({								\
		hfi1_cap_mask &= ~HFI1_CAP_##cap;			\
		hfi1_cap_mask;						\
	})
#define HFI1_CAP_USET(cap)						\
	({								\
		hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
		hfi1_cap_mask;						\
		})
#define HFI1_CAP_UCLEAR(cap)						\
	({								\
		hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
		hfi1_cap_mask;						\
	})
#define HFI1_CAP_SET(cap)						\
	({								\
		hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap <<	\
						  HFI1_CAP_USER_SHIFT)); \
		hfi1_cap_mask;						\
	})
#define HFI1_CAP_CLEAR(cap)						\
	({								\
		hfi1_cap_mask &= ~(HFI1_CAP_##cap |			\
				  (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
		hfi1_cap_mask;						\
	})
#define HFI1_CAP_LOCK()							\
	({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
#define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
/*
 * The set of capability bits that can be changed after initial load
 * This set is the same for kernel and user contexts. However, for
 * user contexts, the set can be further filtered by using the
 * HFI1_CAP_RESERVED_MASK bits.
 */
#define HFI1_CAP_WRITABLE_MASK   (HFI1_CAP_SDMA_AHG |			\
				 HFI1_CAP_HDRSUPP |			\
				 HFI1_CAP_MULTI_PKT_EGR |		\
				 HFI1_CAP_NODROP_RHQ_FULL |		\
				 HFI1_CAP_NODROP_EGR_FULL |		\
				 HFI1_CAP_ALLOW_PERM_JKEY |		\
				 HFI1_CAP_STATIC_RATE_CTRL |		\
				 HFI1_CAP_PRINT_UNIMPL)
/*
 * A set of capability bits that are "global" and are not allowed to be
 * set in the user bitmask.
 */
#define HFI1_CAP_RESERVED_MASK   ((HFI1_CAP_SDMA |			\
				  HFI1_CAP_USE_SDMA_HEAD |		\
				  HFI1_CAP_EXTENDED_PSN |		\
				  HFI1_CAP_PRINT_UNIMPL |		\
				  HFI1_CAP_QSFP_ENABLED |		\
				  HFI1_CAP_NO_INTEGRITY |		\
				  HFI1_CAP_PKEY_CHECK) <<		\
				 HFI1_CAP_USER_SHIFT)
/*
 * Set of capabilities that need to be enabled for kernel context in
 * order to be allowed for user contexts, as well.
 */
#define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
/* Default enabled capabilities (both kernel and user) */
#define HFI1_CAP_MASK_DEFAULT    (HFI1_CAP_HDRSUPP |			\
				 HFI1_CAP_NODROP_RHQ_FULL |		\
				 HFI1_CAP_NODROP_EGR_FULL |		\
				 HFI1_CAP_SDMA |			\
				 HFI1_CAP_PRINT_UNIMPL |		\
				 HFI1_CAP_STATIC_RATE_CTRL |		\
				 HFI1_CAP_QSFP_ENABLED |		\
				 HFI1_CAP_PKEY_CHECK |			\
				 HFI1_CAP_MULTI_PKT_EGR |		\
				 HFI1_CAP_EXTENDED_PSN |		\
				 ((HFI1_CAP_HDRSUPP |			\
				   HFI1_CAP_MULTI_PKT_EGR |		\
				   HFI1_CAP_STATIC_RATE_CTRL |		\
				   HFI1_CAP_PKEY_CHECK |		\
				   HFI1_CAP_EARLY_CREDIT_RETURN) <<	\
				  HFI1_CAP_USER_SHIFT))
/*
 * A bitmask of kernel/global capabilities that should be communicated
 * to user level processes.
 */
#define HFI1_CAP_K2U (HFI1_CAP_SDMA |			\
		     HFI1_CAP_EXTENDED_PSN |		\
		     HFI1_CAP_PKEY_CHECK |		\
		     HFI1_CAP_NO_INTEGRITY)

#define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << 16) | HFI1_USER_SWMINOR)

#ifndef HFI1_KERN_TYPE
#define HFI1_KERN_TYPE 0
#endif

/*
 * Similarly, this is the kernel version going back to the user.  It's
 * slightly different, in that we want to tell if the driver was built as
 * part of a Intel release, or from the driver from openfabrics.org,
 * kernel.org, or a standard distribution, for support reasons.
 * The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
 *
 * It's returned by the driver to the user code during initialization in the
 * spi_sw_version field of hfi1_base_info, so the user code can in turn
 * check for compatibility with the kernel.
*/
#define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION)

/*
 * Define the driver version number.  This is something that refers only
 * to the driver itself, not the software interfaces it supports.
 */
#ifndef HFI1_DRIVER_VERSION_BASE
#define HFI1_DRIVER_VERSION_BASE "0.9-248"
#endif

/* create the final driver version string */
#ifdef HFI1_IDSTR
#define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
#else
#define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
#endif

/*
 * Diagnostics can send a packet by writing the following
 * struct to the diag packet special file.
 *
 * This allows a custom PBC qword, so that special modes and deliberate
 * changes to CRCs can be used.
 */
#define _DIAG_PKT_VERS 1
struct diag_pkt {
	__u16 version;		/* structure version */
	__u16 unit;		/* which device */
	__u16 sw_index;		/* send sw index to use */
	__u16 len;		/* data length, in bytes */
	__u16 port;		/* port number */
	__u16 unused;
	__u32 flags;		/* call flags */
	__u64 data;		/* user data pointer */
	__u64 pbc;		/* PBC for the packet */
};

/* diag_pkt flags */
#define F_DIAGPKT_WAIT 0x1	/* wait until packet is sent */

/*
 * The next set of defines are for packet headers, and chip register
 * and memory bits that are visible to and/or used by user-mode software.
 */

/*
 * Receive Header Flags
 */
#define RHF_PKT_LEN_SHIFT	0
#define RHF_PKT_LEN_MASK	0xfffull
#define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)

#define RHF_RCV_TYPE_SHIFT	12
#define RHF_RCV_TYPE_MASK	0x7ull
#define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)

#define RHF_USE_EGR_BFR_SHIFT	15
#define RHF_USE_EGR_BFR_MASK	0x1ull
#define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)

#define RHF_EGR_INDEX_SHIFT	16
#define RHF_EGR_INDEX_MASK	0x7ffull
#define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)

#define RHF_DC_INFO_SHIFT	27
#define RHF_DC_INFO_MASK	0x1ull
#define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)

#define RHF_RCV_SEQ_SHIFT	28
#define RHF_RCV_SEQ_MASK	0xfull
#define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)

#define RHF_EGR_OFFSET_SHIFT	32
#define RHF_EGR_OFFSET_MASK	0xfffull
#define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
#define RHF_HDRQ_OFFSET_SHIFT	44
#define RHF_HDRQ_OFFSET_MASK	0x1ffull
#define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
#define RHF_K_HDR_LEN_ERR	(0x1ull << 53)
#define RHF_DC_UNC_ERR		(0x1ull << 54)
#define RHF_DC_ERR		(0x1ull << 55)
#define RHF_RCV_TYPE_ERR_SHIFT	56
#define RHF_RCV_TYPE_ERR_MASK	0x7ul
#define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
#define RHF_TID_ERR		(0x1ull << 59)
#define RHF_LEN_ERR		(0x1ull << 60)
#define RHF_ECC_ERR		(0x1ull << 61)
#define RHF_VCRC_ERR		(0x1ull << 62)
#define RHF_ICRC_ERR		(0x1ull << 63)

#define RHF_ERROR_SMASK 0xffe0000000000000ull		/* bits 63:53 */

/* RHF receive types */
#define RHF_RCV_TYPE_EXPECTED 0
#define RHF_RCV_TYPE_EAGER    1
#define RHF_RCV_TYPE_IB       2 /* normal IB, IB Raw, or IPv6 */
#define RHF_RCV_TYPE_ERROR    3
#define RHF_RCV_TYPE_BYPASS   4
#define RHF_RCV_TYPE_INVALID5 5
#define RHF_RCV_TYPE_INVALID6 6
#define RHF_RCV_TYPE_INVALID7 7

/* RHF receive type error - expected packet errors */
#define RHF_RTE_EXPECTED_FLOW_SEQ_ERR	0x2
#define RHF_RTE_EXPECTED_FLOW_GEN_ERR	0x4

/* RHF receive type error - eager packet errors */
#define RHF_RTE_EAGER_NO_ERR		0x0

/* RHF receive type error - IB packet errors */
#define RHF_RTE_IB_NO_ERR		0x0

/* RHF receive type error - error packet errors */
#define RHF_RTE_ERROR_NO_ERR		0x0
#define RHF_RTE_ERROR_OP_CODE_ERR	0x1
#define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR	0x2
#define RHF_RTE_ERROR_KHDR_HCRC_ERR	0x3
#define RHF_RTE_ERROR_KHDR_KVER_ERR	0x4
#define RHF_RTE_ERROR_CONTEXT_ERR	0x5
#define RHF_RTE_ERROR_KHDR_TID_ERR	0x6

/* RHF receive type error - bypass packet errors */
#define RHF_RTE_BYPASS_NO_ERR		0x0

/*
 * This structure contains the first field common to all protocols
 * that employ this chip.
 */
struct hfi1_message_header {
	__be16 lrh[4];
};

/* IB - LRH header constants */
#define HFI1_LRH_GRH 0x0003      /* 1. word of IB LRH - next header: GRH */
#define HFI1_LRH_BTH 0x0002      /* 1. word of IB LRH - next header: BTH */

/* misc. */
#define SIZE_OF_CRC 1

#define LIM_MGMT_P_KEY       0x7FFF
#define FULL_MGMT_P_KEY      0xFFFF

#define DEFAULT_P_KEY LIM_MGMT_P_KEY
#define HFI1_PERMISSIVE_LID 0xFFFF
#define HFI1_AETH_CREDIT_SHIFT 24
#define HFI1_AETH_CREDIT_MASK 0x1F
#define HFI1_AETH_CREDIT_INVAL 0x1F
#define HFI1_MSN_MASK 0xFFFFFF
#define HFI1_QPN_MASK 0xFFFFFF
#define HFI1_FECN_SHIFT 31
#define HFI1_FECN_MASK 1
#define HFI1_FECN_SMASK (1 << HFI1_FECN_SHIFT)
#define HFI1_BECN_SHIFT 30
#define HFI1_BECN_MASK 1
#define HFI1_BECN_SMASK (1 << HFI1_BECN_SHIFT)
#define HFI1_MULTICAST_LID_BASE 0xC000

static inline __u64 rhf_to_cpu(const __le32 *rbuf)
{
	return __le64_to_cpu(*((__le64 *)rbuf));
}

static inline u64 rhf_err_flags(u64 rhf)
{
	return rhf & RHF_ERROR_SMASK;
}

static inline u32 rhf_rcv_type(u64 rhf)
{
	return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
}

static inline u32 rhf_rcv_type_err(u64 rhf)
{
	return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
}

/* return size is in bytes, not DWORDs */
static inline u32 rhf_pkt_len(u64 rhf)
{
	return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
}

static inline u32 rhf_egr_index(u64 rhf)
{
	return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
}

static inline u32 rhf_rcv_seq(u64 rhf)
{
	return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
}

/* returned offset is in DWORDS */
static inline u32 rhf_hdrq_offset(u64 rhf)
{
	return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
}

static inline u64 rhf_use_egr_bfr(u64 rhf)
{
	return rhf & RHF_USE_EGR_BFR_SMASK;
}

static inline u64 rhf_dc_info(u64 rhf)
{
	return rhf & RHF_DC_INFO_SMASK;
}

static inline u32 rhf_egr_buf_offset(u64 rhf)
{
	return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
}
#endif /* _COMMON_H */
Commit	Line	Data
77241056 MM	1	/*
	2	*
	3	* This file is provided under a dual BSD/GPLv2 license. When using or
	4	* redistributing this file, you may do so under either license.
	5	*
	6	* GPL LICENSE SUMMARY
	7	*
	8	* Copyright(c) 2015 Intel Corporation.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of version 2 of the GNU General Public License as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* BSD LICENSE
	20	*
	21	* Copyright(c) 2015 Intel Corporation.
	22	*
	23	* Redistribution and use in source and binary forms, with or without
	24	* modification, are permitted provided that the following conditions
	25	* are met:
	26	*
	27	* - Redistributions of source code must retain the above copyright
	28	* notice, this list of conditions and the following disclaimer.
	29	* - Redistributions in binary form must reproduce the above copyright
	30	* notice, this list of conditions and the following disclaimer in
	31	* the documentation and/or other materials provided with the
	32	* distribution.
	33	* - Neither the name of Intel Corporation nor the names of its
	34	* contributors may be used to endorse or promote products derived
	35	* from this software without specific prior written permission.
	36	*
	37	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	38	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	39	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	40	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	41	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	42	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	43	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	44	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	45	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	46	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	47	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	48	*
	49	*/
	50
	51	#ifndef _COMMON_H
	52	#define _COMMON_H
	53
	54	#include <rdma/hfi/hfi1_user.h>
	55
	56	/*
	57	* This file contains defines, structures, etc. that are used
	58	* to communicate between kernel and user code.
	59	*/
	60
	61	/* version of protocol header (known to chip also). In the long run,
	62	* we should be able to generate and accept a range of version numbers;
	63	* for now we only accept one, and it's compiled in.
	64	*/
65	#define IPS_PROTO_VERSION 2
66
67	/*
68	* These are compile time constants that you may want to enable or disable
69	* if you are trying to debug problems with code or performance.
70	* HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
71	* fast path code
72	* HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
73	* traced in fast path code
74	* _HFI1_TRACING define as 0 if you want to remove all tracing in a
75	* compilation unit
76	*/
77
78	/*
79	* If a packet's QP[23:16] bits match this value, then it is
80	* a PSM packet and the hardware will expect a KDETH header
81	* following the BTH.
82	*/
83	#define DEFAULT_KDETH_QP 0x80
84
85	/* driver/hw feature set bitmask */
86	#define HFI1_CAP_USER_SHIFT 24
87	#define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1)
88	/* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
89	#define HFI1_CAP_LOCKED_SHIFT 63
90	#define HFI1_CAP_LOCKED_MASK 0x1ULL
91	#define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
92	/* extra bits used between kernel and user processes */
93	#define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2)
94	#define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
95	HFI1_CAP_MISC_SHIFT)) - 1)
96
97	#define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask \|= HFI1_CAP_##cap; hfi1_cap_mask; })
98	#define HFI1_CAP_KCLEAR(cap) \
99	({ \
100	hfi1_cap_mask &= ~HFI1_CAP_##cap; \
101	hfi1_cap_mask; \
102	})
103	#define HFI1_CAP_USET(cap) \
104	({ \
105	hfi1_cap_mask \|= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
106	hfi1_cap_mask; \
107	})
108	#define HFI1_CAP_UCLEAR(cap) \
109	({ \
110	hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
111	hfi1_cap_mask; \
112	})
113	#define HFI1_CAP_SET(cap) \
114	({ \
115	hfi1_cap_mask \|= (HFI1_CAP_##cap \| (HFI1_CAP_##cap << \
116	HFI1_CAP_USER_SHIFT)); \
117	hfi1_cap_mask; \
118	})
119	#define HFI1_CAP_CLEAR(cap) \
120	({ \
121	hfi1_cap_mask &= ~(HFI1_CAP_##cap \| \
122	(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
123	hfi1_cap_mask; \
124	})
125	#define HFI1_CAP_LOCK() \
126	({ hfi1_cap_mask \|= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
127	#define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
128	/*
129	* The set of capability bits that can be changed after initial load
130	* This set is the same for kernel and user contexts. However, for
131	* user contexts, the set can be further filtered by using the
132	* HFI1_CAP_RESERVED_MASK bits.
133	*/
134	#define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG \| \
135	HFI1_CAP_HDRSUPP \| \
136	HFI1_CAP_MULTI_PKT_EGR \| \
137	HFI1_CAP_NODROP_RHQ_FULL \| \
138	HFI1_CAP_NODROP_EGR_FULL \| \
139	HFI1_CAP_ALLOW_PERM_JKEY \| \
140	HFI1_CAP_STATIC_RATE_CTRL \| \
141	HFI1_CAP_PRINT_UNIMPL)
142	/*
143	* A set of capability bits that are "global" and are not allowed to be
144	* set in the user bitmask.
145	*/
146	#define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA \| \
147	HFI1_CAP_USE_SDMA_HEAD \| \
148	HFI1_CAP_EXTENDED_PSN \| \
149	HFI1_CAP_PRINT_UNIMPL \| \
150	HFI1_CAP_QSFP_ENABLED \| \
151	HFI1_CAP_NO_INTEGRITY \| \
152	HFI1_CAP_PKEY_CHECK) << \
153	HFI1_CAP_USER_SHIFT)
154	/*
155	* Set of capabilities that need to be enabled for kernel context in
156	* order to be allowed for user contexts, as well.
157	*/
158	#define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
159	/* Default enabled capabilities (both kernel and user) */
160	#define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP \| \
161	HFI1_CAP_NODROP_RHQ_FULL \| \
162	HFI1_CAP_NODROP_EGR_FULL \| \
163	HFI1_CAP_SDMA \| \
164	HFI1_CAP_PRINT_UNIMPL \| \
165	HFI1_CAP_STATIC_RATE_CTRL \| \
166	HFI1_CAP_QSFP_ENABLED \| \
167	HFI1_CAP_PKEY_CHECK \| \
168	HFI1_CAP_MULTI_PKT_EGR \| \
169	HFI1_CAP_EXTENDED_PSN \| \
170	((HFI1_CAP_HDRSUPP \| \
171	HFI1_CAP_MULTI_PKT_EGR \| \
172	HFI1_CAP_STATIC_RATE_CTRL \| \
173	HFI1_CAP_PKEY_CHECK \| \
174	HFI1_CAP_EARLY_CREDIT_RETURN) << \
175	HFI1_CAP_USER_SHIFT))
176	/*
177	* A bitmask of kernel/global capabilities that should be communicated
178	* to user level processes.
179	*/
180	#define HFI1_CAP_K2U (HFI1_CAP_SDMA \| \
181	HFI1_CAP_EXTENDED_PSN \| \
182	HFI1_CAP_PKEY_CHECK \| \
183	HFI1_CAP_NO_INTEGRITY)
184
185	#define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << 16) \| HFI1_USER_SWMINOR)
186
187	#ifndef HFI1_KERN_TYPE
188	#define HFI1_KERN_TYPE 0
189	#endif
190
191	/*
192	* Similarly, this is the kernel version going back to the user. It's
193	* slightly different, in that we want to tell if the driver was built as
194	* part of a Intel release, or from the driver from openfabrics.org,
195	* kernel.org, or a standard distribution, for support reasons.
196	* The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
197	*
198	* It's returned by the driver to the user code during initialization in the
199	* spi_sw_version field of hfi1_base_info, so the user code can in turn
200	* check for compatibility with the kernel.
201	*/
202	#define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) \| HFI1_USER_SWVERSION)
203
204	/*
205	* Define the driver version number. This is something that refers only
206	* to the driver itself, not the software interfaces it supports.
207	*/
208	#ifndef HFI1_DRIVER_VERSION_BASE
209	#define HFI1_DRIVER_VERSION_BASE "0.9-248"
210	#endif
211
212	/* create the final driver version string */
213	#ifdef HFI1_IDSTR
214	#define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
215	#else
216	#define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
217	#endif
218
219	/*
220	* Diagnostics can send a packet by writing the following
221	* struct to the diag packet special file.
222	*
223	* This allows a custom PBC qword, so that special modes and deliberate
224	* changes to CRCs can be used.
225	*/
226	#define _DIAG_PKT_VERS 1
227	struct diag_pkt {
228	__u16 version; /* structure version */
229	__u16 unit; /* which device */
230	__u16 sw_index; /* send sw index to use */
231	__u16 len; /* data length, in bytes */
232	__u16 port; /* port number */
233	__u16 unused;
234	__u32 flags; /* call flags */
235	__u64 data; /* user data pointer */
236	__u64 pbc; /* PBC for the packet */
237	};
238
239	/* diag_pkt flags */
240	#define F_DIAGPKT_WAIT 0x1 /* wait until packet is sent */
241
242	/*
243	* The next set of defines are for packet headers, and chip register
244	* and memory bits that are visible to and/or used by user-mode software.
245	*/
246
247	/*
248	* Receive Header Flags
249	*/
250	#define RHF_PKT_LEN_SHIFT 0
251	#define RHF_PKT_LEN_MASK 0xfffull
252	#define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
253
254	#define RHF_RCV_TYPE_SHIFT 12
255	#define RHF_RCV_TYPE_MASK 0x7ull
256	#define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
257
258	#define RHF_USE_EGR_BFR_SHIFT 15
259	#define RHF_USE_EGR_BFR_MASK 0x1ull
260	#define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
261
262	#define RHF_EGR_INDEX_SHIFT 16
263	#define RHF_EGR_INDEX_MASK 0x7ffull
264	#define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
265
266	#define RHF_DC_INFO_SHIFT 27
267	#define RHF_DC_INFO_MASK 0x1ull
268	#define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
269
270	#define RHF_RCV_SEQ_SHIFT 28
271	#define RHF_RCV_SEQ_MASK 0xfull
272	#define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
273
274	#define RHF_EGR_OFFSET_SHIFT 32
275	#define RHF_EGR_OFFSET_MASK 0xfffull
276	#define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
277	#define RHF_HDRQ_OFFSET_SHIFT 44
278	#define RHF_HDRQ_OFFSET_MASK 0x1ffull
279	#define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
280	#define RHF_K_HDR_LEN_ERR (0x1ull << 53)
281	#define RHF_DC_UNC_ERR (0x1ull << 54)
282	#define RHF_DC_ERR (0x1ull << 55)
283	#define RHF_RCV_TYPE_ERR_SHIFT 56
284	#define RHF_RCV_TYPE_ERR_MASK 0x7ul
285	#define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
286	#define RHF_TID_ERR (0x1ull << 59)
287	#define RHF_LEN_ERR (0x1ull << 60)
288	#define RHF_ECC_ERR (0x1ull << 61)
289	#define RHF_VCRC_ERR (0x1ull << 62)
290	#define RHF_ICRC_ERR (0x1ull << 63)
291
292	#define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */
293
294	/* RHF receive types */
295	#define RHF_RCV_TYPE_EXPECTED 0
296	#define RHF_RCV_TYPE_EAGER 1
297	#define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */
298	#define RHF_RCV_TYPE_ERROR 3
299	#define RHF_RCV_TYPE_BYPASS 4
300	#define RHF_RCV_TYPE_INVALID5 5
301	#define RHF_RCV_TYPE_INVALID6 6
302	#define RHF_RCV_TYPE_INVALID7 7
303
304	/* RHF receive type error - expected packet errors */
305	#define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2
306	#define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4
307
308	/* RHF receive type error - eager packet errors */
309	#define RHF_RTE_EAGER_NO_ERR 0x0
310
311	/* RHF receive type error - IB packet errors */
312	#define RHF_RTE_IB_NO_ERR 0x0
313
314	/* RHF receive type error - error packet errors */
315	#define RHF_RTE_ERROR_NO_ERR 0x0
316	#define RHF_RTE_ERROR_OP_CODE_ERR 0x1
317	#define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2
318	#define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3
319	#define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4
320	#define RHF_RTE_ERROR_CONTEXT_ERR 0x5
321	#define RHF_RTE_ERROR_KHDR_TID_ERR 0x6
322
323	/* RHF receive type error - bypass packet errors */
324	#define RHF_RTE_BYPASS_NO_ERR 0x0
325
326	/*
327	* This structure contains the first field common to all protocols
328	* that employ this chip.
329	*/
330	struct hfi1_message_header {
331	__be16 lrh[4];
332	};
333
334	/* IB - LRH header constants */
335	#define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
336	#define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
337
338	/* misc. */
339	#define SIZE_OF_CRC 1
340
341	#define LIM_MGMT_P_KEY 0x7FFF
342	#define FULL_MGMT_P_KEY 0xFFFF
343
344	#define DEFAULT_P_KEY LIM_MGMT_P_KEY
345	#define HFI1_PERMISSIVE_LID 0xFFFF
346	#define HFI1_AETH_CREDIT_SHIFT 24
347	#define HFI1_AETH_CREDIT_MASK 0x1F
348	#define HFI1_AETH_CREDIT_INVAL 0x1F
349	#define HFI1_MSN_MASK 0xFFFFFF
350	#define HFI1_QPN_MASK 0xFFFFFF
351	#define HFI1_FECN_SHIFT 31
352	#define HFI1_FECN_MASK 1
353	#define HFI1_FECN_SMASK (1 << HFI1_FECN_SHIFT)
354	#define HFI1_BECN_SHIFT 30
355	#define HFI1_BECN_MASK 1
356	#define HFI1_BECN_SMASK (1 << HFI1_BECN_SHIFT)
357	#define HFI1_MULTICAST_LID_BASE 0xC000
358
359	static inline __u64 rhf_to_cpu(const __le32 *rbuf)
360	{
361	return __le64_to_cpu(((__le64 )rbuf));
362	}
363
364	static inline u64 rhf_err_flags(u64 rhf)
365	{
366	return rhf & RHF_ERROR_SMASK;
367	}
368
369	static inline u32 rhf_rcv_type(u64 rhf)
370	{
371	return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
372	}
373
374	static inline u32 rhf_rcv_type_err(u64 rhf)
375	{
376	return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
377	}
378
379	/* return size is in bytes, not DWORDs */
380	static inline u32 rhf_pkt_len(u64 rhf)
381	{
382	return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
383	}
384
385	static inline u32 rhf_egr_index(u64 rhf)
386	{
387	return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
388	}
389
390	static inline u32 rhf_rcv_seq(u64 rhf)
391	{
392	return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
393	}
394
395	/* returned offset is in DWORDS */
396	static inline u32 rhf_hdrq_offset(u64 rhf)
397	{
398	return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
399	}
400
401	static inline u64 rhf_use_egr_bfr(u64 rhf)
402	{
403	return rhf & RHF_USE_EGR_BFR_SMASK;
404	}
405
406	static inline u64 rhf_dc_info(u64 rhf)
407	{
408	return rhf & RHF_DC_INFO_SMASK;
409	}
410
411	static inline u32 rhf_egr_buf_offset(u64 rhf)
412	{
413	return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
414	}
415	#endif /* _COMMON_H */