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77241056 MM |
1 | /* |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2015 Intel Corporation. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * BSD LICENSE | |
20 | * | |
21 | * Copyright(c) 2015 Intel Corporation. | |
22 | * | |
23 | * Redistribution and use in source and binary forms, with or without | |
24 | * modification, are permitted provided that the following conditions | |
25 | * are met: | |
26 | * | |
27 | * - Redistributions of source code must retain the above copyright | |
28 | * notice, this list of conditions and the following disclaimer. | |
29 | * - Redistributions in binary form must reproduce the above copyright | |
30 | * notice, this list of conditions and the following disclaimer in | |
31 | * the documentation and/or other materials provided with the | |
32 | * distribution. | |
33 | * - Neither the name of Intel Corporation nor the names of its | |
34 | * contributors may be used to endorse or promote products derived | |
35 | * from this software without specific prior written permission. | |
36 | * | |
37 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
38 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
39 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
40 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
41 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
42 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
43 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
44 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
45 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
46 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
48 | * | |
49 | */ | |
50 | ||
51 | #include <linux/pci.h> | |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/vmalloc.h> | |
54 | #include <linux/delay.h> | |
55 | #include <linux/idr.h> | |
56 | #include <linux/module.h> | |
57 | #include <linux/printk.h> | |
58 | #include <linux/hrtimer.h> | |
59 | ||
60 | #include "hfi.h" | |
61 | #include "device.h" | |
62 | #include "common.h" | |
63 | #include "mad.h" | |
64 | #include "sdma.h" | |
65 | #include "debugfs.h" | |
66 | #include "verbs.h" | |
67 | ||
68 | #undef pr_fmt | |
69 | #define pr_fmt(fmt) DRIVER_NAME ": " fmt | |
70 | ||
71 | /* | |
72 | * min buffers we want to have per context, after driver | |
73 | */ | |
74 | #define HFI1_MIN_USER_CTXT_BUFCNT 7 | |
75 | ||
76 | #define HFI1_MIN_HDRQ_EGRBUF_CNT 2 | |
77 | #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */ | |
78 | #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */ | |
79 | ||
80 | /* | |
81 | * Number of user receive contexts we are configured to use (to allow for more | |
82 | * pio buffers per ctxt, etc.) Zero means use one user context per CPU. | |
83 | */ | |
84 | uint num_rcv_contexts; | |
85 | module_param_named(num_rcv_contexts, num_rcv_contexts, uint, S_IRUGO); | |
86 | MODULE_PARM_DESC( | |
87 | num_rcv_contexts, "Set max number of user receive contexts to use"); | |
88 | ||
89 | u8 krcvqs[RXE_NUM_DATA_VL]; | |
90 | int krcvqsset; | |
91 | module_param_array(krcvqs, byte, &krcvqsset, S_IRUGO); | |
92 | MODULE_PARM_DESC(krcvqs, "Array of the number of kernel receive queues by VL"); | |
93 | ||
94 | /* computed based on above array */ | |
95 | unsigned n_krcvqs; | |
96 | ||
97 | static unsigned hfi1_rcvarr_split = 25; | |
98 | module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO); | |
99 | MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers"); | |
100 | ||
101 | static uint eager_buffer_size = (2 << 20); /* 2MB */ | |
102 | module_param(eager_buffer_size, uint, S_IRUGO); | |
103 | MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 2MB"); | |
104 | ||
105 | static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */ | |
106 | module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO); | |
107 | MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)"); | |
108 | ||
109 | static uint hfi1_hdrq_entsize = 32; | |
110 | module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, S_IRUGO); | |
111 | MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B"); | |
112 | ||
113 | unsigned int user_credit_return_threshold = 33; /* default is 33% */ | |
114 | module_param(user_credit_return_threshold, uint, S_IRUGO); | |
115 | MODULE_PARM_DESC(user_credit_return_theshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)"); | |
116 | ||
117 | static inline u64 encode_rcv_header_entry_size(u16); | |
118 | ||
119 | static struct idr hfi1_unit_table; | |
120 | u32 hfi1_cpulist_count; | |
121 | unsigned long *hfi1_cpulist; | |
122 | ||
123 | /* | |
124 | * Common code for creating the receive context array. | |
125 | */ | |
126 | int hfi1_create_ctxts(struct hfi1_devdata *dd) | |
127 | { | |
128 | unsigned i; | |
129 | int ret; | |
130 | int local_node_id = pcibus_to_node(dd->pcidev->bus); | |
131 | ||
132 | if (local_node_id < 0) | |
133 | local_node_id = numa_node_id(); | |
134 | dd->assigned_node_id = local_node_id; | |
135 | ||
136 | dd->rcd = kcalloc(dd->num_rcv_contexts, sizeof(*dd->rcd), GFP_KERNEL); | |
806e6e1b | 137 | if (!dd->rcd) |
77241056 | 138 | goto nomem; |
77241056 MM |
139 | |
140 | /* create one or more kernel contexts */ | |
141 | for (i = 0; i < dd->first_user_ctxt; ++i) { | |
142 | struct hfi1_pportdata *ppd; | |
143 | struct hfi1_ctxtdata *rcd; | |
144 | ||
145 | ppd = dd->pport + (i % dd->num_pports); | |
146 | rcd = hfi1_create_ctxtdata(ppd, i); | |
147 | if (!rcd) { | |
148 | dd_dev_err(dd, | |
149 | "Unable to allocate kernel receive context, failing\n"); | |
150 | goto nomem; | |
151 | } | |
152 | /* | |
153 | * Set up the kernel context flags here and now because they | |
154 | * use default values for all receive side memories. User | |
155 | * contexts will be handled as they are created. | |
156 | */ | |
157 | rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) | | |
158 | HFI1_CAP_KGET(NODROP_RHQ_FULL) | | |
159 | HFI1_CAP_KGET(NODROP_EGR_FULL) | | |
160 | HFI1_CAP_KGET(DMA_RTAIL); | |
161 | rcd->seq_cnt = 1; | |
162 | ||
163 | rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node); | |
164 | if (!rcd->sc) { | |
165 | dd_dev_err(dd, | |
166 | "Unable to allocate kernel send context, failing\n"); | |
167 | dd->rcd[rcd->ctxt] = NULL; | |
168 | hfi1_free_ctxtdata(dd, rcd); | |
169 | goto nomem; | |
170 | } | |
171 | ||
172 | ret = hfi1_init_ctxt(rcd->sc); | |
173 | if (ret < 0) { | |
174 | dd_dev_err(dd, | |
175 | "Failed to setup kernel receive context, failing\n"); | |
176 | sc_free(rcd->sc); | |
177 | dd->rcd[rcd->ctxt] = NULL; | |
178 | hfi1_free_ctxtdata(dd, rcd); | |
179 | ret = -EFAULT; | |
180 | goto bail; | |
181 | } | |
182 | } | |
183 | ||
184 | return 0; | |
185 | nomem: | |
186 | ret = -ENOMEM; | |
187 | bail: | |
188 | kfree(dd->rcd); | |
189 | dd->rcd = NULL; | |
190 | return ret; | |
191 | } | |
192 | ||
193 | /* | |
194 | * Common code for user and kernel context setup. | |
195 | */ | |
196 | struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt) | |
197 | { | |
198 | struct hfi1_devdata *dd = ppd->dd; | |
199 | struct hfi1_ctxtdata *rcd; | |
200 | unsigned kctxt_ngroups = 0; | |
201 | u32 base; | |
202 | ||
203 | if (dd->rcv_entries.nctxt_extra > | |
204 | dd->num_rcv_contexts - dd->first_user_ctxt) | |
205 | kctxt_ngroups = (dd->rcv_entries.nctxt_extra - | |
206 | (dd->num_rcv_contexts - dd->first_user_ctxt)); | |
207 | rcd = kzalloc(sizeof(*rcd), GFP_KERNEL); | |
208 | if (rcd) { | |
209 | u32 rcvtids, max_entries; | |
210 | ||
211 | dd_dev_info(dd, "%s: setting up context %u\n", __func__, ctxt); | |
212 | ||
213 | INIT_LIST_HEAD(&rcd->qp_wait_list); | |
214 | rcd->ppd = ppd; | |
215 | rcd->dd = dd; | |
216 | rcd->cnt = 1; | |
217 | rcd->ctxt = ctxt; | |
218 | dd->rcd[ctxt] = rcd; | |
219 | rcd->numa_id = numa_node_id(); | |
220 | rcd->rcv_array_groups = dd->rcv_entries.ngroups; | |
221 | ||
222 | spin_lock_init(&rcd->exp_lock); | |
223 | ||
224 | /* | |
225 | * Calculate the context's RcvArray entry starting point. | |
226 | * We do this here because we have to take into account all | |
227 | * the RcvArray entries that previous context would have | |
228 | * taken and we have to account for any extra groups | |
229 | * assigned to the kernel or user contexts. | |
230 | */ | |
231 | if (ctxt < dd->first_user_ctxt) { | |
232 | if (ctxt < kctxt_ngroups) { | |
233 | base = ctxt * (dd->rcv_entries.ngroups + 1); | |
234 | rcd->rcv_array_groups++; | |
235 | } else | |
236 | base = kctxt_ngroups + | |
237 | (ctxt * dd->rcv_entries.ngroups); | |
238 | } else { | |
239 | u16 ct = ctxt - dd->first_user_ctxt; | |
240 | ||
241 | base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) + | |
242 | kctxt_ngroups); | |
243 | if (ct < dd->rcv_entries.nctxt_extra) { | |
244 | base += ct * (dd->rcv_entries.ngroups + 1); | |
245 | rcd->rcv_array_groups++; | |
246 | } else | |
247 | base += dd->rcv_entries.nctxt_extra + | |
248 | (ct * dd->rcv_entries.ngroups); | |
249 | } | |
250 | rcd->eager_base = base * dd->rcv_entries.group_size; | |
251 | ||
252 | /* Validate and initialize Rcv Hdr Q variables */ | |
253 | if (rcvhdrcnt % HDRQ_INCREMENT) { | |
254 | dd_dev_err(dd, | |
255 | "ctxt%u: header queue count %d must be divisible by %d\n", | |
256 | rcd->ctxt, rcvhdrcnt, HDRQ_INCREMENT); | |
257 | goto bail; | |
258 | } | |
259 | rcd->rcvhdrq_cnt = rcvhdrcnt; | |
260 | rcd->rcvhdrqentsize = hfi1_hdrq_entsize; | |
261 | /* | |
262 | * Simple Eager buffer allocation: we have already pre-allocated | |
263 | * the number of RcvArray entry groups. Each ctxtdata structure | |
264 | * holds the number of groups for that context. | |
265 | * | |
266 | * To follow CSR requirements and maintain cacheline alignment, | |
267 | * make sure all sizes and bases are multiples of group_size. | |
268 | * | |
269 | * The expected entry count is what is left after assigning | |
270 | * eager. | |
271 | */ | |
272 | max_entries = rcd->rcv_array_groups * | |
273 | dd->rcv_entries.group_size; | |
274 | rcvtids = ((max_entries * hfi1_rcvarr_split) / 100); | |
275 | rcd->egrbufs.count = round_down(rcvtids, | |
276 | dd->rcv_entries.group_size); | |
277 | if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) { | |
278 | dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n", | |
279 | rcd->ctxt); | |
280 | rcd->egrbufs.count = MAX_EAGER_ENTRIES; | |
281 | } | |
282 | dd_dev_info(dd, "ctxt%u: max Eager buffer RcvArray entries: %u\n", | |
283 | rcd->ctxt, rcd->egrbufs.count); | |
284 | ||
285 | /* | |
286 | * Allocate array that will hold the eager buffer accounting | |
287 | * data. | |
288 | * This will allocate the maximum possible buffer count based | |
289 | * on the value of the RcvArray split parameter. | |
290 | * The resulting value will be rounded down to the closest | |
291 | * multiple of dd->rcv_entries.group_size. | |
292 | */ | |
314fcc0d SB |
293 | rcd->egrbufs.buffers = kcalloc(rcd->egrbufs.count, |
294 | sizeof(*rcd->egrbufs.buffers), | |
295 | GFP_KERNEL); | |
77241056 MM |
296 | if (!rcd->egrbufs.buffers) |
297 | goto bail; | |
314fcc0d SB |
298 | rcd->egrbufs.rcvtids = kcalloc(rcd->egrbufs.count, |
299 | sizeof(*rcd->egrbufs.rcvtids), | |
300 | GFP_KERNEL); | |
77241056 MM |
301 | if (!rcd->egrbufs.rcvtids) |
302 | goto bail; | |
303 | rcd->egrbufs.size = eager_buffer_size; | |
304 | /* | |
305 | * The size of the buffers programmed into the RcvArray | |
306 | * entries needs to be big enough to handle the highest | |
307 | * MTU supported. | |
308 | */ | |
309 | if (rcd->egrbufs.size < hfi1_max_mtu) { | |
310 | rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu); | |
311 | dd_dev_info(dd, | |
312 | "ctxt%u: eager bufs size too small. Adjusting to %zu\n", | |
313 | rcd->ctxt, rcd->egrbufs.size); | |
314 | } | |
315 | rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE; | |
316 | ||
317 | if (ctxt < dd->first_user_ctxt) { /* N/A for PSM contexts */ | |
318 | rcd->opstats = kzalloc(sizeof(*rcd->opstats), | |
319 | GFP_KERNEL); | |
806e6e1b | 320 | if (!rcd->opstats) |
77241056 | 321 | goto bail; |
77241056 MM |
322 | } |
323 | } | |
324 | return rcd; | |
325 | bail: | |
326 | kfree(rcd->opstats); | |
327 | kfree(rcd->egrbufs.rcvtids); | |
328 | kfree(rcd->egrbufs.buffers); | |
329 | kfree(rcd); | |
330 | return NULL; | |
331 | } | |
332 | ||
333 | /* | |
334 | * Convert a receive header entry size that to the encoding used in the CSR. | |
335 | * | |
336 | * Return a zero if the given size is invalid. | |
337 | */ | |
338 | static inline u64 encode_rcv_header_entry_size(u16 size) | |
339 | { | |
340 | /* there are only 3 valid receive header entry sizes */ | |
341 | if (size == 2) | |
342 | return 1; | |
343 | if (size == 16) | |
344 | return 2; | |
345 | else if (size == 32) | |
346 | return 4; | |
347 | return 0; /* invalid */ | |
348 | } | |
349 | ||
350 | /* | |
351 | * Select the largest ccti value over all SLs to determine the intra- | |
352 | * packet gap for the link. | |
353 | * | |
354 | * called with cca_timer_lock held (to protect access to cca_timer | |
355 | * array), and rcu_read_lock() (to protect access to cc_state). | |
356 | */ | |
357 | void set_link_ipg(struct hfi1_pportdata *ppd) | |
358 | { | |
359 | struct hfi1_devdata *dd = ppd->dd; | |
360 | struct cc_state *cc_state; | |
361 | int i; | |
362 | u16 cce, ccti_limit, max_ccti = 0; | |
363 | u16 shift, mult; | |
364 | u64 src; | |
365 | u32 current_egress_rate; /* Mbits /sec */ | |
366 | u32 max_pkt_time; | |
367 | /* | |
368 | * max_pkt_time is the maximum packet egress time in units | |
369 | * of the fabric clock period 1/(805 MHz). | |
370 | */ | |
371 | ||
372 | cc_state = get_cc_state(ppd); | |
373 | ||
374 | if (cc_state == NULL) | |
375 | /* | |
376 | * This should _never_ happen - rcu_read_lock() is held, | |
377 | * and set_link_ipg() should not be called if cc_state | |
378 | * is NULL. | |
379 | */ | |
380 | return; | |
381 | ||
382 | for (i = 0; i < OPA_MAX_SLS; i++) { | |
383 | u16 ccti = ppd->cca_timer[i].ccti; | |
384 | ||
385 | if (ccti > max_ccti) | |
386 | max_ccti = ccti; | |
387 | } | |
388 | ||
389 | ccti_limit = cc_state->cct.ccti_limit; | |
390 | if (max_ccti > ccti_limit) | |
391 | max_ccti = ccti_limit; | |
392 | ||
393 | cce = cc_state->cct.entries[max_ccti].entry; | |
394 | shift = (cce & 0xc000) >> 14; | |
395 | mult = (cce & 0x3fff); | |
396 | ||
397 | current_egress_rate = active_egress_rate(ppd); | |
398 | ||
399 | max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate); | |
400 | ||
401 | src = (max_pkt_time >> shift) * mult; | |
402 | ||
403 | src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK; | |
404 | src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT; | |
405 | ||
406 | write_csr(dd, SEND_STATIC_RATE_CONTROL, src); | |
407 | } | |
408 | ||
409 | static enum hrtimer_restart cca_timer_fn(struct hrtimer *t) | |
410 | { | |
411 | struct cca_timer *cca_timer; | |
412 | struct hfi1_pportdata *ppd; | |
413 | int sl; | |
414 | u16 ccti, ccti_timer, ccti_min; | |
415 | struct cc_state *cc_state; | |
416 | ||
417 | cca_timer = container_of(t, struct cca_timer, hrtimer); | |
418 | ppd = cca_timer->ppd; | |
419 | sl = cca_timer->sl; | |
420 | ||
421 | rcu_read_lock(); | |
422 | ||
423 | cc_state = get_cc_state(ppd); | |
424 | ||
425 | if (cc_state == NULL) { | |
426 | rcu_read_unlock(); | |
427 | return HRTIMER_NORESTART; | |
428 | } | |
429 | ||
430 | /* | |
431 | * 1) decrement ccti for SL | |
432 | * 2) calculate IPG for link (set_link_ipg()) | |
433 | * 3) restart timer, unless ccti is at min value | |
434 | */ | |
435 | ||
436 | ccti_min = cc_state->cong_setting.entries[sl].ccti_min; | |
437 | ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer; | |
438 | ||
439 | spin_lock(&ppd->cca_timer_lock); | |
440 | ||
441 | ccti = cca_timer->ccti; | |
442 | ||
443 | if (ccti > ccti_min) { | |
444 | cca_timer->ccti--; | |
445 | set_link_ipg(ppd); | |
446 | } | |
447 | ||
448 | spin_unlock(&ppd->cca_timer_lock); | |
449 | ||
450 | rcu_read_unlock(); | |
451 | ||
452 | if (ccti > ccti_min) { | |
453 | unsigned long nsec = 1024 * ccti_timer; | |
454 | /* ccti_timer is in units of 1.024 usec */ | |
455 | hrtimer_forward_now(t, ns_to_ktime(nsec)); | |
456 | return HRTIMER_RESTART; | |
457 | } | |
458 | return HRTIMER_NORESTART; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Common code for initializing the physical port structure. | |
463 | */ | |
464 | void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd, | |
465 | struct hfi1_devdata *dd, u8 hw_pidx, u8 port) | |
466 | { | |
467 | int i, size; | |
468 | uint default_pkey_idx; | |
469 | ||
470 | ppd->dd = dd; | |
471 | ppd->hw_pidx = hw_pidx; | |
472 | ppd->port = port; /* IB port number, not index */ | |
473 | ||
474 | default_pkey_idx = 1; | |
475 | ||
476 | ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY; | |
477 | if (loopback) { | |
478 | hfi1_early_err(&pdev->dev, | |
479 | "Faking data partition 0x8001 in idx %u\n", | |
480 | !default_pkey_idx); | |
481 | ppd->pkeys[!default_pkey_idx] = 0x8001; | |
482 | } | |
483 | ||
484 | INIT_WORK(&ppd->link_vc_work, handle_verify_cap); | |
485 | INIT_WORK(&ppd->link_up_work, handle_link_up); | |
486 | INIT_WORK(&ppd->link_down_work, handle_link_down); | |
487 | INIT_WORK(&ppd->freeze_work, handle_freeze); | |
488 | INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade); | |
489 | INIT_WORK(&ppd->sma_message_work, handle_sma_message); | |
490 | INIT_WORK(&ppd->link_bounce_work, handle_link_bounce); | |
491 | mutex_init(&ppd->hls_lock); | |
492 | spin_lock_init(&ppd->sdma_alllock); | |
493 | spin_lock_init(&ppd->qsfp_info.qsfp_lock); | |
494 | ||
495 | ppd->sm_trap_qp = 0x0; | |
496 | ppd->sa_qp = 0x1; | |
497 | ||
498 | ppd->hfi1_wq = NULL; | |
499 | ||
500 | spin_lock_init(&ppd->cca_timer_lock); | |
501 | ||
502 | for (i = 0; i < OPA_MAX_SLS; i++) { | |
503 | hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC, | |
504 | HRTIMER_MODE_REL); | |
505 | ppd->cca_timer[i].ppd = ppd; | |
506 | ppd->cca_timer[i].sl = i; | |
507 | ppd->cca_timer[i].ccti = 0; | |
508 | ppd->cca_timer[i].hrtimer.function = cca_timer_fn; | |
509 | } | |
510 | ||
511 | ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT; | |
512 | ||
513 | spin_lock_init(&ppd->cc_state_lock); | |
514 | spin_lock_init(&ppd->cc_log_lock); | |
515 | size = sizeof(struct cc_state); | |
516 | RCU_INIT_POINTER(ppd->cc_state, kzalloc(size, GFP_KERNEL)); | |
517 | if (!rcu_dereference(ppd->cc_state)) | |
518 | goto bail; | |
519 | return; | |
520 | ||
521 | bail: | |
522 | ||
523 | hfi1_early_err(&pdev->dev, | |
524 | "Congestion Control Agent disabled for port %d\n", port); | |
525 | } | |
526 | ||
527 | /* | |
528 | * Do initialization for device that is only needed on | |
529 | * first detect, not on resets. | |
530 | */ | |
531 | static int loadtime_init(struct hfi1_devdata *dd) | |
532 | { | |
533 | return 0; | |
534 | } | |
535 | ||
536 | /** | |
537 | * init_after_reset - re-initialize after a reset | |
538 | * @dd: the hfi1_ib device | |
539 | * | |
540 | * sanity check at least some of the values after reset, and | |
541 | * ensure no receive or transmit (explicitly, in case reset | |
542 | * failed | |
543 | */ | |
544 | static int init_after_reset(struct hfi1_devdata *dd) | |
545 | { | |
546 | int i; | |
547 | ||
548 | /* | |
549 | * Ensure chip does no sends or receives, tail updates, or | |
550 | * pioavail updates while we re-initialize. This is mostly | |
551 | * for the driver data structures, not chip registers. | |
552 | */ | |
553 | for (i = 0; i < dd->num_rcv_contexts; i++) | |
554 | hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS | | |
555 | HFI1_RCVCTRL_INTRAVAIL_DIS | | |
556 | HFI1_RCVCTRL_TAILUPD_DIS, i); | |
557 | pio_send_control(dd, PSC_GLOBAL_DISABLE); | |
558 | for (i = 0; i < dd->num_send_contexts; i++) | |
559 | sc_disable(dd->send_contexts[i].sc); | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | static void enable_chip(struct hfi1_devdata *dd) | |
565 | { | |
566 | u32 rcvmask; | |
567 | u32 i; | |
568 | ||
569 | /* enable PIO send */ | |
570 | pio_send_control(dd, PSC_GLOBAL_ENABLE); | |
571 | ||
572 | /* | |
573 | * Enable kernel ctxts' receive and receive interrupt. | |
574 | * Other ctxts done as user opens and initializes them. | |
575 | */ | |
576 | rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB; | |
577 | for (i = 0; i < dd->first_user_ctxt; ++i) { | |
578 | rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ? | |
579 | HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS; | |
580 | if (!HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, MULTI_PKT_EGR)) | |
581 | rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB; | |
582 | if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_RHQ_FULL)) | |
583 | rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB; | |
584 | if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_EGR_FULL)) | |
585 | rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB; | |
586 | hfi1_rcvctrl(dd, rcvmask, i); | |
587 | sc_enable(dd->rcd[i]->sc); | |
588 | } | |
589 | } | |
590 | ||
591 | /** | |
592 | * create_workqueues - create per port workqueues | |
593 | * @dd: the hfi1_ib device | |
594 | */ | |
595 | static int create_workqueues(struct hfi1_devdata *dd) | |
596 | { | |
597 | int pidx; | |
598 | struct hfi1_pportdata *ppd; | |
599 | ||
600 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
601 | ppd = dd->pport + pidx; | |
602 | if (!ppd->hfi1_wq) { | |
603 | char wq_name[8]; /* 3 + 2 + 1 + 1 + 1 */ | |
604 | ||
605 | snprintf(wq_name, sizeof(wq_name), "hfi%d_%d", | |
606 | dd->unit, pidx); | |
607 | ppd->hfi1_wq = | |
608 | create_singlethread_workqueue(wq_name); | |
609 | if (!ppd->hfi1_wq) | |
610 | goto wq_error; | |
611 | } | |
612 | } | |
613 | return 0; | |
614 | wq_error: | |
615 | pr_err("create_singlethread_workqueue failed for port %d\n", | |
616 | pidx + 1); | |
617 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
618 | ppd = dd->pport + pidx; | |
619 | if (ppd->hfi1_wq) { | |
620 | destroy_workqueue(ppd->hfi1_wq); | |
621 | ppd->hfi1_wq = NULL; | |
622 | } | |
623 | } | |
624 | return -ENOMEM; | |
625 | } | |
626 | ||
627 | /** | |
628 | * hfi1_init - do the actual initialization sequence on the chip | |
629 | * @dd: the hfi1_ib device | |
630 | * @reinit: re-initializing, so don't allocate new memory | |
631 | * | |
632 | * Do the actual initialization sequence on the chip. This is done | |
633 | * both from the init routine called from the PCI infrastructure, and | |
634 | * when we reset the chip, or detect that it was reset internally, | |
635 | * or it's administratively re-enabled. | |
636 | * | |
637 | * Memory allocation here and in called routines is only done in | |
638 | * the first case (reinit == 0). We have to be careful, because even | |
639 | * without memory allocation, we need to re-write all the chip registers | |
640 | * TIDs, etc. after the reset or enable has completed. | |
641 | */ | |
642 | int hfi1_init(struct hfi1_devdata *dd, int reinit) | |
643 | { | |
644 | int ret = 0, pidx, lastfail = 0; | |
645 | unsigned i, len; | |
646 | struct hfi1_ctxtdata *rcd; | |
647 | struct hfi1_pportdata *ppd; | |
648 | ||
649 | /* Set up recv low level handlers */ | |
650 | dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EXPECTED] = | |
651 | kdeth_process_expected; | |
652 | dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EAGER] = | |
653 | kdeth_process_eager; | |
654 | dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_IB] = process_receive_ib; | |
655 | dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_ERROR] = | |
656 | process_receive_error; | |
657 | dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_BYPASS] = | |
658 | process_receive_bypass; | |
659 | dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID5] = | |
660 | process_receive_invalid; | |
661 | dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID6] = | |
662 | process_receive_invalid; | |
663 | dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID7] = | |
664 | process_receive_invalid; | |
665 | dd->rhf_rcv_function_map = dd->normal_rhf_rcv_functions; | |
666 | ||
667 | /* Set up send low level handlers */ | |
668 | dd->process_pio_send = hfi1_verbs_send_pio; | |
669 | dd->process_dma_send = hfi1_verbs_send_dma; | |
670 | dd->pio_inline_send = pio_copy; | |
671 | ||
672 | if (is_a0(dd)) { | |
673 | atomic_set(&dd->drop_packet, DROP_PACKET_ON); | |
674 | dd->do_drop = 1; | |
675 | } else { | |
676 | atomic_set(&dd->drop_packet, DROP_PACKET_OFF); | |
677 | dd->do_drop = 0; | |
678 | } | |
679 | ||
680 | /* make sure the link is not "up" */ | |
681 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
682 | ppd = dd->pport + pidx; | |
683 | ppd->linkup = 0; | |
684 | } | |
685 | ||
686 | if (reinit) | |
687 | ret = init_after_reset(dd); | |
688 | else | |
689 | ret = loadtime_init(dd); | |
690 | if (ret) | |
691 | goto done; | |
692 | ||
693 | /* dd->rcd can be NULL if early initialization failed */ | |
694 | for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) { | |
695 | /* | |
696 | * Set up the (kernel) rcvhdr queue and egr TIDs. If doing | |
697 | * re-init, the simplest way to handle this is to free | |
698 | * existing, and re-allocate. | |
699 | * Need to re-create rest of ctxt 0 ctxtdata as well. | |
700 | */ | |
701 | rcd = dd->rcd[i]; | |
702 | if (!rcd) | |
703 | continue; | |
704 | ||
705 | rcd->do_interrupt = &handle_receive_interrupt; | |
706 | ||
707 | lastfail = hfi1_create_rcvhdrq(dd, rcd); | |
708 | if (!lastfail) | |
709 | lastfail = hfi1_setup_eagerbufs(rcd); | |
710 | if (lastfail) | |
711 | dd_dev_err(dd, | |
712 | "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n"); | |
713 | } | |
714 | if (lastfail) | |
715 | ret = lastfail; | |
716 | ||
717 | /* Allocate enough memory for user event notification. */ | |
718 | len = ALIGN(dd->chip_rcv_contexts * HFI1_MAX_SHARED_CTXTS * | |
719 | sizeof(*dd->events), PAGE_SIZE); | |
720 | dd->events = vmalloc_user(len); | |
721 | if (!dd->events) | |
722 | dd_dev_err(dd, "Failed to allocate user events page\n"); | |
723 | /* | |
724 | * Allocate a page for device and port status. | |
725 | * Page will be shared amongst all user processes. | |
726 | */ | |
727 | dd->status = vmalloc_user(PAGE_SIZE); | |
728 | if (!dd->status) | |
729 | dd_dev_err(dd, "Failed to allocate dev status page\n"); | |
730 | else | |
731 | dd->freezelen = PAGE_SIZE - (sizeof(*dd->status) - | |
732 | sizeof(dd->status->freezemsg)); | |
733 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
734 | ppd = dd->pport + pidx; | |
735 | if (dd->status) | |
736 | /* Currently, we only have one port */ | |
737 | ppd->statusp = &dd->status->port; | |
738 | ||
739 | set_mtu(ppd); | |
740 | } | |
741 | ||
742 | /* enable chip even if we have an error, so we can debug cause */ | |
743 | enable_chip(dd); | |
744 | ||
745 | ret = hfi1_cq_init(dd); | |
746 | done: | |
747 | /* | |
748 | * Set status even if port serdes is not initialized | |
749 | * so that diags will work. | |
750 | */ | |
751 | if (dd->status) | |
752 | dd->status->dev |= HFI1_STATUS_CHIP_PRESENT | | |
753 | HFI1_STATUS_INITTED; | |
754 | if (!ret) { | |
755 | /* enable all interrupts from the chip */ | |
756 | set_intr_state(dd, 1); | |
757 | ||
758 | /* chip is OK for user apps; mark it as initialized */ | |
759 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
760 | ppd = dd->pport + pidx; | |
761 | ||
762 | /* initialize the qsfp if it exists | |
763 | * Requires interrupts to be enabled so we are notified | |
764 | * when the QSFP completes reset, and has | |
765 | * to be done before bringing up the SERDES | |
766 | */ | |
767 | init_qsfp(ppd); | |
768 | ||
769 | /* start the serdes - must be after interrupts are | |
770 | enabled so we are notified when the link goes up */ | |
771 | lastfail = bringup_serdes(ppd); | |
772 | if (lastfail) | |
773 | dd_dev_info(dd, | |
774 | "Failed to bring up port %u\n", | |
775 | ppd->port); | |
776 | ||
777 | /* | |
778 | * Set status even if port serdes is not initialized | |
779 | * so that diags will work. | |
780 | */ | |
781 | if (ppd->statusp) | |
782 | *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT | | |
783 | HFI1_STATUS_INITTED; | |
784 | if (!ppd->link_speed_enabled) | |
785 | continue; | |
786 | } | |
787 | } | |
788 | ||
789 | /* if ret is non-zero, we probably should do some cleanup here... */ | |
790 | return ret; | |
791 | } | |
792 | ||
793 | static inline struct hfi1_devdata *__hfi1_lookup(int unit) | |
794 | { | |
795 | return idr_find(&hfi1_unit_table, unit); | |
796 | } | |
797 | ||
798 | struct hfi1_devdata *hfi1_lookup(int unit) | |
799 | { | |
800 | struct hfi1_devdata *dd; | |
801 | unsigned long flags; | |
802 | ||
803 | spin_lock_irqsave(&hfi1_devs_lock, flags); | |
804 | dd = __hfi1_lookup(unit); | |
805 | spin_unlock_irqrestore(&hfi1_devs_lock, flags); | |
806 | ||
807 | return dd; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Stop the timers during unit shutdown, or after an error late | |
812 | * in initialization. | |
813 | */ | |
814 | static void stop_timers(struct hfi1_devdata *dd) | |
815 | { | |
816 | struct hfi1_pportdata *ppd; | |
817 | int pidx; | |
818 | ||
819 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
820 | ppd = dd->pport + pidx; | |
821 | if (ppd->led_override_timer.data) { | |
822 | del_timer_sync(&ppd->led_override_timer); | |
823 | atomic_set(&ppd->led_override_timer_active, 0); | |
824 | } | |
825 | } | |
826 | } | |
827 | ||
828 | /** | |
829 | * shutdown_device - shut down a device | |
830 | * @dd: the hfi1_ib device | |
831 | * | |
832 | * This is called to make the device quiet when we are about to | |
833 | * unload the driver, and also when the device is administratively | |
834 | * disabled. It does not free any data structures. | |
835 | * Everything it does has to be setup again by hfi1_init(dd, 1) | |
836 | */ | |
837 | static void shutdown_device(struct hfi1_devdata *dd) | |
838 | { | |
839 | struct hfi1_pportdata *ppd; | |
840 | unsigned pidx; | |
841 | int i; | |
842 | ||
843 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
844 | ppd = dd->pport + pidx; | |
845 | ||
846 | ppd->linkup = 0; | |
847 | if (ppd->statusp) | |
848 | *ppd->statusp &= ~(HFI1_STATUS_IB_CONF | | |
849 | HFI1_STATUS_IB_READY); | |
850 | } | |
851 | dd->flags &= ~HFI1_INITTED; | |
852 | ||
853 | /* mask interrupts, but not errors */ | |
854 | set_intr_state(dd, 0); | |
855 | ||
856 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
857 | ppd = dd->pport + pidx; | |
858 | for (i = 0; i < dd->num_rcv_contexts; i++) | |
859 | hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS | | |
860 | HFI1_RCVCTRL_CTXT_DIS | | |
861 | HFI1_RCVCTRL_INTRAVAIL_DIS | | |
862 | HFI1_RCVCTRL_PKEY_DIS | | |
863 | HFI1_RCVCTRL_ONE_PKT_EGR_DIS, i); | |
864 | /* | |
865 | * Gracefully stop all sends allowing any in progress to | |
866 | * trickle out first. | |
867 | */ | |
868 | for (i = 0; i < dd->num_send_contexts; i++) | |
869 | sc_flush(dd->send_contexts[i].sc); | |
870 | } | |
871 | ||
872 | /* | |
873 | * Enough for anything that's going to trickle out to have actually | |
874 | * done so. | |
875 | */ | |
876 | udelay(20); | |
877 | ||
878 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
879 | ppd = dd->pport + pidx; | |
880 | ||
881 | /* disable all contexts */ | |
882 | for (i = 0; i < dd->num_send_contexts; i++) | |
883 | sc_disable(dd->send_contexts[i].sc); | |
884 | /* disable the send device */ | |
885 | pio_send_control(dd, PSC_GLOBAL_DISABLE); | |
886 | ||
887 | /* | |
888 | * Clear SerdesEnable. | |
889 | * We can't count on interrupts since we are stopping. | |
890 | */ | |
891 | hfi1_quiet_serdes(ppd); | |
892 | ||
893 | if (ppd->hfi1_wq) { | |
894 | destroy_workqueue(ppd->hfi1_wq); | |
895 | ppd->hfi1_wq = NULL; | |
896 | } | |
897 | } | |
898 | sdma_exit(dd); | |
899 | } | |
900 | ||
901 | /** | |
902 | * hfi1_free_ctxtdata - free a context's allocated data | |
903 | * @dd: the hfi1_ib device | |
904 | * @rcd: the ctxtdata structure | |
905 | * | |
906 | * free up any allocated data for a context | |
907 | * This should not touch anything that would affect a simultaneous | |
908 | * re-allocation of context data, because it is called after hfi1_mutex | |
909 | * is released (and can be called from reinit as well). | |
910 | * It should never change any chip state, or global driver state. | |
911 | */ | |
912 | void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) | |
913 | { | |
914 | unsigned e; | |
915 | ||
916 | if (!rcd) | |
917 | return; | |
918 | ||
919 | if (rcd->rcvhdrq) { | |
920 | dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size, | |
921 | rcd->rcvhdrq, rcd->rcvhdrq_phys); | |
922 | rcd->rcvhdrq = NULL; | |
923 | if (rcd->rcvhdrtail_kvaddr) { | |
924 | dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE, | |
925 | (void *)rcd->rcvhdrtail_kvaddr, | |
926 | rcd->rcvhdrqtailaddr_phys); | |
927 | rcd->rcvhdrtail_kvaddr = NULL; | |
928 | } | |
929 | } | |
930 | ||
931 | /* all the RcvArray entries should have been cleared by now */ | |
932 | kfree(rcd->egrbufs.rcvtids); | |
933 | ||
934 | for (e = 0; e < rcd->egrbufs.alloced; e++) { | |
935 | if (rcd->egrbufs.buffers[e].phys) | |
936 | dma_free_coherent(&dd->pcidev->dev, | |
937 | rcd->egrbufs.buffers[e].len, | |
938 | rcd->egrbufs.buffers[e].addr, | |
939 | rcd->egrbufs.buffers[e].phys); | |
940 | } | |
941 | kfree(rcd->egrbufs.buffers); | |
942 | ||
943 | sc_free(rcd->sc); | |
944 | vfree(rcd->physshadow); | |
945 | vfree(rcd->tid_pg_list); | |
946 | vfree(rcd->user_event_mask); | |
947 | vfree(rcd->subctxt_uregbase); | |
948 | vfree(rcd->subctxt_rcvegrbuf); | |
949 | vfree(rcd->subctxt_rcvhdr_base); | |
950 | kfree(rcd->tidusemap); | |
951 | kfree(rcd->opstats); | |
952 | kfree(rcd); | |
953 | } | |
954 | ||
955 | void hfi1_free_devdata(struct hfi1_devdata *dd) | |
956 | { | |
957 | unsigned long flags; | |
958 | ||
959 | spin_lock_irqsave(&hfi1_devs_lock, flags); | |
960 | idr_remove(&hfi1_unit_table, dd->unit); | |
961 | list_del(&dd->list); | |
962 | spin_unlock_irqrestore(&hfi1_devs_lock, flags); | |
963 | hfi1_dbg_ibdev_exit(&dd->verbs_dev); | |
964 | rcu_barrier(); /* wait for rcu callbacks to complete */ | |
965 | free_percpu(dd->int_counter); | |
966 | free_percpu(dd->rcv_limit); | |
967 | ib_dealloc_device(&dd->verbs_dev.ibdev); | |
968 | } | |
969 | ||
970 | /* | |
971 | * Allocate our primary per-unit data structure. Must be done via verbs | |
972 | * allocator, because the verbs cleanup process both does cleanup and | |
973 | * free of the data structure. | |
974 | * "extra" is for chip-specific data. | |
975 | * | |
976 | * Use the idr mechanism to get a unit number for this unit. | |
977 | */ | |
978 | struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra) | |
979 | { | |
980 | unsigned long flags; | |
981 | struct hfi1_devdata *dd; | |
982 | int ret; | |
983 | ||
984 | dd = (struct hfi1_devdata *)ib_alloc_device(sizeof(*dd) + extra); | |
985 | if (!dd) | |
986 | return ERR_PTR(-ENOMEM); | |
987 | /* extra is * number of ports */ | |
988 | dd->num_pports = extra / sizeof(struct hfi1_pportdata); | |
989 | dd->pport = (struct hfi1_pportdata *)(dd + 1); | |
990 | ||
991 | INIT_LIST_HEAD(&dd->list); | |
992 | dd->node = dev_to_node(&pdev->dev); | |
993 | if (dd->node < 0) | |
994 | dd->node = 0; | |
995 | idr_preload(GFP_KERNEL); | |
996 | spin_lock_irqsave(&hfi1_devs_lock, flags); | |
997 | ||
998 | ret = idr_alloc(&hfi1_unit_table, dd, 0, 0, GFP_NOWAIT); | |
999 | if (ret >= 0) { | |
1000 | dd->unit = ret; | |
1001 | list_add(&dd->list, &hfi1_dev_list); | |
1002 | } | |
1003 | ||
1004 | spin_unlock_irqrestore(&hfi1_devs_lock, flags); | |
1005 | idr_preload_end(); | |
1006 | ||
1007 | if (ret < 0) { | |
1008 | hfi1_early_err(&pdev->dev, | |
1009 | "Could not allocate unit ID: error %d\n", -ret); | |
1010 | goto bail; | |
1011 | } | |
1012 | /* | |
1013 | * Initialize all locks for the device. This needs to be as early as | |
1014 | * possible so locks are usable. | |
1015 | */ | |
1016 | spin_lock_init(&dd->sc_lock); | |
1017 | spin_lock_init(&dd->sendctrl_lock); | |
1018 | spin_lock_init(&dd->rcvctrl_lock); | |
1019 | spin_lock_init(&dd->uctxt_lock); | |
1020 | spin_lock_init(&dd->hfi1_diag_trans_lock); | |
1021 | spin_lock_init(&dd->sc_init_lock); | |
1022 | spin_lock_init(&dd->dc8051_lock); | |
1023 | spin_lock_init(&dd->dc8051_memlock); | |
1024 | mutex_init(&dd->qsfp_i2c_mutex); | |
1025 | seqlock_init(&dd->sc2vl_lock); | |
1026 | spin_lock_init(&dd->sde_map_lock); | |
1027 | init_waitqueue_head(&dd->event_queue); | |
1028 | ||
1029 | dd->int_counter = alloc_percpu(u64); | |
1030 | if (!dd->int_counter) { | |
1031 | ret = -ENOMEM; | |
1032 | hfi1_early_err(&pdev->dev, | |
1033 | "Could not allocate per-cpu int_counter\n"); | |
1034 | goto bail; | |
1035 | } | |
1036 | ||
1037 | dd->rcv_limit = alloc_percpu(u64); | |
1038 | if (!dd->rcv_limit) { | |
1039 | ret = -ENOMEM; | |
1040 | hfi1_early_err(&pdev->dev, | |
1041 | "Could not allocate per-cpu rcv_limit\n"); | |
1042 | goto bail; | |
1043 | } | |
1044 | ||
1045 | if (!hfi1_cpulist_count) { | |
1046 | u32 count = num_online_cpus(); | |
1047 | ||
314fcc0d SB |
1048 | hfi1_cpulist = kcalloc(BITS_TO_LONGS(count), sizeof(long), |
1049 | GFP_KERNEL); | |
77241056 MM |
1050 | if (hfi1_cpulist) |
1051 | hfi1_cpulist_count = count; | |
1052 | else | |
1053 | hfi1_early_err( | |
1054 | &pdev->dev, | |
1055 | "Could not alloc cpulist info, cpu affinity might be wrong\n"); | |
1056 | } | |
1057 | hfi1_dbg_ibdev_init(&dd->verbs_dev); | |
1058 | return dd; | |
1059 | ||
1060 | bail: | |
1061 | if (!list_empty(&dd->list)) | |
1062 | list_del_init(&dd->list); | |
1063 | ib_dealloc_device(&dd->verbs_dev.ibdev); | |
1064 | return ERR_PTR(ret); | |
1065 | } | |
1066 | ||
1067 | /* | |
1068 | * Called from freeze mode handlers, and from PCI error | |
1069 | * reporting code. Should be paranoid about state of | |
1070 | * system and data structures. | |
1071 | */ | |
1072 | void hfi1_disable_after_error(struct hfi1_devdata *dd) | |
1073 | { | |
1074 | if (dd->flags & HFI1_INITTED) { | |
1075 | u32 pidx; | |
1076 | ||
1077 | dd->flags &= ~HFI1_INITTED; | |
1078 | if (dd->pport) | |
1079 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
1080 | struct hfi1_pportdata *ppd; | |
1081 | ||
1082 | ppd = dd->pport + pidx; | |
1083 | if (dd->flags & HFI1_PRESENT) | |
1084 | set_link_state(ppd, HLS_DN_DISABLE); | |
1085 | ||
1086 | if (ppd->statusp) | |
1087 | *ppd->statusp &= ~HFI1_STATUS_IB_READY; | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * Mark as having had an error for driver, and also | |
1093 | * for /sys and status word mapped to user programs. | |
1094 | * This marks unit as not usable, until reset. | |
1095 | */ | |
1096 | if (dd->status) | |
1097 | dd->status->dev |= HFI1_STATUS_HWERROR; | |
1098 | } | |
1099 | ||
1100 | static void remove_one(struct pci_dev *); | |
1101 | static int init_one(struct pci_dev *, const struct pci_device_id *); | |
1102 | ||
1103 | #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: " | |
1104 | #define PFX DRIVER_NAME ": " | |
1105 | ||
1106 | static const struct pci_device_id hfi1_pci_tbl[] = { | |
1107 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) }, | |
1108 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) }, | |
1109 | { 0, } | |
1110 | }; | |
1111 | ||
1112 | MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl); | |
1113 | ||
1114 | static struct pci_driver hfi1_pci_driver = { | |
1115 | .name = DRIVER_NAME, | |
1116 | .probe = init_one, | |
1117 | .remove = remove_one, | |
1118 | .id_table = hfi1_pci_tbl, | |
1119 | .err_handler = &hfi1_pci_err_handler, | |
1120 | }; | |
1121 | ||
1122 | static void __init compute_krcvqs(void) | |
1123 | { | |
1124 | int i; | |
1125 | ||
1126 | for (i = 0; i < krcvqsset; i++) | |
1127 | n_krcvqs += krcvqs[i]; | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * Do all the generic driver unit- and chip-independent memory | |
1132 | * allocation and initialization. | |
1133 | */ | |
1134 | static int __init hfi1_mod_init(void) | |
1135 | { | |
1136 | int ret; | |
1137 | ||
1138 | ret = dev_init(); | |
1139 | if (ret) | |
1140 | goto bail; | |
1141 | ||
1142 | /* validate max MTU before any devices start */ | |
1143 | if (!valid_opa_max_mtu(hfi1_max_mtu)) { | |
1144 | pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n", | |
1145 | hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU); | |
1146 | hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU; | |
1147 | } | |
1148 | /* valid CUs run from 1-128 in powers of 2 */ | |
1149 | if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu)) | |
1150 | hfi1_cu = 1; | |
1151 | /* valid credit return threshold is 0-100, variable is unsigned */ | |
1152 | if (user_credit_return_threshold > 100) | |
1153 | user_credit_return_threshold = 100; | |
1154 | ||
1155 | compute_krcvqs(); | |
1156 | /* sanitize receive interrupt count, time must wait until after | |
1157 | the hardware type is known */ | |
1158 | if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK) | |
1159 | rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK; | |
1160 | /* reject invalid combinations */ | |
1161 | if (rcv_intr_count == 0 && rcv_intr_timeout == 0) { | |
1162 | pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n"); | |
1163 | rcv_intr_count = 1; | |
1164 | } | |
1165 | if (rcv_intr_count > 1 && rcv_intr_timeout == 0) { | |
1166 | /* | |
1167 | * Avoid indefinite packet delivery by requiring a timeout | |
1168 | * if count is > 1. | |
1169 | */ | |
1170 | pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n"); | |
1171 | rcv_intr_timeout = 1; | |
1172 | } | |
1173 | if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) { | |
1174 | /* | |
1175 | * The dynamic algorithm expects a non-zero timeout | |
1176 | * and a count > 1. | |
1177 | */ | |
1178 | pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n"); | |
1179 | rcv_intr_dynamic = 0; | |
1180 | } | |
1181 | ||
1182 | /* sanitize link CRC options */ | |
1183 | link_crc_mask &= SUPPORTED_CRCS; | |
1184 | ||
1185 | /* | |
1186 | * These must be called before the driver is registered with | |
1187 | * the PCI subsystem. | |
1188 | */ | |
1189 | idr_init(&hfi1_unit_table); | |
1190 | ||
1191 | hfi1_dbg_init(); | |
1192 | ret = pci_register_driver(&hfi1_pci_driver); | |
1193 | if (ret < 0) { | |
1194 | pr_err("Unable to register driver: error %d\n", -ret); | |
1195 | goto bail_dev; | |
1196 | } | |
1197 | goto bail; /* all OK */ | |
1198 | ||
1199 | bail_dev: | |
1200 | hfi1_dbg_exit(); | |
1201 | idr_destroy(&hfi1_unit_table); | |
1202 | dev_cleanup(); | |
1203 | bail: | |
1204 | return ret; | |
1205 | } | |
1206 | ||
1207 | module_init(hfi1_mod_init); | |
1208 | ||
1209 | /* | |
1210 | * Do the non-unit driver cleanup, memory free, etc. at unload. | |
1211 | */ | |
1212 | static void __exit hfi1_mod_cleanup(void) | |
1213 | { | |
1214 | pci_unregister_driver(&hfi1_pci_driver); | |
1215 | hfi1_dbg_exit(); | |
1216 | hfi1_cpulist_count = 0; | |
1217 | kfree(hfi1_cpulist); | |
1218 | ||
1219 | idr_destroy(&hfi1_unit_table); | |
1220 | dispose_firmware(); /* asymmetric with obtain_firmware() */ | |
1221 | dev_cleanup(); | |
1222 | } | |
1223 | ||
1224 | module_exit(hfi1_mod_cleanup); | |
1225 | ||
1226 | /* this can only be called after a successful initialization */ | |
1227 | static void cleanup_device_data(struct hfi1_devdata *dd) | |
1228 | { | |
1229 | int ctxt; | |
1230 | int pidx; | |
1231 | struct hfi1_ctxtdata **tmp; | |
1232 | unsigned long flags; | |
1233 | ||
1234 | /* users can't do anything more with chip */ | |
1235 | for (pidx = 0; pidx < dd->num_pports; ++pidx) { | |
1236 | struct hfi1_pportdata *ppd = &dd->pport[pidx]; | |
1237 | struct cc_state *cc_state; | |
1238 | int i; | |
1239 | ||
1240 | if (ppd->statusp) | |
1241 | *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT; | |
1242 | ||
1243 | for (i = 0; i < OPA_MAX_SLS; i++) | |
1244 | hrtimer_cancel(&ppd->cca_timer[i].hrtimer); | |
1245 | ||
1246 | spin_lock(&ppd->cc_state_lock); | |
1247 | cc_state = get_cc_state(ppd); | |
1248 | rcu_assign_pointer(ppd->cc_state, NULL); | |
1249 | spin_unlock(&ppd->cc_state_lock); | |
1250 | ||
1251 | if (cc_state) | |
1252 | call_rcu(&cc_state->rcu, cc_state_reclaim); | |
1253 | } | |
1254 | ||
1255 | free_credit_return(dd); | |
1256 | ||
1257 | /* | |
1258 | * Free any resources still in use (usually just kernel contexts) | |
1259 | * at unload; we do for ctxtcnt, because that's what we allocate. | |
1260 | * We acquire lock to be really paranoid that rcd isn't being | |
1261 | * accessed from some interrupt-related code (that should not happen, | |
1262 | * but best to be sure). | |
1263 | */ | |
1264 | spin_lock_irqsave(&dd->uctxt_lock, flags); | |
1265 | tmp = dd->rcd; | |
1266 | dd->rcd = NULL; | |
1267 | spin_unlock_irqrestore(&dd->uctxt_lock, flags); | |
1268 | for (ctxt = 0; tmp && ctxt < dd->num_rcv_contexts; ctxt++) { | |
1269 | struct hfi1_ctxtdata *rcd = tmp[ctxt]; | |
1270 | ||
1271 | tmp[ctxt] = NULL; /* debugging paranoia */ | |
1272 | if (rcd) { | |
1273 | hfi1_clear_tids(rcd); | |
1274 | hfi1_free_ctxtdata(dd, rcd); | |
1275 | } | |
1276 | } | |
1277 | kfree(tmp); | |
1278 | /* must follow rcv context free - need to remove rcv's hooks */ | |
1279 | for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++) | |
1280 | sc_free(dd->send_contexts[ctxt].sc); | |
1281 | dd->num_send_contexts = 0; | |
1282 | kfree(dd->send_contexts); | |
1283 | dd->send_contexts = NULL; | |
1284 | kfree(dd->boardname); | |
1285 | vfree(dd->events); | |
1286 | vfree(dd->status); | |
1287 | hfi1_cq_exit(dd); | |
1288 | } | |
1289 | ||
1290 | /* | |
1291 | * Clean up on unit shutdown, or error during unit load after | |
1292 | * successful initialization. | |
1293 | */ | |
1294 | static void postinit_cleanup(struct hfi1_devdata *dd) | |
1295 | { | |
1296 | hfi1_start_cleanup(dd); | |
1297 | ||
1298 | hfi1_pcie_ddcleanup(dd); | |
1299 | hfi1_pcie_cleanup(dd->pcidev); | |
1300 | ||
1301 | cleanup_device_data(dd); | |
1302 | ||
1303 | hfi1_free_devdata(dd); | |
1304 | } | |
1305 | ||
1306 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1307 | { | |
1308 | int ret = 0, j, pidx, initfail; | |
1309 | struct hfi1_devdata *dd = NULL; | |
1310 | ||
1311 | /* First, lock the non-writable module parameters */ | |
1312 | HFI1_CAP_LOCK(); | |
1313 | ||
1314 | /* Validate some global module parameters */ | |
1315 | if (rcvhdrcnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) { | |
1316 | hfi1_early_err(&pdev->dev, "Header queue count too small\n"); | |
1317 | ret = -EINVAL; | |
1318 | goto bail; | |
1319 | } | |
1320 | /* use the encoding function as a sanitization check */ | |
1321 | if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) { | |
1322 | hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n", | |
1323 | hfi1_hdrq_entsize); | |
1324 | goto bail; | |
1325 | } | |
1326 | ||
1327 | /* The receive eager buffer size must be set before the receive | |
1328 | * contexts are created. | |
1329 | * | |
1330 | * Set the eager buffer size. Validate that it falls in a range | |
1331 | * allowed by the hardware - all powers of 2 between the min and | |
1332 | * max. The maximum valid MTU is within the eager buffer range | |
1333 | * so we do not need to cap the max_mtu by an eager buffer size | |
1334 | * setting. | |
1335 | */ | |
1336 | if (eager_buffer_size) { | |
1337 | if (!is_power_of_2(eager_buffer_size)) | |
1338 | eager_buffer_size = | |
1339 | roundup_pow_of_two(eager_buffer_size); | |
1340 | eager_buffer_size = | |
1341 | clamp_val(eager_buffer_size, | |
1342 | MIN_EAGER_BUFFER * 8, | |
1343 | MAX_EAGER_BUFFER_TOTAL); | |
1344 | hfi1_early_info(&pdev->dev, "Eager buffer size %u\n", | |
1345 | eager_buffer_size); | |
1346 | } else { | |
1347 | hfi1_early_err(&pdev->dev, "Invalid Eager buffer size of 0\n"); | |
1348 | ret = -EINVAL; | |
1349 | goto bail; | |
1350 | } | |
1351 | ||
1352 | /* restrict value of hfi1_rcvarr_split */ | |
1353 | hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100); | |
1354 | ||
1355 | ret = hfi1_pcie_init(pdev, ent); | |
1356 | if (ret) | |
1357 | goto bail; | |
1358 | ||
1359 | /* | |
1360 | * Do device-specific initialization, function table setup, dd | |
1361 | * allocation, etc. | |
1362 | */ | |
1363 | switch (ent->device) { | |
1364 | case PCI_DEVICE_ID_INTEL0: | |
1365 | case PCI_DEVICE_ID_INTEL1: | |
1366 | dd = hfi1_init_dd(pdev, ent); | |
1367 | break; | |
1368 | default: | |
1369 | hfi1_early_err(&pdev->dev, | |
1370 | "Failing on unknown Intel deviceid 0x%x\n", | |
1371 | ent->device); | |
1372 | ret = -ENODEV; | |
1373 | } | |
1374 | ||
1375 | if (IS_ERR(dd)) | |
1376 | ret = PTR_ERR(dd); | |
1377 | if (ret) | |
1378 | goto clean_bail; /* error already printed */ | |
1379 | ||
1380 | ret = create_workqueues(dd); | |
1381 | if (ret) | |
1382 | goto clean_bail; | |
1383 | ||
1384 | /* do the generic initialization */ | |
1385 | initfail = hfi1_init(dd, 0); | |
1386 | ||
1387 | ret = hfi1_register_ib_device(dd); | |
1388 | ||
1389 | /* | |
1390 | * Now ready for use. this should be cleared whenever we | |
1391 | * detect a reset, or initiate one. If earlier failure, | |
1392 | * we still create devices, so diags, etc. can be used | |
1393 | * to determine cause of problem. | |
1394 | */ | |
1395 | if (!initfail && !ret) | |
1396 | dd->flags |= HFI1_INITTED; | |
1397 | ||
1398 | j = hfi1_device_create(dd); | |
1399 | if (j) | |
1400 | dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j); | |
1401 | ||
1402 | if (initfail || ret) { | |
1403 | stop_timers(dd); | |
1404 | flush_workqueue(ib_wq); | |
1405 | for (pidx = 0; pidx < dd->num_pports; ++pidx) | |
1406 | hfi1_quiet_serdes(dd->pport + pidx); | |
1407 | if (!j) | |
1408 | hfi1_device_remove(dd); | |
1409 | if (!ret) | |
1410 | hfi1_unregister_ib_device(dd); | |
1411 | postinit_cleanup(dd); | |
1412 | if (initfail) | |
1413 | ret = initfail; | |
1414 | goto bail; /* everything already cleaned */ | |
1415 | } | |
1416 | ||
1417 | sdma_start(dd); | |
1418 | ||
1419 | return 0; | |
1420 | ||
1421 | clean_bail: | |
1422 | hfi1_pcie_cleanup(pdev); | |
1423 | bail: | |
1424 | return ret; | |
1425 | } | |
1426 | ||
1427 | static void remove_one(struct pci_dev *pdev) | |
1428 | { | |
1429 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
1430 | ||
1431 | /* unregister from IB core */ | |
1432 | hfi1_unregister_ib_device(dd); | |
1433 | ||
1434 | /* | |
1435 | * Disable the IB link, disable interrupts on the device, | |
1436 | * clear dma engines, etc. | |
1437 | */ | |
1438 | shutdown_device(dd); | |
1439 | ||
1440 | stop_timers(dd); | |
1441 | ||
1442 | /* wait until all of our (qsfp) queue_work() calls complete */ | |
1443 | flush_workqueue(ib_wq); | |
1444 | ||
1445 | hfi1_device_remove(dd); | |
1446 | ||
1447 | postinit_cleanup(dd); | |
1448 | } | |
1449 | ||
1450 | /** | |
1451 | * hfi1_create_rcvhdrq - create a receive header queue | |
1452 | * @dd: the hfi1_ib device | |
1453 | * @rcd: the context data | |
1454 | * | |
1455 | * This must be contiguous memory (from an i/o perspective), and must be | |
1456 | * DMA'able (which means for some systems, it will go through an IOMMU, | |
1457 | * or be forced into a low address range). | |
1458 | */ | |
1459 | int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) | |
1460 | { | |
1461 | unsigned amt; | |
1462 | u64 reg; | |
1463 | ||
1464 | if (!rcd->rcvhdrq) { | |
1465 | dma_addr_t phys_hdrqtail; | |
1466 | gfp_t gfp_flags; | |
1467 | ||
1468 | /* | |
1469 | * rcvhdrqentsize is in DWs, so we have to convert to bytes | |
1470 | * (* sizeof(u32)). | |
1471 | */ | |
1472 | amt = ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize * | |
1473 | sizeof(u32), PAGE_SIZE); | |
1474 | ||
1475 | gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ? | |
1476 | GFP_USER : GFP_KERNEL; | |
1477 | rcd->rcvhdrq = dma_zalloc_coherent( | |
1478 | &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys, | |
1479 | gfp_flags | __GFP_COMP); | |
1480 | ||
1481 | if (!rcd->rcvhdrq) { | |
1482 | dd_dev_err(dd, | |
1483 | "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n", | |
1484 | amt, rcd->ctxt); | |
1485 | goto bail; | |
1486 | } | |
1487 | ||
1488 | /* Event mask is per device now and is in hfi1_devdata */ | |
1489 | /*if (rcd->ctxt >= dd->first_user_ctxt) { | |
1490 | rcd->user_event_mask = vmalloc_user(PAGE_SIZE); | |
1491 | if (!rcd->user_event_mask) | |
1492 | goto bail_free_hdrq; | |
1493 | }*/ | |
1494 | ||
1495 | if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) { | |
1496 | rcd->rcvhdrtail_kvaddr = dma_zalloc_coherent( | |
1497 | &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, | |
1498 | gfp_flags); | |
1499 | if (!rcd->rcvhdrtail_kvaddr) | |
1500 | goto bail_free; | |
1501 | rcd->rcvhdrqtailaddr_phys = phys_hdrqtail; | |
1502 | } | |
1503 | ||
1504 | rcd->rcvhdrq_size = amt; | |
1505 | } | |
1506 | /* | |
1507 | * These values are per-context: | |
1508 | * RcvHdrCnt | |
1509 | * RcvHdrEntSize | |
1510 | * RcvHdrSize | |
1511 | */ | |
1512 | reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT) | |
1513 | & RCV_HDR_CNT_CNT_MASK) | |
1514 | << RCV_HDR_CNT_CNT_SHIFT; | |
1515 | write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg); | |
1516 | reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize) | |
1517 | & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) | |
1518 | << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT; | |
1519 | write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg); | |
1520 | reg = (dd->rcvhdrsize & RCV_HDR_SIZE_HDR_SIZE_MASK) | |
1521 | << RCV_HDR_SIZE_HDR_SIZE_SHIFT; | |
1522 | write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg); | |
1523 | return 0; | |
1524 | ||
1525 | bail_free: | |
1526 | dd_dev_err(dd, | |
1527 | "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n", | |
1528 | rcd->ctxt); | |
1529 | vfree(rcd->user_event_mask); | |
1530 | rcd->user_event_mask = NULL; | |
1531 | dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq, | |
1532 | rcd->rcvhdrq_phys); | |
1533 | rcd->rcvhdrq = NULL; | |
1534 | bail: | |
1535 | return -ENOMEM; | |
1536 | } | |
1537 | ||
1538 | /** | |
1539 | * allocate eager buffers, both kernel and user contexts. | |
1540 | * @rcd: the context we are setting up. | |
1541 | * | |
1542 | * Allocate the eager TID buffers and program them into hip. | |
1543 | * They are no longer completely contiguous, we do multiple allocation | |
1544 | * calls. Otherwise we get the OOM code involved, by asking for too | |
1545 | * much per call, with disastrous results on some kernels. | |
1546 | */ | |
1547 | int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd) | |
1548 | { | |
1549 | struct hfi1_devdata *dd = rcd->dd; | |
1550 | u32 max_entries, egrtop, alloced_bytes = 0, idx = 0; | |
1551 | gfp_t gfp_flags; | |
1552 | u16 order; | |
1553 | int ret = 0; | |
1554 | u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu); | |
1555 | ||
1556 | /* | |
1557 | * GFP_USER, but without GFP_FS, so buffer cache can be | |
1558 | * coalesced (we hope); otherwise, even at order 4, | |
1559 | * heavy filesystem activity makes these fail, and we can | |
1560 | * use compound pages. | |
1561 | */ | |
1562 | gfp_flags = __GFP_WAIT | __GFP_IO | __GFP_COMP; | |
1563 | ||
1564 | /* | |
1565 | * The minimum size of the eager buffers is a groups of MTU-sized | |
1566 | * buffers. | |
1567 | * The global eager_buffer_size parameter is checked against the | |
1568 | * theoretical lower limit of the value. Here, we check against the | |
1569 | * MTU. | |
1570 | */ | |
1571 | if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size)) | |
1572 | rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size; | |
1573 | /* | |
1574 | * If using one-pkt-per-egr-buffer, lower the eager buffer | |
1575 | * size to the max MTU (page-aligned). | |
1576 | */ | |
1577 | if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) | |
1578 | rcd->egrbufs.rcvtid_size = round_mtu; | |
1579 | ||
1580 | /* | |
1581 | * Eager buffers sizes of 1MB or less require smaller TID sizes | |
1582 | * to satisfy the "multiple of 8 RcvArray entries" requirement. | |
1583 | */ | |
1584 | if (rcd->egrbufs.size <= (1 << 20)) | |
1585 | rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu, | |
1586 | rounddown_pow_of_two(rcd->egrbufs.size / 8)); | |
1587 | ||
1588 | while (alloced_bytes < rcd->egrbufs.size && | |
1589 | rcd->egrbufs.alloced < rcd->egrbufs.count) { | |
1590 | rcd->egrbufs.buffers[idx].addr = | |
1591 | dma_zalloc_coherent(&dd->pcidev->dev, | |
1592 | rcd->egrbufs.rcvtid_size, | |
1593 | &rcd->egrbufs.buffers[idx].phys, | |
1594 | gfp_flags); | |
1595 | if (rcd->egrbufs.buffers[idx].addr) { | |
1596 | rcd->egrbufs.buffers[idx].len = | |
1597 | rcd->egrbufs.rcvtid_size; | |
1598 | rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr = | |
1599 | rcd->egrbufs.buffers[idx].addr; | |
1600 | rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].phys = | |
1601 | rcd->egrbufs.buffers[idx].phys; | |
1602 | rcd->egrbufs.alloced++; | |
1603 | alloced_bytes += rcd->egrbufs.rcvtid_size; | |
1604 | idx++; | |
1605 | } else { | |
1606 | u32 new_size, i, j; | |
1607 | u64 offset = 0; | |
1608 | ||
1609 | /* | |
1610 | * Fail the eager buffer allocation if: | |
1611 | * - we are already using the lowest acceptable size | |
1612 | * - we are using one-pkt-per-egr-buffer (this implies | |
1613 | * that we are accepting only one size) | |
1614 | */ | |
1615 | if (rcd->egrbufs.rcvtid_size == round_mtu || | |
1616 | !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) { | |
1617 | dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n", | |
1618 | rcd->ctxt); | |
1619 | goto bail_rcvegrbuf_phys; | |
1620 | } | |
1621 | ||
1622 | new_size = rcd->egrbufs.rcvtid_size / 2; | |
1623 | ||
1624 | /* | |
1625 | * If the first attempt to allocate memory failed, don't | |
1626 | * fail everything but continue with the next lower | |
1627 | * size. | |
1628 | */ | |
1629 | if (idx == 0) { | |
1630 | rcd->egrbufs.rcvtid_size = new_size; | |
1631 | continue; | |
1632 | } | |
1633 | ||
1634 | /* | |
1635 | * Re-partition already allocated buffers to a smaller | |
1636 | * size. | |
1637 | */ | |
1638 | rcd->egrbufs.alloced = 0; | |
1639 | for (i = 0, j = 0, offset = 0; j < idx; i++) { | |
1640 | if (i >= rcd->egrbufs.count) | |
1641 | break; | |
1642 | rcd->egrbufs.rcvtids[i].phys = | |
1643 | rcd->egrbufs.buffers[j].phys + offset; | |
1644 | rcd->egrbufs.rcvtids[i].addr = | |
1645 | rcd->egrbufs.buffers[j].addr + offset; | |
1646 | rcd->egrbufs.alloced++; | |
1647 | if ((rcd->egrbufs.buffers[j].phys + offset + | |
1648 | new_size) == | |
1649 | (rcd->egrbufs.buffers[j].phys + | |
1650 | rcd->egrbufs.buffers[j].len)) { | |
1651 | j++; | |
1652 | offset = 0; | |
1653 | } else | |
1654 | offset += new_size; | |
1655 | } | |
1656 | rcd->egrbufs.rcvtid_size = new_size; | |
1657 | } | |
1658 | } | |
1659 | rcd->egrbufs.numbufs = idx; | |
1660 | rcd->egrbufs.size = alloced_bytes; | |
1661 | ||
1662 | dd_dev_info(dd, "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n", | |
1663 | rcd->ctxt, rcd->egrbufs.alloced, rcd->egrbufs.rcvtid_size, | |
1664 | rcd->egrbufs.size); | |
1665 | ||
1666 | /* | |
1667 | * Set the contexts rcv array head update threshold to the closest | |
1668 | * power of 2 (so we can use a mask instead of modulo) below half | |
1669 | * the allocated entries. | |
1670 | */ | |
1671 | rcd->egrbufs.threshold = | |
1672 | rounddown_pow_of_two(rcd->egrbufs.alloced / 2); | |
1673 | /* | |
1674 | * Compute the expected RcvArray entry base. This is done after | |
1675 | * allocating the eager buffers in order to maximize the | |
1676 | * expected RcvArray entries for the context. | |
1677 | */ | |
1678 | max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size; | |
1679 | egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size); | |
1680 | rcd->expected_count = max_entries - egrtop; | |
1681 | if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2) | |
1682 | rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2; | |
1683 | ||
1684 | rcd->expected_base = rcd->eager_base + egrtop; | |
1685 | dd_dev_info(dd, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n", | |
1686 | rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count, | |
1687 | rcd->eager_base, rcd->expected_base); | |
1688 | ||
1689 | if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) { | |
1690 | dd_dev_err(dd, "ctxt%u: current Eager buffer size is invalid %u\n", | |
1691 | rcd->ctxt, rcd->egrbufs.rcvtid_size); | |
1692 | ret = -EINVAL; | |
1693 | goto bail; | |
1694 | } | |
1695 | ||
1696 | for (idx = 0; idx < rcd->egrbufs.alloced; idx++) { | |
1697 | hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER, | |
1698 | rcd->egrbufs.rcvtids[idx].phys, order); | |
1699 | cond_resched(); | |
1700 | } | |
1701 | goto bail; | |
1702 | ||
1703 | bail_rcvegrbuf_phys: | |
1704 | for (idx = 0; idx < rcd->egrbufs.alloced && | |
1705 | rcd->egrbufs.buffers[idx].addr; | |
1706 | idx++) { | |
1707 | dma_free_coherent(&dd->pcidev->dev, | |
1708 | rcd->egrbufs.buffers[idx].len, | |
1709 | rcd->egrbufs.buffers[idx].addr, | |
1710 | rcd->egrbufs.buffers[idx].phys); | |
1711 | rcd->egrbufs.buffers[idx].addr = NULL; | |
1712 | rcd->egrbufs.buffers[idx].phys = 0; | |
1713 | rcd->egrbufs.buffers[idx].len = 0; | |
1714 | } | |
1715 | bail: | |
1716 | return ret; | |
1717 | } |