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77241056 MM |
1 | /* |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2015 Intel Corporation. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * BSD LICENSE | |
20 | * | |
21 | * Copyright(c) 2015 Intel Corporation. | |
22 | * | |
23 | * Redistribution and use in source and binary forms, with or without | |
24 | * modification, are permitted provided that the following conditions | |
25 | * are met: | |
26 | * | |
27 | * - Redistributions of source code must retain the above copyright | |
28 | * notice, this list of conditions and the following disclaimer. | |
29 | * - Redistributions in binary form must reproduce the above copyright | |
30 | * notice, this list of conditions and the following disclaimer in | |
31 | * the documentation and/or other materials provided with the | |
32 | * distribution. | |
33 | * - Neither the name of Intel Corporation nor the names of its | |
34 | * contributors may be used to endorse or promote products derived | |
35 | * from this software without specific prior written permission. | |
36 | * | |
37 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
38 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
39 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
40 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
41 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
42 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
43 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
44 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
45 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
46 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
48 | * | |
49 | */ | |
50 | ||
51 | #include <linux/pci.h> | |
52 | #include <linux/io.h> | |
53 | #include <linux/delay.h> | |
54 | #include <linux/vmalloc.h> | |
55 | #include <linux/aer.h> | |
56 | #include <linux/module.h> | |
57 | ||
58 | #include "hfi.h" | |
59 | #include "chip_registers.h" | |
60 | ||
61 | /* link speed vector for Gen3 speed - not in Linux headers */ | |
62 | #define GEN1_SPEED_VECTOR 0x1 | |
63 | #define GEN2_SPEED_VECTOR 0x2 | |
64 | #define GEN3_SPEED_VECTOR 0x3 | |
65 | ||
66 | /* | |
67 | * This file contains PCIe utility routines. | |
68 | */ | |
69 | ||
70 | /* | |
71 | * Code to adjust PCIe capabilities. | |
72 | */ | |
73 | static void tune_pcie_caps(struct hfi1_devdata *); | |
74 | ||
75 | /* | |
76 | * Do all the common PCIe setup and initialization. | |
77 | * devdata is not yet allocated, and is not allocated until after this | |
78 | * routine returns success. Therefore dd_dev_err() can't be used for error | |
79 | * printing. | |
80 | */ | |
81 | int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) | |
82 | { | |
83 | int ret; | |
84 | ||
85 | ret = pci_enable_device(pdev); | |
86 | if (ret) { | |
87 | /* | |
88 | * This can happen (in theory) iff: | |
89 | * We did a chip reset, and then failed to reprogram the | |
90 | * BAR, or the chip reset due to an internal error. We then | |
91 | * unloaded the driver and reloaded it. | |
92 | * | |
93 | * Both reset cases set the BAR back to initial state. For | |
94 | * the latter case, the AER sticky error bit at offset 0x718 | |
95 | * should be set, but the Linux kernel doesn't yet know | |
96 | * about that, it appears. If the original BAR was retained | |
97 | * in the kernel data structures, this may be OK. | |
98 | */ | |
99 | hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n", | |
100 | -ret); | |
101 | goto done; | |
102 | } | |
103 | ||
104 | ret = pci_request_regions(pdev, DRIVER_NAME); | |
105 | if (ret) { | |
106 | hfi1_early_err(&pdev->dev, | |
107 | "pci_request_regions fails: err %d\n", -ret); | |
108 | goto bail; | |
109 | } | |
110 | ||
111 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
112 | if (ret) { | |
113 | /* | |
114 | * If the 64 bit setup fails, try 32 bit. Some systems | |
115 | * do not setup 64 bit maps on systems with 2GB or less | |
116 | * memory installed. | |
117 | */ | |
118 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
119 | if (ret) { | |
120 | hfi1_early_err(&pdev->dev, | |
121 | "Unable to set DMA mask: %d\n", ret); | |
122 | goto bail; | |
123 | } | |
124 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
125 | } else | |
126 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
127 | if (ret) { | |
128 | hfi1_early_err(&pdev->dev, | |
129 | "Unable to set DMA consistent mask: %d\n", ret); | |
130 | goto bail; | |
131 | } | |
132 | ||
133 | pci_set_master(pdev); | |
134 | ret = pci_enable_pcie_error_reporting(pdev); | |
135 | if (ret) { | |
136 | hfi1_early_err(&pdev->dev, | |
137 | "Unable to enable pcie error reporting: %d\n", | |
138 | ret); | |
139 | ret = 0; | |
140 | } | |
141 | goto done; | |
142 | ||
143 | bail: | |
144 | hfi1_pcie_cleanup(pdev); | |
145 | done: | |
146 | return ret; | |
147 | } | |
148 | ||
149 | /* | |
150 | * Clean what was done in hfi1_pcie_init() | |
151 | */ | |
152 | void hfi1_pcie_cleanup(struct pci_dev *pdev) | |
153 | { | |
154 | pci_disable_device(pdev); | |
155 | /* | |
156 | * Release regions should be called after the disable. OK to | |
157 | * call if request regions has not been called or failed. | |
158 | */ | |
159 | pci_release_regions(pdev); | |
160 | } | |
161 | ||
162 | /* | |
163 | * Do remaining PCIe setup, once dd is allocated, and save away | |
164 | * fields required to re-initialize after a chip reset, or for | |
165 | * various other purposes | |
166 | */ | |
167 | int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev, | |
168 | const struct pci_device_id *ent) | |
169 | { | |
170 | unsigned long len; | |
171 | resource_size_t addr; | |
172 | ||
173 | dd->pcidev = pdev; | |
174 | pci_set_drvdata(pdev, dd); | |
175 | ||
176 | addr = pci_resource_start(pdev, 0); | |
177 | len = pci_resource_len(pdev, 0); | |
178 | ||
179 | /* | |
180 | * The TXE PIO buffers are at the tail end of the chip space. | |
181 | * Cut them off and map them separately. | |
182 | */ | |
183 | ||
184 | /* sanity check vs expectations */ | |
185 | if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { | |
186 | dd_dev_err(dd, "chip PIO range does not match\n"); | |
187 | return -EINVAL; | |
188 | } | |
189 | ||
190 | dd->kregbase = ioremap_nocache(addr, TXE_PIO_SEND); | |
191 | if (!dd->kregbase) | |
192 | return -ENOMEM; | |
193 | ||
194 | dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); | |
195 | if (!dd->piobase) { | |
196 | iounmap(dd->kregbase); | |
197 | return -ENOMEM; | |
198 | } | |
199 | ||
200 | dd->flags |= HFI1_PRESENT; /* now register routines work */ | |
201 | ||
202 | dd->kregend = dd->kregbase + TXE_PIO_SEND; | |
203 | dd->physaddr = addr; /* used for io_remap, etc. */ | |
204 | ||
205 | /* | |
206 | * Re-map the chip's RcvArray as write-combining to allow us | |
207 | * to write an entire cacheline worth of entries in one shot. | |
208 | * If this re-map fails, just continue - the RcvArray programming | |
209 | * function will handle both cases. | |
210 | */ | |
211 | dd->chip_rcv_array_count = read_csr(dd, RCV_ARRAY_CNT); | |
212 | dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, | |
213 | dd->chip_rcv_array_count * 8); | |
214 | dd_dev_info(dd, "WC Remapped RcvArray: %p\n", dd->rcvarray_wc); | |
215 | /* | |
216 | * Save BARs and command to rewrite after device reset. | |
217 | */ | |
218 | dd->pcibar0 = addr; | |
219 | dd->pcibar1 = addr >> 32; | |
220 | pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); | |
221 | pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); | |
222 | pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &dd->pcie_devctl); | |
223 | pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, &dd->pcie_lnkctl); | |
224 | pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, | |
225 | &dd->pcie_devctl2); | |
226 | pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); | |
227 | pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, | |
228 | &dd->pci_lnkctl3); | |
229 | pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | /* | |
235 | * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior | |
236 | * to releasing the dd memory. | |
237 | * Void because all of the core pcie cleanup functions are void. | |
238 | */ | |
239 | void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) | |
240 | { | |
241 | u64 __iomem *base = (void __iomem *) dd->kregbase; | |
242 | ||
243 | dd->flags &= ~HFI1_PRESENT; | |
244 | dd->kregbase = NULL; | |
245 | iounmap(base); | |
246 | if (dd->rcvarray_wc) | |
247 | iounmap(dd->rcvarray_wc); | |
248 | if (dd->piobase) | |
249 | iounmap(dd->piobase); | |
250 | ||
251 | pci_set_drvdata(dd->pcidev, NULL); | |
252 | } | |
253 | ||
254 | /* | |
255 | * Do a Function Level Reset (FLR) on the device. | |
256 | * Based on static function drivers/pci/pci.c:pcie_flr(). | |
257 | */ | |
258 | void hfi1_pcie_flr(struct hfi1_devdata *dd) | |
259 | { | |
260 | int i; | |
261 | u16 status; | |
262 | ||
263 | /* no need to check for the capability - we know the device has it */ | |
264 | ||
265 | /* wait for Transaction Pending bit to clear, at most a few ms */ | |
266 | for (i = 0; i < 4; i++) { | |
267 | if (i) | |
268 | msleep((1 << (i - 1)) * 100); | |
269 | ||
270 | pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVSTA, &status); | |
271 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | |
272 | goto clear; | |
273 | } | |
274 | ||
275 | dd_dev_err(dd, "Transaction Pending bit is not clearing, proceeding with reset anyway\n"); | |
276 | ||
277 | clear: | |
278 | pcie_capability_set_word(dd->pcidev, PCI_EXP_DEVCTL, | |
279 | PCI_EXP_DEVCTL_BCR_FLR); | |
280 | /* PCIe spec requires the function to be back within 100ms */ | |
281 | msleep(100); | |
282 | } | |
283 | ||
284 | static void msix_setup(struct hfi1_devdata *dd, int pos, u32 *msixcnt, | |
285 | struct hfi1_msix_entry *hfi1_msix_entry) | |
286 | { | |
287 | int ret; | |
288 | int nvec = *msixcnt; | |
289 | struct msix_entry *msix_entry; | |
290 | int i; | |
291 | ||
292 | /* We can't pass hfi1_msix_entry array to msix_setup | |
293 | * so use a dummy msix_entry array and copy the allocated | |
294 | * irq back to the hfi1_msix_entry array. */ | |
295 | msix_entry = kmalloc_array(nvec, sizeof(*msix_entry), GFP_KERNEL); | |
296 | if (!msix_entry) { | |
297 | ret = -ENOMEM; | |
298 | goto do_intx; | |
299 | } | |
300 | ||
301 | for (i = 0; i < nvec; i++) | |
302 | msix_entry[i] = hfi1_msix_entry[i].msix; | |
303 | ||
304 | ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec); | |
305 | if (ret < 0) | |
306 | goto free_msix_entry; | |
307 | nvec = ret; | |
308 | ||
309 | for (i = 0; i < nvec; i++) | |
310 | hfi1_msix_entry[i].msix = msix_entry[i]; | |
311 | ||
312 | kfree(msix_entry); | |
313 | *msixcnt = nvec; | |
314 | return; | |
315 | ||
316 | free_msix_entry: | |
317 | kfree(msix_entry); | |
318 | ||
319 | do_intx: | |
320 | dd_dev_err(dd, "pci_enable_msix_range %d vectors failed: %d, falling back to INTx\n", | |
321 | nvec, ret); | |
322 | *msixcnt = 0; | |
323 | hfi1_enable_intx(dd->pcidev); | |
324 | ||
325 | } | |
326 | ||
327 | /* return the PCIe link speed from the given link status */ | |
328 | static u32 extract_speed(u16 linkstat) | |
329 | { | |
330 | u32 speed; | |
331 | ||
332 | switch (linkstat & PCI_EXP_LNKSTA_CLS) { | |
333 | default: /* not defined, assume Gen1 */ | |
334 | case PCI_EXP_LNKSTA_CLS_2_5GB: | |
335 | speed = 2500; /* Gen 1, 2.5GHz */ | |
336 | break; | |
337 | case PCI_EXP_LNKSTA_CLS_5_0GB: | |
338 | speed = 5000; /* Gen 2, 5GHz */ | |
339 | break; | |
340 | case GEN3_SPEED_VECTOR: | |
341 | speed = 8000; /* Gen 3, 8GHz */ | |
342 | break; | |
343 | } | |
344 | return speed; | |
345 | } | |
346 | ||
347 | /* return the PCIe link speed from the given link status */ | |
348 | static u32 extract_width(u16 linkstat) | |
349 | { | |
350 | return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; | |
351 | } | |
352 | ||
353 | /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ | |
354 | static void update_lbus_info(struct hfi1_devdata *dd) | |
355 | { | |
356 | u16 linkstat; | |
357 | ||
358 | pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); | |
359 | dd->lbus_width = extract_width(linkstat); | |
360 | dd->lbus_speed = extract_speed(linkstat); | |
361 | snprintf(dd->lbus_info, sizeof(dd->lbus_info), | |
362 | "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); | |
363 | } | |
364 | ||
365 | /* | |
366 | * Read in the current PCIe link width and speed. Find if the link is | |
367 | * Gen3 capable. | |
368 | */ | |
369 | int pcie_speeds(struct hfi1_devdata *dd) | |
370 | { | |
371 | u32 linkcap; | |
372 | ||
373 | if (!pci_is_pcie(dd->pcidev)) { | |
374 | dd_dev_err(dd, "Can't find PCI Express capability!\n"); | |
375 | return -EINVAL; | |
376 | } | |
377 | ||
378 | /* find if our max speed is Gen3 and parent supports Gen3 speeds */ | |
379 | dd->link_gen3_capable = 1; | |
380 | ||
381 | pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); | |
382 | if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) { | |
383 | dd_dev_info(dd, | |
384 | "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", | |
385 | linkcap & PCI_EXP_LNKCAP_SLS); | |
386 | dd->link_gen3_capable = 0; | |
387 | } | |
388 | ||
389 | /* | |
390 | * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed | |
391 | */ | |
392 | if (dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { | |
393 | dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); | |
394 | dd->link_gen3_capable = 0; | |
395 | } | |
396 | ||
397 | /* obtain the link width and current speed */ | |
398 | update_lbus_info(dd); | |
399 | ||
400 | /* check against expected pcie width and complain if "wrong" */ | |
401 | if (dd->lbus_width < 16) | |
402 | dd_dev_err(dd, "PCIe width %u (x16 HFI)\n", dd->lbus_width); | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | /* | |
408 | * Returns in *nent: | |
409 | * - actual number of interrupts allocated | |
410 | * - 0 if fell back to INTx. | |
411 | */ | |
412 | void request_msix(struct hfi1_devdata *dd, u32 *nent, | |
413 | struct hfi1_msix_entry *entry) | |
414 | { | |
415 | int pos; | |
416 | ||
417 | pos = dd->pcidev->msix_cap; | |
418 | if (*nent && pos) { | |
419 | msix_setup(dd, pos, nent, entry); | |
420 | /* did it, either MSI-X or INTx */ | |
421 | } else { | |
422 | *nent = 0; | |
423 | hfi1_enable_intx(dd->pcidev); | |
424 | } | |
425 | ||
426 | tune_pcie_caps(dd); | |
427 | } | |
428 | ||
429 | /* | |
430 | * Disable MSI-X. | |
431 | */ | |
432 | void hfi1_nomsix(struct hfi1_devdata *dd) | |
433 | { | |
434 | pci_disable_msix(dd->pcidev); | |
435 | } | |
436 | ||
437 | void hfi1_enable_intx(struct pci_dev *pdev) | |
438 | { | |
439 | /* first, turn on INTx */ | |
440 | pci_intx(pdev, 1); | |
441 | /* then turn off MSI-X */ | |
442 | pci_disable_msix(pdev); | |
443 | } | |
444 | ||
445 | /* restore command and BARs after a reset has wiped them out */ | |
446 | void restore_pci_variables(struct hfi1_devdata *dd) | |
447 | { | |
448 | pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); | |
449 | pci_write_config_dword(dd->pcidev, | |
450 | PCI_BASE_ADDRESS_0, dd->pcibar0); | |
451 | pci_write_config_dword(dd->pcidev, | |
452 | PCI_BASE_ADDRESS_1, dd->pcibar1); | |
453 | pci_write_config_dword(dd->pcidev, | |
454 | PCI_ROM_ADDRESS, dd->pci_rom); | |
455 | pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, dd->pcie_devctl); | |
456 | pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, dd->pcie_lnkctl); | |
457 | pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, | |
458 | dd->pcie_devctl2); | |
459 | pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); | |
460 | pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1, | |
461 | dd->pci_lnkctl3); | |
462 | pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2); | |
463 | } | |
464 | ||
465 | ||
466 | /* | |
467 | * BIOS may not set PCIe bus-utilization parameters for best performance. | |
468 | * Check and optionally adjust them to maximize our throughput. | |
469 | */ | |
470 | static int hfi1_pcie_caps; | |
471 | module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO); | |
472 | MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); | |
473 | ||
474 | static void tune_pcie_caps(struct hfi1_devdata *dd) | |
475 | { | |
476 | struct pci_dev *parent; | |
477 | u16 rc_mpss, rc_mps, ep_mpss, ep_mps; | |
478 | u16 rc_mrrs, ep_mrrs, max_mrrs; | |
479 | ||
480 | /* Find out supported and configured values for parent (root) */ | |
481 | parent = dd->pcidev->bus->self; | |
482 | if (!pci_is_root_bus(parent->bus)) { | |
483 | dd_dev_info(dd, "Parent not root\n"); | |
484 | return; | |
485 | } | |
486 | ||
487 | if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) | |
488 | return; | |
489 | rc_mpss = parent->pcie_mpss; | |
490 | rc_mps = ffs(pcie_get_mps(parent)) - 8; | |
491 | /* Find out supported and configured values for endpoint (us) */ | |
492 | ep_mpss = dd->pcidev->pcie_mpss; | |
493 | ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; | |
494 | ||
495 | /* Find max payload supported by root, endpoint */ | |
496 | if (rc_mpss > ep_mpss) | |
497 | rc_mpss = ep_mpss; | |
498 | ||
499 | /* If Supported greater than limit in module param, limit it */ | |
500 | if (rc_mpss > (hfi1_pcie_caps & 7)) | |
501 | rc_mpss = hfi1_pcie_caps & 7; | |
502 | /* If less than (allowed, supported), bump root payload */ | |
503 | if (rc_mpss > rc_mps) { | |
504 | rc_mps = rc_mpss; | |
505 | pcie_set_mps(parent, 128 << rc_mps); | |
506 | } | |
507 | /* If less than (allowed, supported), bump endpoint payload */ | |
508 | if (rc_mpss > ep_mps) { | |
509 | ep_mps = rc_mpss; | |
510 | pcie_set_mps(dd->pcidev, 128 << ep_mps); | |
511 | } | |
512 | ||
513 | /* | |
514 | * Now the Read Request size. | |
515 | * No field for max supported, but PCIe spec limits it to 4096, | |
516 | * which is code '5' (log2(4096) - 7) | |
517 | */ | |
518 | max_mrrs = 5; | |
519 | if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) | |
520 | max_mrrs = (hfi1_pcie_caps >> 4) & 7; | |
521 | ||
522 | max_mrrs = 128 << max_mrrs; | |
523 | rc_mrrs = pcie_get_readrq(parent); | |
524 | ep_mrrs = pcie_get_readrq(dd->pcidev); | |
525 | ||
526 | if (max_mrrs > rc_mrrs) { | |
527 | rc_mrrs = max_mrrs; | |
528 | pcie_set_readrq(parent, rc_mrrs); | |
529 | } | |
530 | if (max_mrrs > ep_mrrs) { | |
531 | ep_mrrs = max_mrrs; | |
532 | pcie_set_readrq(dd->pcidev, ep_mrrs); | |
533 | } | |
534 | } | |
535 | /* End of PCIe capability tuning */ | |
536 | ||
537 | /* | |
538 | * From here through hfi1_pci_err_handler definition is invoked via | |
539 | * PCI error infrastructure, registered via pci | |
540 | */ | |
541 | static pci_ers_result_t | |
542 | pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
543 | { | |
544 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
545 | pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; | |
546 | ||
547 | switch (state) { | |
548 | case pci_channel_io_normal: | |
549 | dd_dev_info(dd, "State Normal, ignoring\n"); | |
550 | break; | |
551 | ||
552 | case pci_channel_io_frozen: | |
553 | dd_dev_info(dd, "State Frozen, requesting reset\n"); | |
554 | pci_disable_device(pdev); | |
555 | ret = PCI_ERS_RESULT_NEED_RESET; | |
556 | break; | |
557 | ||
558 | case pci_channel_io_perm_failure: | |
559 | if (dd) { | |
560 | dd_dev_info(dd, "State Permanent Failure, disabling\n"); | |
561 | /* no more register accesses! */ | |
562 | dd->flags &= ~HFI1_PRESENT; | |
563 | hfi1_disable_after_error(dd); | |
564 | } | |
565 | /* else early, or other problem */ | |
566 | ret = PCI_ERS_RESULT_DISCONNECT; | |
567 | break; | |
568 | ||
569 | default: /* shouldn't happen */ | |
570 | dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", | |
571 | state); | |
572 | break; | |
573 | } | |
574 | return ret; | |
575 | } | |
576 | ||
577 | static pci_ers_result_t | |
578 | pci_mmio_enabled(struct pci_dev *pdev) | |
579 | { | |
580 | u64 words = 0U; | |
581 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
582 | pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; | |
583 | ||
584 | if (dd && dd->pport) { | |
585 | words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); | |
586 | if (words == ~0ULL) | |
587 | ret = PCI_ERS_RESULT_NEED_RESET; | |
588 | dd_dev_info(dd, | |
589 | "HFI1 mmio_enabled function called, read wordscntr %Lx, returning %d\n", | |
590 | words, ret); | |
591 | } | |
592 | return ret; | |
593 | } | |
594 | ||
595 | static pci_ers_result_t | |
596 | pci_slot_reset(struct pci_dev *pdev) | |
597 | { | |
598 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
599 | ||
600 | dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); | |
601 | return PCI_ERS_RESULT_CAN_RECOVER; | |
602 | } | |
603 | ||
604 | static pci_ers_result_t | |
605 | pci_link_reset(struct pci_dev *pdev) | |
606 | { | |
607 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
608 | ||
609 | dd_dev_info(dd, "HFI1 link_reset function called, ignored\n"); | |
610 | return PCI_ERS_RESULT_CAN_RECOVER; | |
611 | } | |
612 | ||
613 | static void | |
614 | pci_resume(struct pci_dev *pdev) | |
615 | { | |
616 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
617 | ||
618 | dd_dev_info(dd, "HFI1 resume function called\n"); | |
619 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
620 | /* | |
621 | * Running jobs will fail, since it's asynchronous | |
622 | * unlike sysfs-requested reset. Better than | |
623 | * doing nothing. | |
624 | */ | |
625 | hfi1_init(dd, 1); /* same as re-init after reset */ | |
626 | } | |
627 | ||
628 | const struct pci_error_handlers hfi1_pci_err_handler = { | |
629 | .error_detected = pci_error_detected, | |
630 | .mmio_enabled = pci_mmio_enabled, | |
631 | .link_reset = pci_link_reset, | |
632 | .slot_reset = pci_slot_reset, | |
633 | .resume = pci_resume, | |
634 | }; | |
635 | ||
636 | /*============================================================================*/ | |
637 | /* PCIe Gen3 support */ | |
638 | ||
639 | /* | |
640 | * This code is separated out because it is expected to be removed in the | |
641 | * final shipping product. If not, then it will be revisited and items | |
642 | * will be moved to more standard locations. | |
643 | */ | |
644 | ||
645 | /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ | |
646 | #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ | |
647 | #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ | |
648 | #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ | |
649 | ||
650 | /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ | |
651 | #define DL_ERR_NONE 0x0 /* no error */ | |
652 | #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ | |
653 | /* or response data */ | |
654 | #define DL_ERR_DISABLED 0x2 /* hfi disabled */ | |
655 | #define DL_ERR_SECURITY 0x3 /* security check failed */ | |
656 | #define DL_ERR_SBUS 0x4 /* SBus status error */ | |
657 | #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ | |
658 | ||
659 | /* gasket block secondary bus reset delay */ | |
660 | #define SBR_DELAY_US 200000 /* 200ms */ | |
661 | ||
662 | /* mask for PCIe capability register lnkctl2 target link speed */ | |
663 | #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf | |
664 | ||
665 | static uint pcie_target = 3; | |
666 | module_param(pcie_target, uint, S_IRUGO); | |
667 | MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); | |
668 | ||
669 | static uint pcie_force; | |
670 | module_param(pcie_force, uint, S_IRUGO); | |
671 | MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); | |
672 | ||
673 | static uint pcie_retry = 5; | |
674 | module_param(pcie_retry, uint, S_IRUGO); | |
675 | MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); | |
676 | ||
677 | #define UNSET_PSET 255 | |
678 | #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ | |
679 | #define DEFAULT_MCP_PSET 4 /* MCP HFI */ | |
680 | static uint pcie_pset = UNSET_PSET; | |
681 | module_param(pcie_pset, uint, S_IRUGO); | |
682 | MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); | |
683 | ||
684 | /* equalization columns */ | |
685 | #define PREC 0 | |
686 | #define ATTN 1 | |
687 | #define POST 2 | |
688 | ||
689 | /* discrete silicon preliminary equalization values */ | |
690 | static const u8 discrete_preliminary_eq[11][3] = { | |
691 | /* prec attn post */ | |
692 | { 0x00, 0x00, 0x12 }, /* p0 */ | |
693 | { 0x00, 0x00, 0x0c }, /* p1 */ | |
694 | { 0x00, 0x00, 0x0f }, /* p2 */ | |
695 | { 0x00, 0x00, 0x09 }, /* p3 */ | |
696 | { 0x00, 0x00, 0x00 }, /* p4 */ | |
697 | { 0x06, 0x00, 0x00 }, /* p5 */ | |
698 | { 0x09, 0x00, 0x00 }, /* p6 */ | |
699 | { 0x06, 0x00, 0x0f }, /* p7 */ | |
700 | { 0x09, 0x00, 0x09 }, /* p8 */ | |
701 | { 0x0c, 0x00, 0x00 }, /* p9 */ | |
702 | { 0x00, 0x00, 0x18 }, /* p10 */ | |
703 | }; | |
704 | ||
705 | /* integrated silicon preliminary equalization values */ | |
706 | static const u8 integrated_preliminary_eq[11][3] = { | |
707 | /* prec attn post */ | |
708 | { 0x00, 0x1e, 0x07 }, /* p0 */ | |
709 | { 0x00, 0x1e, 0x05 }, /* p1 */ | |
710 | { 0x00, 0x1e, 0x06 }, /* p2 */ | |
711 | { 0x00, 0x1e, 0x04 }, /* p3 */ | |
712 | { 0x00, 0x1e, 0x00 }, /* p4 */ | |
713 | { 0x03, 0x1e, 0x00 }, /* p5 */ | |
714 | { 0x04, 0x1e, 0x00 }, /* p6 */ | |
715 | { 0x03, 0x1e, 0x06 }, /* p7 */ | |
716 | { 0x03, 0x1e, 0x04 }, /* p8 */ | |
717 | { 0x05, 0x1e, 0x00 }, /* p9 */ | |
718 | { 0x00, 0x1e, 0x0a }, /* p10 */ | |
719 | }; | |
720 | ||
721 | /* helper to format the value to write to hardware */ | |
722 | #define eq_value(pre, curr, post) \ | |
723 | ((((u32)(pre)) << \ | |
724 | PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ | |
725 | | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ | |
726 | | (((u32)(post)) << \ | |
727 | PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) | |
728 | ||
729 | /* | |
730 | * Load the given EQ preset table into the PCIe hardware. | |
731 | */ | |
732 | static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, | |
733 | u8 div) | |
734 | { | |
735 | struct pci_dev *pdev = dd->pcidev; | |
736 | u32 hit_error = 0; | |
737 | u32 violation; | |
738 | u32 i; | |
739 | u8 c_minus1, c0, c_plus1; | |
740 | ||
741 | for (i = 0; i < 11; i++) { | |
742 | /* set index */ | |
743 | pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); | |
744 | /* write the value */ | |
745 | c_minus1 = eq[i][PREC] / div; | |
746 | c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); | |
747 | c_plus1 = eq[i][POST] / div; | |
748 | pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, | |
749 | eq_value(c_minus1, c0, c_plus1)); | |
750 | /* check if these coefficients violate EQ rules */ | |
751 | pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL105, | |
752 | &violation); | |
753 | if (violation | |
754 | & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ | |
755 | if (hit_error == 0) { | |
756 | dd_dev_err(dd, | |
757 | "Gen3 EQ Table Coefficient rule violations\n"); | |
758 | dd_dev_err(dd, " prec attn post\n"); | |
759 | } | |
760 | dd_dev_err(dd, " p%02d: %02x %02x %02x\n", | |
761 | i, (u32)eq[i][0], (u32)eq[i][1], (u32)eq[i][2]); | |
762 | dd_dev_err(dd, " %02x %02x %02x\n", | |
763 | (u32)c_minus1, (u32)c0, (u32)c_plus1); | |
764 | hit_error = 1; | |
765 | } | |
766 | } | |
767 | if (hit_error) | |
768 | return -EINVAL; | |
769 | return 0; | |
770 | } | |
771 | ||
772 | /* | |
773 | * Steps to be done after the PCIe firmware is downloaded and | |
774 | * before the SBR for the Pcie Gen3. | |
775 | * The hardware mutex is already being held. | |
776 | */ | |
777 | static void pcie_post_steps(struct hfi1_devdata *dd) | |
778 | { | |
779 | int i; | |
780 | ||
781 | set_sbus_fast_mode(dd); | |
782 | /* | |
783 | * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. | |
784 | * This avoids a spurious framing error that can otherwise be | |
785 | * generated by the MAC layer. | |
786 | * | |
787 | * Use individual addresses since no broadcast is set up. | |
788 | */ | |
789 | for (i = 0; i < NUM_PCIE_SERDES; i++) { | |
790 | sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], | |
791 | 0x03, WRITE_SBUS_RECEIVER, 0x00022132); | |
792 | } | |
793 | ||
794 | clear_sbus_fast_mode(dd); | |
795 | } | |
796 | ||
797 | /* | |
798 | * Trigger a secondary bus reset (SBR) on ourselves using our parent. | |
799 | * | |
800 | * Based on pci_parent_bus_reset() which is not exported by the | |
801 | * kernel core. | |
802 | */ | |
803 | static int trigger_sbr(struct hfi1_devdata *dd) | |
804 | { | |
805 | struct pci_dev *dev = dd->pcidev; | |
806 | struct pci_dev *pdev; | |
807 | ||
808 | /* need a parent */ | |
809 | if (!dev->bus->self) { | |
810 | dd_dev_err(dd, "%s: no parent device\n", __func__); | |
811 | return -ENOTTY; | |
812 | } | |
813 | ||
814 | /* should not be anyone else on the bus */ | |
815 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
816 | if (pdev != dev) { | |
817 | dd_dev_err(dd, | |
818 | "%s: another device is on the same bus\n", | |
819 | __func__); | |
820 | return -ENOTTY; | |
821 | } | |
822 | ||
823 | /* | |
824 | * A secondary bus reset (SBR) issues a hot reset to our device. | |
825 | * The following routine does a 1s wait after the reset is dropped | |
826 | * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - | |
827 | * Conventional Reset, paragraph 3, line 35 also says that a 1s | |
828 | * delay after a reset is required. Per spec requirements, | |
829 | * the link is either working or not after that point. | |
830 | */ | |
831 | pci_reset_bridge_secondary_bus(dev->bus->self); | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
836 | /* | |
837 | * Write the given gasket interrupt register. | |
838 | */ | |
839 | static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, | |
840 | u16 code, u16 data) | |
841 | { | |
842 | write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), | |
843 | (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | |
844 | |((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); | |
845 | } | |
846 | ||
847 | /* | |
848 | * Tell the gasket logic how to react to the reset. | |
849 | */ | |
850 | static void arm_gasket_logic(struct hfi1_devdata *dd) | |
851 | { | |
852 | u64 reg; | |
853 | ||
854 | reg = (((u64)1 << dd->hfi1_id) | |
855 | << ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | |
856 | | ((u64)pcie_serdes_broadcast[dd->hfi1_id] | |
857 | << ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | |
858 | | ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | |
859 | | ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) | |
860 | << ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT | |
861 | ); | |
862 | write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); | |
863 | /* read back to push the write */ | |
864 | read_csr(dd, ASIC_PCIE_SD_HOST_CMD); | |
865 | } | |
866 | ||
867 | /* | |
868 | * Do all the steps needed to transition the PCIe link to Gen3 speed. | |
869 | */ | |
870 | int do_pcie_gen3_transition(struct hfi1_devdata *dd) | |
871 | { | |
872 | struct pci_dev *parent; | |
873 | u64 fw_ctrl; | |
874 | u64 reg, therm; | |
875 | u32 reg32, fs, lf; | |
876 | u32 status, err; | |
877 | int ret; | |
878 | int do_retry, retry_count = 0; | |
879 | uint default_pset; | |
880 | u16 target_vector, target_speed; | |
881 | u16 lnkctl, lnkctl2, vendor; | |
882 | u8 nsbr = 1; | |
883 | u8 div; | |
884 | const u8 (*eq)[3]; | |
885 | int return_error = 0; | |
886 | ||
887 | /* PCIe Gen3 is for the ASIC only */ | |
888 | if (dd->icode != ICODE_RTL_SILICON) | |
889 | return 0; | |
890 | ||
891 | if (pcie_target == 1) { /* target Gen1 */ | |
892 | target_vector = GEN1_SPEED_VECTOR; | |
893 | target_speed = 2500; | |
894 | } else if (pcie_target == 2) { /* target Gen2 */ | |
895 | target_vector = GEN2_SPEED_VECTOR; | |
896 | target_speed = 5000; | |
897 | } else if (pcie_target == 3) { /* target Gen3 */ | |
898 | target_vector = GEN3_SPEED_VECTOR; | |
899 | target_speed = 8000; | |
900 | } else { | |
901 | /* off or invalid target - skip */ | |
902 | dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); | |
903 | return 0; | |
904 | } | |
905 | ||
906 | /* if already at target speed, done (unless forced) */ | |
907 | if (dd->lbus_speed == target_speed) { | |
908 | dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, | |
909 | pcie_target, | |
910 | pcie_force ? "re-doing anyway" : "skipping"); | |
911 | if (!pcie_force) | |
912 | return 0; | |
913 | } | |
914 | ||
915 | /* | |
916 | * A0 needs an additional SBR | |
917 | */ | |
918 | if (is_a0(dd)) | |
919 | nsbr++; | |
920 | ||
921 | /* | |
922 | * Do the Gen3 transition. Steps are those of the PCIe Gen3 | |
923 | * recipe. | |
924 | */ | |
925 | ||
926 | /* step 1: pcie link working in gen1/gen2 */ | |
927 | ||
928 | /* step 2: if either side is not capable of Gen3, done */ | |
929 | if (pcie_target == 3 && !dd->link_gen3_capable) { | |
930 | dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); | |
931 | ret = -ENOSYS; | |
932 | goto done_no_mutex; | |
933 | } | |
934 | ||
935 | /* hold the HW mutex across the firmware download and SBR */ | |
936 | ret = acquire_hw_mutex(dd); | |
937 | if (ret) | |
938 | return ret; | |
939 | ||
940 | /* make sure thermal polling is not causing interrupts */ | |
941 | therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); | |
942 | if (therm) { | |
943 | write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); | |
944 | msleep(100); | |
945 | dd_dev_info(dd, "%s: Disabled therm polling\n", | |
946 | __func__); | |
947 | } | |
948 | ||
949 | /* step 3: download SBus Master firmware */ | |
950 | /* step 4: download PCIe Gen3 SerDes firmware */ | |
951 | retry: | |
952 | dd_dev_info(dd, "%s: downloading firmware\n", __func__); | |
953 | ret = load_pcie_firmware(dd); | |
954 | if (ret) | |
955 | goto done; | |
956 | ||
957 | /* step 5: set up device parameter settings */ | |
958 | dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); | |
959 | ||
960 | /* | |
961 | * PcieCfgSpcie1 - Link Control 3 | |
962 | * Leave at reset value. No need to set PerfEq - link equalization | |
963 | * will be performed automatically after the SBR when the target | |
964 | * speed is 8GT/s. | |
965 | */ | |
966 | ||
967 | /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ | |
968 | pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); | |
969 | ||
970 | /* step 5a: Set Synopsys Port Logic registers */ | |
971 | ||
972 | /* | |
973 | * PcieCfgRegPl2 - Port Force Link | |
974 | * | |
975 | * Set the low power field to 0x10 to avoid unnecessary power | |
976 | * management messages. All other fields are zero. | |
977 | */ | |
978 | reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; | |
979 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); | |
980 | ||
981 | /* | |
982 | * PcieCfgRegPl100 - Gen3 Control | |
983 | * | |
984 | * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl | |
985 | * turn on PcieCfgRegPl100.EqEieosCnt (erratum) | |
986 | * Everything else zero. | |
987 | */ | |
988 | reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; | |
989 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); | |
990 | ||
991 | /* | |
992 | * PcieCfgRegPl101 - Gen3 EQ FS and LF | |
993 | * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping | |
994 | * PcieCfgRegPl103 - Gen3 EQ Preset Index | |
995 | * PcieCfgRegPl105 - Gen3 EQ Status | |
996 | * | |
997 | * Give initial EQ settings. | |
998 | */ | |
999 | if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ | |
1000 | /* 1000mV, FS=24, LF = 8 */ | |
1001 | fs = 24; | |
1002 | lf = 8; | |
1003 | div = 3; | |
1004 | eq = discrete_preliminary_eq; | |
1005 | default_pset = DEFAULT_DISCRETE_PSET; | |
1006 | } else { | |
1007 | /* 400mV, FS=29, LF = 9 */ | |
1008 | fs = 29; | |
1009 | lf = 9; | |
1010 | div = 1; | |
1011 | eq = integrated_preliminary_eq; | |
1012 | default_pset = DEFAULT_MCP_PSET; | |
1013 | } | |
1014 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, | |
1015 | (fs << PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | |
1016 | | (lf << PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); | |
1017 | ret = load_eq_table(dd, eq, fs, div); | |
1018 | if (ret) | |
1019 | goto done; | |
1020 | ||
1021 | /* | |
1022 | * PcieCfgRegPl106 - Gen3 EQ Control | |
1023 | * | |
1024 | * Set Gen3EqPsetReqVec, leave other fields 0. | |
1025 | */ | |
1026 | if (pcie_pset == UNSET_PSET) | |
1027 | pcie_pset = default_pset; | |
1028 | if (pcie_pset > 10) { /* valid range is 0-10, inclusive */ | |
1029 | dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", | |
1030 | __func__, pcie_pset, default_pset); | |
1031 | pcie_pset = default_pset; | |
1032 | } | |
1033 | dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset); | |
1034 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, | |
1035 | ((1 << pcie_pset) | |
1036 | << PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | |
1037 | | PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | |
1038 | | PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); | |
1039 | ||
1040 | /* | |
1041 | * step 5b: Do post firmware download steps via SBus | |
1042 | */ | |
1043 | dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); | |
1044 | pcie_post_steps(dd); | |
1045 | ||
1046 | /* | |
1047 | * step 5c: Program gasket interrupts | |
1048 | */ | |
1049 | /* set the Rx Bit Rate to REFCLK ratio */ | |
1050 | write_gasket_interrupt(dd, 0, 0x0006, 0x0050); | |
1051 | /* disable pCal for PCIe Gen3 RX equalization */ | |
1052 | write_gasket_interrupt(dd, 1, 0x0026, 0x5b01); | |
1053 | /* | |
1054 | * Enable iCal for PCIe Gen3 RX equalization, and set which | |
1055 | * evaluation of RX_EQ_EVAL will launch the iCal procedure. | |
1056 | */ | |
1057 | write_gasket_interrupt(dd, 2, 0x0026, 0x5202); | |
1058 | /* terminate list */ | |
1059 | write_gasket_interrupt(dd, 3, 0x0000, 0x0000); | |
1060 | ||
1061 | /* | |
1062 | * step 5d: program XMT margin | |
1063 | * Right now, leave the default alone. To change, do a | |
1064 | * read-modify-write of: | |
1065 | * CcePcieCtrl.XmtMargin | |
1066 | * CcePcieCtrl.XmitMarginOverwriteEnable | |
1067 | */ | |
1068 | ||
1069 | /* step 5e: disable active state power management (ASPM) */ | |
1070 | dd_dev_info(dd, "%s: clearing ASPM\n", __func__); | |
1071 | pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, &lnkctl); | |
1072 | lnkctl &= ~PCI_EXP_LNKCTL_ASPMC; | |
1073 | pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, lnkctl); | |
1074 | ||
1075 | /* | |
1076 | * step 5f: clear DirectSpeedChange | |
1077 | * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the | |
1078 | * change in the speed target from starting before we are ready. | |
1079 | * This field defaults to 0 and we are not changing it, so nothing | |
1080 | * needs to be done. | |
1081 | */ | |
1082 | ||
1083 | /* step 5g: Set target link speed */ | |
1084 | /* | |
1085 | * Set target link speed to be target on both device and parent. | |
1086 | * On setting the parent: Some system BIOSs "helpfully" set the | |
1087 | * parent target speed to Gen2 to match the ASIC's initial speed. | |
1088 | * We can set the target Gen3 because we have already checked | |
1089 | * that it is Gen3 capable earlier. | |
1090 | */ | |
1091 | dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); | |
1092 | parent = dd->pcidev->bus->self; | |
1093 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); | |
1094 | dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, | |
1095 | (u32)lnkctl2); | |
1096 | /* only write to parent if target is not as high as ours */ | |
1097 | if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) { | |
1098 | lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; | |
1099 | lnkctl2 |= target_vector; | |
1100 | dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, | |
1101 | (u32)lnkctl2); | |
1102 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL2, lnkctl2); | |
1103 | } else { | |
1104 | dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); | |
1105 | } | |
1106 | ||
1107 | dd_dev_info(dd, "%s: setting target link speed\n", __func__); | |
1108 | pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); | |
1109 | dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, | |
1110 | (u32)lnkctl2); | |
1111 | lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK; | |
1112 | lnkctl2 |= target_vector; | |
1113 | dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, | |
1114 | (u32)lnkctl2); | |
1115 | pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); | |
1116 | ||
1117 | /* step 5h: arm gasket logic */ | |
1118 | /* hold DC in reset across the SBR */ | |
1119 | write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); | |
1120 | (void) read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ | |
1121 | /* save firmware control across the SBR */ | |
1122 | fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); | |
1123 | ||
1124 | dd_dev_info(dd, "%s: arming gasket logic\n", __func__); | |
1125 | arm_gasket_logic(dd); | |
1126 | ||
1127 | /* | |
1128 | * step 6: quiesce PCIe link | |
1129 | * The chip has already been reset, so there will be no traffic | |
1130 | * from the chip. Linux has no easy way to enforce that it will | |
1131 | * not try to access the device, so we just need to hope it doesn't | |
1132 | * do it while we are doing the reset. | |
1133 | */ | |
1134 | ||
1135 | /* | |
1136 | * step 7: initiate the secondary bus reset (SBR) | |
1137 | * step 8: hardware brings the links back up | |
1138 | * step 9: wait for link speed transition to be complete | |
1139 | */ | |
1140 | dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); | |
1141 | ret = trigger_sbr(dd); | |
1142 | if (ret) | |
1143 | goto done; | |
1144 | ||
1145 | /* step 10: decide what to do next */ | |
1146 | ||
1147 | /* check if we can read PCI space */ | |
1148 | ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); | |
1149 | if (ret) { | |
1150 | dd_dev_info(dd, | |
1151 | "%s: read of VendorID failed after SBR, err %d\n", | |
1152 | __func__, ret); | |
1153 | return_error = 1; | |
1154 | goto done; | |
1155 | } | |
1156 | if (vendor == 0xffff) { | |
1157 | dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); | |
1158 | return_error = 1; | |
1159 | ret = -EIO; | |
1160 | goto done; | |
1161 | } | |
1162 | ||
1163 | /* restore PCI space registers we know were reset */ | |
1164 | dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); | |
1165 | restore_pci_variables(dd); | |
1166 | /* restore firmware control */ | |
1167 | write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); | |
1168 | ||
1169 | /* | |
1170 | * Check the gasket block status. | |
1171 | * | |
1172 | * This is the first CSR read after the SBR. If the read returns | |
1173 | * all 1s (fails), the link did not make it back. | |
1174 | * | |
1175 | * Once we're sure we can read and write, clear the DC reset after | |
1176 | * the SBR. Then check for any per-lane errors. Then look over | |
1177 | * the status. | |
1178 | */ | |
1179 | reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); | |
1180 | dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); | |
1181 | if (reg == ~0ull) { /* PCIe read failed/timeout */ | |
1182 | dd_dev_err(dd, "SBR failed - unable to read from device\n"); | |
1183 | return_error = 1; | |
1184 | ret = -ENOSYS; | |
1185 | goto done; | |
1186 | } | |
1187 | ||
1188 | /* clear the DC reset */ | |
1189 | write_csr(dd, CCE_DC_CTRL, 0); | |
1190 | /* Set the LED off */ | |
1191 | if (is_a0(dd)) | |
1192 | setextled(dd, 0); | |
1193 | ||
1194 | /* check for any per-lane errors */ | |
1195 | pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); | |
1196 | dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); | |
1197 | ||
1198 | /* extract status, look for our HFI */ | |
1199 | status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) | |
1200 | & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; | |
1201 | if ((status & (1 << dd->hfi1_id)) == 0) { | |
1202 | dd_dev_err(dd, | |
1203 | "%s: gasket status 0x%x, expecting 0x%x\n", | |
1204 | __func__, status, 1 << dd->hfi1_id); | |
1205 | ret = -EIO; | |
1206 | goto done; | |
1207 | } | |
1208 | ||
1209 | /* extract error */ | |
1210 | err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) | |
1211 | & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; | |
1212 | if (err) { | |
1213 | dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); | |
1214 | ret = -EIO; | |
1215 | goto done; | |
1216 | } | |
1217 | ||
1218 | /* update our link information cache */ | |
1219 | update_lbus_info(dd); | |
1220 | dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, | |
1221 | dd->lbus_info); | |
1222 | ||
1223 | if (dd->lbus_speed != target_speed) { /* not target */ | |
1224 | /* maybe retry */ | |
1225 | do_retry = retry_count < pcie_retry; | |
1226 | dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n", | |
1227 | pcie_target, do_retry ? ", retrying" : ""); | |
1228 | retry_count++; | |
1229 | if (do_retry) { | |
1230 | msleep(100); /* allow time to settle */ | |
1231 | goto retry; | |
1232 | } | |
1233 | ret = -EIO; | |
1234 | } | |
1235 | ||
1236 | done: | |
1237 | if (therm) { | |
1238 | write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); | |
1239 | msleep(100); | |
1240 | dd_dev_info(dd, "%s: Re-enable therm polling\n", | |
1241 | __func__); | |
1242 | } | |
1243 | release_hw_mutex(dd); | |
1244 | done_no_mutex: | |
1245 | /* return no error if it is OK to be at current speed */ | |
1246 | if (ret && !return_error) { | |
1247 | dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); | |
1248 | ret = 0; | |
1249 | } | |
1250 | ||
1251 | dd_dev_info(dd, "%s: done\n", __func__); | |
1252 | return ret; | |
1253 | } |