Commit | Line | Data |
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77241056 MM |
1 | /* |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2015 Intel Corporation. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * BSD LICENSE | |
20 | * | |
21 | * Copyright(c) 2015 Intel Corporation. | |
22 | * | |
23 | * Redistribution and use in source and binary forms, with or without | |
24 | * modification, are permitted provided that the following conditions | |
25 | * are met: | |
26 | * | |
27 | * - Redistributions of source code must retain the above copyright | |
28 | * notice, this list of conditions and the following disclaimer. | |
29 | * - Redistributions in binary form must reproduce the above copyright | |
30 | * notice, this list of conditions and the following disclaimer in | |
31 | * the documentation and/or other materials provided with the | |
32 | * distribution. | |
33 | * - Neither the name of Intel Corporation nor the names of its | |
34 | * contributors may be used to endorse or promote products derived | |
35 | * from this software without specific prior written permission. | |
36 | * | |
37 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
38 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
39 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
40 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
41 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
42 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
43 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
44 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
45 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
46 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
48 | * | |
49 | */ | |
50 | #include <linux/mm.h> | |
51 | #include <linux/types.h> | |
52 | #include <linux/device.h> | |
53 | #include <linux/dmapool.h> | |
54 | #include <linux/slab.h> | |
55 | #include <linux/list.h> | |
56 | #include <linux/highmem.h> | |
57 | #include <linux/io.h> | |
58 | #include <linux/uio.h> | |
59 | #include <linux/rbtree.h> | |
60 | #include <linux/spinlock.h> | |
61 | #include <linux/delay.h> | |
62 | #include <linux/kthread.h> | |
63 | #include <linux/mmu_context.h> | |
64 | #include <linux/module.h> | |
65 | #include <linux/vmalloc.h> | |
66 | ||
67 | #include "hfi.h" | |
68 | #include "sdma.h" | |
69 | #include "user_sdma.h" | |
70 | #include "sdma.h" | |
71 | #include "verbs.h" /* for the headers */ | |
72 | #include "common.h" /* for struct hfi1_tid_info */ | |
73 | #include "trace.h" | |
74 | ||
75 | static uint hfi1_sdma_comp_ring_size = 128; | |
76 | module_param_named(sdma_comp_size, hfi1_sdma_comp_ring_size, uint, S_IRUGO); | |
77 | MODULE_PARM_DESC(sdma_comp_size, "Size of User SDMA completion ring. Default: 128"); | |
78 | ||
79 | /* The maximum number of Data io vectors per message/request */ | |
80 | #define MAX_VECTORS_PER_REQ 8 | |
81 | /* | |
82 | * Maximum number of packet to send from each message/request | |
83 | * before moving to the next one. | |
84 | */ | |
85 | #define MAX_PKTS_PER_QUEUE 16 | |
86 | ||
87 | #define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT)) | |
88 | ||
89 | #define req_opcode(x) \ | |
90 | (((x) >> HFI1_SDMA_REQ_OPCODE_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK) | |
91 | #define req_version(x) \ | |
92 | (((x) >> HFI1_SDMA_REQ_VERSION_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK) | |
93 | #define req_iovcnt(x) \ | |
94 | (((x) >> HFI1_SDMA_REQ_IOVCNT_SHIFT) & HFI1_SDMA_REQ_IOVCNT_MASK) | |
95 | ||
96 | /* Number of BTH.PSN bits used for sequence number in expected rcvs */ | |
97 | #define BTH_SEQ_MASK 0x7ffull | |
98 | ||
99 | /* | |
100 | * Define fields in the KDETH header so we can update the header | |
101 | * template. | |
102 | */ | |
103 | #define KDETH_OFFSET_SHIFT 0 | |
104 | #define KDETH_OFFSET_MASK 0x7fff | |
105 | #define KDETH_OM_SHIFT 15 | |
106 | #define KDETH_OM_MASK 0x1 | |
107 | #define KDETH_TID_SHIFT 16 | |
108 | #define KDETH_TID_MASK 0x3ff | |
109 | #define KDETH_TIDCTRL_SHIFT 26 | |
110 | #define KDETH_TIDCTRL_MASK 0x3 | |
111 | #define KDETH_INTR_SHIFT 28 | |
112 | #define KDETH_INTR_MASK 0x1 | |
113 | #define KDETH_SH_SHIFT 29 | |
114 | #define KDETH_SH_MASK 0x1 | |
115 | #define KDETH_HCRC_UPPER_SHIFT 16 | |
116 | #define KDETH_HCRC_UPPER_MASK 0xff | |
117 | #define KDETH_HCRC_LOWER_SHIFT 24 | |
118 | #define KDETH_HCRC_LOWER_MASK 0xff | |
119 | ||
120 | #define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4) | |
121 | #define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff) | |
122 | ||
123 | #define KDETH_GET(val, field) \ | |
124 | (((le32_to_cpu((val))) >> KDETH_##field##_SHIFT) & KDETH_##field##_MASK) | |
125 | #define KDETH_SET(dw, field, val) do { \ | |
126 | u32 dwval = le32_to_cpu(dw); \ | |
127 | dwval &= ~(KDETH_##field##_MASK << KDETH_##field##_SHIFT); \ | |
128 | dwval |= (((val) & KDETH_##field##_MASK) << \ | |
129 | KDETH_##field##_SHIFT); \ | |
130 | dw = cpu_to_le32(dwval); \ | |
131 | } while (0) | |
132 | ||
133 | #define AHG_HEADER_SET(arr, idx, dw, bit, width, value) \ | |
134 | do { \ | |
135 | if ((idx) < ARRAY_SIZE((arr))) \ | |
136 | (arr)[(idx++)] = sdma_build_ahg_descriptor( \ | |
137 | (__force u16)(value), (dw), (bit), \ | |
138 | (width)); \ | |
139 | else \ | |
140 | return -ERANGE; \ | |
141 | } while (0) | |
142 | ||
143 | /* KDETH OM multipliers and switch over point */ | |
144 | #define KDETH_OM_SMALL 4 | |
145 | #define KDETH_OM_LARGE 64 | |
146 | #define KDETH_OM_MAX_SIZE (1 << ((KDETH_OM_LARGE / KDETH_OM_SMALL) + 1)) | |
147 | ||
148 | /* Last packet in the request */ | |
cb32649d | 149 | #define TXREQ_FLAGS_REQ_LAST_PKT BIT(0) |
0f2d87d2 MH |
150 | |
151 | /* Last packet that uses a particular io vector */ | |
cb32649d | 152 | #define TXREQ_FLAGS_IOVEC_LAST_PKT BIT(0) |
77241056 MM |
153 | |
154 | #define SDMA_REQ_IN_USE 0 | |
155 | #define SDMA_REQ_FOR_THREAD 1 | |
156 | #define SDMA_REQ_SEND_DONE 2 | |
157 | #define SDMA_REQ_HAVE_AHG 3 | |
158 | #define SDMA_REQ_HAS_ERROR 4 | |
159 | #define SDMA_REQ_DONE_ERROR 5 | |
160 | ||
cb32649d SK |
161 | #define SDMA_PKT_Q_INACTIVE BIT(0) |
162 | #define SDMA_PKT_Q_ACTIVE BIT(1) | |
163 | #define SDMA_PKT_Q_DEFERRED BIT(2) | |
77241056 MM |
164 | |
165 | /* | |
166 | * Maximum retry attempts to submit a TX request | |
167 | * before putting the process to sleep. | |
168 | */ | |
169 | #define MAX_DEFER_RETRY_COUNT 1 | |
170 | ||
171 | static unsigned initial_pkt_count = 8; | |
172 | ||
173 | #define SDMA_IOWAIT_TIMEOUT 1000 /* in milliseconds */ | |
174 | ||
175 | struct user_sdma_iovec { | |
0f2d87d2 | 176 | struct list_head list; |
77241056 MM |
177 | struct iovec iov; |
178 | /* number of pages in this vector */ | |
179 | unsigned npages; | |
180 | /* array of pinned pages for this vector */ | |
181 | struct page **pages; | |
182 | /* offset into the virtual address space of the vector at | |
183 | * which we last left off. */ | |
184 | u64 offset; | |
185 | }; | |
186 | ||
187 | struct user_sdma_request { | |
188 | struct sdma_req_info info; | |
189 | struct hfi1_user_sdma_pkt_q *pq; | |
190 | struct hfi1_user_sdma_comp_q *cq; | |
191 | /* This is the original header from user space */ | |
192 | struct hfi1_pkt_header hdr; | |
193 | /* | |
194 | * Pointer to the SDMA engine for this request. | |
195 | * Since different request could be on different VLs, | |
196 | * each request will need it's own engine pointer. | |
197 | */ | |
198 | struct sdma_engine *sde; | |
199 | u8 ahg_idx; | |
200 | u32 ahg[9]; | |
201 | /* | |
202 | * KDETH.Offset (Eager) field | |
203 | * We need to remember the initial value so the headers | |
204 | * can be updated properly. | |
205 | */ | |
206 | u32 koffset; | |
207 | /* | |
208 | * KDETH.OFFSET (TID) field | |
209 | * The offset can cover multiple packets, depending on the | |
210 | * size of the TID entry. | |
211 | */ | |
212 | u32 tidoffset; | |
213 | /* | |
214 | * KDETH.OM | |
215 | * Remember this because the header template always sets it | |
216 | * to 0. | |
217 | */ | |
218 | u8 omfactor; | |
77241056 MM |
219 | /* |
220 | * We copy the iovs for this request (based on | |
221 | * info.iovcnt). These are only the data vectors | |
222 | */ | |
223 | unsigned data_iovs; | |
224 | /* total length of the data in the request */ | |
225 | u32 data_len; | |
226 | /* progress index moving along the iovs array */ | |
227 | unsigned iov_idx; | |
228 | struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ]; | |
229 | /* number of elements copied to the tids array */ | |
230 | u16 n_tids; | |
231 | /* TID array values copied from the tid_iov vector */ | |
232 | u32 *tids; | |
233 | u16 tididx; | |
234 | u32 sent; | |
235 | u64 seqnum; | |
0f2d87d2 | 236 | u64 seqcomp; |
77241056 | 237 | struct list_head txps; |
a0d40693 MH |
238 | spinlock_t txcmp_lock; /* protect txcmp list */ |
239 | struct list_head txcmp; | |
77241056 | 240 | unsigned long flags; |
a0d40693 MH |
241 | /* status of the last txreq completed */ |
242 | int status; | |
77241056 MM |
243 | }; |
244 | ||
b9fb6318 MH |
245 | /* |
246 | * A single txreq could span up to 3 physical pages when the MTU | |
247 | * is sufficiently large (> 4K). Each of the IOV pointers also | |
248 | * needs it's own set of flags so the vector has been handled | |
249 | * independently of each other. | |
250 | */ | |
77241056 MM |
251 | struct user_sdma_txreq { |
252 | /* Packet header for the txreq */ | |
253 | struct hfi1_pkt_header hdr; | |
254 | struct sdma_txreq txreq; | |
a0d40693 | 255 | struct list_head list; |
77241056 | 256 | struct user_sdma_request *req; |
b9fb6318 MH |
257 | struct { |
258 | struct user_sdma_iovec *vec; | |
259 | u8 flags; | |
260 | } iovecs[3]; | |
261 | int idx; | |
77241056 MM |
262 | u16 flags; |
263 | unsigned busycount; | |
264 | u64 seqnum; | |
265 | }; | |
266 | ||
267 | #define SDMA_DBG(req, fmt, ...) \ | |
268 | hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \ | |
269 | (req)->pq->ctxt, (req)->pq->subctxt, (req)->info.comp_idx, \ | |
270 | ##__VA_ARGS__) | |
271 | #define SDMA_Q_DBG(pq, fmt, ...) \ | |
272 | hfi1_cdbg(SDMA, "[%u:%u:%u] " fmt, (pq)->dd->unit, (pq)->ctxt, \ | |
273 | (pq)->subctxt, ##__VA_ARGS__) | |
274 | ||
275 | static int user_sdma_send_pkts(struct user_sdma_request *, unsigned); | |
276 | static int num_user_pages(const struct iovec *); | |
277 | static void user_sdma_txreq_cb(struct sdma_txreq *, int, int); | |
0f2d87d2 MH |
278 | static inline void pq_update(struct hfi1_user_sdma_pkt_q *); |
279 | static void user_sdma_free_request(struct user_sdma_request *, bool); | |
77241056 MM |
280 | static int pin_vector_pages(struct user_sdma_request *, |
281 | struct user_sdma_iovec *); | |
0f2d87d2 | 282 | static void unpin_vector_pages(struct user_sdma_iovec *); |
77241056 MM |
283 | static int check_header_template(struct user_sdma_request *, |
284 | struct hfi1_pkt_header *, u32, u32); | |
285 | static int set_txreq_header(struct user_sdma_request *, | |
286 | struct user_sdma_txreq *, u32); | |
287 | static int set_txreq_header_ahg(struct user_sdma_request *, | |
288 | struct user_sdma_txreq *, u32); | |
0f2d87d2 MH |
289 | static inline void set_comp_state(struct hfi1_user_sdma_pkt_q *, |
290 | struct hfi1_user_sdma_comp_q *, | |
291 | u16, enum hfi1_sdma_comp_state, int); | |
77241056 MM |
292 | static inline u32 set_pkt_bth_psn(__be32, u8, u32); |
293 | static inline u32 get_lrh_len(struct hfi1_pkt_header, u32 len); | |
294 | ||
295 | static int defer_packet_queue( | |
296 | struct sdma_engine *, | |
297 | struct iowait *, | |
298 | struct sdma_txreq *, | |
299 | unsigned seq); | |
300 | static void activate_packet_queue(struct iowait *, int); | |
301 | ||
77241056 MM |
302 | static int defer_packet_queue( |
303 | struct sdma_engine *sde, | |
304 | struct iowait *wait, | |
305 | struct sdma_txreq *txreq, | |
306 | unsigned seq) | |
307 | { | |
308 | struct hfi1_user_sdma_pkt_q *pq = | |
309 | container_of(wait, struct hfi1_user_sdma_pkt_q, busy); | |
310 | struct hfi1_ibdev *dev = &pq->dd->verbs_dev; | |
311 | struct user_sdma_txreq *tx = | |
312 | container_of(txreq, struct user_sdma_txreq, txreq); | |
313 | ||
314 | if (sdma_progress(sde, seq, txreq)) { | |
315 | if (tx->busycount++ < MAX_DEFER_RETRY_COUNT) | |
316 | goto eagain; | |
317 | } | |
318 | /* | |
319 | * We are assuming that if the list is enqueued somewhere, it | |
320 | * is to the dmawait list since that is the only place where | |
321 | * it is supposed to be enqueued. | |
322 | */ | |
323 | xchg(&pq->state, SDMA_PKT_Q_DEFERRED); | |
324 | write_seqlock(&dev->iowait_lock); | |
325 | if (list_empty(&pq->busy.list)) | |
326 | list_add_tail(&pq->busy.list, &sde->dmawait); | |
327 | write_sequnlock(&dev->iowait_lock); | |
328 | return -EBUSY; | |
329 | eagain: | |
330 | return -EAGAIN; | |
331 | } | |
332 | ||
333 | static void activate_packet_queue(struct iowait *wait, int reason) | |
334 | { | |
335 | struct hfi1_user_sdma_pkt_q *pq = | |
336 | container_of(wait, struct hfi1_user_sdma_pkt_q, busy); | |
337 | xchg(&pq->state, SDMA_PKT_Q_ACTIVE); | |
338 | wake_up(&wait->wait_dma); | |
339 | }; | |
340 | ||
341 | static void sdma_kmem_cache_ctor(void *obj) | |
342 | { | |
343 | struct user_sdma_txreq *tx = (struct user_sdma_txreq *)obj; | |
344 | ||
345 | memset(tx, 0, sizeof(*tx)); | |
346 | } | |
347 | ||
348 | int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt, struct file *fp) | |
349 | { | |
9e10af47 | 350 | struct hfi1_filedata *fd; |
77241056 MM |
351 | int ret = 0; |
352 | unsigned memsize; | |
353 | char buf[64]; | |
354 | struct hfi1_devdata *dd; | |
355 | struct hfi1_user_sdma_comp_q *cq; | |
356 | struct hfi1_user_sdma_pkt_q *pq; | |
357 | unsigned long flags; | |
358 | ||
359 | if (!uctxt || !fp) { | |
360 | ret = -EBADF; | |
361 | goto done; | |
362 | } | |
363 | ||
9e10af47 IW |
364 | fd = fp->private_data; |
365 | ||
77241056 MM |
366 | if (!hfi1_sdma_comp_ring_size) { |
367 | ret = -EINVAL; | |
368 | goto done; | |
369 | } | |
370 | ||
371 | dd = uctxt->dd; | |
372 | ||
373 | pq = kzalloc(sizeof(*pq), GFP_KERNEL); | |
806e6e1b | 374 | if (!pq) |
77241056 | 375 | goto pq_nomem; |
806e6e1b | 376 | |
77241056 | 377 | memsize = sizeof(*pq->reqs) * hfi1_sdma_comp_ring_size; |
0f2d87d2 | 378 | pq->reqs = kzalloc(memsize, GFP_KERNEL); |
806e6e1b | 379 | if (!pq->reqs) |
77241056 | 380 | goto pq_reqs_nomem; |
806e6e1b | 381 | |
77241056 | 382 | INIT_LIST_HEAD(&pq->list); |
0f2d87d2 | 383 | INIT_LIST_HEAD(&pq->iovec_list); |
77241056 MM |
384 | pq->dd = dd; |
385 | pq->ctxt = uctxt->ctxt; | |
9e10af47 | 386 | pq->subctxt = fd->subctxt; |
77241056 MM |
387 | pq->n_max_reqs = hfi1_sdma_comp_ring_size; |
388 | pq->state = SDMA_PKT_Q_INACTIVE; | |
389 | atomic_set(&pq->n_reqs, 0); | |
0f2d87d2 | 390 | spin_lock_init(&pq->iovec_lock); |
a0d40693 | 391 | init_waitqueue_head(&pq->wait); |
77241056 MM |
392 | |
393 | iowait_init(&pq->busy, 0, NULL, defer_packet_queue, | |
394 | activate_packet_queue); | |
395 | pq->reqidx = 0; | |
396 | snprintf(buf, 64, "txreq-kmem-cache-%u-%u-%u", dd->unit, uctxt->ctxt, | |
9e10af47 | 397 | fd->subctxt); |
77241056 MM |
398 | pq->txreq_cache = kmem_cache_create(buf, |
399 | sizeof(struct user_sdma_txreq), | |
400 | L1_CACHE_BYTES, | |
401 | SLAB_HWCACHE_ALIGN, | |
402 | sdma_kmem_cache_ctor); | |
403 | if (!pq->txreq_cache) { | |
404 | dd_dev_err(dd, "[%u] Failed to allocate TxReq cache\n", | |
405 | uctxt->ctxt); | |
406 | goto pq_txreq_nomem; | |
407 | } | |
9e10af47 | 408 | fd->pq = pq; |
77241056 | 409 | cq = kzalloc(sizeof(*cq), GFP_KERNEL); |
806e6e1b | 410 | if (!cq) |
77241056 | 411 | goto cq_nomem; |
77241056 MM |
412 | |
413 | memsize = ALIGN(sizeof(*cq->comps) * hfi1_sdma_comp_ring_size, | |
414 | PAGE_SIZE); | |
415 | cq->comps = vmalloc_user(memsize); | |
806e6e1b | 416 | if (!cq->comps) |
77241056 | 417 | goto cq_comps_nomem; |
806e6e1b | 418 | |
77241056 | 419 | cq->nentries = hfi1_sdma_comp_ring_size; |
9e10af47 | 420 | fd->cq = cq; |
77241056 MM |
421 | |
422 | spin_lock_irqsave(&uctxt->sdma_qlock, flags); | |
423 | list_add(&pq->list, &uctxt->sdma_queues); | |
424 | spin_unlock_irqrestore(&uctxt->sdma_qlock, flags); | |
425 | goto done; | |
426 | ||
427 | cq_comps_nomem: | |
428 | kfree(cq); | |
429 | cq_nomem: | |
430 | kmem_cache_destroy(pq->txreq_cache); | |
431 | pq_txreq_nomem: | |
432 | kfree(pq->reqs); | |
433 | pq_reqs_nomem: | |
434 | kfree(pq); | |
9e10af47 | 435 | fd->pq = NULL; |
77241056 MM |
436 | pq_nomem: |
437 | ret = -ENOMEM; | |
438 | done: | |
439 | return ret; | |
440 | } | |
441 | ||
442 | int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd) | |
443 | { | |
444 | struct hfi1_ctxtdata *uctxt = fd->uctxt; | |
445 | struct hfi1_user_sdma_pkt_q *pq; | |
0f2d87d2 | 446 | struct user_sdma_iovec *iov; |
77241056 MM |
447 | unsigned long flags; |
448 | ||
449 | hfi1_cdbg(SDMA, "[%u:%u:%u] Freeing user SDMA queues", uctxt->dd->unit, | |
450 | uctxt->ctxt, fd->subctxt); | |
451 | pq = fd->pq; | |
452 | if (pq) { | |
77241056 MM |
453 | spin_lock_irqsave(&uctxt->sdma_qlock, flags); |
454 | if (!list_empty(&pq->list)) | |
455 | list_del_init(&pq->list); | |
456 | spin_unlock_irqrestore(&uctxt->sdma_qlock, flags); | |
457 | iowait_sdma_drain(&pq->busy); | |
a0d40693 MH |
458 | /* Wait until all requests have been freed. */ |
459 | wait_event_interruptible( | |
460 | pq->wait, | |
461 | (ACCESS_ONCE(pq->state) == SDMA_PKT_Q_INACTIVE)); | |
0f2d87d2 MH |
462 | /* Unpin any left over buffers. */ |
463 | while (!list_empty(&pq->iovec_list)) { | |
464 | spin_lock_irqsave(&pq->iovec_lock, flags); | |
465 | iov = list_first_entry(&pq->iovec_list, | |
466 | struct user_sdma_iovec, list); | |
467 | list_del_init(&iov->list); | |
468 | spin_unlock_irqrestore(&pq->iovec_lock, flags); | |
469 | unpin_vector_pages(iov); | |
470 | } | |
a0d40693 | 471 | kfree(pq->reqs); |
adad44d1 | 472 | kmem_cache_destroy(pq->txreq_cache); |
77241056 MM |
473 | kfree(pq); |
474 | fd->pq = NULL; | |
475 | } | |
476 | if (fd->cq) { | |
477 | if (fd->cq->comps) | |
478 | vfree(fd->cq->comps); | |
479 | kfree(fd->cq); | |
480 | fd->cq = NULL; | |
481 | } | |
482 | return 0; | |
483 | } | |
484 | ||
485 | int hfi1_user_sdma_process_request(struct file *fp, struct iovec *iovec, | |
486 | unsigned long dim, unsigned long *count) | |
487 | { | |
0f2d87d2 | 488 | int ret = 0, i = 0; |
9e10af47 IW |
489 | struct hfi1_filedata *fd = fp->private_data; |
490 | struct hfi1_ctxtdata *uctxt = fd->uctxt; | |
491 | struct hfi1_user_sdma_pkt_q *pq = fd->pq; | |
492 | struct hfi1_user_sdma_comp_q *cq = fd->cq; | |
77241056 | 493 | struct hfi1_devdata *dd = pq->dd; |
0f2d87d2 | 494 | unsigned long idx = 0, flags; |
77241056 MM |
495 | u8 pcount = initial_pkt_count; |
496 | struct sdma_req_info info; | |
497 | struct user_sdma_request *req; | |
0f2d87d2 | 498 | struct user_sdma_iovec *ioptr; |
77241056 MM |
499 | u8 opcode, sc, vl; |
500 | ||
501 | if (iovec[idx].iov_len < sizeof(info) + sizeof(req->hdr)) { | |
502 | hfi1_cdbg( | |
503 | SDMA, | |
504 | "[%u:%u:%u] First vector not big enough for header %lu/%lu", | |
9e10af47 | 505 | dd->unit, uctxt->ctxt, fd->subctxt, |
77241056 | 506 | iovec[idx].iov_len, sizeof(info) + sizeof(req->hdr)); |
faa98b86 | 507 | return -EINVAL; |
77241056 MM |
508 | } |
509 | ret = copy_from_user(&info, iovec[idx].iov_base, sizeof(info)); | |
510 | if (ret) { | |
511 | hfi1_cdbg(SDMA, "[%u:%u:%u] Failed to copy info QW (%d)", | |
9e10af47 | 512 | dd->unit, uctxt->ctxt, fd->subctxt, ret); |
faa98b86 | 513 | return -EFAULT; |
77241056 | 514 | } |
0f2d87d2 MH |
515 | |
516 | /* Process any completed vectors */ | |
517 | while (!list_empty(&pq->iovec_list)) { | |
518 | spin_lock_irqsave(&pq->iovec_lock, flags); | |
519 | ioptr = list_first_entry(&pq->iovec_list, | |
520 | struct user_sdma_iovec, list); | |
521 | list_del_init(&ioptr->list); | |
522 | spin_unlock_irqrestore(&pq->iovec_lock, flags); | |
523 | unpin_vector_pages(ioptr); | |
524 | } | |
525 | ||
9e10af47 | 526 | trace_hfi1_sdma_user_reqinfo(dd, uctxt->ctxt, fd->subctxt, |
77241056 | 527 | (u16 *)&info); |
0f2d87d2 MH |
528 | if (cq->comps[info.comp_idx].status == QUEUED || |
529 | test_bit(SDMA_REQ_IN_USE, &pq->reqs[info.comp_idx].flags)) { | |
77241056 | 530 | hfi1_cdbg(SDMA, "[%u:%u:%u] Entry %u is in QUEUED state", |
9e10af47 | 531 | dd->unit, uctxt->ctxt, fd->subctxt, |
77241056 | 532 | info.comp_idx); |
faa98b86 | 533 | return -EBADSLT; |
77241056 MM |
534 | } |
535 | if (!info.fragsize) { | |
536 | hfi1_cdbg(SDMA, | |
537 | "[%u:%u:%u:%u] Request does not specify fragsize", | |
9e10af47 | 538 | dd->unit, uctxt->ctxt, fd->subctxt, info.comp_idx); |
faa98b86 | 539 | return -EINVAL; |
77241056 MM |
540 | } |
541 | /* | |
542 | * We've done all the safety checks that we can up to this point, | |
543 | * "allocate" the request entry. | |
544 | */ | |
545 | hfi1_cdbg(SDMA, "[%u:%u:%u] Using req/comp entry %u\n", dd->unit, | |
9e10af47 | 546 | uctxt->ctxt, fd->subctxt, info.comp_idx); |
77241056 MM |
547 | req = pq->reqs + info.comp_idx; |
548 | memset(req, 0, sizeof(*req)); | |
549 | /* Mark the request as IN_USE before we start filling it in. */ | |
550 | set_bit(SDMA_REQ_IN_USE, &req->flags); | |
551 | req->data_iovs = req_iovcnt(info.ctrl) - 1; | |
552 | req->pq = pq; | |
553 | req->cq = cq; | |
a0d40693 | 554 | req->status = -1; |
77241056 | 555 | INIT_LIST_HEAD(&req->txps); |
a0d40693 | 556 | |
77241056 MM |
557 | memcpy(&req->info, &info, sizeof(info)); |
558 | ||
559 | if (req_opcode(info.ctrl) == EXPECTED) | |
560 | req->data_iovs--; | |
561 | ||
562 | if (!info.npkts || req->data_iovs > MAX_VECTORS_PER_REQ) { | |
563 | SDMA_DBG(req, "Too many vectors (%u/%u)", req->data_iovs, | |
564 | MAX_VECTORS_PER_REQ); | |
faa98b86 | 565 | return -EINVAL; |
77241056 MM |
566 | } |
567 | /* Copy the header from the user buffer */ | |
568 | ret = copy_from_user(&req->hdr, iovec[idx].iov_base + sizeof(info), | |
569 | sizeof(req->hdr)); | |
570 | if (ret) { | |
571 | SDMA_DBG(req, "Failed to copy header template (%d)", ret); | |
572 | ret = -EFAULT; | |
573 | goto free_req; | |
574 | } | |
575 | ||
576 | /* If Static rate control is not enabled, sanitize the header. */ | |
577 | if (!HFI1_CAP_IS_USET(STATIC_RATE_CTRL)) | |
578 | req->hdr.pbc[2] = 0; | |
579 | ||
580 | /* Validate the opcode. Do not trust packets from user space blindly. */ | |
581 | opcode = (be32_to_cpu(req->hdr.bth[0]) >> 24) & 0xff; | |
582 | if ((opcode & USER_OPCODE_CHECK_MASK) != | |
583 | USER_OPCODE_CHECK_VAL) { | |
584 | SDMA_DBG(req, "Invalid opcode (%d)", opcode); | |
585 | ret = -EINVAL; | |
586 | goto free_req; | |
587 | } | |
588 | /* | |
589 | * Validate the vl. Do not trust packets from user space blindly. | |
590 | * VL comes from PBC, SC comes from LRH, and the VL needs to | |
591 | * match the SC look up. | |
592 | */ | |
593 | vl = (le16_to_cpu(req->hdr.pbc[0]) >> 12) & 0xF; | |
594 | sc = (((be16_to_cpu(req->hdr.lrh[0]) >> 12) & 0xF) | | |
595 | (((le16_to_cpu(req->hdr.pbc[1]) >> 14) & 0x1) << 4)); | |
596 | if (vl >= dd->pport->vls_operational || | |
597 | vl != sc_to_vlt(dd, sc)) { | |
598 | SDMA_DBG(req, "Invalid SC(%u)/VL(%u)", sc, vl); | |
599 | ret = -EINVAL; | |
600 | goto free_req; | |
601 | } | |
602 | ||
603 | /* | |
604 | * Also should check the BTH.lnh. If it says the next header is GRH then | |
605 | * the RXE parsing will be off and will land in the middle of the KDETH | |
606 | * or miss it entirely. | |
607 | */ | |
608 | if ((be16_to_cpu(req->hdr.lrh[0]) & 0x3) == HFI1_LRH_GRH) { | |
609 | SDMA_DBG(req, "User tried to pass in a GRH"); | |
610 | ret = -EINVAL; | |
611 | goto free_req; | |
612 | } | |
613 | ||
614 | req->koffset = le32_to_cpu(req->hdr.kdeth.swdata[6]); | |
615 | /* Calculate the initial TID offset based on the values of | |
616 | KDETH.OFFSET and KDETH.OM that are passed in. */ | |
617 | req->tidoffset = KDETH_GET(req->hdr.kdeth.ver_tid_offset, OFFSET) * | |
618 | (KDETH_GET(req->hdr.kdeth.ver_tid_offset, OM) ? | |
619 | KDETH_OM_LARGE : KDETH_OM_SMALL); | |
620 | SDMA_DBG(req, "Initial TID offset %u", req->tidoffset); | |
621 | idx++; | |
622 | ||
623 | /* Save all the IO vector structures */ | |
624 | while (i < req->data_iovs) { | |
0f2d87d2 | 625 | INIT_LIST_HEAD(&req->iovs[i].list); |
77241056 MM |
626 | memcpy(&req->iovs[i].iov, iovec + idx++, sizeof(struct iovec)); |
627 | req->iovs[i].offset = 0; | |
628 | req->data_len += req->iovs[i++].iov.iov_len; | |
629 | } | |
630 | SDMA_DBG(req, "total data length %u", req->data_len); | |
631 | ||
632 | if (pcount > req->info.npkts) | |
633 | pcount = req->info.npkts; | |
634 | /* | |
635 | * Copy any TID info | |
636 | * User space will provide the TID info only when the | |
637 | * request type is EXPECTED. This is true even if there is | |
638 | * only one packet in the request and the header is already | |
639 | * setup. The reason for the singular TID case is that the | |
640 | * driver needs to perform safety checks. | |
641 | */ | |
642 | if (req_opcode(req->info.ctrl) == EXPECTED) { | |
643 | u16 ntids = iovec[idx].iov_len / sizeof(*req->tids); | |
644 | ||
645 | if (!ntids || ntids > MAX_TID_PAIR_ENTRIES) { | |
646 | ret = -EINVAL; | |
647 | goto free_req; | |
648 | } | |
649 | req->tids = kcalloc(ntids, sizeof(*req->tids), GFP_KERNEL); | |
650 | if (!req->tids) { | |
651 | ret = -ENOMEM; | |
652 | goto free_req; | |
653 | } | |
654 | /* | |
655 | * We have to copy all of the tids because they may vary | |
656 | * in size and, therefore, the TID count might not be | |
657 | * equal to the pkt count. However, there is no way to | |
658 | * tell at this point. | |
659 | */ | |
660 | ret = copy_from_user(req->tids, iovec[idx].iov_base, | |
661 | ntids * sizeof(*req->tids)); | |
662 | if (ret) { | |
663 | SDMA_DBG(req, "Failed to copy %d TIDs (%d)", | |
664 | ntids, ret); | |
665 | ret = -EFAULT; | |
666 | goto free_req; | |
667 | } | |
668 | req->n_tids = ntids; | |
669 | idx++; | |
670 | } | |
671 | ||
672 | /* Have to select the engine */ | |
673 | req->sde = sdma_select_engine_vl(dd, | |
9e10af47 | 674 | (u32)(uctxt->ctxt + fd->subctxt), |
77241056 MM |
675 | vl); |
676 | if (!req->sde || !sdma_running(req->sde)) { | |
677 | ret = -ECOMM; | |
678 | goto free_req; | |
679 | } | |
680 | ||
681 | /* We don't need an AHG entry if the request contains only one packet */ | |
682 | if (req->info.npkts > 1 && HFI1_CAP_IS_USET(SDMA_AHG)) { | |
683 | int ahg = sdma_ahg_alloc(req->sde); | |
684 | ||
685 | if (likely(ahg >= 0)) { | |
686 | req->ahg_idx = (u8)ahg; | |
687 | set_bit(SDMA_REQ_HAVE_AHG, &req->flags); | |
688 | } | |
689 | } | |
690 | ||
0f2d87d2 MH |
691 | set_comp_state(pq, cq, info.comp_idx, QUEUED, 0); |
692 | atomic_inc(&pq->n_reqs); | |
77241056 | 693 | /* Send the first N packets in the request to buy us some time */ |
0f2d87d2 MH |
694 | ret = user_sdma_send_pkts(req, pcount); |
695 | if (unlikely(ret < 0 && ret != -EBUSY)) { | |
696 | req->status = ret; | |
697 | atomic_dec(&pq->n_reqs); | |
698 | goto free_req; | |
77241056 | 699 | } |
77241056 | 700 | |
0f2d87d2 MH |
701 | /* |
702 | * It is possible that the SDMA engine would have processed all the | |
703 | * submitted packets by the time we get here. Therefore, only set | |
704 | * packet queue state to ACTIVE if there are still uncompleted | |
705 | * requests. | |
706 | */ | |
707 | if (atomic_read(&pq->n_reqs)) | |
708 | xchg(&pq->state, SDMA_PKT_Q_ACTIVE); | |
709 | ||
710 | /* | |
711 | * This is a somewhat blocking send implementation. | |
712 | * The driver will block the caller until all packets of the | |
713 | * request have been submitted to the SDMA engine. However, it | |
714 | * will not wait for send completions. | |
715 | */ | |
716 | while (!test_bit(SDMA_REQ_SEND_DONE, &req->flags)) { | |
717 | ret = user_sdma_send_pkts(req, pcount); | |
718 | if (ret < 0) { | |
719 | if (ret != -EBUSY) { | |
720 | req->status = ret; | |
721 | set_bit(SDMA_REQ_DONE_ERROR, &req->flags); | |
722 | return ret; | |
77241056 | 723 | } |
0f2d87d2 MH |
724 | wait_event_interruptible_timeout( |
725 | pq->busy.wait_dma, | |
726 | (pq->state == SDMA_PKT_Q_ACTIVE), | |
727 | msecs_to_jiffies( | |
728 | SDMA_IOWAIT_TIMEOUT)); | |
77241056 MM |
729 | } |
730 | ||
731 | } | |
77241056 | 732 | *count += idx; |
a0d40693 | 733 | return 0; |
77241056 | 734 | free_req: |
0f2d87d2 MH |
735 | user_sdma_free_request(req, true); |
736 | set_comp_state(pq, cq, info.comp_idx, ERROR, req->status); | |
77241056 MM |
737 | return ret; |
738 | } | |
739 | ||
740 | static inline u32 compute_data_length(struct user_sdma_request *req, | |
741 | struct user_sdma_txreq *tx) | |
742 | { | |
743 | /* | |
744 | * Determine the proper size of the packet data. | |
745 | * The size of the data of the first packet is in the header | |
746 | * template. However, it includes the header and ICRC, which need | |
747 | * to be subtracted. | |
748 | * The size of the remaining packets is the minimum of the frag | |
749 | * size (MTU) or remaining data in the request. | |
750 | */ | |
751 | u32 len; | |
752 | ||
753 | if (!req->seqnum) { | |
754 | len = ((be16_to_cpu(req->hdr.lrh[2]) << 2) - | |
755 | (sizeof(tx->hdr) - 4)); | |
756 | } else if (req_opcode(req->info.ctrl) == EXPECTED) { | |
757 | u32 tidlen = EXP_TID_GET(req->tids[req->tididx], LEN) * | |
758 | PAGE_SIZE; | |
759 | /* Get the data length based on the remaining space in the | |
760 | * TID pair. */ | |
761 | len = min(tidlen - req->tidoffset, (u32)req->info.fragsize); | |
762 | /* If we've filled up the TID pair, move to the next one. */ | |
763 | if (unlikely(!len) && ++req->tididx < req->n_tids && | |
764 | req->tids[req->tididx]) { | |
765 | tidlen = EXP_TID_GET(req->tids[req->tididx], | |
766 | LEN) * PAGE_SIZE; | |
767 | req->tidoffset = 0; | |
768 | len = min_t(u32, tidlen, req->info.fragsize); | |
769 | } | |
770 | /* Since the TID pairs map entire pages, make sure that we | |
771 | * are not going to try to send more data that we have | |
772 | * remaining. */ | |
773 | len = min(len, req->data_len - req->sent); | |
774 | } else | |
775 | len = min(req->data_len - req->sent, (u32)req->info.fragsize); | |
776 | SDMA_DBG(req, "Data Length = %u", len); | |
777 | return len; | |
778 | } | |
779 | ||
780 | static inline u32 get_lrh_len(struct hfi1_pkt_header hdr, u32 len) | |
781 | { | |
782 | /* (Size of complete header - size of PBC) + 4B ICRC + data length */ | |
783 | return ((sizeof(hdr) - sizeof(hdr.pbc)) + 4 + len); | |
784 | } | |
785 | ||
786 | static int user_sdma_send_pkts(struct user_sdma_request *req, unsigned maxpkts) | |
787 | { | |
788 | int ret = 0; | |
789 | unsigned npkts = 0; | |
790 | struct user_sdma_txreq *tx = NULL; | |
791 | struct hfi1_user_sdma_pkt_q *pq = NULL; | |
792 | struct user_sdma_iovec *iovec = NULL; | |
793 | ||
faa98b86 MH |
794 | if (!req->pq) |
795 | return -EINVAL; | |
77241056 MM |
796 | |
797 | pq = req->pq; | |
798 | ||
6a5464f2 MH |
799 | /* If tx completion has reported an error, we are done. */ |
800 | if (test_bit(SDMA_REQ_HAS_ERROR, &req->flags)) { | |
801 | set_bit(SDMA_REQ_DONE_ERROR, &req->flags); | |
802 | return -EFAULT; | |
803 | } | |
804 | ||
77241056 MM |
805 | /* |
806 | * Check if we might have sent the entire request already | |
807 | */ | |
808 | if (unlikely(req->seqnum == req->info.npkts)) { | |
809 | if (!list_empty(&req->txps)) | |
810 | goto dosend; | |
faa98b86 | 811 | return ret; |
77241056 MM |
812 | } |
813 | ||
814 | if (!maxpkts || maxpkts > req->info.npkts - req->seqnum) | |
815 | maxpkts = req->info.npkts - req->seqnum; | |
816 | ||
817 | while (npkts < maxpkts) { | |
818 | u32 datalen = 0, queued = 0, data_sent = 0; | |
819 | u64 iov_offset = 0; | |
820 | ||
821 | /* | |
822 | * Check whether any of the completions have come back | |
823 | * with errors. If so, we are not going to process any | |
824 | * more packets from this request. | |
825 | */ | |
826 | if (test_bit(SDMA_REQ_HAS_ERROR, &req->flags)) { | |
827 | set_bit(SDMA_REQ_DONE_ERROR, &req->flags); | |
faa98b86 | 828 | return -EFAULT; |
77241056 MM |
829 | } |
830 | ||
831 | tx = kmem_cache_alloc(pq->txreq_cache, GFP_KERNEL); | |
faa98b86 MH |
832 | if (!tx) |
833 | return -ENOMEM; | |
834 | ||
77241056 MM |
835 | tx->flags = 0; |
836 | tx->req = req; | |
837 | tx->busycount = 0; | |
b9fb6318 | 838 | tx->idx = -1; |
a0d40693 | 839 | INIT_LIST_HEAD(&tx->list); |
b9fb6318 | 840 | memset(tx->iovecs, 0, sizeof(tx->iovecs)); |
77241056 MM |
841 | |
842 | if (req->seqnum == req->info.npkts - 1) | |
b9fb6318 | 843 | tx->flags |= TXREQ_FLAGS_REQ_LAST_PKT; |
77241056 MM |
844 | |
845 | /* | |
846 | * Calculate the payload size - this is min of the fragment | |
847 | * (MTU) size or the remaining bytes in the request but only | |
848 | * if we have payload data. | |
849 | */ | |
850 | if (req->data_len) { | |
851 | iovec = &req->iovs[req->iov_idx]; | |
852 | if (ACCESS_ONCE(iovec->offset) == iovec->iov.iov_len) { | |
853 | if (++req->iov_idx == req->data_iovs) { | |
854 | ret = -EFAULT; | |
855 | goto free_txreq; | |
856 | } | |
857 | iovec = &req->iovs[req->iov_idx]; | |
858 | WARN_ON(iovec->offset); | |
859 | } | |
860 | ||
861 | /* | |
862 | * This request might include only a header and no user | |
863 | * data, so pin pages only if there is data and it the | |
864 | * pages have not been pinned already. | |
865 | */ | |
866 | if (unlikely(!iovec->pages && iovec->iov.iov_len)) { | |
867 | ret = pin_vector_pages(req, iovec); | |
868 | if (ret) | |
869 | goto free_tx; | |
870 | } | |
871 | ||
b9fb6318 | 872 | tx->iovecs[++tx->idx].vec = iovec; |
77241056 MM |
873 | datalen = compute_data_length(req, tx); |
874 | if (!datalen) { | |
875 | SDMA_DBG(req, | |
876 | "Request has data but pkt len is 0"); | |
877 | ret = -EFAULT; | |
878 | goto free_tx; | |
879 | } | |
880 | } | |
881 | ||
882 | if (test_bit(SDMA_REQ_HAVE_AHG, &req->flags)) { | |
883 | if (!req->seqnum) { | |
884 | u16 pbclen = le16_to_cpu(req->hdr.pbc[0]); | |
885 | u32 lrhlen = get_lrh_len(req->hdr, datalen); | |
886 | /* | |
887 | * Copy the request header into the tx header | |
888 | * because the HW needs a cacheline-aligned | |
889 | * address. | |
890 | * This copy can be optimized out if the hdr | |
891 | * member of user_sdma_request were also | |
892 | * cacheline aligned. | |
893 | */ | |
894 | memcpy(&tx->hdr, &req->hdr, sizeof(tx->hdr)); | |
895 | if (PBC2LRH(pbclen) != lrhlen) { | |
896 | pbclen = (pbclen & 0xf000) | | |
897 | LRH2PBC(lrhlen); | |
898 | tx->hdr.pbc[0] = cpu_to_le16(pbclen); | |
899 | } | |
900 | ret = sdma_txinit_ahg(&tx->txreq, | |
901 | SDMA_TXREQ_F_AHG_COPY, | |
902 | sizeof(tx->hdr) + datalen, | |
903 | req->ahg_idx, 0, NULL, 0, | |
904 | user_sdma_txreq_cb); | |
905 | if (ret) | |
906 | goto free_tx; | |
907 | ret = sdma_txadd_kvaddr(pq->dd, &tx->txreq, | |
908 | &tx->hdr, | |
909 | sizeof(tx->hdr)); | |
910 | if (ret) | |
911 | goto free_txreq; | |
912 | } else { | |
913 | int changes; | |
914 | ||
915 | changes = set_txreq_header_ahg(req, tx, | |
916 | datalen); | |
917 | if (changes < 0) | |
918 | goto free_tx; | |
919 | sdma_txinit_ahg(&tx->txreq, | |
920 | SDMA_TXREQ_F_USE_AHG, | |
921 | datalen, req->ahg_idx, changes, | |
922 | req->ahg, sizeof(req->hdr), | |
923 | user_sdma_txreq_cb); | |
924 | } | |
925 | } else { | |
926 | ret = sdma_txinit(&tx->txreq, 0, sizeof(req->hdr) + | |
927 | datalen, user_sdma_txreq_cb); | |
928 | if (ret) | |
929 | goto free_tx; | |
930 | /* | |
931 | * Modify the header for this packet. This only needs | |
932 | * to be done if we are not going to use AHG. Otherwise, | |
933 | * the HW will do it based on the changes we gave it | |
934 | * during sdma_txinit_ahg(). | |
935 | */ | |
936 | ret = set_txreq_header(req, tx, datalen); | |
937 | if (ret) | |
938 | goto free_txreq; | |
939 | } | |
940 | ||
941 | /* | |
942 | * If the request contains any data vectors, add up to | |
943 | * fragsize bytes to the descriptor. | |
944 | */ | |
945 | while (queued < datalen && | |
946 | (req->sent + data_sent) < req->data_len) { | |
947 | unsigned long base, offset; | |
948 | unsigned pageidx, len; | |
949 | ||
950 | base = (unsigned long)iovec->iov.iov_base; | |
951 | offset = ((base + iovec->offset + iov_offset) & | |
952 | ~PAGE_MASK); | |
953 | pageidx = (((iovec->offset + iov_offset + | |
954 | base) - (base & PAGE_MASK)) >> PAGE_SHIFT); | |
955 | len = offset + req->info.fragsize > PAGE_SIZE ? | |
956 | PAGE_SIZE - offset : req->info.fragsize; | |
957 | len = min((datalen - queued), len); | |
958 | ret = sdma_txadd_page(pq->dd, &tx->txreq, | |
959 | iovec->pages[pageidx], | |
960 | offset, len); | |
961 | if (ret) { | |
a0d40693 MH |
962 | SDMA_DBG(req, "SDMA txreq add page failed %d\n", |
963 | ret); | |
77241056 MM |
964 | goto free_txreq; |
965 | } | |
966 | iov_offset += len; | |
967 | queued += len; | |
968 | data_sent += len; | |
969 | if (unlikely(queued < datalen && | |
970 | pageidx == iovec->npages && | |
b9fb6318 MH |
971 | req->iov_idx < req->data_iovs - 1 && |
972 | tx->idx < ARRAY_SIZE(tx->iovecs))) { | |
77241056 | 973 | iovec->offset += iov_offset; |
b9fb6318 MH |
974 | tx->iovecs[tx->idx].flags |= |
975 | TXREQ_FLAGS_IOVEC_LAST_PKT; | |
77241056 MM |
976 | iovec = &req->iovs[++req->iov_idx]; |
977 | if (!iovec->pages) { | |
978 | ret = pin_vector_pages(req, iovec); | |
979 | if (ret) | |
980 | goto free_txreq; | |
981 | } | |
982 | iov_offset = 0; | |
b9fb6318 | 983 | tx->iovecs[++tx->idx].vec = iovec; |
77241056 MM |
984 | } |
985 | } | |
986 | /* | |
987 | * The txreq was submitted successfully so we can update | |
988 | * the counters. | |
989 | */ | |
990 | req->koffset += datalen; | |
991 | if (req_opcode(req->info.ctrl) == EXPECTED) | |
992 | req->tidoffset += datalen; | |
993 | req->sent += data_sent; | |
994 | if (req->data_len) { | |
b9fb6318 MH |
995 | tx->iovecs[tx->idx].vec->offset += iov_offset; |
996 | /* If we've reached the end of the io vector, mark it | |
997 | * so the callback can unpin the pages and free it. */ | |
998 | if (tx->iovecs[tx->idx].vec->offset == | |
999 | tx->iovecs[tx->idx].vec->iov.iov_len) | |
1000 | tx->iovecs[tx->idx].flags |= | |
1001 | TXREQ_FLAGS_IOVEC_LAST_PKT; | |
77241056 | 1002 | } |
b9fb6318 | 1003 | |
77241056 MM |
1004 | /* |
1005 | * It is important to increment this here as it is used to | |
1006 | * generate the BTH.PSN and, therefore, can't be bulk-updated | |
1007 | * outside of the loop. | |
1008 | */ | |
1009 | tx->seqnum = req->seqnum++; | |
1010 | list_add_tail(&tx->txreq.list, &req->txps); | |
1011 | npkts++; | |
1012 | } | |
1013 | dosend: | |
1014 | ret = sdma_send_txlist(req->sde, &pq->busy, &req->txps); | |
1015 | if (list_empty(&req->txps)) | |
1016 | if (req->seqnum == req->info.npkts) { | |
1017 | set_bit(SDMA_REQ_SEND_DONE, &req->flags); | |
1018 | /* | |
1019 | * The txreq has already been submitted to the HW queue | |
1020 | * so we can free the AHG entry now. Corruption will not | |
1021 | * happen due to the sequential manner in which | |
1022 | * descriptors are processed. | |
1023 | */ | |
1024 | if (test_bit(SDMA_REQ_HAVE_AHG, &req->flags)) | |
1025 | sdma_ahg_free(req->sde, req->ahg_idx); | |
1026 | } | |
faa98b86 MH |
1027 | return ret; |
1028 | ||
77241056 MM |
1029 | free_txreq: |
1030 | sdma_txclean(pq->dd, &tx->txreq); | |
1031 | free_tx: | |
1032 | kmem_cache_free(pq->txreq_cache, tx); | |
77241056 MM |
1033 | return ret; |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * How many pages in this iovec element? | |
1038 | */ | |
1039 | static inline int num_user_pages(const struct iovec *iov) | |
1040 | { | |
1041 | const unsigned long addr = (unsigned long) iov->iov_base; | |
1042 | const unsigned long len = iov->iov_len; | |
1043 | const unsigned long spage = addr & PAGE_MASK; | |
1044 | const unsigned long epage = (addr + len - 1) & PAGE_MASK; | |
1045 | ||
1046 | return 1 + ((epage - spage) >> PAGE_SHIFT); | |
1047 | } | |
1048 | ||
1049 | static int pin_vector_pages(struct user_sdma_request *req, | |
1050 | struct user_sdma_iovec *iovec) { | |
a0d40693 | 1051 | int pinned, npages; |
77241056 | 1052 | |
a0d40693 MH |
1053 | npages = num_user_pages(&iovec->iov); |
1054 | iovec->pages = kcalloc(npages, sizeof(*iovec->pages), GFP_KERNEL); | |
77241056 MM |
1055 | if (!iovec->pages) { |
1056 | SDMA_DBG(req, "Failed page array alloc"); | |
a0d40693 | 1057 | return -ENOMEM; |
77241056 | 1058 | } |
a0d40693 | 1059 | |
a0d40693 MH |
1060 | pinned = hfi1_acquire_user_pages((unsigned long)iovec->iov.iov_base, |
1061 | npages, 0, iovec->pages); | |
1062 | ||
1063 | if (pinned < 0) | |
1064 | return pinned; | |
1065 | ||
1066 | iovec->npages = pinned; | |
1067 | if (pinned != npages) { | |
1068 | SDMA_DBG(req, "Failed to pin pages (%d/%u)", pinned, npages); | |
0f2d87d2 | 1069 | unpin_vector_pages(iovec); |
a0d40693 | 1070 | return -EFAULT; |
77241056 | 1071 | } |
0f2d87d2 MH |
1072 | /* |
1073 | * Get a reference to the process's mm so we can use it when | |
1074 | * unpinning the io vectors. | |
1075 | */ | |
a0d40693 | 1076 | return 0; |
77241056 MM |
1077 | } |
1078 | ||
0f2d87d2 | 1079 | static void unpin_vector_pages(struct user_sdma_iovec *iovec) |
77241056 | 1080 | { |
a0d40693 MH |
1081 | hfi1_release_user_pages(iovec->pages, iovec->npages, 0); |
1082 | ||
77241056 MM |
1083 | kfree(iovec->pages); |
1084 | iovec->pages = NULL; | |
1085 | iovec->npages = 0; | |
1086 | iovec->offset = 0; | |
1087 | } | |
1088 | ||
1089 | static int check_header_template(struct user_sdma_request *req, | |
1090 | struct hfi1_pkt_header *hdr, u32 lrhlen, | |
1091 | u32 datalen) | |
1092 | { | |
1093 | /* | |
1094 | * Perform safety checks for any type of packet: | |
1095 | * - transfer size is multiple of 64bytes | |
1096 | * - packet length is multiple of 4bytes | |
1097 | * - entire request length is multiple of 4bytes | |
1098 | * - packet length is not larger than MTU size | |
1099 | * | |
1100 | * These checks are only done for the first packet of the | |
1101 | * transfer since the header is "given" to us by user space. | |
1102 | * For the remainder of the packets we compute the values. | |
1103 | */ | |
1104 | if (req->info.fragsize % PIO_BLOCK_SIZE || | |
1105 | lrhlen & 0x3 || req->data_len & 0x3 || | |
1106 | lrhlen > get_lrh_len(*hdr, req->info.fragsize)) | |
1107 | return -EINVAL; | |
1108 | ||
1109 | if (req_opcode(req->info.ctrl) == EXPECTED) { | |
1110 | /* | |
1111 | * The header is checked only on the first packet. Furthermore, | |
1112 | * we ensure that at least one TID entry is copied when the | |
1113 | * request is submitted. Therefore, we don't have to verify that | |
1114 | * tididx points to something sane. | |
1115 | */ | |
1116 | u32 tidval = req->tids[req->tididx], | |
1117 | tidlen = EXP_TID_GET(tidval, LEN) * PAGE_SIZE, | |
1118 | tididx = EXP_TID_GET(tidval, IDX), | |
1119 | tidctrl = EXP_TID_GET(tidval, CTRL), | |
1120 | tidoff; | |
1121 | __le32 kval = hdr->kdeth.ver_tid_offset; | |
1122 | ||
1123 | tidoff = KDETH_GET(kval, OFFSET) * | |
1124 | (KDETH_GET(req->hdr.kdeth.ver_tid_offset, OM) ? | |
1125 | KDETH_OM_LARGE : KDETH_OM_SMALL); | |
1126 | /* | |
1127 | * Expected receive packets have the following | |
1128 | * additional checks: | |
1129 | * - offset is not larger than the TID size | |
1130 | * - TIDCtrl values match between header and TID array | |
1131 | * - TID indexes match between header and TID array | |
1132 | */ | |
1133 | if ((tidoff + datalen > tidlen) || | |
1134 | KDETH_GET(kval, TIDCTRL) != tidctrl || | |
1135 | KDETH_GET(kval, TID) != tididx) | |
1136 | return -EINVAL; | |
1137 | } | |
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | /* | |
1142 | * Correctly set the BTH.PSN field based on type of | |
1143 | * transfer - eager packets can just increment the PSN but | |
1144 | * expected packets encode generation and sequence in the | |
1145 | * BTH.PSN field so just incrementing will result in errors. | |
1146 | */ | |
1147 | static inline u32 set_pkt_bth_psn(__be32 bthpsn, u8 expct, u32 frags) | |
1148 | { | |
1149 | u32 val = be32_to_cpu(bthpsn), | |
1150 | mask = (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffffull : | |
1151 | 0xffffffull), | |
1152 | psn = val & mask; | |
1153 | if (expct) | |
1154 | psn = (psn & ~BTH_SEQ_MASK) | ((psn + frags) & BTH_SEQ_MASK); | |
1155 | else | |
1156 | psn = psn + frags; | |
1157 | return psn & mask; | |
1158 | } | |
1159 | ||
1160 | static int set_txreq_header(struct user_sdma_request *req, | |
1161 | struct user_sdma_txreq *tx, u32 datalen) | |
1162 | { | |
1163 | struct hfi1_user_sdma_pkt_q *pq = req->pq; | |
1164 | struct hfi1_pkt_header *hdr = &tx->hdr; | |
1165 | u16 pbclen; | |
1166 | int ret; | |
1167 | u32 tidval = 0, lrhlen = get_lrh_len(*hdr, datalen); | |
1168 | ||
1169 | /* Copy the header template to the request before modification */ | |
1170 | memcpy(hdr, &req->hdr, sizeof(*hdr)); | |
1171 | ||
1172 | /* | |
1173 | * Check if the PBC and LRH length are mismatched. If so | |
1174 | * adjust both in the header. | |
1175 | */ | |
1176 | pbclen = le16_to_cpu(hdr->pbc[0]); | |
1177 | if (PBC2LRH(pbclen) != lrhlen) { | |
1178 | pbclen = (pbclen & 0xf000) | LRH2PBC(lrhlen); | |
1179 | hdr->pbc[0] = cpu_to_le16(pbclen); | |
1180 | hdr->lrh[2] = cpu_to_be16(lrhlen >> 2); | |
1181 | /* | |
1182 | * Third packet | |
1183 | * This is the first packet in the sequence that has | |
1184 | * a "static" size that can be used for the rest of | |
1185 | * the packets (besides the last one). | |
1186 | */ | |
1187 | if (unlikely(req->seqnum == 2)) { | |
1188 | /* | |
1189 | * From this point on the lengths in both the | |
1190 | * PBC and LRH are the same until the last | |
1191 | * packet. | |
1192 | * Adjust the template so we don't have to update | |
1193 | * every packet | |
1194 | */ | |
1195 | req->hdr.pbc[0] = hdr->pbc[0]; | |
1196 | req->hdr.lrh[2] = hdr->lrh[2]; | |
1197 | } | |
1198 | } | |
1199 | /* | |
1200 | * We only have to modify the header if this is not the | |
1201 | * first packet in the request. Otherwise, we use the | |
1202 | * header given to us. | |
1203 | */ | |
1204 | if (unlikely(!req->seqnum)) { | |
1205 | ret = check_header_template(req, hdr, lrhlen, datalen); | |
1206 | if (ret) | |
1207 | return ret; | |
1208 | goto done; | |
1209 | ||
1210 | } | |
1211 | ||
1212 | hdr->bth[2] = cpu_to_be32( | |
1213 | set_pkt_bth_psn(hdr->bth[2], | |
1214 | (req_opcode(req->info.ctrl) == EXPECTED), | |
1215 | req->seqnum)); | |
1216 | ||
1217 | /* Set ACK request on last packet */ | |
b9fb6318 | 1218 | if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) |
77241056 MM |
1219 | hdr->bth[2] |= cpu_to_be32(1UL<<31); |
1220 | ||
1221 | /* Set the new offset */ | |
1222 | hdr->kdeth.swdata[6] = cpu_to_le32(req->koffset); | |
1223 | /* Expected packets have to fill in the new TID information */ | |
1224 | if (req_opcode(req->info.ctrl) == EXPECTED) { | |
1225 | tidval = req->tids[req->tididx]; | |
1226 | /* | |
1227 | * If the offset puts us at the end of the current TID, | |
1228 | * advance everything. | |
1229 | */ | |
1230 | if ((req->tidoffset) == (EXP_TID_GET(tidval, LEN) * | |
1231 | PAGE_SIZE)) { | |
1232 | req->tidoffset = 0; | |
1233 | /* Since we don't copy all the TIDs, all at once, | |
1234 | * we have to check again. */ | |
1235 | if (++req->tididx > req->n_tids - 1 || | |
1236 | !req->tids[req->tididx]) { | |
1237 | return -EINVAL; | |
1238 | } | |
1239 | tidval = req->tids[req->tididx]; | |
1240 | } | |
1241 | req->omfactor = EXP_TID_GET(tidval, LEN) * PAGE_SIZE >= | |
1242 | KDETH_OM_MAX_SIZE ? KDETH_OM_LARGE : KDETH_OM_SMALL; | |
1243 | /* Set KDETH.TIDCtrl based on value for this TID. */ | |
1244 | KDETH_SET(hdr->kdeth.ver_tid_offset, TIDCTRL, | |
1245 | EXP_TID_GET(tidval, CTRL)); | |
1246 | /* Set KDETH.TID based on value for this TID */ | |
1247 | KDETH_SET(hdr->kdeth.ver_tid_offset, TID, | |
1248 | EXP_TID_GET(tidval, IDX)); | |
1249 | /* Clear KDETH.SH only on the last packet */ | |
b9fb6318 | 1250 | if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) |
77241056 MM |
1251 | KDETH_SET(hdr->kdeth.ver_tid_offset, SH, 0); |
1252 | /* | |
1253 | * Set the KDETH.OFFSET and KDETH.OM based on size of | |
1254 | * transfer. | |
1255 | */ | |
1256 | SDMA_DBG(req, "TID offset %ubytes %uunits om%u", | |
1257 | req->tidoffset, req->tidoffset / req->omfactor, | |
1258 | !!(req->omfactor - KDETH_OM_SMALL)); | |
1259 | KDETH_SET(hdr->kdeth.ver_tid_offset, OFFSET, | |
1260 | req->tidoffset / req->omfactor); | |
1261 | KDETH_SET(hdr->kdeth.ver_tid_offset, OM, | |
1262 | !!(req->omfactor - KDETH_OM_SMALL)); | |
1263 | } | |
1264 | done: | |
1265 | trace_hfi1_sdma_user_header(pq->dd, pq->ctxt, pq->subctxt, | |
1266 | req->info.comp_idx, hdr, tidval); | |
1267 | return sdma_txadd_kvaddr(pq->dd, &tx->txreq, hdr, sizeof(*hdr)); | |
1268 | } | |
1269 | ||
1270 | static int set_txreq_header_ahg(struct user_sdma_request *req, | |
1271 | struct user_sdma_txreq *tx, u32 len) | |
1272 | { | |
1273 | int diff = 0; | |
1274 | struct hfi1_user_sdma_pkt_q *pq = req->pq; | |
1275 | struct hfi1_pkt_header *hdr = &req->hdr; | |
1276 | u16 pbclen = le16_to_cpu(hdr->pbc[0]); | |
1277 | u32 val32, tidval = 0, lrhlen = get_lrh_len(*hdr, len); | |
1278 | ||
1279 | if (PBC2LRH(pbclen) != lrhlen) { | |
1280 | /* PBC.PbcLengthDWs */ | |
1281 | AHG_HEADER_SET(req->ahg, diff, 0, 0, 12, | |
1282 | cpu_to_le16(LRH2PBC(lrhlen))); | |
1283 | /* LRH.PktLen (we need the full 16 bits due to byte swap) */ | |
1284 | AHG_HEADER_SET(req->ahg, diff, 3, 0, 16, | |
1285 | cpu_to_be16(lrhlen >> 2)); | |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * Do the common updates | |
1290 | */ | |
1291 | /* BTH.PSN and BTH.A */ | |
1292 | val32 = (be32_to_cpu(hdr->bth[2]) + req->seqnum) & | |
1293 | (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffff : 0xffffff); | |
b9fb6318 | 1294 | if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) |
77241056 MM |
1295 | val32 |= 1UL << 31; |
1296 | AHG_HEADER_SET(req->ahg, diff, 6, 0, 16, cpu_to_be16(val32 >> 16)); | |
1297 | AHG_HEADER_SET(req->ahg, diff, 6, 16, 16, cpu_to_be16(val32 & 0xffff)); | |
1298 | /* KDETH.Offset */ | |
1299 | AHG_HEADER_SET(req->ahg, diff, 15, 0, 16, | |
1300 | cpu_to_le16(req->koffset & 0xffff)); | |
1301 | AHG_HEADER_SET(req->ahg, diff, 15, 16, 16, | |
1302 | cpu_to_le16(req->koffset >> 16)); | |
1303 | if (req_opcode(req->info.ctrl) == EXPECTED) { | |
1304 | __le16 val; | |
1305 | ||
1306 | tidval = req->tids[req->tididx]; | |
1307 | ||
1308 | /* | |
1309 | * If the offset puts us at the end of the current TID, | |
1310 | * advance everything. | |
1311 | */ | |
1312 | if ((req->tidoffset) == (EXP_TID_GET(tidval, LEN) * | |
1313 | PAGE_SIZE)) { | |
1314 | req->tidoffset = 0; | |
1315 | /* Since we don't copy all the TIDs, all at once, | |
1316 | * we have to check again. */ | |
1317 | if (++req->tididx > req->n_tids - 1 || | |
1318 | !req->tids[req->tididx]) { | |
1319 | return -EINVAL; | |
1320 | } | |
1321 | tidval = req->tids[req->tididx]; | |
1322 | } | |
1323 | req->omfactor = ((EXP_TID_GET(tidval, LEN) * | |
1324 | PAGE_SIZE) >= | |
1325 | KDETH_OM_MAX_SIZE) ? KDETH_OM_LARGE : | |
1326 | KDETH_OM_SMALL; | |
1327 | /* KDETH.OM and KDETH.OFFSET (TID) */ | |
1328 | AHG_HEADER_SET(req->ahg, diff, 7, 0, 16, | |
1329 | ((!!(req->omfactor - KDETH_OM_SMALL)) << 15 | | |
1330 | ((req->tidoffset / req->omfactor) & 0x7fff))); | |
1331 | /* KDETH.TIDCtrl, KDETH.TID */ | |
1332 | val = cpu_to_le16(((EXP_TID_GET(tidval, CTRL) & 0x3) << 10) | | |
1333 | (EXP_TID_GET(tidval, IDX) & 0x3ff)); | |
1334 | /* Clear KDETH.SH on last packet */ | |
b9fb6318 | 1335 | if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) { |
77241056 MM |
1336 | val |= cpu_to_le16(KDETH_GET(hdr->kdeth.ver_tid_offset, |
1337 | INTR) >> 16); | |
1338 | val &= cpu_to_le16(~(1U << 13)); | |
1339 | AHG_HEADER_SET(req->ahg, diff, 7, 16, 14, val); | |
1340 | } else | |
1341 | AHG_HEADER_SET(req->ahg, diff, 7, 16, 12, val); | |
1342 | } | |
1343 | ||
1344 | trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt, | |
1345 | req->info.comp_idx, req->sde->this_idx, | |
1346 | req->ahg_idx, req->ahg, diff, tidval); | |
1347 | return diff; | |
1348 | } | |
1349 | ||
a0d40693 MH |
1350 | /* |
1351 | * SDMA tx request completion callback. Called when the SDMA progress | |
1352 | * state machine gets notification that the SDMA descriptors for this | |
1353 | * tx request have been processed by the DMA engine. Called in | |
1354 | * interrupt context. | |
1355 | */ | |
77241056 MM |
1356 | static void user_sdma_txreq_cb(struct sdma_txreq *txreq, int status, |
1357 | int drain) | |
1358 | { | |
1359 | struct user_sdma_txreq *tx = | |
1360 | container_of(txreq, struct user_sdma_txreq, txreq); | |
a0d40693 | 1361 | struct user_sdma_request *req; |
0f2d87d2 MH |
1362 | struct hfi1_user_sdma_pkt_q *pq; |
1363 | struct hfi1_user_sdma_comp_q *cq; | |
1364 | u16 idx; | |
a0d40693 | 1365 | int i; |
77241056 | 1366 | |
a0d40693 | 1367 | if (!tx->req) |
77241056 MM |
1368 | return; |
1369 | ||
a0d40693 | 1370 | req = tx->req; |
0f2d87d2 MH |
1371 | pq = req->pq; |
1372 | cq = req->cq; | |
b9fb6318 | 1373 | |
a0d40693 MH |
1374 | /* |
1375 | * If we have any io vectors associated with this txreq, | |
1376 | * check whether they need to be 'freed'. We can't free them | |
1377 | * here because the unpin function needs to be able to sleep. | |
1378 | */ | |
1379 | for (i = tx->idx; i >= 0; i--) { | |
1380 | if (tx->iovecs[i].flags & TXREQ_FLAGS_IOVEC_LAST_PKT) { | |
0f2d87d2 MH |
1381 | spin_lock(&pq->iovec_lock); |
1382 | list_add_tail(&tx->iovecs[i].vec->list, | |
1383 | &pq->iovec_list); | |
1384 | spin_unlock(&pq->iovec_lock); | |
b9fb6318 MH |
1385 | } |
1386 | } | |
77241056 | 1387 | |
77241056 | 1388 | if (status != SDMA_TXREQ_S_OK) { |
a0d40693 MH |
1389 | SDMA_DBG(req, "SDMA completion with error %d", |
1390 | status); | |
77241056 | 1391 | set_bit(SDMA_REQ_HAS_ERROR, &req->flags); |
a0d40693 MH |
1392 | } |
1393 | ||
0f2d87d2 MH |
1394 | req->seqcomp = tx->seqnum; |
1395 | kmem_cache_free(pq->txreq_cache, tx); | |
1396 | tx = NULL; | |
1397 | ||
1398 | idx = req->info.comp_idx; | |
1399 | if (req->status == -1 && status == SDMA_TXREQ_S_OK) { | |
1400 | if (req->seqcomp == req->info.npkts - 1) { | |
1401 | req->status = 0; | |
1402 | user_sdma_free_request(req, false); | |
1403 | pq_update(pq); | |
1404 | set_comp_state(pq, cq, idx, COMPLETE, 0); | |
1405 | } | |
77241056 | 1406 | } else { |
0f2d87d2 MH |
1407 | if (status != SDMA_TXREQ_S_OK) |
1408 | req->status = status; | |
1409 | if (req->seqcomp == ACCESS_ONCE(req->seqnum) && | |
1410 | test_bit(SDMA_REQ_DONE_ERROR, &req->flags)) { | |
1411 | user_sdma_free_request(req, false); | |
1412 | pq_update(pq); | |
1413 | set_comp_state(pq, cq, idx, ERROR, req->status); | |
1414 | } | |
a0d40693 MH |
1415 | } |
1416 | } | |
1417 | ||
0f2d87d2 | 1418 | static inline void pq_update(struct hfi1_user_sdma_pkt_q *pq) |
a0d40693 | 1419 | { |
0f2d87d2 | 1420 | if (atomic_dec_and_test(&pq->n_reqs)) { |
77241056 | 1421 | xchg(&pq->state, SDMA_PKT_Q_INACTIVE); |
a0d40693 MH |
1422 | wake_up(&pq->wait); |
1423 | } | |
77241056 MM |
1424 | } |
1425 | ||
0f2d87d2 | 1426 | static void user_sdma_free_request(struct user_sdma_request *req, bool unpin) |
77241056 MM |
1427 | { |
1428 | if (!list_empty(&req->txps)) { | |
1429 | struct sdma_txreq *t, *p; | |
1430 | ||
1431 | list_for_each_entry_safe(t, p, &req->txps, list) { | |
1432 | struct user_sdma_txreq *tx = | |
1433 | container_of(t, struct user_sdma_txreq, txreq); | |
1434 | list_del_init(&t->list); | |
1435 | sdma_txclean(req->pq->dd, t); | |
1436 | kmem_cache_free(req->pq->txreq_cache, tx); | |
1437 | } | |
1438 | } | |
0f2d87d2 | 1439 | if (req->data_iovs && unpin) { |
77241056 MM |
1440 | int i; |
1441 | ||
1442 | for (i = 0; i < req->data_iovs; i++) | |
1443 | if (req->iovs[i].npages && req->iovs[i].pages) | |
0f2d87d2 | 1444 | unpin_vector_pages(&req->iovs[i]); |
77241056 | 1445 | } |
77241056 MM |
1446 | kfree(req->tids); |
1447 | clear_bit(SDMA_REQ_IN_USE, &req->flags); | |
1448 | } | |
1449 | ||
0f2d87d2 MH |
1450 | static inline void set_comp_state(struct hfi1_user_sdma_pkt_q *pq, |
1451 | struct hfi1_user_sdma_comp_q *cq, | |
1452 | u16 idx, enum hfi1_sdma_comp_state state, | |
1453 | int ret) | |
77241056 | 1454 | { |
0f2d87d2 MH |
1455 | hfi1_cdbg(SDMA, "[%u:%u:%u:%u] Setting completion status %u %d", |
1456 | pq->dd->unit, pq->ctxt, pq->subctxt, idx, state, ret); | |
1457 | cq->comps[idx].status = state; | |
77241056 | 1458 | if (state == ERROR) |
0f2d87d2 MH |
1459 | cq->comps[idx].errcode = -ret; |
1460 | trace_hfi1_sdma_user_completion(pq->dd, pq->ctxt, pq->subctxt, | |
1461 | idx, state, ret); | |
77241056 | 1462 | } |