projects / deliverable / linux.git / blame
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|---|---|---|
| 58c43401 LF |
1 | /****************************************************************************** |
| 2 | * | |
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify it | |
| 6 | * under the terms of version 2 of the GNU General Public License as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 12 | * more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License along with | |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., | |
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
| 17 | * | |
| 18 | *******************************************************************************/ | |
| 19 | #ifndef __RTL8188E_SPEC_H__ | |
| 20 | #define __RTL8188E_SPEC_H__ | |
| 21 | ||
| 58c43401 LF |
22 | #define BIT0 0x00000001 |
| 23 | #define BIT1 0x00000002 | |
| 24 | #define BIT2 0x00000004 | |
| 25 | #define BIT3 0x00000008 | |
| 26 | #define BIT4 0x00000010 | |
| 27 | #define BIT5 0x00000020 | |
| 28 | #define BIT6 0x00000040 | |
| 29 | #define BIT7 0x00000080 | |
| 30 | #define BIT8 0x00000100 | |
| 31 | #define BIT9 0x00000200 | |
| 32 | #define BIT10 0x00000400 | |
| 33 | #define BIT11 0x00000800 | |
| 34 | #define BIT12 0x00001000 | |
| 35 | #define BIT13 0x00002000 | |
| 36 | #define BIT14 0x00004000 | |
| 37 | #define BIT15 0x00008000 | |
| 38 | #define BIT16 0x00010000 | |
| 39 | #define BIT17 0x00020000 | |
| 40 | #define BIT18 0x00040000 | |
| 41 | #define BIT19 0x00080000 | |
| 42 | #define BIT20 0x00100000 | |
| 43 | #define BIT21 0x00200000 | |
| 44 | #define BIT22 0x00400000 | |
| 45 | #define BIT23 0x00800000 | |
| 46 | #define BIT24 0x01000000 | |
| 47 | #define BIT25 0x02000000 | |
| 48 | #define BIT26 0x04000000 | |
| 49 | #define BIT27 0x08000000 | |
| 50 | #define BIT28 0x10000000 | |
| 51 | #define BIT29 0x20000000 | |
| 52 | #define BIT30 0x40000000 | |
| 53 | #define BIT31 0x80000000 | |
| 54 | ||
| 55 | /* 8192C Regsiter offset definition */ | |
| 56 | ||
| 57 | #define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ | |
| 58 | #define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */ | |
| 59 | ||
| 60 | #define MAC_ADDR_LEN 6 | |
| 61 | /* 8188E PKT_BUFF_ACCESS_CTRL value */ | |
| 62 | #define TXPKT_BUF_SELECT 0x69 | |
| 63 | #define RXPKT_BUF_SELECT 0xA5 | |
| 64 | #define DISABLE_TRXPKT_BUF_ACCESS 0x0 | |
| 65 | ||
| 66 | ||
| 7194ea87 | 67 | /* 0x0000h ~ 0x00FFh System Configuration */ |
| 58c43401 LF |
68 | #define REG_SYS_ISO_CTRL 0x0000 |
| 69 | #define REG_SYS_FUNC_EN 0x0002 | |
| 70 | #define REG_APS_FSMCO 0x0004 | |
| 71 | #define REG_SYS_CLKR 0x0008 | |
| 72 | #define REG_9346CR 0x000A | |
| 73 | #define REG_EE_VPD 0x000C | |
| 74 | #define REG_AFE_MISC 0x0010 | |
| 75 | #define REG_SPS0_CTRL 0x0011 | |
| 76 | #define REG_SPS_OCP_CFG 0x0018 | |
| 77 | #define REG_RSV_CTRL 0x001C | |
| 78 | #define REG_RF_CTRL 0x001F | |
| 79 | #define REG_LDOA15_CTRL 0x0020 | |
| 80 | #define REG_LDOV12D_CTRL 0x0021 | |
| 81 | #define REG_LDOHCI12_CTRL 0x0022 | |
| 82 | #define REG_LPLDO_CTRL 0x0023 | |
| 83 | #define REG_AFE_XTAL_CTRL 0x0024 | |
| 84 | #define REG_AFE_PLL_CTRL 0x0028 | |
| 85 | #define REG_APE_PLL_CTRL_EXT 0x002c | |
| 86 | #define REG_EFUSE_CTRL 0x0030 | |
| 87 | #define REG_EFUSE_TEST 0x0034 | |
| 88 | #define REG_GPIO_MUXCFG 0x0040 | |
| 89 | #define REG_GPIO_IO_SEL 0x0042 | |
| 90 | #define REG_MAC_PINMUX_CFG 0x0043 | |
| 91 | #define REG_GPIO_PIN_CTRL 0x0044 | |
| 92 | #define REG_GPIO_INTM 0x0048 | |
| 93 | #define REG_LEDCFG0 0x004C | |
| 94 | #define REG_LEDCFG1 0x004D | |
| 95 | #define REG_LEDCFG2 0x004E | |
| 96 | #define REG_LEDCFG3 0x004F | |
| 97 | #define REG_FSIMR 0x0050 | |
| 98 | #define REG_FSISR 0x0054 | |
| 99 | #define REG_HSIMR 0x0058 | |
| 100 | #define REG_HSISR 0x005c | |
| 101 | #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS | |
| 102 | * Multi-Function GPIO Pin Control. */ | |
| 103 | #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS | |
| 104 | * Multi-Function GPIO Select. */ | |
| 105 | #define REG_BB_PAD_CTRL 0x0064 | |
| 106 | #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS | |
| 107 | * Multi-Function control source. */ | |
| 108 | #define REG_GPIO_OUTPUT 0x006c | |
| 109 | #define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ | |
| 110 | #define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ | |
| 111 | #define REG_MCUFWDL 0x0080 | |
| 112 | #define REG_WOL_EVENT 0x0081 /* RTL8188E */ | |
| 113 | #define REG_MCUTSTCFG 0x0084 | |
| 114 | #define REG_HMEBOX_E0 0x0088 | |
| 115 | #define REG_HMEBOX_E1 0x008A | |
| 116 | #define REG_HMEBOX_E2 0x008C | |
| 117 | #define REG_HMEBOX_E3 0x008E | |
| 118 | #define REG_HMEBOX_EXT_0 0x01F0 | |
| 119 | #define REG_HMEBOX_EXT_1 0x01F4 | |
| 120 | #define REG_HMEBOX_EXT_2 0x01F8 | |
| 121 | #define REG_HMEBOX_EXT_3 0x01FC | |
| 122 | #define REG_HIMR_88E 0x00B0 | |
| 123 | #define REG_HISR_88E 0x00B4 | |
| 124 | #define REG_HIMRE_88E 0x00B8 | |
| 125 | #define REG_HISRE_88E 0x00BC | |
| 126 | #define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection | |
| 127 | * for RTL8723 */ | |
| 128 | #define REG_BIST_SCAN 0x00D0 | |
| 129 | #define REG_BIST_RPT 0x00D4 | |
| 130 | #define REG_BIST_ROM_RPT 0x00D8 | |
| 131 | #define REG_USB_SIE_INTF 0x00E0 | |
| 132 | #define REG_PCIE_MIO_INTF 0x00E4 | |
| 133 | #define REG_PCIE_MIO_INTD 0x00E8 | |
| 134 | #define REG_HPON_FSM 0x00EC | |
| 135 | #define REG_SYS_CFG 0x00F0 | |
| 136 | #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ | |
| 137 | #define REG_TYPE_ID 0x00FC | |
| 138 | ||
| 139 | #define REG_MAC_PHY_CTRL_NORMAL 0x00f8 | |
| 140 | ||
| 7194ea87 | 141 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ |
| 58c43401 LF |
142 | #define REG_CR 0x0100 |
| 143 | #define REG_PBP 0x0104 | |
| 144 | #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 | |
| 145 | #define REG_TRXDMA_CTRL 0x010C | |
| 146 | #define REG_TRXFF_BNDY 0x0114 | |
| 147 | #define REG_TRXFF_STATUS 0x0118 | |
| 148 | #define REG_RXFF_PTR 0x011C | |
| 149 | /* define REG_HIMR 0x0120 */ | |
| 150 | /* define REG_HISR 0x0124 */ | |
| 151 | #define REG_HIMRE 0x0128 | |
| 152 | #define REG_HISRE 0x012C | |
| 153 | #define REG_CPWM 0x012F | |
| 154 | #define REG_FWIMR 0x0130 | |
| 155 | #define REG_FTIMR 0x0138 | |
| 156 | #define REG_FWISR 0x0134 | |
| 157 | #define REG_PKTBUF_DBG_CTRL 0x0140 | |
| 158 | #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) | |
| 159 | #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) | |
| 160 | #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) | |
| 161 | #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) | |
| 162 | #define REG_PKTBUF_DBG_DATA_L 0x0144 | |
| 163 | #define REG_PKTBUF_DBG_DATA_H 0x0148 | |
| 164 | ||
| 165 | #define REG_TC0_CTRL 0x0150 | |
| 166 | #define REG_TC1_CTRL 0x0154 | |
| 167 | #define REG_TC2_CTRL 0x0158 | |
| 168 | #define REG_TC3_CTRL 0x015C | |
| 169 | #define REG_TC4_CTRL 0x0160 | |
| 170 | #define REG_TCUNIT_BASE 0x0164 | |
| 171 | #define REG_MBIST_START 0x0174 | |
| 172 | #define REG_MBIST_DONE 0x0178 | |
| 173 | #define REG_MBIST_FAIL 0x017C | |
| 174 | #define REG_32K_CTRL 0x0194 /* RTL8188E */ | |
| 175 | #define REG_C2HEVT_MSG_NORMAL 0x01A0 | |
| 176 | #define REG_C2HEVT_CLEAR 0x01AF | |
| 177 | #define REG_MCUTST_1 0x01c0 | |
| 178 | #define REG_FMETHR 0x01C8 | |
| 179 | #define REG_HMETFR 0x01CC | |
| 180 | #define REG_HMEBOX_0 0x01D0 | |
| 181 | #define REG_HMEBOX_1 0x01D4 | |
| 182 | #define REG_HMEBOX_2 0x01D8 | |
| 183 | #define REG_HMEBOX_3 0x01DC | |
| 184 | ||
| 185 | #define REG_LLT_INIT 0x01E0 | |
| 186 | ||
| 7194ea87 | 187 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ |
| 58c43401 LF |
188 | #define REG_RQPN 0x0200 |
| 189 | #define REG_FIFOPAGE 0x0204 | |
| 190 | #define REG_TDECTRL 0x0208 | |
| 191 | #define REG_TXDMA_OFFSET_CHK 0x020C | |
| 192 | #define REG_TXDMA_STATUS 0x0210 | |
| 193 | #define REG_RQPN_NPQ 0x0214 | |
| 194 | ||
| 7194ea87 | 195 | /* 0x0280h ~ 0x02FFh RXDMA Configuration */ |
| 58c43401 LF |
196 | #define REG_RXDMA_AGG_PG_TH 0x0280 |
| 197 | #define REG_RXPKT_NUM 0x0284 | |
| 198 | #define REG_RXDMA_STATUS 0x0288 | |
| 199 | ||
| 7194ea87 | 200 | /* 0x0300h ~ 0x03FFh PCIe */ |
| 58c43401 LF |
201 | #define REG_PCIE_CTRL_REG 0x0300 |
| 202 | #define REG_INT_MIG 0x0304 /* Interrupt Migration */ | |
| 203 | #define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */ | |
| 204 | #define REG_HQ_DESA 0x0310 /* TX High Queue Descr Addr */ | |
| 205 | #define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descr Addr*/ | |
| 206 | #define REG_VOQ_DESA 0x0320 /* TX VO Queue Descr Addr */ | |
| 207 | #define REG_VIQ_DESA 0x0328 /* TX VI Queue Descr Addr */ | |
| 208 | #define REG_BEQ_DESA 0x0330 /* TX BE Queue Descr Addr */ | |
| 209 | #define REG_BKQ_DESA 0x0338 /* TX BK Queue Descr Addr */ | |
| 210 | #define REG_RX_DESA 0x0340 /* RX Queue Descr Addr */ | |
| 211 | #define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ | |
| 212 | #define REG_DBG_SEL 0x0360 /* Debug Selection Register */ | |
| 213 | #define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ | |
| 214 | #define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ | |
| 215 | #define REG_WATCH_DOG 0x0368 | |
| 216 | ||
| 217 | /* RTL8723 series ------------------------------ */ | |
| 218 | #define REG_PCIE_HISR 0x03A0 | |
| 219 | ||
| 220 | /* spec version 11 */ | |
| 7194ea87 | 221 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ |
| 58c43401 LF |
222 | #define REG_VOQ_INFORMATION 0x0400 |
| 223 | #define REG_VIQ_INFORMATION 0x0404 | |
| 224 | #define REG_BEQ_INFORMATION 0x0408 | |
| 225 | #define REG_BKQ_INFORMATION 0x040C | |
| 226 | #define REG_MGQ_INFORMATION 0x0410 | |
| 227 | #define REG_HGQ_INFORMATION 0x0414 | |
| 228 | #define REG_BCNQ_INFORMATION 0x0418 | |
| 229 | #define REG_TXPKT_EMPTY 0x041A | |
| 230 | ||
| 231 | #define REG_CPU_MGQ_INFORMATION 0x041C | |
| 232 | #define REG_FWHW_TXQ_CTRL 0x0420 | |
| 233 | #define REG_HWSEQ_CTRL 0x0423 | |
| 234 | #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 | |
| 235 | #define REG_TXPKTBUF_MGQ_BDNY 0x0425 | |
| 236 | #define REG_LIFETIME_EN 0x0426 | |
| 237 | #define REG_MULTI_BCNQ_OFFSET 0x0427 | |
| 238 | #define REG_SPEC_SIFS 0x0428 | |
| 239 | #define REG_RL 0x042A | |
| 240 | #define REG_DARFRC 0x0430 | |
| 241 | #define REG_RARFRC 0x0438 | |
| 242 | #define REG_RRSR 0x0440 | |
| 243 | #define REG_ARFR0 0x0444 | |
| 244 | #define REG_ARFR1 0x0448 | |
| 245 | #define REG_ARFR2 0x044C | |
| 246 | #define REG_ARFR3 0x0450 | |
| 247 | #define REG_AGGLEN_LMT 0x0458 | |
| 248 | #define REG_AMPDU_MIN_SPACE 0x045C | |
| 249 | #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D | |
| 250 | #define REG_FAST_EDCA_CTRL 0x0460 | |
| 251 | #define REG_RD_RESP_PKT_TH 0x0463 | |
| 252 | #define REG_INIRTS_RATE_SEL 0x0480 | |
| 253 | /* define REG_INIDATA_RATE_SEL 0x0484 */ | |
| 254 | #define REG_POWER_STATUS 0x04A4 | |
| 255 | #define REG_POWER_STAGE1 0x04B4 | |
| 256 | #define REG_POWER_STAGE2 0x04B8 | |
| 257 | #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 | |
| 258 | #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 | |
| 259 | #define REG_STBC_SETTING 0x04C4 | |
| 260 | #define REG_PROT_MODE_CTRL 0x04C8 | |
| 261 | #define REG_MAX_AGGR_NUM 0x04CA | |
| 262 | #define REG_RTS_MAX_AGGR_NUM 0x04CB | |
| 263 | #define REG_BAR_MODE_CTRL 0x04CC | |
| 264 | #define REG_RA_TRY_RATE_AGG_LMT 0x04CF | |
| 265 | #define REG_EARLY_MODE_CONTROL 0x4D0 | |
| 266 | #define REG_NQOS_SEQ 0x04DC | |
| 267 | #define REG_QOS_SEQ 0x04DE | |
| 268 | #define REG_NEED_CPU_HANDLE 0x04E0 | |
| 269 | #define REG_PKT_LOSE_RPT 0x04E1 | |
| 270 | #define REG_PTCL_ERR_STATUS 0x04E2 | |
| 271 | #define REG_TX_RPT_CTRL 0x04EC | |
| 272 | #define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ | |
| 273 | #define REG_DUMMY 0x04FC | |
| 274 | ||
| 7194ea87 | 275 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ |
| 58c43401 LF |
276 | #define REG_EDCA_VO_PARAM 0x0500 |
| 277 | #define REG_EDCA_VI_PARAM 0x0504 | |
| 278 | #define REG_EDCA_BE_PARAM 0x0508 | |
| 279 | #define REG_EDCA_BK_PARAM 0x050C | |
| 280 | #define REG_BCNTCFG 0x0510 | |
| 281 | #define REG_PIFS 0x0512 | |
| 282 | #define REG_RDG_PIFS 0x0513 | |
| 283 | #define REG_SIFS_CTX 0x0514 | |
| 284 | #define REG_SIFS_TRX 0x0516 | |
| 285 | #define REG_TSFTR_SYN_OFFSET 0x0518 | |
| 286 | #define REG_AGGR_BREAK_TIME 0x051A | |
| 287 | #define REG_SLOT 0x051B | |
| 288 | #define REG_TX_PTCL_CTRL 0x0520 | |
| 289 | #define REG_TXPAUSE 0x0522 | |
| 290 | #define REG_DIS_TXREQ_CLR 0x0523 | |
| 291 | #define REG_RD_CTRL 0x0524 | |
| 292 | /* Format for offset 540h-542h: */ | |
| 7194ea87 | 293 | /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting |
| 58c43401 | 294 | * beacon content before TBTT. */ |
| 7194ea87 TJP |
295 | /* [7:4]: Reserved. */ |
| 296 | /* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding | |
| 58c43401 | 297 | * to send the beacon packet. */ |
| 7194ea87 | 298 | /* [23:20]: Reserved */ |
| 58c43401 | 299 | /* Description: */ |
| 7194ea87 | 300 | /* | */ |
| 58c43401 | 301 | /* |<--Setup--|--Hold------------>| */ |
| 7194ea87 | 302 | /* --------------|---------------------- */ |
| 58c43401 LF |
303 | /* | */ |
| 304 | /* TBTT */ | |
| 305 | /* Note: We cannot update beacon content to HW or send any AC packets during | |
| 306 | * the time between Setup and Hold. */ | |
| 307 | #define REG_TBTT_PROHIBIT 0x0540 | |
| 308 | #define REG_RD_NAV_NXT 0x0544 | |
| 309 | #define REG_NAV_PROT_LEN 0x0546 | |
| 310 | #define REG_BCN_CTRL 0x0550 | |
| 311 | #define REG_BCN_CTRL_1 0x0551 | |
| 312 | #define REG_MBID_NUM 0x0552 | |
| 313 | #define REG_DUAL_TSF_RST 0x0553 | |
| 314 | #define REG_BCN_INTERVAL 0x0554 | |
| 315 | #define REG_DRVERLYINT 0x0558 | |
| 316 | #define REG_BCNDMATIM 0x0559 | |
| 317 | #define REG_ATIMWND 0x055A | |
| 318 | #define REG_BCN_MAX_ERR 0x055D | |
| 319 | #define REG_RXTSF_OFFSET_CCK 0x055E | |
| 320 | #define REG_RXTSF_OFFSET_OFDM 0x055F | |
| 321 | #define REG_TSFTR 0x0560 | |
| 322 | #define REG_TSFTR1 0x0568 | |
| 323 | #define REG_ATIMWND_1 0x0570 | |
| 324 | #define REG_PSTIMER 0x0580 | |
| 325 | #define REG_TIMER0 0x0584 | |
| 326 | #define REG_TIMER1 0x0588 | |
| 327 | #define REG_ACMHWCTRL 0x05C0 | |
| 328 | ||
| 329 | /* define REG_FW_TSF_SYNC_CNT 0x04A0 */ | |
| 330 | #define REG_FW_RESET_TSF_CNT_1 0x05FC | |
| 331 | #define REG_FW_RESET_TSF_CNT_0 0x05FD | |
| 332 | #define REG_FW_BCN_DIS_CNT 0x05FE | |
| 333 | ||
| 7194ea87 | 334 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ |
| 58c43401 LF |
335 | #define REG_APSD_CTRL 0x0600 |
| 336 | #define REG_BWOPMODE 0x0603 | |
| 337 | #define REG_TCR 0x0604 | |
| 338 | #define REG_RCR 0x0608 | |
| 339 | #define REG_RX_PKT_LIMIT 0x060C | |
| 340 | #define REG_RX_DLK_TIME 0x060D | |
| 341 | #define REG_RX_DRVINFO_SZ 0x060F | |
| 342 | ||
| 343 | #define REG_MACID 0x0610 | |
| 344 | #define REG_BSSID 0x0618 | |
| 345 | #define REG_MAR 0x0620 | |
| 346 | #define REG_MBIDCAMCFG 0x0628 | |
| 347 | ||
| 348 | #define REG_USTIME_EDCA 0x0638 | |
| 349 | #define REG_MAC_SPEC_SIFS 0x063A | |
| 350 | ||
| 351 | /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ | |
| 352 | /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ | |
| 353 | #define REG_R2T_SIFS 0x063C | |
| 354 | /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ | |
| 355 | #define REG_T2T_SIFS 0x063E | |
| 356 | #define REG_ACKTO 0x0640 | |
| 357 | #define REG_CTS2TO 0x0641 | |
| 358 | #define REG_EIFS 0x0642 | |
| 359 | ||
| 360 | /* RXERR_RPT */ | |
| 361 | #define RXERR_TYPE_OFDM_PPDU 0 | |
| 362 | #define RXERR_TYPE_OFDM_false_ALARM 1 | |
| 363 | #define RXERR_TYPE_OFDM_MPDU_OK 2 | |
| 364 | #define RXERR_TYPE_OFDM_MPDU_FAIL 3 | |
| 365 | #define RXERR_TYPE_CCK_PPDU 4 | |
| 366 | #define RXERR_TYPE_CCK_false_ALARM 5 | |
| 367 | #define RXERR_TYPE_CCK_MPDU_OK 6 | |
| 368 | #define RXERR_TYPE_CCK_MPDU_FAIL 7 | |
| 369 | #define RXERR_TYPE_HT_PPDU 8 | |
| 370 | #define RXERR_TYPE_HT_false_ALARM 9 | |
| 371 | #define RXERR_TYPE_HT_MPDU_TOTAL 10 | |
| 372 | #define RXERR_TYPE_HT_MPDU_OK 11 | |
| 373 | #define RXERR_TYPE_HT_MPDU_FAIL 12 | |
| 374 | #define RXERR_TYPE_RX_FULL_DROP 15 | |
| 375 | ||
| 376 | #define RXERR_COUNTER_MASK 0xFFFFF | |
| 377 | #define RXERR_RPT_RST BIT(27) | |
| 378 | #define _RXERR_RPT_SEL(type) ((type) << 28) | |
| 379 | ||
| 380 | /* Note: */ | |
| 7194ea87 | 381 | /* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. |
| 58c43401 LF |
382 | * The default value is always too small, but the WiFi TestPlan test |
| 383 | * by 25,000 microseconds of NAV through sending CTS in the air. | |
| 384 | * We must update this value greater than 25,000 microseconds to pass | |
| 385 | * the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and | |
| 386 | * the offset should be 0x0652. */ | |
| 387 | #define REG_NAV_UPPER 0x0652 /* unit of 128 */ | |
| 388 | ||
| 389 | /* WMA, BA, CCX */ | |
| 390 | /* define REG_NAV_CTRL 0x0650 */ | |
| 391 | #define REG_BACAMCMD 0x0654 | |
| 392 | #define REG_BACAMCONTENT 0x0658 | |
| 393 | #define REG_LBDLY 0x0660 | |
| 394 | #define REG_FWDLY 0x0661 | |
| 395 | #define REG_RXERR_RPT 0x0664 | |
| 396 | #define REG_WMAC_TRXPTCL_CTL 0x0668 | |
| 397 | ||
| 398 | /* Security */ | |
| 399 | #define REG_CAMCMD 0x0670 | |
| 400 | #define REG_CAMWRITE 0x0674 | |
| 401 | #define REG_CAMREAD 0x0678 | |
| 402 | #define REG_CAMDBG 0x067C | |
| 403 | #define REG_SECCFG 0x0680 | |
| 404 | ||
| 405 | /* Power */ | |
| 406 | #define REG_WOW_CTRL 0x0690 | |
| 407 | #define REG_PS_RX_INFO 0x0692 | |
| 408 | #define REG_UAPSD_TID 0x0693 | |
| 409 | #define REG_WKFMCAM_CMD 0x0698 | |
| 410 | #define REG_WKFMCAM_NUM_88E 0x698 | |
| 411 | #define REG_RXFLTMAP0 0x06A0 | |
| 412 | #define REG_RXFLTMAP1 0x06A2 | |
| 413 | #define REG_RXFLTMAP2 0x06A4 | |
| 414 | #define REG_BCN_PSR_RPT 0x06A8 | |
| 415 | #define REG_BT_COEX_TABLE 0x06C0 | |
| 416 | ||
| 417 | /* Hardware Port 2 */ | |
| 418 | #define REG_MACID1 0x0700 | |
| 419 | #define REG_BSSID1 0x0708 | |
| 420 | ||
| 7194ea87 | 421 | /* 0xFE00h ~ 0xFE55h USB Configuration */ |
| 58c43401 LF |
422 | #define REG_USB_INFO 0xFE17 |
| 423 | #define REG_USB_SPECIAL_OPTION 0xFE55 | |
| 424 | #define REG_USB_DMA_AGG_TO 0xFE5B | |
| 425 | #define REG_USB_AGG_TO 0xFE5C | |
| 426 | #define REG_USB_AGG_TH 0xFE5D | |
| 427 | ||
| 428 | /* For normal chip */ | |
| 429 | #define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ | |
| 430 | #define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ | |
| 431 | #define REG_NORMAL_SIE_OPTIONAL 0xFE64 | |
| 432 | #define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ | |
| 433 | #define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ | |
| 434 | #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C | |
| 435 | #define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ | |
| 436 | #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ | |
| 437 | #define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ | |
| 438 | ||
| 439 | /* TODO: use these definition when using REG_xxx naming rule. */ | |
| 440 | /* NOTE: DO NOT Remove these definition. Use later. */ | |
| 441 | ||
| 442 | #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ | |
| 443 | #define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ | |
| 444 | #define MSR (REG_CR + 2) /* Media Status reg */ | |
| 445 | #define ISR REG_HISR_88E | |
| 446 | /* Timing Sync Function Timer Register. */ | |
| 447 | #define TSFR REG_TSFTR | |
| 448 | ||
| 449 | #define PBP REG_PBP | |
| 450 | ||
| 451 | /* Redifine MACID register, to compatible prior ICs. */ | |
| 452 | /* MAC ID Register, Offset 0x0050-0x0053 */ | |
| 453 | #define IDR0 REG_MACID | |
| 454 | /* MAC ID Register, Offset 0x0054-0x0055 */ | |
| 455 | #define IDR4 (REG_MACID + 4) | |
| 456 | ||
| 457 | /* 9. Security Control Registers (Offset: ) */ | |
| 458 | /* IN 8190 Data Sheet is called CAMcmd */ | |
| 459 | #define RWCAM REG_CAMCMD | |
| 460 | /* Software write CAM input content */ | |
| 461 | #define WCAMI REG_CAMWRITE | |
| 462 | /* Software read/write CAM config */ | |
| 463 | #define RCAMO REG_CAMREAD | |
| 464 | #define CAMDBG REG_CAMDBG | |
| 465 | /* Security Configuration Register */ | |
| 466 | #define SECR REG_SECCFG | |
| 467 | ||
| 468 | /* Unused register */ | |
| 469 | #define UnusedRegister 0x1BF | |
| 470 | #define DCAM UnusedRegister | |
| 471 | #define PSR UnusedRegister | |
| 472 | #define BBAddr UnusedRegister | |
| 473 | #define PhyDataR UnusedRegister | |
| 474 | ||
| 475 | /* Min Spacing related settings. */ | |
| 476 | #define MAX_MSS_DENSITY_2T 0x13 | |
| 477 | #define MAX_MSS_DENSITY_1T 0x0A | |
| 478 | ||
| 479 | /* EEPROM enable when set 1 */ | |
| 480 | #define CmdEEPROM_En BIT5 | |
| 481 | /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ | |
| 482 | #define CmdEERPOMSEL BIT4 | |
| 483 | #define Cmd9346CR_9356SEL BIT4 | |
| 484 | ||
| 485 | /* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ | |
| 486 | #define GPIOSEL_GPIO 0 | |
| 487 | #define GPIOSEL_ENBT BIT5 | |
| 488 | ||
| 489 | /* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ | |
| 490 | /* GPIO pins input value */ | |
| 491 | #define GPIO_IN REG_GPIO_PIN_CTRL | |
| 492 | /* GPIO pins output value */ | |
| 493 | #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) | |
| 494 | /* GPIO pins output enable when a bit is set to "1"; otherwise, | |
| 495 | * input is configured. */ | |
| 496 | #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) | |
| 497 | #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) | |
| 498 | ||
| 499 | /* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ | |
| 500 | #define HSIMR_GPIO12_0_INT_EN BIT0 | |
| 501 | #define HSIMR_SPS_OCP_INT_EN BIT5 | |
| 502 | #define HSIMR_RON_INT_EN BIT6 | |
| 503 | #define HSIMR_PDN_INT_EN BIT7 | |
| 504 | #define HSIMR_GPIO9_INT_EN BIT25 | |
| 505 | ||
| 506 | /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ | |
| 507 | #define HSISR_GPIO12_0_INT BIT0 | |
| 508 | #define HSISR_SPS_OCP_INT BIT5 | |
| 509 | #define HSISR_RON_INT_EN BIT6 | |
| 510 | #define HSISR_PDNINT BIT7 | |
| 511 | #define HSISR_GPIO9_INT BIT25 | |
| 512 | ||
| 513 | /* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ | |
| 514 | /* | |
| 515 | Network Type | |
| 516 | 00: No link | |
| 517 | 01: Link in ad hoc network | |
| 518 | 10: Link in infrastructure network | |
| 519 | 11: AP mode | |
| 520 | Default: 00b. | |
| 521 | */ | |
| 522 | #define MSR_NOLINK 0x00 | |
| 523 | #define MSR_ADHOC 0x01 | |
| 524 | #define MSR_INFRA 0x02 | |
| 525 | #define MSR_AP 0x03 | |
| 526 | ||
| 527 | /* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */ | |
| 528 | #define USB_INTR_CONTENT_C2H_OFFSET 0 | |
| 529 | #define USB_INTR_CONTENT_CPWM1_OFFSET 16 | |
| 530 | #define USB_INTR_CONTENT_CPWM2_OFFSET 20 | |
| 531 | #define USB_INTR_CONTENT_HISR_OFFSET 48 | |
| 532 | #define USB_INTR_CONTENT_HISRE_OFFSET 52 | |
| 533 | ||
| 534 | /* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ | |
| 535 | /* IOL config for REG_FDHM0(Reg0x88) */ | |
| 536 | #define CMD_INIT_LLT BIT0 | |
| 537 | #define CMD_READ_EFUSE_MAP BIT1 | |
| 538 | #define CMD_EFUSE_PATCH BIT2 | |
| 539 | #define CMD_IOCONFIG BIT3 | |
| 540 | #define CMD_INIT_LLT_ERR BIT4 | |
| 541 | #define CMD_READ_EFUSE_MAP_ERR BIT5 | |
| 542 | #define CMD_EFUSE_PATCH_ERR BIT6 | |
| 543 | #define CMD_IOCONFIG_ERR BIT7 | |
| 544 | ||
| 545 | /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ | |
| 546 | /* 8192C Response Rate Set Register (offset 0x181, 24bits) */ | |
| 547 | #define RRSR_1M BIT0 | |
| 548 | #define RRSR_2M BIT1 | |
| 549 | #define RRSR_5_5M BIT2 | |
| 550 | #define RRSR_11M BIT3 | |
| 551 | #define RRSR_6M BIT4 | |
| 552 | #define RRSR_9M BIT5 | |
| 553 | #define RRSR_12M BIT6 | |
| 554 | #define RRSR_18M BIT7 | |
| 555 | #define RRSR_24M BIT8 | |
| 556 | #define RRSR_36M BIT9 | |
| 557 | #define RRSR_48M BIT10 | |
| 558 | #define RRSR_54M BIT11 | |
| 559 | #define RRSR_MCS0 BIT12 | |
| 560 | #define RRSR_MCS1 BIT13 | |
| 561 | #define RRSR_MCS2 BIT14 | |
| 562 | #define RRSR_MCS3 BIT15 | |
| 563 | #define RRSR_MCS4 BIT16 | |
| 564 | #define RRSR_MCS5 BIT17 | |
| 565 | #define RRSR_MCS6 BIT18 | |
| 566 | #define RRSR_MCS7 BIT19 | |
| 567 | ||
| 568 | /* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */ | |
| 569 | /* WOL bit information */ | |
| 570 | #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 | |
| 571 | #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 | |
| 572 | ||
| 573 | /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ | |
| 574 | #define BW_OPMODE_20MHZ BIT2 | |
| 575 | #define BW_OPMODE_5G BIT1 | |
| 576 | ||
| 577 | /* 8192C CAM Config Setting (offset 0x250, 1 byte) */ | |
| 578 | #define CAM_VALID BIT15 | |
| 579 | #define CAM_NOTVALID 0x0000 | |
| 580 | #define CAM_USEDK BIT5 | |
| 581 | ||
| 582 | #define CAM_CONTENT_COUNT 8 | |
| 583 | ||
| 584 | #define CAM_NONE 0x0 | |
| 585 | #define CAM_WEP40 0x01 | |
| 586 | #define CAM_TKIP 0x02 | |
| 587 | #define CAM_AES 0x04 | |
| 588 | #define CAM_WEP104 0x05 | |
| 589 | #define CAM_SMS4 0x6 | |
| 590 | ||
| 591 | #define TOTAL_CAM_ENTRY 32 | |
| 592 | #define HALF_CAM_ENTRY 16 | |
| 593 | ||
| 594 | #define CAM_CONFIG_USEDK true | |
| 595 | #define CAM_CONFIG_NO_USEDK false | |
| 596 | ||
| 597 | #define CAM_WRITE BIT16 | |
| 598 | #define CAM_READ 0x00000000 | |
| 599 | #define CAM_POLLINIG BIT31 | |
| 600 | ||
| 601 | #define SCR_UseDK 0x01 | |
| 602 | #define SCR_TxSecEnable 0x02 | |
| 603 | #define SCR_RxSecEnable 0x04 | |
| 604 | ||
| 605 | /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ | |
| 606 | #define WOW_PMEN BIT0 /* Power management Enable. */ | |
| 607 | #define WOW_WOMEN BIT1 /* WoW function on or off. */ | |
| 608 | #define WOW_MAGIC BIT2 /* Magic packet */ | |
| 609 | #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ | |
| 610 | ||
| 611 | /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ | |
| 612 | /* 8188 IMR/ISR bits */ | |
| 613 | #define IMR_DISABLED_88E 0x0 | |
| 614 | /* IMR DW0(0x0060-0063) Bit 0-31 */ | |
| 615 | #define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ | |
| 616 | #define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ | |
| 617 | #define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ | |
| 618 | #define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ | |
| 619 | #define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ | |
| 620 | #define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ | |
| 621 | #define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ | |
| 622 | #define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ | |
| 623 | #define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ | |
| 624 | #define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ | |
| 625 | #define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ | |
| 626 | #define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ | |
| 627 | #define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ | |
| 628 | #define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ | |
| 629 | #define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ | |
| 630 | #define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ | |
| 631 | #define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ | |
| 632 | #define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ | |
| 633 | #define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ | |
| 634 | #define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ | |
| 635 | #define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ | |
| 636 | #define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ | |
| 637 | #define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ | |
| 638 | #define IMR_ROK_88E BIT0 /* Receive DMA OK */ | |
| 639 | ||
| 640 | /* IMR DW1(0x00B4-00B7) Bit 0-31 */ | |
| 641 | #define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ | |
| 642 | #define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ | |
| 643 | #define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ | |
| 644 | #define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ | |
| 645 | #define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ | |
| 646 | #define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ | |
| 647 | #define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ | |
| 648 | #define IMR_BCNDERR7_88E BIT20 /* Beacon DMA Error Int 7 */ | |
| 649 | #define IMR_BCNDERR6_88E BIT19 /* Beacon DMA Error Int 6 */ | |
| 650 | #define IMR_BCNDERR5_88E BIT18 /* Beacon DMA Error Int 5 */ | |
| 651 | #define IMR_BCNDERR4_88E BIT17 /* Beacon DMA Error Int 4 */ | |
| 652 | #define IMR_BCNDERR3_88E BIT16 /* Beacon DMA Error Int 3 */ | |
| 653 | #define IMR_BCNDERR2_88E BIT15 /* Beacon DMA Error Int 2 */ | |
| 654 | #define IMR_BCNDERR1_88E BIT14 /* Beacon DMA Error Int 1 */ | |
| 655 | #define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Ext for Win7 */ | |
| 656 | #define IMR_TXERR_88E BIT11 /* Tx Err Flag Int Status, write 1 clear. */ | |
| 657 | #define IMR_RXERR_88E BIT10 /* Rx Err Flag INT Status, Write 1 clear */ | |
| 658 | #define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ | |
| 659 | #define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ | |
| 660 | ||
| 661 | #define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ | |
| 662 | ||
| 663 | /* 8192C EFUSE */ | |
| 664 | #define HWSET_MAX_SIZE 256 | |
| 665 | #define HWSET_MAX_SIZE_88E 512 | |
| 666 | ||
| 667 | /*=================================================================== | |
| 668 | ===================================================================== | |
| 669 | Here the register defines are for 92C. When the define is as same with 92C, | |
| 670 | we will use the 92C's define for the consistency | |
| 671 | So the following defines for 92C is not entire!!!!!! | |
| 672 | ===================================================================== | |
| 673 | =====================================================================*/ | |
| 674 | /* | |
| 675 | Based on Datasheet V33---090401 | |
| 676 | Register Summary | |
| 677 | Current IOREG MAP | |
| 678 | 0x0000h ~ 0x00FFh System Configuration (256 Bytes) | |
| 679 | 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) | |
| 680 | 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) | |
| 681 | 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) | |
| 682 | 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) | |
| 683 | 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) | |
| 684 | 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) | |
| 685 | 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) | |
| 686 | 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) | |
| 687 | */ | |
| 7194ea87 | 688 | /* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ |
| 58c43401 | 689 | /* Note: */ |
| 7194ea87 | 690 | /* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet |
| 58c43401 | 691 | * RTL8192S/RTL8192C are wrong, */ |
| 7194ea87 | 692 | /* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, |
| 58c43401 | 693 | * and BK - Bit3. */ |
| 7194ea87 | 694 | /* 8723 and 88E may be not correct either in the earlier version. */ |
| 58c43401 LF |
695 | #define StopBecon BIT6 |
| 696 | #define StopHigh BIT5 | |
| 697 | #define StopMgt BIT4 | |
| 698 | #define StopBK BIT3 | |
| 699 | #define StopBE BIT2 | |
| 700 | #define StopVI BIT1 | |
| 701 | #define StopVO BIT0 | |
| 702 | ||
| 703 | /* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */ | |
| 704 | #define RCR_APPFCS BIT31 /* WMAC append FCS after payload */ | |
| 705 | #define RCR_APP_MIC BIT30 | |
| 706 | #define RCR_APP_PHYSTS BIT28 | |
| 707 | #define RCR_APP_ICV BIT29 | |
| 708 | #define RCR_APP_PHYST_RXFF BIT28 | |
| 709 | #define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */ | |
| 710 | #define RCR_ENMBID BIT24 /* Enable Multiple BssId. */ | |
| 711 | #define RCR_LSIGEN BIT23 | |
| 712 | #define RCR_MFBEN BIT22 | |
| 713 | #define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */ | |
| 714 | #define RCR_AMF BIT13 /* Accept management type frame */ | |
| 715 | #define RCR_ACF BIT12 /* Accept control type frame */ | |
| 716 | #define RCR_ADF BIT11 /* Accept data type frame */ | |
| 717 | #define RCR_AICV BIT9 /* Accept ICV error packet */ | |
| 718 | #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ | |
| 719 | #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet | |
| 720 | * (Rx beacon, probe rsp) */ | |
| 721 | #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match (Data)*/ | |
| 722 | #define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */ | |
| 723 | #define RCR_APWRMGT BIT5 /* Accept power management pkt*/ | |
| 724 | #define RCR_ADD3 BIT4 /* Accept address 3 match pkt */ | |
| 725 | #define RCR_AB BIT3 /* Accept broadcast packet */ | |
| 726 | #define RCR_AM BIT2 /* Accept multicast packet */ | |
| 727 | #define RCR_APM BIT1 /* Accept physical match pkt */ | |
| 728 | #define RCR_AAP BIT0 /* Accept all unicast packet */ | |
| 729 | #define RCR_MXDMA_OFFSET 8 | |
| 730 | #define RCR_FIFO_OFFSET 13 | |
| 731 | ||
| 7194ea87 | 732 | /* 0xFE00h ~ 0xFE55h USB Configuration */ |
| 58c43401 LF |
733 | #define REG_USB_INFO 0xFE17 |
| 734 | #define REG_USB_SPECIAL_OPTION 0xFE55 | |
| 735 | #define REG_USB_DMA_AGG_TO 0xFE5B | |
| 736 | #define REG_USB_AGG_TO 0xFE5C | |
| 737 | #define REG_USB_AGG_TH 0xFE5D | |
| 738 | ||
| 739 | #define REG_USB_HRPWM 0xFE58 | |
| 740 | #define REG_USB_HCPWM 0xFE57 | |
| 741 | /* 8192C Regsiter Bit and Content definition */ | |
| 7194ea87 | 742 | /* 0x0000h ~ 0x00FFh System Configuration */ |
| 58c43401 LF |
743 | |
| 744 | /* 2 SYS_ISO_CTRL */ | |
| 745 | #define ISO_MD2PP BIT(0) | |
| 746 | #define ISO_UA2USB BIT(1) | |
| 747 | #define ISO_UD2CORE BIT(2) | |
| 748 | #define ISO_PA2PCIE BIT(3) | |
| 749 | #define ISO_PD2CORE BIT(4) | |
| 750 | #define ISO_IP2MAC BIT(5) | |
| 751 | #define ISO_DIOP BIT(6) | |
| 752 | #define ISO_DIOE BIT(7) | |
| 753 | #define ISO_EB2CORE BIT(8) | |
| 754 | #define ISO_DIOR BIT(9) | |
| 755 | #define PWC_EV12V BIT(15) | |
| 756 | ||
| 757 | /* 2 SYS_FUNC_EN */ | |
| 758 | #define FEN_BBRSTB BIT(0) | |
| 759 | #define FEN_BB_GLB_RSTn BIT(1) | |
| 760 | #define FEN_USBA BIT(2) | |
| 761 | #define FEN_UPLL BIT(3) | |
| 762 | #define FEN_USBD BIT(4) | |
| 763 | #define FEN_DIO_PCIE BIT(5) | |
| 764 | #define FEN_PCIEA BIT(6) | |
| 765 | #define FEN_PPLL BIT(7) | |
| 766 | #define FEN_PCIED BIT(8) | |
| 767 | #define FEN_DIOE BIT(9) | |
| 768 | #define FEN_CPUEN BIT(10) | |
| 769 | #define FEN_DCORE BIT(11) | |
| 770 | #define FEN_ELDR BIT(12) | |
| 771 | #define FEN_DIO_RF BIT(13) | |
| 772 | #define FEN_HWPDN BIT(14) | |
| 773 | #define FEN_MREGEN BIT(15) | |
| 774 | ||
| 775 | /* 2 APS_FSMCO */ | |
| 776 | #define PFM_LDALL BIT(0) | |
| 777 | #define PFM_ALDN BIT(1) | |
| 778 | #define PFM_LDKP BIT(2) | |
| 779 | #define PFM_WOWL BIT(3) | |
| 780 | #define EnPDN BIT(4) | |
| 781 | #define PDN_PL BIT(5) | |
| 782 | #define APFM_ONMAC BIT(8) | |
| 783 | #define APFM_OFF BIT(9) | |
| 784 | #define APFM_RSM BIT(10) | |
| 785 | #define AFSM_HSUS BIT(11) | |
| 786 | #define AFSM_PCIE BIT(12) | |
| 787 | #define APDM_MAC BIT(13) | |
| 788 | #define APDM_HOST BIT(14) | |
| 789 | #define APDM_HPDN BIT(15) | |
| 790 | #define RDY_MACON BIT(16) | |
| 791 | #define SUS_HOST BIT(17) | |
| 792 | #define ROP_ALD BIT(20) | |
| 793 | #define ROP_PWR BIT(21) | |
| 794 | #define ROP_SPS BIT(22) | |
| 795 | #define SOP_MRST BIT(25) | |
| 796 | #define SOP_FUSE BIT(26) | |
| 797 | #define SOP_ABG BIT(27) | |
| 798 | #define SOP_AMB BIT(28) | |
| 799 | #define SOP_RCK BIT(29) | |
| 800 | #define SOP_A8M BIT(30) | |
| 801 | #define XOP_BTCK BIT(31) | |
| 802 | ||
| 803 | /* 2 SYS_CLKR */ | |
| 804 | #define ANAD16V_EN BIT(0) | |
| 805 | #define ANA8M BIT(1) | |
| 806 | #define MACSLP BIT(4) | |
| 807 | #define LOADER_CLK_EN BIT(5) | |
| 808 | ||
| 809 | /* 2 9346CR */ | |
| 810 | ||
| 811 | #define BOOT_FROM_EEPROM BIT(4) | |
| 812 | #define EEPROM_EN BIT(5) | |
| 813 | ||
| 814 | /* 2 SPS0_CTRL */ | |
| 815 | ||
| 816 | /* 2 SPS_OCP_CFG */ | |
| 817 | ||
| 818 | /* 2 RF_CTRL */ | |
| 819 | #define RF_EN BIT(0) | |
| 820 | #define RF_RSTB BIT(1) | |
| 821 | #define RF_SDMRSTB BIT(2) | |
| 822 | ||
| 823 | /* 2 LDOV12D_CTRL */ | |
| 824 | #define LDV12_EN BIT(0) | |
| 825 | #define LDV12_SDBY BIT(1) | |
| 826 | #define LPLDO_HSM BIT(2) | |
| 827 | #define LPLDO_LSM_DIS BIT(3) | |
| 828 | #define _LDV12_VADJ(x) (((x) & 0xF) << 4) | |
| 829 | ||
| 830 | /* 2EFUSE_CTRL */ | |
| 831 | #define ALD_EN BIT(18) | |
| 832 | #define EF_PD BIT(19) | |
| 833 | #define EF_FLAG BIT(31) | |
| 834 | ||
| 835 | /* 2 EFUSE_TEST (For RTL8723 partially) */ | |
| 836 | #define EF_TRPT BIT(7) | |
| 837 | /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ | |
| 838 | #define EF_CELL_SEL (BIT(8)|BIT(9)) | |
| 839 | #define LDOE25_EN BIT(31) | |
| 840 | #define EFUSE_SEL(x) (((x) & 0x3) << 8) | |
| 841 | #define EFUSE_SEL_MASK 0x300 | |
| 842 | #define EFUSE_WIFI_SEL_0 0x0 | |
| 843 | #define EFUSE_BT_SEL_0 0x1 | |
| 844 | #define EFUSE_BT_SEL_1 0x2 | |
| 845 | #define EFUSE_BT_SEL_2 0x3 | |
| 846 | ||
| 847 | #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ | |
| 848 | #define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ | |
| 849 | ||
| 850 | /* 2 8051FWDL */ | |
| 851 | /* 2 MCUFWDL */ | |
| 852 | #define MCUFWDL_EN BIT(0) | |
| 853 | #define MCUFWDL_RDY BIT(1) | |
| 854 | #define FWDL_ChkSum_rpt BIT(2) | |
| 855 | #define MACINI_RDY BIT(3) | |
| 856 | #define BBINI_RDY BIT(4) | |
| 857 | #define RFINI_RDY BIT(5) | |
| 858 | #define WINTINI_RDY BIT(6) | |
| 859 | #define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ | |
| 860 | #define ROM_DLEN BIT(19) | |
| 861 | #define CPRST BIT(23) | |
| 862 | ||
| 863 | /* 2 REG_SYS_CFG */ | |
| 864 | #define XCLK_VLD BIT(0) | |
| 865 | #define ACLK_VLD BIT(1) | |
| 866 | #define UCLK_VLD BIT(2) | |
| 867 | #define PCLK_VLD BIT(3) | |
| 868 | #define PCIRSTB BIT(4) | |
| 869 | #define V15_VLD BIT(5) | |
| 870 | #define SW_OFFLOAD_EN BIT(7) | |
| 871 | #define SIC_IDLE BIT(8) | |
| 872 | #define BD_MAC2 BIT(9) | |
| 873 | #define BD_MAC1 BIT(10) | |
| 874 | #define IC_MACPHY_MODE BIT(11) | |
| 875 | #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) | |
| 876 | #define BT_FUNC BIT(16) | |
| 877 | #define VENDOR_ID BIT(19) | |
| 878 | #define PAD_HWPD_IDN BIT(22) | |
| 879 | #define TRP_VAUX_EN BIT(23) /* RTL ID */ | |
| 880 | #define TRP_BT_EN BIT(24) | |
| 881 | #define BD_PKG_SEL BIT(25) | |
| 882 | #define BD_HCI_SEL BIT(26) | |
| 883 | #define TYPE_ID BIT(27) | |
| 884 | ||
| 885 | #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ | |
| 886 | #define CHIP_VER_RTL_SHIFT 12 | |
| 887 | ||
| 888 | /* 2REG_GPIO_OUTSTS (For RTL8723 only) */ | |
| 889 | #define EFS_HCI_SEL (BIT(0)|BIT(1)) | |
| 890 | #define PAD_HCI_SEL (BIT(2)|BIT(3)) | |
| 891 | #define HCI_SEL (BIT(4)|BIT(5)) | |
| 892 | #define PKG_SEL_HCI BIT(6) | |
| 893 | #define FEN_GPS BIT(7) | |
| 894 | #define FEN_BT BIT(8) | |
| 895 | #define FEN_WL BIT(9) | |
| 896 | #define FEN_PCI BIT(10) | |
| 897 | #define FEN_USB BIT(11) | |
| 898 | #define BTRF_HWPDN_N BIT(12) | |
| 899 | #define WLRF_HWPDN_N BIT(13) | |
| 900 | #define PDN_BT_N BIT(14) | |
| 901 | #define PDN_GPS_N BIT(15) | |
| 902 | #define BT_CTL_HWPDN BIT(16) | |
| 903 | #define GPS_CTL_HWPDN BIT(17) | |
| 904 | #define PPHY_SUSB BIT(20) | |
| 905 | #define UPHY_SUSB BIT(21) | |
| 906 | #define PCI_SUSEN BIT(22) | |
| 907 | #define USB_SUSEN BIT(23) | |
| 908 | #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) | |
| 909 | ||
| 910 | /* 2SYS_CFG */ | |
| 911 | #define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ | |
| 912 | ||
| 7194ea87 | 913 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ |
| 58c43401 LF |
914 | |
| 915 | /* 2 Function Enable Registers */ | |
| 916 | /* 2 CR */ | |
| 917 | ||
| 918 | #define HCI_TXDMA_EN BIT(0) | |
| 919 | #define HCI_RXDMA_EN BIT(1) | |
| 920 | #define TXDMA_EN BIT(2) | |
| 921 | #define RXDMA_EN BIT(3) | |
| 922 | #define PROTOCOL_EN BIT(4) | |
| 923 | #define SCHEDULE_EN BIT(5) | |
| 924 | #define MACTXEN BIT(6) | |
| 925 | #define MACRXEN BIT(7) | |
| 926 | #define ENSWBCN BIT(8) | |
| 927 | #define ENSEC BIT(9) | |
| 928 | #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ | |
| 929 | ||
| 930 | /* Network type */ | |
| 931 | #define _NETTYPE(x) (((x) & 0x3) << 16) | |
| 932 | #define MASK_NETTYPE 0x30000 | |
| 933 | #define NT_NO_LINK 0x0 | |
| 934 | #define NT_LINK_AD_HOC 0x1 | |
| 935 | #define NT_LINK_AP 0x2 | |
| 936 | #define NT_AS_AP 0x3 | |
| 937 | ||
| 938 | /* 2 PBP - Page Size Register */ | |
| 939 | #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) | |
| 940 | #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) | |
| 941 | #define _PSRX_MASK 0xF | |
| 942 | #define _PSTX_MASK 0xF0 | |
| 943 | #define _PSRX(x) (x) | |
| 944 | #define _PSTX(x) ((x) << 4) | |
| 945 | ||
| 946 | #define PBP_64 0x0 | |
| 947 | #define PBP_128 0x1 | |
| 948 | #define PBP_256 0x2 | |
| 949 | #define PBP_512 0x3 | |
| 950 | #define PBP_1024 0x4 | |
| 951 | ||
| 952 | /* 2 TX/RXDMA */ | |
| 953 | #define RXDMA_ARBBW_EN BIT(0) | |
| 954 | #define RXSHFT_EN BIT(1) | |
| 955 | #define RXDMA_AGG_EN BIT(2) | |
| 956 | #define QS_VO_QUEUE BIT(8) | |
| 957 | #define QS_VI_QUEUE BIT(9) | |
| 958 | #define QS_BE_QUEUE BIT(10) | |
| 959 | #define QS_BK_QUEUE BIT(11) | |
| 960 | #define QS_MANAGER_QUEUE BIT(12) | |
| 961 | #define QS_HIGH_QUEUE BIT(13) | |
| 962 | ||
| 963 | #define HQSEL_VOQ BIT(0) | |
| 964 | #define HQSEL_VIQ BIT(1) | |
| 965 | #define HQSEL_BEQ BIT(2) | |
| 966 | #define HQSEL_BKQ BIT(3) | |
| 967 | #define HQSEL_MGTQ BIT(4) | |
| 968 | #define HQSEL_HIQ BIT(5) | |
| 969 | ||
| 970 | /* For normal driver, 0x10C */ | |
| 971 | #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) | |
| 972 | #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) | |
| 973 | #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) | |
| 7194ea87 TJP |
974 | #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) |
| 975 | #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) | |
| 976 | #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) | |
| 58c43401 LF |
977 | |
| 978 | #define QUEUE_LOW 1 | |
| 979 | #define QUEUE_NORMAL 2 | |
| 980 | #define QUEUE_HIGH 3 | |
| 981 | ||
| 982 | /* 2 TRXFF_BNDY */ | |
| 983 | ||
| 984 | /* 2 LLT_INIT */ | |
| 985 | #define _LLT_NO_ACTIVE 0x0 | |
| 986 | #define _LLT_WRITE_ACCESS 0x1 | |
| 987 | #define _LLT_READ_ACCESS 0x2 | |
| 988 | ||
| 989 | #define _LLT_INIT_DATA(x) ((x) & 0xFF) | |
| 990 | #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) | |
| 991 | #define _LLT_OP(x) (((x) & 0x3) << 30) | |
| 992 | #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) | |
| 993 | ||
| 7194ea87 | 994 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ |
| 58c43401 LF |
995 | /* 2RQPN */ |
| 996 | #define _HPQ(x) ((x) & 0xFF) | |
| 997 | #define _LPQ(x) (((x) & 0xFF) << 8) | |
| 998 | #define _PUBQ(x) (((x) & 0xFF) << 16) | |
| 999 | /* NOTE: in RQPN_NPQ register */ | |
| 1000 | #define _NPQ(x) ((x) & 0xFF) | |
| 1001 | ||
| 1002 | #define HPQ_PUBLIC_DIS BIT(24) | |
| 1003 | #define LPQ_PUBLIC_DIS BIT(25) | |
| 1004 | #define LD_RQPN BIT(31) | |
| 1005 | ||
| 1006 | /* 2TDECTRL */ | |
| 1007 | #define BCN_VALID BIT(16) | |
| 1008 | #define BCN_HEAD(x) (((x) & 0xFF) << 8) | |
| 1009 | #define BCN_HEAD_MASK 0xFF00 | |
| 1010 | ||
| 1011 | /* 2 TDECTL */ | |
| 1012 | #define BLK_DESC_NUM_SHIFT 4 | |
| 1013 | #define BLK_DESC_NUM_MASK 0xF | |
| 1014 | ||
| 1015 | /* 2 TXDMA_OFFSET_CHK */ | |
| 1016 | #define DROP_DATA_EN BIT(9) | |
| 1017 | ||
| 7194ea87 | 1018 | /* 0x0280h ~ 0x028Bh RX DMA Configuration */ |
| 58c43401 LF |
1019 | |
| 1020 | /* REG_RXDMA_CONTROL, 0x0286h */ | |
| 1021 | ||
| 1022 | /* 2 REG_RXPKT_NUM, 0x0284 */ | |
| 1023 | #define RXPKT_RELEASE_POLL BIT(16) | |
| 1024 | #define RXDMA_IDLE BIT(17) | |
| 1025 | #define RW_RELEASE_EN BIT(18) | |
| 1026 | ||
| 7194ea87 | 1027 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ |
| 58c43401 LF |
1028 | /* 2 FWHW_TXQ_CTRL */ |
| 1029 | #define EN_AMPDU_RTY_NEW BIT(7) | |
| 1030 | ||
| 1031 | /* 2 SPEC SIFS */ | |
| 1032 | #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) | |
| 1033 | #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) | |
| 1034 | ||
| 1035 | /* 2 RL */ | |
| 1036 | #define RETRY_LIMIT_SHORT_SHIFT 8 | |
| 1037 | #define RETRY_LIMIT_LONG_SHIFT 0 | |
| 1038 | ||
| 7194ea87 | 1039 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ |
| 58c43401 LF |
1040 | |
| 1041 | /* 2 EDCA setting */ | |
| 1042 | #define AC_PARAM_TXOP_LIMIT_OFFSET 16 | |
| 1043 | #define AC_PARAM_ECW_MAX_OFFSET 12 | |
| 1044 | #define AC_PARAM_ECW_MIN_OFFSET 8 | |
| 1045 | #define AC_PARAM_AIFS_OFFSET 0 | |
| 1046 | ||
| 1047 | #define _LRL(x) ((x) & 0x3F) | |
| 1048 | #define _SRL(x) (((x) & 0x3F) << 8) | |
| 1049 | ||
| 1050 | /* 2 BCN_CTRL */ | |
| 1051 | #define EN_MBSSID BIT(1) | |
| 1052 | #define EN_TXBCN_RPT BIT(2) | |
| 1053 | #define EN_BCN_FUNCTION BIT(3) | |
| 1054 | #define DIS_TSF_UPDATE BIT(3) | |
| 1055 | ||
| 1056 | /* The same function but different bit field. */ | |
| 1057 | #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) | |
| 1058 | #define DIS_TSF_UDT0_TEST_CHIP BIT(5) | |
| 1059 | #define STOP_BCNQ BIT(6) | |
| 1060 | ||
| 1061 | /* 2 ACMHWCTRL */ | |
| 1062 | #define AcmHw_HwEn BIT(0) | |
| 1063 | #define AcmHw_BeqEn BIT(1) | |
| 1064 | #define AcmHw_ViqEn BIT(2) | |
| 1065 | #define AcmHw_VoqEn BIT(3) | |
| 1066 | #define AcmHw_BeqStatus BIT(4) | |
| 1067 | #define AcmHw_ViqStatus BIT(5) | |
| 1068 | #define AcmHw_VoqStatus BIT(6) | |
| 1069 | ||
| 7194ea87 | 1070 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ |
| 58c43401 LF |
1071 | /* 2APSD_CTRL */ |
| 1072 | #define APSDOFF BIT(6) | |
| 1073 | #define APSDOFF_STATUS BIT(7) | |
| 1074 | ||
| 1075 | #define RATE_BITMAP_ALL 0xFFFFF | |
| 1076 | ||
| 1077 | /* Only use CCK 1M rate for ACK */ | |
| 1078 | #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 | |
| 1079 | ||
| 1080 | /* 2 TCR */ | |
| 1081 | #define TSFRST BIT(0) | |
| 1082 | #define DIS_GCLK BIT(1) | |
| 1083 | #define PAD_SEL BIT(2) | |
| 1084 | #define PWR_ST BIT(6) | |
| 1085 | #define PWRBIT_OW_EN BIT(7) | |
| 1086 | #define ACRC BIT(8) | |
| 1087 | #define CFENDFORM BIT(9) | |
| 1088 | #define ICV BIT(10) | |
| 1089 | ||
| 1090 | /* 2 RCR */ | |
| 1091 | #define AAP BIT(0) | |
| 1092 | #define APM BIT(1) | |
| 1093 | #define AM BIT(2) | |
| 1094 | #define AB BIT(3) | |
| 1095 | #define ADD3 BIT(4) | |
| 1096 | #define APWRMGT BIT(5) | |
| 1097 | #define CBSSID BIT(6) | |
| 1098 | #define CBSSID_DATA BIT(6) | |
| 1099 | #define CBSSID_BCN BIT(7) | |
| 1100 | #define ACRC32 BIT(8) | |
| 1101 | #define AICV BIT(9) | |
| 1102 | #define ADF BIT(11) | |
| 1103 | #define ACF BIT(12) | |
| 1104 | #define AMF BIT(13) | |
| 1105 | #define HTC_LOC_CTRL BIT(14) | |
| 1106 | #define UC_DATA_EN BIT(16) | |
| 1107 | #define BM_DATA_EN BIT(17) | |
| 1108 | #define MFBEN BIT(22) | |
| 1109 | #define LSIGEN BIT(23) | |
| 1110 | #define EnMBID BIT(24) | |
| 1111 | #define APP_BASSN BIT(27) | |
| 1112 | #define APP_PHYSTS BIT(28) | |
| 1113 | #define APP_ICV BIT(29) | |
| 1114 | #define APP_MIC BIT(30) | |
| 1115 | #define APP_FCS BIT(31) | |
| 1116 | ||
| 1117 | /* 2 SECCFG */ | |
| 1118 | #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ | |
| 1119 | #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ | |
| 1120 | #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ | |
| 1121 | #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ | |
| 1122 | #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ | |
| 1123 | #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ | |
| 1124 | #define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */ | |
| 1125 | #define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */ | |
| 1126 | ||
| 7194ea87 | 1127 | /* RTL8188E SDIO Configuration */ |
| 58c43401 LF |
1128 | |
| 1129 | /* I/O bus domain address mapping */ | |
| 1130 | #define SDIO_LOCAL_BASE 0x10250000 | |
| 1131 | #define WLAN_IOREG_BASE 0x10260000 | |
| 1132 | #define FIRMWARE_FIFO_BASE 0x10270000 | |
| 1133 | #define TX_HIQ_BASE 0x10310000 | |
| 1134 | #define TX_MIQ_BASE 0x10320000 | |
| 1135 | #define TX_LOQ_BASE 0x10330000 | |
| 1136 | #define RX_RX0FF_BASE 0x10340000 | |
| 1137 | ||
| 1138 | /* SDIO host local register space mapping. */ | |
| 1139 | #define SDIO_LOCAL_MSK 0x0FFF | |
| 1140 | #define WLAN_IOREG_MSK 0x7FFF | |
| 1141 | #define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ | |
| 1142 | #define WLAN_RX0FF_MSK 0x0003 | |
| 1143 | ||
| 1144 | /* Without ref to the SDIO Device ID */ | |
| 1145 | #define SDIO_WITHOUT_REF_DEVICE_ID 0 | |
| 1146 | #define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ | |
| 1147 | #define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ | |
| 1148 | #define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ | |
| 1149 | #define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ | |
| 1150 | #define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ | |
| 1151 | #define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ | |
| 1152 | ||
| 1153 | /* SDIO Tx Free Page Index */ | |
| 1154 | #define HI_QUEUE_IDX 0 | |
| 1155 | #define MID_QUEUE_IDX 1 | |
| 1156 | #define LOW_QUEUE_IDX 2 | |
| 1157 | #define PUBLIC_QUEUE_IDX 3 | |
| 1158 | ||
| 1159 | #define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ | |
| 1160 | #define SDIO_MAX_RX_QUEUE 1 | |
| 1161 | ||
| 1162 | /* SDIO Tx Control */ | |
| 1163 | #define SDIO_REG_TX_CTRL 0x0000 | |
| 1164 | /* SDIO Host Interrupt Mask */ | |
| 1165 | #define SDIO_REG_HIMR 0x0014 | |
| 1166 | /* SDIO Host Interrupt Service Routine */ | |
| 1167 | #define SDIO_REG_HISR 0x0018 | |
| 1168 | /* HCI Current Power Mode */ | |
| 1169 | #define SDIO_REG_HCPWM 0x0019 | |
| 1170 | /* RXDMA Request Length */ | |
| 1171 | #define SDIO_REG_RX0_REQ_LEN 0x001C | |
| 1172 | /* Free Tx Buffer Page */ | |
| 1173 | #define SDIO_REG_FREE_TXPG 0x0020 | |
| 1174 | /* HCI Current Power Mode 1 */ | |
| 1175 | #define SDIO_REG_HCPWM1 0x0024 | |
| 1176 | /* HCI Current Power Mode 2 */ | |
| 1177 | #define SDIO_REG_HCPWM2 0x0026 | |
| 1178 | /* HTSF Informaion */ | |
| 1179 | #define SDIO_REG_HTSFR_INFO 0x0030 | |
| 1180 | /* HCI Request Power Mode 1 */ | |
| 1181 | #define SDIO_REG_HRPWM1 0x0080 | |
| 1182 | /* HCI Request Power Mode 2 */ | |
| 1183 | #define SDIO_REG_HRPWM2 0x0082 | |
| 1184 | /* HCI Power Save Clock */ | |
| 1185 | #define SDIO_REG_HPS_CLKR 0x0084 | |
| 1186 | /* SDIO HCI Suspend Control */ | |
| 1187 | #define SDIO_REG_HSUS_CTRL 0x0086 | |
| 1188 | /* SDIO Host Extension Interrupt Mask Always */ | |
| 1189 | #define SDIO_REG_HIMR_ON 0x0090 | |
| 1190 | /* SDIO Host Extension Interrupt Status Always */ | |
| 1191 | #define SDIO_REG_HISR_ON 0x0091 | |
| 1192 | ||
| 1193 | #define SDIO_HIMR_DISABLED 0 | |
| 1194 | ||
| 1195 | /* RTL8188E SDIO Host Interrupt Mask Register */ | |
| 1196 | #define SDIO_HIMR_RX_REQUEST_MSK BIT0 | |
| 1197 | #define SDIO_HIMR_AVAL_MSK BIT1 | |
| 1198 | #define SDIO_HIMR_TXERR_MSK BIT2 | |
| 1199 | #define SDIO_HIMR_RXERR_MSK BIT3 | |
| 1200 | #define SDIO_HIMR_TXFOVW_MSK BIT4 | |
| 1201 | #define SDIO_HIMR_RXFOVW_MSK BIT5 | |
| 1202 | #define SDIO_HIMR_TXBCNOK_MSK BIT6 | |
| 1203 | #define SDIO_HIMR_TXBCNERR_MSK BIT7 | |
| 1204 | #define SDIO_HIMR_BCNERLY_INT_MSK BIT16 | |
| 1205 | #define SDIO_HIMR_C2HCMD_MSK BIT17 | |
| 1206 | #define SDIO_HIMR_CPWM1_MSK BIT18 | |
| 1207 | #define SDIO_HIMR_CPWM2_MSK BIT19 | |
| 1208 | #define SDIO_HIMR_HSISR_IND_MSK BIT20 | |
| 1209 | #define SDIO_HIMR_GTINT3_IND_MSK BIT21 | |
| 1210 | #define SDIO_HIMR_GTINT4_IND_MSK BIT22 | |
| 1211 | #define SDIO_HIMR_PSTIMEOUT_MSK BIT23 | |
| 1212 | #define SDIO_HIMR_OCPINT_MSK BIT24 | |
| 1213 | #define SDIO_HIMR_ATIMEND_MSK BIT25 | |
| 1214 | #define SDIO_HIMR_ATIMEND_E_MSK BIT26 | |
| 1215 | #define SDIO_HIMR_CTWEND_MSK BIT27 | |
| 1216 | ||
| 1217 | /* RTL8188E SDIO Specific */ | |
| 1218 | #define SDIO_HIMR_MCU_ERR_MSK BIT28 | |
| 1219 | #define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 | |
| 1220 | ||
| 1221 | /* SDIO Host Interrupt Service Routine */ | |
| 1222 | #define SDIO_HISR_RX_REQUEST BIT0 | |
| 1223 | #define SDIO_HISR_AVAL BIT1 | |
| 1224 | #define SDIO_HISR_TXERR BIT2 | |
| 1225 | #define SDIO_HISR_RXERR BIT3 | |
| 1226 | #define SDIO_HISR_TXFOVW BIT4 | |
| 1227 | #define SDIO_HISR_RXFOVW BIT5 | |
| 1228 | #define SDIO_HISR_TXBCNOK BIT6 | |
| 1229 | #define SDIO_HISR_TXBCNERR BIT7 | |
| 1230 | #define SDIO_HISR_BCNERLY_INT BIT16 | |
| 1231 | #define SDIO_HISR_C2HCMD BIT17 | |
| 1232 | #define SDIO_HISR_CPWM1 BIT18 | |
| 1233 | #define SDIO_HISR_CPWM2 BIT19 | |
| 1234 | #define SDIO_HISR_HSISR_IND BIT20 | |
| 1235 | #define SDIO_HISR_GTINT3_IND BIT21 | |
| 1236 | #define SDIO_HISR_GTINT4_IND BIT22 | |
| 1237 | #define SDIO_HISR_PSTIME BIT23 | |
| 1238 | #define SDIO_HISR_OCPINT BIT24 | |
| 1239 | #define SDIO_HISR_ATIMEND BIT25 | |
| 1240 | #define SDIO_HISR_ATIMEND_E BIT26 | |
| 1241 | #define SDIO_HISR_CTWEND BIT27 | |
| 1242 | ||
| 1243 | /* RTL8188E SDIO Specific */ | |
| 1244 | #define SDIO_HISR_MCU_ERR BIT28 | |
| 1245 | #define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 | |
| 1246 | ||
| 1247 | #define MASK_SDIO_HISR_CLEAR \ | |
| 1248 | (SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\ | |
| 1249 | SDIO_HISR_RXFOVW | SDIO_HISR_TXBCNOK | SDIO_HISR_TXBCNERR |\ | |
| 1250 | SDIO_HISR_C2HCMD | SDIO_HISR_CPWM1 | SDIO_HISR_CPWM2 |\ | |
| 1251 | SDIO_HISR_HSISR_IND | SDIO_HISR_GTINT3_IND | SDIO_HISR_GTINT4_IND |\ | |
| 1252 | SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT) | |
| 1253 | ||
| 1254 | /* SDIO HCI Suspend Control Register */ | |
| 1255 | #define HCI_RESUME_PWR_RDY BIT1 | |
| 1256 | #define HCI_SUS_CTRL BIT0 | |
| 1257 | ||
| 1258 | /* SDIO Tx FIFO related */ | |
| 1259 | /* The number of Tx FIFO free page */ | |
| 1260 | #define SDIO_TX_FREE_PG_QUEUE 4 | |
| 1261 | #define SDIO_TX_FIFO_PAGE_SZ 128 | |
| 1262 | ||
| 7194ea87 | 1263 | /* 0xFE00h ~ 0xFE55h USB Configuration */ |
| 58c43401 LF |
1264 | |
| 1265 | /* 2 USB Information (0xFE17) */ | |
| 1266 | #define USB_IS_HIGH_SPEED 0 | |
| 1267 | #define USB_IS_FULL_SPEED 1 | |
| 1268 | #define USB_SPEED_MASK BIT(5) | |
| 1269 | ||
| 1270 | #define USB_NORMAL_SIE_EP_MASK 0xF | |
| 1271 | #define USB_NORMAL_SIE_EP_SHIFT 4 | |
| 1272 | ||
| 1273 | /* 2 Special Option */ | |
| 1274 | #define USB_AGG_EN BIT(3) | |
| 1275 | ||
| 1276 | /* 0; Use interrupt endpoint to upload interrupt pkt */ | |
| 1277 | /* 1; Use bulk endpoint to upload interrupt pkt, */ | |
| 1278 | #define INT_BULK_SEL BIT(4) | |
| 1279 | ||
| 1280 | /* 2REG_C2HEVT_CLEAR */ | |
| 1281 | /* Set by driver and notify FW that the driver has read | |
| 1282 | * the C2H command message */ | |
| 1283 | #define C2H_EVT_HOST_CLOSE 0x00 | |
| 1284 | /* Set by FW indicating that FW had set the C2H command | |
| 1285 | * message and it's not yet read by driver. */ | |
| 1286 | #define C2H_EVT_FW_CLOSE 0xFF | |
| 1287 | ||
| 1288 | /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ | |
| 1289 | /* Enable GPIO[9] as WiFi HW PDn source */ | |
| 1290 | #define WL_HWPDN_EN BIT0 | |
| 1291 | /* WiFi HW PDn polarity control */ | |
| 1292 | #define WL_HWPDN_SL BIT1 | |
| 1293 | /* WiFi function enable */ | |
| 1294 | #define WL_FUNC_EN BIT2 | |
| 1295 | /* Enable GPIO[9] as WiFi RF HW PDn source */ | |
| 1296 | #define WL_HWROF_EN BIT3 | |
| 1297 | /* Enable GPIO[11] as BT HW PDn source */ | |
| 1298 | #define BT_HWPDN_EN BIT16 | |
| 1299 | /* BT HW PDn polarity control */ | |
| 1300 | #define BT_HWPDN_SL BIT17 | |
| 1301 | /* BT function enable */ | |
| 1302 | #define BT_FUNC_EN BIT18 | |
| 1303 | /* Enable GPIO[11] as BT/GPS RF HW PDn source */ | |
| 1304 | #define BT_HWROF_EN BIT19 | |
| 1305 | /* Enable GPIO[10] as GPS HW PDn source */ | |
| 1306 | #define GPS_HWPDN_EN BIT20 | |
| 1307 | /* GPS HW PDn polarity control */ | |
| 1308 | #define GPS_HWPDN_SL BIT21 | |
| 1309 | /* GPS function enable */ | |
| 1310 | #define GPS_FUNC_EN BIT22 | |
| 1311 | ||
| 1312 | /* 3 REG_LIFECTRL_CTRL */ | |
| 1313 | #define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 | |
| 1314 | #define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 | |
| 1315 | #define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 | |
| 1316 | #define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 | |
| 1317 | ||
| 1318 | #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */ | |
| 1319 | ||
| 1320 | /* General definitions */ | |
| 1321 | #define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */ | |
| 1322 | ||
| 1323 | #define POLLING_LLT_THRESHOLD 20 | |
| 1324 | #define POLLING_READY_TIMEOUT_COUNT 1000 | |
| 1325 | /* GPIO BIT */ | |
| 1326 | #define HAL_8192C_HW_GPIO_WPS_BIT BIT2 | |
| 1327 | ||
| 1328 | /* 8192C EEPROM/EFUSE share register definition. */ | |
| 1329 | ||
| 7194ea87 | 1330 | /* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */ |
| 58c43401 LF |
1331 | #define EEPROM_TX_PWR_INX_88E 0x10 |
| 1332 | ||
| 1333 | #define EEPROM_ChannelPlan_88E 0xB8 | |
| 1334 | #define EEPROM_XTAL_88E 0xB9 | |
| 1335 | #define EEPROM_THERMAL_METER_88E 0xBA | |
| 1336 | #define EEPROM_IQK_LCK_88E 0xBB | |
| 1337 | ||
| 1338 | #define EEPROM_RF_BOARD_OPTION_88E 0xC1 | |
| 1339 | #define EEPROM_RF_FEATURE_OPTION_88E 0xC2 | |
| 1340 | #define EEPROM_RF_BT_SETTING_88E 0xC3 | |
| 1341 | #define EEPROM_VERSION_88E 0xC4 | |
| 1342 | #define EEPROM_CUSTOMERID_88E 0xC5 | |
| 1343 | #define EEPROM_RF_ANTENNA_OPT_88E 0xC9 | |
| 1344 | ||
| 1345 | /* RTL88EE */ | |
| 1346 | #define EEPROM_MAC_ADDR_88EE 0xD0 | |
| 1347 | #define EEPROM_VID_88EE 0xD6 | |
| 1348 | #define EEPROM_DID_88EE 0xD8 | |
| 1349 | #define EEPROM_SVID_88EE 0xDA | |
| 1350 | #define EEPROM_SMID_88EE 0xDC | |
| 1351 | ||
| 1352 | /* RTL88EU */ | |
| 1353 | #define EEPROM_MAC_ADDR_88EU 0xD7 | |
| 1354 | #define EEPROM_VID_88EU 0xD0 | |
| 1355 | #define EEPROM_PID_88EU 0xD2 | |
| 1356 | #define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 | |
| 1357 | ||
| 1358 | /* RTL88ES */ | |
| 1359 | #define EEPROM_MAC_ADDR_88ES 0x11A | |
| 1360 | ||
| 7194ea87 | 1361 | /* EEPROM/Efuse Value Type */ |
| 58c43401 LF |
1362 | #define EETYPE_TX_PWR 0x0 |
| 1363 | ||
| 1364 | /* Default Value for EEPROM or EFUSE!!! */ | |
| 1365 | #define EEPROM_Default_TSSI 0x0 | |
| 1366 | #define EEPROM_Default_TxPowerDiff 0x0 | |
| 1367 | #define EEPROM_Default_CrystalCap 0x5 | |
| 1368 | /* Default: 2X2, RTL8192CE(QFPN68) */ | |
| 1369 | #define EEPROM_Default_BoardType 0x02 | |
| 1370 | #define EEPROM_Default_TxPower 0x1010 | |
| 1371 | #define EEPROM_Default_HT2T_TxPwr 0x10 | |
| 1372 | ||
| 1373 | #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 | |
| 1374 | #define EEPROM_Default_ThermalMeter 0x12 | |
| 1375 | ||
| 1376 | #define EEPROM_Default_AntTxPowerDiff 0x0 | |
| 1377 | #define EEPROM_Default_TxPwDiff_CrystalCap 0x5 | |
| 1378 | #define EEPROM_Default_TxPowerLevel 0x2A | |
| 1379 | ||
| 1380 | #define EEPROM_Default_HT40_2SDiff 0x0 | |
| 1381 | /* HT20<->40 default Tx Power Index Difference */ | |
| 1382 | #define EEPROM_Default_HT20_Diff 2 | |
| 1383 | #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 | |
| 1384 | #define EEPROM_Default_HT40_PwrMaxOffset 0 | |
| 1385 | #define EEPROM_Default_HT20_PwrMaxOffset 0 | |
| 1386 | ||
| 1387 | #define EEPROM_Default_CrystalCap_88E 0x20 | |
| 1388 | #define EEPROM_Default_ThermalMeter_88E 0x18 | |
| 1389 | ||
| 1390 | /* New EFUSE deafult value */ | |
| 1391 | #define EEPROM_DEFAULT_24G_INDEX 0x2D | |
| 1392 | #define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 | |
| 1393 | #define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 | |
| 1394 | ||
| 1395 | #define EEPROM_DEFAULT_5G_INDEX 0X2A | |
| 1396 | #define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 | |
| 1397 | #define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 | |
| 1398 | ||
| 1399 | #define EEPROM_DEFAULT_DIFF 0XFE | |
| 1400 | #define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F | |
| 1401 | #define EEPROM_DEFAULT_BOARD_OPTION 0x00 | |
| 1402 | #define EEPROM_DEFAULT_FEATURE_OPTION 0x00 | |
| 1403 | #define EEPROM_DEFAULT_BT_OPTION 0x10 | |
| 1404 | ||
| 1405 | /* For debug */ | |
| 1406 | #define EEPROM_Default_PID 0x1234 | |
| 1407 | #define EEPROM_Default_VID 0x5678 | |
| 1408 | #define EEPROM_Default_CustomerID 0xAB | |
| 1409 | #define EEPROM_Default_CustomerID_8188E 0x00 | |
| 1410 | #define EEPROM_Default_SubCustomerID 0xCD | |
| 1411 | #define EEPROM_Default_Version 0 | |
| 1412 | ||
| 1413 | #define EEPROM_CHANNEL_PLAN_FCC 0x0 | |
| 1414 | #define EEPROM_CHANNEL_PLAN_IC 0x1 | |
| 1415 | #define EEPROM_CHANNEL_PLAN_ETSI 0x2 | |
| 1416 | #define EEPROM_CHANNEL_PLAN_SPA 0x3 | |
| 1417 | #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 | |
| 1418 | #define EEPROM_CHANNEL_PLAN_MKK 0x5 | |
| 1419 | #define EEPROM_CHANNEL_PLAN_MKK1 0x6 | |
| 1420 | #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 | |
| 1421 | #define EEPROM_CHANNEL_PLAN_TELEC 0x8 | |
| 1422 | #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9 | |
| 1423 | #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA | |
| 1424 | #define EEPROM_CHANNEL_PLAN_NCC 0xB | |
| 1425 | #define EEPROM_USB_OPTIONAL1 0xE | |
| 1426 | #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 | |
| 1427 | ||
| 1428 | #define EEPROM_CID_DEFAULT 0x0 | |
| 1429 | #define EEPROM_CID_TOSHIBA 0x4 | |
| 1430 | #define EEPROM_CID_CCX 0x10 /* CCX test. */ | |
| 1431 | #define EEPROM_CID_QMI 0x0D | |
| 1432 | #define EEPROM_CID_WHQL 0xFE | |
| 1433 | #define RTL_EEPROM_ID 0x8129 | |
| 1434 | ||
| 1435 | #endif /* __RTL8188E_SPEC_H__ */ |