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staging: rtl8192e: Delete commented code
[deliverable/linux.git] / drivers / staging / rtl8192e / r8192E_core.c
CommitLineData
ecdfa446
GKH		 1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4803ef77 3 * Linux device driver for RTL8192E
ecdfa446
GKH		 4 *
5 * Based on the r8180 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Jerry chuang <wlanfae@realtek.com>
25 */
26
97a6688a 27
3d14b518 28#include <linux/vmalloc.h>
5a0e3ad6 29#include <linux/slab.h>
ecdfa446
GKH		 30#include <asm/uaccess.h>
31#include "r8192E_hw.h"
32#include "r8192E.h"
33#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */
34#include "r8180_93cx6.h" /* Card EEPROM */
35#include "r8192E_wx.h"
36#include "r819xE_phy.h" //added by WB 4.30.2008
37#include "r819xE_phyreg.h"
38#include "r819xE_cmdpkt.h"
39#include "r8192E_dm.h"
ecdfa446 40
bebdf809 41#ifdef CONFIG_PM
ecdfa446
GKH		 42#include "r8192_pm.h"
43#endif
44
45#ifdef ENABLE_DOT11D
65a43784 46#include "ieee80211/dot11d.h"
ecdfa446
GKH		 47#endif
48
49//set here to open your trace code. //WB
57be9583 50u32 rt_global_debug_component = COMP_ERR ; //always open err flags on
cf3d3d38 51
5eaa53de 52static DEFINE_PCI_DEVICE_TABLE(rtl8192_pci_id_tbl) = {
ecdfa446
GKH		 53 /* Realtek */
54 { PCI_DEVICE(0x10ec, 0x8192) },
55
56 /* Corega */
57 { PCI_DEVICE(0x07aa, 0x0044) },
58 { PCI_DEVICE(0x07aa, 0x0047) },
ecdfa446
GKH		 59 {}
60};
61
dca41306 62static char ifname[IFNAMSIZ] = "wlan%d";
ecdfa446
GKH		 63static int hwwep = 1; //default use hw. set 0 to use software security
64static int channels = 0x3fff;
65
66MODULE_LICENSE("GPL");
ecdfa446 67MODULE_VERSION("V 1.1");
ecdfa446
GKH		 68MODULE_DEVICE_TABLE(pci, rtl8192_pci_id_tbl);
69//MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
70MODULE_DESCRIPTION("Linux driver for Realtek RTL819x WiFi cards");
71
ecdfa446 72
dca41306 73module_param_string(ifname, ifname, sizeof(ifname), S_IRUGO|S_IWUSR);
ecdfa446
GKH		 74module_param(hwwep,int, S_IRUGO|S_IWUSR);
75module_param(channels,int, S_IRUGO|S_IWUSR);
ecdfa446
GKH		 76
77MODULE_PARM_DESC(ifname," Net interface name, wlan%d=default");
ecdfa446
GKH		 78MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards");
79MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
80
81static int __devinit rtl8192_pci_probe(struct pci_dev *pdev,
82 const struct pci_device_id *id);
83static void __devexit rtl8192_pci_disconnect(struct pci_dev *pdev);
84
85static struct pci_driver rtl8192_pci_driver = {
86 .name = RTL819xE_MODULE_NAME, /* Driver name */
87 .id_table = rtl8192_pci_id_tbl, /* PCI_ID table */
88 .probe = rtl8192_pci_probe, /* probe fn */
89 .remove = __devexit_p(rtl8192_pci_disconnect), /* remove fn */
bebdf809 90#ifdef CONFIG_PM
ecdfa446
GKH		 91 .suspend = rtl8192E_suspend, /* PM suspend fn */
92 .resume = rtl8192E_resume, /* PM resume fn */
93#else
94 .suspend = NULL, /* PM suspend fn */
214985a6 95 .resume = NULL, /* PM resume fn */
ecdfa446 96#endif
ecdfa446
GKH		 97};
98
559fba5e
MM		 99static void rtl8192_start_beacon(struct net_device *dev);
100static void rtl8192_stop_beacon(struct net_device *dev);
101static void rtl819x_watchdog_wqcallback(struct work_struct *work);
80a4dead
MM		 102static void rtl8192_irq_rx_tasklet(unsigned long arg);
103static void rtl8192_irq_tx_tasklet(unsigned long arg);
104static void rtl8192_prepare_beacon(unsigned long arg);
559fba5e 105static irqreturn_t rtl8192_interrupt(int irq, void *netdev);
762bf6de 106static void rtl819xE_tx_cmd(struct r8192_priv *priv, struct sk_buff *skb);
480ab9dc 107static void rtl8192_update_ratr_table(struct r8192_priv *priv);
5b3b1a7b
MM		 108static void rtl8192_restart(struct work_struct *work);
109static void watch_dog_timer_callback(unsigned long data);
af59c39d 110static int _rtl8192_up(struct r8192_priv *priv);
5b3b1a7b 111static void rtl8192_cancel_deferred_work(struct r8192_priv* priv);
af59c39d 112static short rtl8192_tx(struct r8192_priv *priv, struct sk_buff* skb);
559fba5e 113
ecdfa446
GKH		 114#ifdef ENABLE_DOT11D
115
116typedef struct _CHANNEL_LIST
117{
118 u8 Channel[32];
119 u8 Len;
120}CHANNEL_LIST, *PCHANNEL_LIST;
121
ab2161a0 122static const CHANNEL_LIST ChannelPlan[] = {
ecdfa446
GKH		 123 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC
124 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
125 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
126 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Spain. Change to ETSI.
127 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI.
128 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, //MKK //MKK
129 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22},//MKK1
130 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Israel.
131 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // For 11a , TELEC
132 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64}, 22}, //MIC
133 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14} //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
134};
135
136static void rtl819x_set_channel_map(u8 channel_plan, struct r8192_priv* priv)
137{
138 int i, max_chan=-1, min_chan=-1;
139 struct ieee80211_device* ieee = priv->ieee80211;
140 switch (channel_plan)
141 {
142 case COUNTRY_CODE_FCC:
143 case COUNTRY_CODE_IC:
144 case COUNTRY_CODE_ETSI:
145 case COUNTRY_CODE_SPAIN:
146 case COUNTRY_CODE_FRANCE:
147 case COUNTRY_CODE_MKK:
148 case COUNTRY_CODE_MKK1:
149 case COUNTRY_CODE_ISRAEL:
150 case COUNTRY_CODE_TELEC:
151 case COUNTRY_CODE_MIC:
152 {
153 Dot11d_Init(ieee);
154 ieee->bGlobalDomain = false;
155 //acturally 8225 & 8256 rf chip only support B,G,24N mode
6f304eb2
MM		 156 min_chan = 1;
157 max_chan = 14;
158
ecdfa446
GKH		 159 if (ChannelPlan[channel_plan].Len != 0){
160 // Clear old channel map
161 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
162 // Set new channel map
163 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
164 {
165 if (ChannelPlan[channel_plan].Channel[i] < min_chan || ChannelPlan[channel_plan].Channel[i] > max_chan)
166 break;
167 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
168 }
169 }
170 break;
171 }
172 case COUNTRY_CODE_GLOBAL_DOMAIN:
173 {
174 GET_DOT11D_INFO(ieee)->bEnabled = 0; //this flag enabled to follow 11d country IE setting, otherwise, it shall follow global domain setting
175 Dot11d_Reset(ieee);
176 ieee->bGlobalDomain = true;
177 break;
178 }
179 default:
180 break;
181 }
182}
183#endif
184
52cab756
MM		 185static inline bool rx_hal_is_cck_rate(prx_fwinfo_819x_pci pdrvinfo)
186{
187 return (pdrvinfo->RxRate == DESC90_RATE1M ||
188 pdrvinfo->RxRate == DESC90_RATE2M ||
189 pdrvinfo->RxRate == DESC90_RATE5_5M ||
190 pdrvinfo->RxRate == DESC90_RATE11M) &&
191 !pdrvinfo->RxHT;
192}
ecdfa446 193
480ab9dc 194void CamResetAllEntry(struct r8192_priv* priv)
ecdfa446 195{
3f9ab1ee 196 write_nic_dword(priv, RWCAM, BIT31|BIT30);
ecdfa446
GKH		 197}
198
3f9ab1ee 199void write_cam(struct r8192_priv *priv, u8 addr, u32 data)
ecdfa446 200{
3f9ab1ee
MM		 201 write_nic_dword(priv, WCAMI, data);
202 write_nic_dword(priv, RWCAM, BIT31|BIT16|(addr&0xff) );
ecdfa446 203}
3f9ab1ee
MM		 204
205u32 read_cam(struct r8192_priv *priv, u8 addr)
ecdfa446 206{
3f9ab1ee
MM		 207 write_nic_dword(priv, RWCAM, 0x80000000|(addr&0xff) );
208 return read_nic_dword(priv, 0xa8);
ecdfa446
GKH		 209}
210
3f9ab1ee 211u8 read_nic_byte(struct r8192_priv *priv, int x)
ecdfa446 212{
3f9ab1ee 213 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 214 return 0xff&readb((u8*)dev->mem_start +x);
215}
216
3f9ab1ee 217u32 read_nic_dword(struct r8192_priv *priv, int x)
ecdfa446 218{
3f9ab1ee 219 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 220 return readl((u8*)dev->mem_start +x);
221}
222
3f9ab1ee 223u16 read_nic_word(struct r8192_priv *priv, int x)
ecdfa446 224{
3f9ab1ee 225 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 226 return readw((u8*)dev->mem_start +x);
227}
228
3f9ab1ee 229void write_nic_byte(struct r8192_priv *priv, int x,u8 y)
ecdfa446 230{
3f9ab1ee 231 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 232 writeb(y,(u8*)dev->mem_start +x);
233 udelay(20);
234}
235
3f9ab1ee 236void write_nic_dword(struct r8192_priv *priv, int x,u32 y)
ecdfa446 237{
3f9ab1ee 238 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 239 writel(y,(u8*)dev->mem_start +x);
240 udelay(20);
241}
242
3f9ab1ee 243void write_nic_word(struct r8192_priv *priv, int x,u16 y)
ecdfa446 244{
3f9ab1ee 245 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 246 writew(y,(u8*)dev->mem_start +x);
247 udelay(20);
248}
249
65a43784 250u8 rtl8192e_ap_sec_type(struct ieee80211_device *ieee)
251{
4a533365
MM		 252 static const u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04};
253 static const u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04};
65a43784 254 int wpa_ie_len= ieee->wpa_ie_len;
255 struct ieee80211_crypt_data* crypt;
256 int encrypt;
257
258 crypt = ieee->crypt[ieee->tx_keyidx];
259
207b58fb
MM		 260 encrypt = (ieee->current_network.capability & WLAN_CAPABILITY_PRIVACY) ||
261 (ieee->host_encrypt && crypt && crypt->ops &&
65a43784 262 (0 == strcmp(crypt->ops->name,"WEP")));
263
264 /* simply judge */
265 if(encrypt && (wpa_ie_len == 0)) {
266 // wep encryption, no N mode setting */
267 return SEC_ALG_WEP;
268 } else if((wpa_ie_len != 0)) {
269 // parse pairwise key type */
270 if (((ieee->wpa_ie[0] == 0xdd) && (!memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) ||
271 ((ieee->wpa_ie[0] == 0x30) && (!memcmp(&ieee->wpa_ie[10],ccmp_rsn_ie, 4))))
272 return SEC_ALG_CCMP;
273 else
274 return SEC_ALG_TKIP;
275 } else {
276 return SEC_ALG_NONE;
277 }
278}
279
280void
281rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val)
282{
283 struct r8192_priv* priv = ieee80211_priv(dev);
284
285 switch(variable)
286 {
287
288 case HW_VAR_BSSID:
3f9ab1ee
MM		 289 write_nic_dword(priv, BSSIDR, ((u32*)(val))[0]);
290 write_nic_word(priv, BSSIDR+2, ((u16*)(val+2))[0]);
65a43784 291 break;
292
293 case HW_VAR_MEDIA_STATUS:
294 {
295 RT_OP_MODE OpMode = *((RT_OP_MODE *)(val));
3f9ab1ee 296 u8 btMsr = read_nic_byte(priv, MSR);
65a43784 297
298 btMsr &= 0xfc;
299
300 switch(OpMode)
301 {
302 case RT_OP_MODE_INFRASTRUCTURE:
303 btMsr |= MSR_INFRA;
65a43784 304 break;
305
306 case RT_OP_MODE_IBSS:
307 btMsr |= MSR_ADHOC;
65a43784 308 break;
309
310 case RT_OP_MODE_AP:
311 btMsr |= MSR_AP;
65a43784 312 break;
313
314 default:
315 btMsr |= MSR_NOLINK;
316 break;
317 }
318
3f9ab1ee 319 write_nic_byte(priv, MSR, btMsr);
65a43784 320 }
321 break;
322
951fc8ed 323 case HW_VAR_CHECK_BSSID:
65a43784 324 {
325 u32 RegRCR, Type;
326
327 Type = ((u8*)(val))[0];
3f9ab1ee 328 RegRCR = read_nic_dword(priv, RCR);
65a43784 329 priv->ReceiveConfig = RegRCR;
330
331 if (Type == true)
332 RegRCR |= (RCR_CBSSID);
333 else if (Type == false)
334 RegRCR &= (~RCR_CBSSID);
335
3f9ab1ee 336 write_nic_dword(priv, RCR,RegRCR);
65a43784 337 priv->ReceiveConfig = RegRCR;
338
339 }
340 break;
341
342 case HW_VAR_SLOT_TIME:
343 {
65a43784 344 priv->slot_time = val[0];
3f9ab1ee 345 write_nic_byte(priv, SLOT_TIME, val[0]);
65a43784 346
347 }
348 break;
349
350 case HW_VAR_ACK_PREAMBLE:
351 {
352 u32 regTmp = 0;
353 priv->short_preamble = (bool)(*(u8*)val );
354 regTmp = priv->basic_rate;
355 if (priv->short_preamble)
356 regTmp |= BRSR_AckShortPmb;
3f9ab1ee 357 write_nic_dword(priv, RRSR, regTmp);
65a43784 358 }
359 break;
360
361 case HW_VAR_CPU_RST:
3f9ab1ee 362 write_nic_dword(priv, CPU_GEN, ((u32*)(val))[0]);
65a43784 363 break;
364
365 default:
366 break;
367 }
368
369}
370
ecdfa446
GKH		 371static struct proc_dir_entry *rtl8192_proc = NULL;
372
ecdfa446
GKH		 373static int proc_get_stats_ap(char *page, char **start,
374 off_t offset, int count,
375 int *eof, void *data)
376{
377 struct net_device *dev = data;
378 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
379 struct ieee80211_device *ieee = priv->ieee80211;
380 struct ieee80211_network *target;
ecdfa446
GKH		 381 int len = 0;
382
383 list_for_each_entry(target, &ieee->network_list, list) {
384
385 len += snprintf(page + len, count - len,
386 "%s ", target->ssid);
387
388 if(target->wpa_ie_len>0 || target->rsn_ie_len>0){
389 len += snprintf(page + len, count - len,
390 "WPA\n");
391 }
392 else{
393 len += snprintf(page + len, count - len,
394 "non_WPA\n");
395 }
396
397 }
398
399 *eof = 1;
400 return len;
401}
402
403static int proc_get_registers(char *page, char **start,
404 off_t offset, int count,
405 int *eof, void *data)
406{
407 struct net_device *dev = data;
3f9ab1ee 408 struct r8192_priv *priv = ieee80211_priv(dev);
ecdfa446
GKH		 409 int len = 0;
410 int i,n;
ecdfa446
GKH		 411 int max=0xff;
412
413 /* This dump the current register page */
414 len += snprintf(page + len, count - len,
415 "\n####################page 0##################\n ");
416
417 for(n=0;n<=max;)
418 {
ecdfa446
GKH		 419 len += snprintf(page + len, count - len,
420 "\nD: %2x > ",n);
421
422 for(i=0;i<16 && n<=max;i++,n++)
423 len += snprintf(page + len, count - len,
3f9ab1ee 424 "%2x ",read_nic_byte(priv,n));
ecdfa446
GKH		 425 }
426 len += snprintf(page + len, count - len,"\n");
427 len += snprintf(page + len, count - len,
428 "\n####################page 1##################\n ");
429 for(n=0;n<=max;)
430 {
ecdfa446
GKH		 431 len += snprintf(page + len, count - len,
432 "\nD: %2x > ",n);
433
434 for(i=0;i<16 && n<=max;i++,n++)
435 len += snprintf(page + len, count - len,
3f9ab1ee 436 "%2x ",read_nic_byte(priv,0x100|n));
ecdfa446
GKH		 437 }
438
439 len += snprintf(page + len, count - len,
440 "\n####################page 3##################\n ");
441 for(n=0;n<=max;)
442 {
ecdfa446
GKH		 443 len += snprintf(page + len, count - len,
444 "\nD: %2x > ",n);
445
446 for(i=0;i<16 && n<=max;i++,n++)
447 len += snprintf(page + len, count - len,
3f9ab1ee 448 "%2x ",read_nic_byte(priv,0x300|n));
ecdfa446
GKH		 449 }
450
ecdfa446
GKH		 451 *eof = 1;
452 return len;
453
454}
455
ecdfa446
GKH		 456static int proc_get_stats_tx(char *page, char **start,
457 off_t offset, int count,
458 int *eof, void *data)
459{
460 struct net_device *dev = data;
461 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
462
463 int len = 0;
464
465 len += snprintf(page + len, count - len,
466 "TX VI priority ok int: %lu\n"
ecdfa446 467 "TX VO priority ok int: %lu\n"
ecdfa446 468 "TX BE priority ok int: %lu\n"
ecdfa446 469 "TX BK priority ok int: %lu\n"
ecdfa446 470 "TX MANAGE priority ok int: %lu\n"
ecdfa446
GKH		 471 "TX BEACON priority ok int: %lu\n"
472 "TX BEACON priority error int: %lu\n"
473 "TX CMDPKT priority ok int: %lu\n"
ecdfa446
GKH		 474 "TX queue stopped?: %d\n"
475 "TX fifo overflow: %lu\n"
ecdfa446
GKH		 476 "TX total data packets %lu\n"
477 "TX total data bytes :%lu\n",
ecdfa446 478 priv->stats.txviokint,
ecdfa446 479 priv->stats.txvookint,
ecdfa446 480 priv->stats.txbeokint,
ecdfa446 481 priv->stats.txbkokint,
ecdfa446 482 priv->stats.txmanageokint,
ecdfa446
GKH		 483 priv->stats.txbeaconokint,
484 priv->stats.txbeaconerr,
485 priv->stats.txcmdpktokint,
ecdfa446
GKH		 486 netif_queue_stopped(dev),
487 priv->stats.txoverflow,
ecdfa446 488 priv->ieee80211->stats.tx_packets,
3059f2de 489 priv->ieee80211->stats.tx_bytes);
ecdfa446
GKH		 490
491 *eof = 1;
492 return len;
493}
494
495
496
497static int proc_get_stats_rx(char *page, char **start,
498 off_t offset, int count,
499 int *eof, void *data)
500{
501 struct net_device *dev = data;
502 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
503
504 int len = 0;
505
506 len += snprintf(page + len, count - len,
507 "RX packets: %lu\n"
508 "RX desc err: %lu\n"
c282f2e3 509 "RX rx overflow error: %lu\n",
ecdfa446
GKH		 510 priv->stats.rxint,
511 priv->stats.rxrdu,
c282f2e3 512 priv->stats.rxoverflow);
ecdfa446
GKH		 513
514 *eof = 1;
515 return len;
516}
517
5e1ad18a 518static void rtl8192_proc_module_init(void)
ecdfa446 519{
703fdcc3 520 RT_TRACE(COMP_INIT, "Initializing proc filesystem\n");
ecdfa446 521 rtl8192_proc=create_proc_entry(RTL819xE_MODULE_NAME, S_IFDIR, init_net.proc_net);
ecdfa446
GKH		 522}
523
524
5e1ad18a 525static void rtl8192_proc_module_remove(void)
ecdfa446 526{
ecdfa446 527 remove_proc_entry(RTL819xE_MODULE_NAME, init_net.proc_net);
ecdfa446
GKH		 528}
529
530
af59c39d 531static void rtl8192_proc_remove_one(struct r8192_priv *priv)
ecdfa446 532{
af59c39d 533 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 534
535 printk("dev name=======> %s\n",dev->name);
536
537 if (priv->dir_dev) {
ecdfa446
GKH		 538 remove_proc_entry("stats-tx", priv->dir_dev);
539 remove_proc_entry("stats-rx", priv->dir_dev);
ecdfa446
GKH		 540 remove_proc_entry("stats-ap", priv->dir_dev);
541 remove_proc_entry("registers", priv->dir_dev);
ecdfa446
GKH		 542 remove_proc_entry("wlan0", rtl8192_proc);
543 priv->dir_dev = NULL;
544 }
545}
546
547
af59c39d 548static void rtl8192_proc_init_one(struct r8192_priv *priv)
ecdfa446 549{
af59c39d 550 struct net_device *dev = priv->ieee80211->dev;
ecdfa446 551 struct proc_dir_entry *e;
af59c39d 552
ecdfa446
GKH		 553 priv->dir_dev = create_proc_entry(dev->name,
554 S_IFDIR | S_IRUGO | S_IXUGO,
555 rtl8192_proc);
556 if (!priv->dir_dev) {
557 RT_TRACE(COMP_ERR, "Unable to initialize /proc/net/rtl8192/%s\n",
558 dev->name);
559 return;
560 }
ecdfa446
GKH		 561 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
562 priv->dir_dev, proc_get_stats_rx, dev);
563
564 if (!e) {
565 RT_TRACE(COMP_ERR,"Unable to initialize "
566 "/proc/net/rtl8192/%s/stats-rx\n",
567 dev->name);
568 }
569
570
571 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
572 priv->dir_dev, proc_get_stats_tx, dev);
573
574 if (!e) {
575 RT_TRACE(COMP_ERR, "Unable to initialize "
576 "/proc/net/rtl8192/%s/stats-tx\n",
577 dev->name);
578 }
ecdfa446
GKH		 579
580 e = create_proc_read_entry("stats-ap", S_IFREG | S_IRUGO,
581 priv->dir_dev, proc_get_stats_ap, dev);
582
583 if (!e) {
584 RT_TRACE(COMP_ERR, "Unable to initialize "
585 "/proc/net/rtl8192/%s/stats-ap\n",
586 dev->name);
587 }
588
589 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
590 priv->dir_dev, proc_get_registers, dev);
591 if (!e) {
592 RT_TRACE(COMP_ERR, "Unable to initialize "
593 "/proc/net/rtl8192/%s/registers\n",
594 dev->name);
595 }
ecdfa446 596}
ecdfa446 597
9f17b076 598static short check_nic_enough_desc(struct net_device *dev, int prio)
ecdfa446
GKH		 599{
600 struct r8192_priv *priv = ieee80211_priv(dev);
601 struct rtl8192_tx_ring *ring = &priv->tx_ring[prio];
602
603 /* for now we reserve two free descriptor as a safety boundary
604 * between the tail and the head
605 */
285f660c 606 return (ring->entries - skb_queue_len(&ring->queue) >= 2);
ecdfa446
GKH		 607}
608
5e1ad18a 609static void tx_timeout(struct net_device *dev)
ecdfa446
GKH		 610{
611 struct r8192_priv *priv = ieee80211_priv(dev);
ecdfa446 612
ecdfa446 613 schedule_work(&priv->reset_wq);
ecdfa446
GKH		 614 printk("TXTIMEOUT");
615}
616
480ab9dc 617static void rtl8192_irq_enable(struct r8192_priv *priv)
ecdfa446 618{
ae9f66da
MM		 619 u32 mask;
620
621 mask = IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK |
622 IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
623 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 | IMR_RDU | IMR_RXFOVW |
624 IMR_TXFOVW | IMR_BcnInt | IMR_TBDOK | IMR_TBDER;
625
626 write_nic_dword(priv, INTA_MASK, mask);
ecdfa446
GKH		 627}
628
af59c39d 629static void rtl8192_irq_disable(struct r8192_priv *priv)
ecdfa446 630{
3f9ab1ee 631 write_nic_dword(priv, INTA_MASK, 0);
af59c39d 632 synchronize_irq(priv->irq);
ecdfa446
GKH		 633}
634
480ab9dc 635static void rtl8192_update_msr(struct r8192_priv *priv)
ecdfa446 636{
ecdfa446
GKH		 637 u8 msr;
638
3f9ab1ee 639 msr = read_nic_byte(priv, MSR);
ecdfa446
GKH		 640 msr &= ~ MSR_LINK_MASK;
641
642 /* do not change in link_state != WLAN_LINK_ASSOCIATED.
643 * msr must be updated if the state is ASSOCIATING.
644 * this is intentional and make sense for ad-hoc and
645 * master (see the create BSS/IBSS func)
646 */
647 if (priv->ieee80211->state == IEEE80211_LINKED){
648
649 if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
650 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
651 else if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
652 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
653 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
654 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
655
656 }else
657 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
658
3f9ab1ee 659 write_nic_byte(priv, MSR, msr);
ecdfa446
GKH		 660}
661
9f17b076 662static void rtl8192_set_chan(struct net_device *dev,short ch)
ecdfa446 663{
61d0e67a 664 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
ecdfa446 665
61d0e67a 666 priv->chan = ch;
ecdfa446 667
61d0e67a 668 /* need to implement rf set channel here WB */
ecdfa446 669
61d0e67a
MM		 670 if (priv->rf_set_chan)
671 priv->rf_set_chan(dev, priv->chan);
ecdfa446
GKH		 672}
673
480ab9dc 674static void rtl8192_rx_enable(struct r8192_priv *priv)
ecdfa446 675{
480ab9dc 676 write_nic_dword(priv, RDQDA, priv->rx_ring_dma);
ecdfa446
GKH		 677}
678
679/* the TX_DESC_BASE setting is according to the following queue index
680 * BK_QUEUE ===> 0
681 * BE_QUEUE ===> 1
682 * VI_QUEUE ===> 2
683 * VO_QUEUE ===> 3
684 * HCCA_QUEUE ===> 4
685 * TXCMD_QUEUE ===> 5
686 * MGNT_QUEUE ===> 6
687 * HIGH_QUEUE ===> 7
688 * BEACON_QUEUE ===> 8
689 * */
881a975b 690static const u32 TX_DESC_BASE[] = {BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA};
480ab9dc 691static void rtl8192_tx_enable(struct r8192_priv *priv)
ecdfa446 692{
7aed48d9 693 u32 i;
ecdfa446 694
7aed48d9 695 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
3f9ab1ee 696 write_nic_dword(priv, TX_DESC_BASE[i], priv->tx_ring[i].dma);
7aed48d9
MM		 697
698 ieee80211_reset_queue(priv->ieee80211);
ecdfa446
GKH		 699}
700
ecdfa446 701
af59c39d 702static void rtl8192_free_rx_ring(struct r8192_priv *priv)
ecdfa446 703{
7aed48d9 704 int i;
ecdfa446 705
7aed48d9
MM		 706 for (i = 0; i < priv->rxringcount; i++) {
707 struct sk_buff *skb = priv->rx_buf[i];
708 if (!skb)
709 continue;
ecdfa446 710
7aed48d9
MM		 711 pci_unmap_single(priv->pdev,
712 *((dma_addr_t *)skb->cb),
713 priv->rxbuffersize, PCI_DMA_FROMDEVICE);
714 kfree_skb(skb);
715 }
ecdfa446 716
7aed48d9
MM		 717 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * priv->rxringcount,
718 priv->rx_ring, priv->rx_ring_dma);
719 priv->rx_ring = NULL;
ecdfa446
GKH		 720}
721
af59c39d 722static void rtl8192_free_tx_ring(struct r8192_priv *priv, unsigned int prio)
ecdfa446 723{
7aed48d9 724 struct rtl8192_tx_ring *ring = &priv->tx_ring[prio];
ecdfa446 725
7aed48d9
MM		 726 while (skb_queue_len(&ring->queue)) {
727 tx_desc_819x_pci *entry = &ring->desc[ring->idx];
728 struct sk_buff *skb = __skb_dequeue(&ring->queue);
ecdfa446 729
7aed48d9
MM		 730 pci_unmap_single(priv->pdev, le32_to_cpu(entry->TxBuffAddr),
731 skb->len, PCI_DMA_TODEVICE);
732 kfree_skb(skb);
733 ring->idx = (ring->idx + 1) % ring->entries;
734 }
ecdfa446 735
7aed48d9
MM		 736 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
737 ring->desc, ring->dma);
738 ring->desc = NULL;
ecdfa446
GKH		 739}
740
480ab9dc 741void PHY_SetRtl8192eRfOff(struct r8192_priv *priv)
ecdfa446 742{
65a43784 743 //disable RF-Chip A/B
d9ffa6c2 744 rtl8192_setBBreg(priv, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
65a43784 745 //analog to digital off, for power save
d9ffa6c2 746 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x0);
65a43784 747 //digital to analog off, for power save
d9ffa6c2 748 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x18, 0x0);
65a43784 749 //rx antenna off
d9ffa6c2 750 rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0xf, 0x0);
65a43784 751 //rx antenna off
d9ffa6c2 752 rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0xf, 0x0);
65a43784 753 //analog to digital part2 off, for power save
d9ffa6c2
MM		 754 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x60, 0x0);
755 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x4, 0x0);
65a43784 756 // Analog parameter!!Change bias and Lbus control.
3f9ab1ee 757 write_nic_byte(priv, ANAPAR_FOR_8192PciE, 0x07);
65a43784 758}
ecdfa446 759
af59c39d 760static void rtl8192_halt_adapter(struct r8192_priv *priv, bool reset)
ecdfa446 761{
af59c39d 762 struct net_device *dev = priv->ieee80211->dev;
65a43784 763 int i;
932f4b3a
MM		 764 u8 OpMode;
765 u32 ulRegRead;
65a43784 766
767 OpMode = RT_OP_MODE_NO_LINK;
768 priv->ieee80211->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
ecdfa446 769
932f4b3a
MM		 770 if (!priv->ieee80211->bSupportRemoteWakeUp) {
771 /*
772 * disable tx/rx. In 8185 we write 0x10 (Reset bit),
773 * but here we make reference to WMAC and wirte 0x0
774 */
3f9ab1ee 775 write_nic_byte(priv, CMDR, 0);
65a43784 776 }
ecdfa446 777
65a43784 778 mdelay(20);
ecdfa446 779
932f4b3a 780 if (!reset) {
65a43784 781 mdelay(150);
782
932f4b3a 783 priv->bHwRfOffAction = 2;
65a43784 784
932f4b3a
MM		 785 /*
786 * Call MgntActSet_RF_State instead to
787 * prevent RF config race condition.
788 */
789 if (!priv->ieee80211->bSupportRemoteWakeUp) {
480ab9dc 790 PHY_SetRtl8192eRfOff(priv);
3f9ab1ee 791 ulRegRead = read_nic_dword(priv, CPU_GEN);
932f4b3a 792 ulRegRead |= CPU_GEN_SYSTEM_RESET;
3f9ab1ee 793 write_nic_dword(priv,CPU_GEN, ulRegRead);
932f4b3a
MM		 794 } else {
795 /* for WOL */
3f9ab1ee
MM		 796 write_nic_dword(priv, WFCRC0, 0xffffffff);
797 write_nic_dword(priv, WFCRC1, 0xffffffff);
798 write_nic_dword(priv, WFCRC2, 0xffffffff);
65a43784 799
932f4b3a 800 /* Write PMR register */
3f9ab1ee 801 write_nic_byte(priv, PMR, 0x5);
932f4b3a 802 /* Disable tx, enanble rx */
3f9ab1ee 803 write_nic_byte(priv, MacBlkCtrl, 0xa);
65a43784 804 }
805 }
806
807 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
808 skb_queue_purge(&priv->ieee80211->skb_waitQ [i]);
809 }
810 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
811 skb_queue_purge(&priv->ieee80211->skb_aggQ [i]);
812 }
ecdfa446
GKH		 813
814 skb_queue_purge(&priv->skb_queue);
ecdfa446
GKH		 815}
816
5e1ad18a 817static void rtl8192_data_hard_stop(struct net_device *dev)
ecdfa446 818{
ecdfa446
GKH		 819}
820
5e1ad18a 821static void rtl8192_data_hard_resume(struct net_device *dev)
ecdfa446 822{
ecdfa446
GKH		 823}
824
214985a6
MM		 825/*
826 * this function TX data frames when the ieee80211 stack requires this.
ecdfa446
GKH		 827 * It checks also if we need to stop the ieee tx queue, eventually do it
828 */
5e1ad18a 829static void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int rate)
ecdfa446
GKH		 830{
831 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
832 int ret;
ecdfa446
GKH		 833 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
834 u8 queue_index = tcb_desc->queue_index;
dcf663fb 835
ecdfa446 836 /* shall not be referred by command packet */
5d33549a 837 BUG_ON(queue_index == TXCMD_QUEUE);
ecdfa446 838
dcf663fb 839 if (priv->bHwRadioOff || (!priv->up))
65a43784 840 {
841 kfree_skb(skb);
842 return;
843 }
844
dcf663fb 845 memcpy(skb->cb, &dev, sizeof(dev));
ecdfa446 846
ecdfa446 847 skb_push(skb, priv->ieee80211->tx_headroom);
af59c39d 848 ret = rtl8192_tx(priv, skb);
dcf663fb 849 if (ret != 0) {
ecdfa446 850 kfree_skb(skb);
ecdfa446
GKH		 851 }
852
dcf663fb
MM		 853 if (queue_index != MGNT_QUEUE) {
854 priv->ieee80211->stats.tx_bytes += (skb->len - priv->ieee80211->tx_headroom);
855 priv->ieee80211->stats.tx_packets++;
856 }
ecdfa446
GKH		 857}
858
214985a6
MM		 859/*
860 * This is a rough attempt to TX a frame
ecdfa446
GKH		 861 * This is called by the ieee 80211 stack to TX management frames.
862 * If the ring is full packet are dropped (for data frame the queue
863 * is stopped before this can happen).
864 */
5e1ad18a 865static int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
ecdfa446
GKH		 866{
867 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
ecdfa446 868 int ret;
ecdfa446
GKH		 869 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
870 u8 queue_index = tcb_desc->queue_index;
871
162f535f
MM		 872 if (queue_index != TXCMD_QUEUE) {
873 if (priv->bHwRadioOff || (!priv->up))
65a43784 874 {
162f535f
MM		 875 kfree_skb(skb);
876 return 0;
877 }
65a43784 878 }
ecdfa446 879
162f535f
MM		 880 memcpy(skb->cb, &dev, sizeof(dev));
881 if (queue_index == TXCMD_QUEUE) {
762bf6de 882 rtl819xE_tx_cmd(priv, skb);
ecdfa446 883 ret = 0;
ecdfa446
GKH		 884 return ret;
885 } else {
ecdfa446
GKH		 886 tcb_desc->RATRIndex = 7;
887 tcb_desc->bTxDisableRateFallBack = 1;
888 tcb_desc->bTxUseDriverAssingedRate = 1;
889 tcb_desc->bTxEnableFwCalcDur = 1;
890 skb_push(skb, priv->ieee80211->tx_headroom);
af59c39d 891 ret = rtl8192_tx(priv, skb);
162f535f 892 if (ret != 0) {
ecdfa446 893 kfree_skb(skb);
162f535f 894 }
ecdfa446
GKH		 895 }
896
ecdfa446 897 return ret;
ecdfa446
GKH		 898}
899
900
af59c39d 901static void rtl8192_tx_isr(struct r8192_priv *priv, int prio)
ecdfa446 902{
a922a4b7 903 struct rtl8192_tx_ring *ring = &priv->tx_ring[prio];
ecdfa446 904
a922a4b7
MM		 905 while (skb_queue_len(&ring->queue)) {
906 tx_desc_819x_pci *entry = &ring->desc[ring->idx];
907 struct sk_buff *skb;
ecdfa446 908
a922a4b7
MM		 909 /*
910 * beacon packet will only use the first descriptor defaultly,
911 * and the OWN may not be cleared by the hardware
912 */
913 if (prio != BEACON_QUEUE) {
914 if (entry->OWN)
915 return;
916 ring->idx = (ring->idx + 1) % ring->entries;
917 }
ecdfa446 918
a922a4b7
MM		 919 skb = __skb_dequeue(&ring->queue);
920 pci_unmap_single(priv->pdev, le32_to_cpu(entry->TxBuffAddr),
921 skb->len, PCI_DMA_TODEVICE);
ecdfa446 922
a922a4b7
MM		 923 kfree_skb(skb);
924 }
ecdfa446 925
a922a4b7
MM		 926 if (prio != BEACON_QUEUE) {
927 /* try to deal with the pending packets */
928 tasklet_schedule(&priv->irq_tx_tasklet);
929 }
ecdfa446
GKH		 930}
931
5e1ad18a 932static void rtl8192_stop_beacon(struct net_device *dev)
ecdfa446 933{
ecdfa446
GKH		 934}
935
480ab9dc 936static void rtl8192_config_rate(struct r8192_priv *priv, u16* rate_config)
ecdfa446 937{
ecdfa446
GKH		 938 struct ieee80211_network *net;
939 u8 i=0, basic_rate = 0;
940 net = & priv->ieee80211->current_network;
941
942 for (i=0; i<net->rates_len; i++)
943 {
944 basic_rate = net->rates[i]&0x7f;
945 switch(basic_rate)
946 {
947 case MGN_1M: *rate_config |= RRSR_1M; break;
948 case MGN_2M: *rate_config |= RRSR_2M; break;
949 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
950 case MGN_11M: *rate_config |= RRSR_11M; break;
951 case MGN_6M: *rate_config |= RRSR_6M; break;
952 case MGN_9M: *rate_config |= RRSR_9M; break;
953 case MGN_12M: *rate_config |= RRSR_12M; break;
954 case MGN_18M: *rate_config |= RRSR_18M; break;
955 case MGN_24M: *rate_config |= RRSR_24M; break;
956 case MGN_36M: *rate_config |= RRSR_36M; break;
957 case MGN_48M: *rate_config |= RRSR_48M; break;
958 case MGN_54M: *rate_config |= RRSR_54M; break;
959 }
960 }
961 for (i=0; i<net->rates_ex_len; i++)
962 {
963 basic_rate = net->rates_ex[i]&0x7f;
964 switch(basic_rate)
965 {
966 case MGN_1M: *rate_config |= RRSR_1M; break;
967 case MGN_2M: *rate_config |= RRSR_2M; break;
968 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
969 case MGN_11M: *rate_config |= RRSR_11M; break;
970 case MGN_6M: *rate_config |= RRSR_6M; break;
971 case MGN_9M: *rate_config |= RRSR_9M; break;
972 case MGN_12M: *rate_config |= RRSR_12M; break;
973 case MGN_18M: *rate_config |= RRSR_18M; break;
974 case MGN_24M: *rate_config |= RRSR_24M; break;
975 case MGN_36M: *rate_config |= RRSR_36M; break;
976 case MGN_48M: *rate_config |= RRSR_48M; break;
977 case MGN_54M: *rate_config |= RRSR_54M; break;
978 }
979 }
980}
981
982
983#define SHORT_SLOT_TIME 9
984#define NON_SHORT_SLOT_TIME 20
985
480ab9dc 986static void rtl8192_update_cap(struct r8192_priv *priv, u16 cap)
ecdfa446
GKH		 987{
988 u32 tmp = 0;
ecdfa446 989 struct ieee80211_network *net = &priv->ieee80211->current_network;
480ab9dc 990
ecdfa446
GKH		 991 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
992 tmp = priv->basic_rate;
993 if (priv->short_preamble)
994 tmp |= BRSR_AckShortPmb;
3f9ab1ee 995 write_nic_dword(priv, RRSR, tmp);
ecdfa446
GKH		 996
997 if (net->mode & (IEEE_G|IEEE_N_24G))
998 {
999 u8 slot_time = 0;
1000 if ((cap & WLAN_CAPABILITY_SHORT_SLOT)&&(!priv->ieee80211->pHTInfo->bCurrentRT2RTLongSlotTime))
1001 {//short slot time
1002 slot_time = SHORT_SLOT_TIME;
1003 }
1004 else //long slot time
1005 slot_time = NON_SHORT_SLOT_TIME;
1006 priv->slot_time = slot_time;
3f9ab1ee 1007 write_nic_byte(priv, SLOT_TIME, slot_time);
ecdfa446
GKH		 1008 }
1009
1010}
5e1ad18a 1011
480ab9dc 1012static void rtl8192_net_update(struct r8192_priv *priv)
ecdfa446 1013{
ecdfa446
GKH		 1014 struct ieee80211_network *net;
1015 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
1016 u16 rate_config = 0;
1017 net = &priv->ieee80211->current_network;
eb40aeac
MM		 1018
1019 /* update Basic rate: RR, BRSR */
480ab9dc 1020 rtl8192_config_rate(priv, &rate_config);
ecdfa446 1021
eb40aeac
MM		 1022 /*
1023 * Select RRSR (in Legacy-OFDM and CCK)
1024 * For 8190, we select only 24M, 12M, 6M, 11M, 5.5M,
1025 * 2M, and 1M from the Basic rate.
1026 * We do not use other rates.
1027 */
1028 priv->basic_rate = rate_config &= 0x15f;
1029
1030 /* BSSID */
3f9ab1ee
MM		 1031 write_nic_dword(priv, BSSIDR, ((u32 *)net->bssid)[0]);
1032 write_nic_word(priv, BSSIDR+4, ((u16 *)net->bssid)[2]);
ecdfa446 1033
ecdfa446
GKH		 1034 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1035 {
3f9ab1ee
MM		 1036 write_nic_word(priv, ATIMWND, 2);
1037 write_nic_word(priv, BCN_DMATIME, 256);
1038 write_nic_word(priv, BCN_INTERVAL, net->beacon_interval);
eb40aeac
MM		 1039 /*
1040 * BIT15 of BCN_DRV_EARLY_INT will indicate
1041 * whether software beacon or hw beacon is applied.
1042 */
3f9ab1ee
MM		 1043 write_nic_word(priv, BCN_DRV_EARLY_INT, 10);
1044 write_nic_byte(priv, BCN_ERR_THRESH, 100);
ecdfa446
GKH		 1045
1046 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
eb40aeac
MM		 1047 /* TODO: BcnIFS may required to be changed on ASIC */
1048 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
3f9ab1ee 1049 write_nic_word(priv, BCN_TCFG, BcnTimeCfg);
ecdfa446 1050 }
ecdfa446
GKH		 1051}
1052
762bf6de 1053static void rtl819xE_tx_cmd(struct r8192_priv *priv, struct sk_buff *skb)
ecdfa446 1054{
ecdfa446
GKH		 1055 struct rtl8192_tx_ring *ring;
1056 tx_desc_819x_pci *entry;
1057 unsigned int idx;
1058 dma_addr_t mapping;
1059 cb_desc *tcb_desc;
1060 unsigned long flags;
1061
1062 ring = &priv->tx_ring[TXCMD_QUEUE];
1063 mapping = pci_map_single(priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
1064
1065 spin_lock_irqsave(&priv->irq_th_lock,flags);
1066 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
1067 entry = &ring->desc[idx];
1068
1069 tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
1070 memset(entry,0,12);
1071 entry->LINIP = tcb_desc->bLastIniPkt;
1072 entry->FirstSeg = 1;//first segment
1073 entry->LastSeg = 1; //last segment
1074 if(tcb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1075 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1076 } else {
1077 entry->CmdInit = DESC_PACKET_TYPE_NORMAL;
1078 entry->Offset = sizeof(TX_FWINFO_8190PCI) + 8;
1079 entry->PktSize = (u16)(tcb_desc->pkt_size + entry->Offset);
1080 entry->QueueSelect = QSLT_CMD;
1081 entry->TxFWInfoSize = 0x08;
1082 entry->RATid = (u8)DESC_PACKET_TYPE_INIT;
1083 }
1084 entry->TxBufferSize = skb->len;
1085 entry->TxBuffAddr = cpu_to_le32(mapping);
1086 entry->OWN = 1;
1087
ecdfa446
GKH		 1088 __skb_queue_tail(&ring->queue, skb);
1089 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
1090
3f9ab1ee 1091 write_nic_byte(priv, TPPoll, TPPoll_CQ);
ecdfa446
GKH		 1092
1093 return;
1094}
1095
1096/*
1097 * Mapping Software/Hardware descriptor queue id to "Queue Select Field"
1098 * in TxFwInfo data structure
214985a6 1099 */
5e1ad18a 1100static u8 MapHwQueueToFirmwareQueue(u8 QueueID)
ecdfa446 1101{
f72b6a50 1102 u8 QueueSelect = 0;
ecdfa446 1103
f72b6a50
MM		 1104 switch (QueueID) {
1105 case BE_QUEUE:
1106 QueueSelect = QSLT_BE;
1107 break;
ecdfa446 1108
f72b6a50
MM		 1109 case BK_QUEUE:
1110 QueueSelect = QSLT_BK;
1111 break;
ecdfa446 1112
f72b6a50
MM		 1113 case VO_QUEUE:
1114 QueueSelect = QSLT_VO;
1115 break;
ecdfa446 1116
f72b6a50
MM		 1117 case VI_QUEUE:
1118 QueueSelect = QSLT_VI;
1119 break;
ecdfa446 1120
f72b6a50
MM		 1121 case MGNT_QUEUE:
1122 QueueSelect = QSLT_MGNT;
1123 break;
ecdfa446 1124
f72b6a50
MM		 1125 case BEACON_QUEUE:
1126 QueueSelect = QSLT_BEACON;
1127 break;
ecdfa446 1128
f72b6a50
MM		 1129 case TXCMD_QUEUE:
1130 QueueSelect = QSLT_CMD;
1131 break;
1132
1133 case HIGH_QUEUE:
1134 default:
1135 RT_TRACE(COMP_ERR, "Impossible Queue Selection: %d\n", QueueID);
1136 break;
ecdfa446
GKH		 1137 }
1138 return QueueSelect;
1139}
1140
5e1ad18a 1141static u8 MRateToHwRate8190Pci(u8 rate)
ecdfa446
GKH		 1142{
1143 u8 ret = DESC90_RATE1M;
1144
1145 switch(rate) {
1146 case MGN_1M: ret = DESC90_RATE1M; break;
1147 case MGN_2M: ret = DESC90_RATE2M; break;
1148 case MGN_5_5M: ret = DESC90_RATE5_5M; break;
1149 case MGN_11M: ret = DESC90_RATE11M; break;
1150 case MGN_6M: ret = DESC90_RATE6M; break;
1151 case MGN_9M: ret = DESC90_RATE9M; break;
1152 case MGN_12M: ret = DESC90_RATE12M; break;
1153 case MGN_18M: ret = DESC90_RATE18M; break;
1154 case MGN_24M: ret = DESC90_RATE24M; break;
1155 case MGN_36M: ret = DESC90_RATE36M; break;
1156 case MGN_48M: ret = DESC90_RATE48M; break;
1157 case MGN_54M: ret = DESC90_RATE54M; break;
1158
1159 // HT rate since here
1160 case MGN_MCS0: ret = DESC90_RATEMCS0; break;
1161 case MGN_MCS1: ret = DESC90_RATEMCS1; break;
1162 case MGN_MCS2: ret = DESC90_RATEMCS2; break;
1163 case MGN_MCS3: ret = DESC90_RATEMCS3; break;
1164 case MGN_MCS4: ret = DESC90_RATEMCS4; break;
1165 case MGN_MCS5: ret = DESC90_RATEMCS5; break;
1166 case MGN_MCS6: ret = DESC90_RATEMCS6; break;
1167 case MGN_MCS7: ret = DESC90_RATEMCS7; break;
1168 case MGN_MCS8: ret = DESC90_RATEMCS8; break;
1169 case MGN_MCS9: ret = DESC90_RATEMCS9; break;
1170 case MGN_MCS10: ret = DESC90_RATEMCS10; break;
1171 case MGN_MCS11: ret = DESC90_RATEMCS11; break;
1172 case MGN_MCS12: ret = DESC90_RATEMCS12; break;
1173 case MGN_MCS13: ret = DESC90_RATEMCS13; break;
1174 case MGN_MCS14: ret = DESC90_RATEMCS14; break;
1175 case MGN_MCS15: ret = DESC90_RATEMCS15; break;
1176 case (0x80|0x20): ret = DESC90_RATEMCS32; break;
1177
1178 default: break;
1179 }
1180 return ret;
1181}
1182
1183
5e1ad18a 1184static u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc)
ecdfa446
GKH		 1185{
1186 u8 tmp_Short;
1187
1188 tmp_Short = (TxHT==1)?((tcb_desc->bUseShortGI)?1:0):((tcb_desc->bUseShortPreamble)?1:0);
1189
1190 if(TxHT==1 && TxRate != DESC90_RATEMCS15)
1191 tmp_Short = 0;
1192
1193 return tmp_Short;
1194}
1195
1196/*
1197 * The tx procedure is just as following,
1198 * skb->cb will contain all the following information,
1199 * priority, morefrag, rate, &dev.
214985a6 1200 */
af59c39d 1201static short rtl8192_tx(struct r8192_priv *priv, struct sk_buff* skb)
ecdfa446 1202{
067ba6cf
MM		 1203 struct rtl8192_tx_ring *ring;
1204 unsigned long flags;
1205 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
1206 tx_desc_819x_pci *pdesc = NULL;
1207 TX_FWINFO_8190PCI *pTxFwInfo = NULL;
1208 dma_addr_t mapping;
1209 bool multi_addr = false, broad_addr = false, uni_addr = false;
1210 u8 *pda_addr = NULL;
1211 int idx;
1212
1213 if (priv->bdisable_nic) {
1214 RT_TRACE(COMP_ERR, "Nic is disabled! Can't tx packet len=%d qidx=%d!!!\n",
1215 skb->len, tcb_desc->queue_index);
65a43784 1216 return skb->len;
067ba6cf 1217 }
65a43784 1218
1219#ifdef ENABLE_LPS
1220 priv->ieee80211->bAwakePktSent = true;
1221#endif
1222
067ba6cf
MM		 1223 mapping = pci_map_single(priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
1224
1225 /* collect the tx packets statitcs */
1226 pda_addr = ((u8 *)skb->data) + sizeof(TX_FWINFO_8190PCI);
1227 if (is_multicast_ether_addr(pda_addr))
1228 multi_addr = true;
1229 else if (is_broadcast_ether_addr(pda_addr))
1230 broad_addr = true;
1231 else
1232 uni_addr = true;
1233
1234 if (uni_addr)
1235 priv->stats.txbytesunicast += (u8)(skb->len) - sizeof(TX_FWINFO_8190PCI);
067ba6cf
MM		 1236
1237 /* fill tx firmware */
1238 pTxFwInfo = (PTX_FWINFO_8190PCI)skb->data;
1239 memset(pTxFwInfo, 0, sizeof(TX_FWINFO_8190PCI));
1240 pTxFwInfo->TxHT = (tcb_desc->data_rate&0x80) ? 1 : 0;
1241 pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)tcb_desc->data_rate);
1242 pTxFwInfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
1243 pTxFwInfo->Short = QueryIsShort(pTxFwInfo->TxHT, pTxFwInfo->TxRate, tcb_desc);
1244
1245 /* Aggregation related */
1246 if (tcb_desc->bAMPDUEnable) {
1247 pTxFwInfo->AllowAggregation = 1;
1248 pTxFwInfo->RxMF = tcb_desc->ampdu_factor;
1249 pTxFwInfo->RxAMD = tcb_desc->ampdu_density;
1250 } else {
1251 pTxFwInfo->AllowAggregation = 0;
1252 pTxFwInfo->RxMF = 0;
1253 pTxFwInfo->RxAMD = 0;
1254 }
ecdfa446 1255
067ba6cf
MM		 1256 /* Protection mode related */
1257 pTxFwInfo->RtsEnable = (tcb_desc->bRTSEnable) ? 1 : 0;
1258 pTxFwInfo->CtsEnable = (tcb_desc->bCTSEnable) ? 1 : 0;
1259 pTxFwInfo->RtsSTBC = (tcb_desc->bRTSSTBC) ? 1 : 0;
1260 pTxFwInfo->RtsHT = (tcb_desc->rts_rate&0x80) ? 1 : 0;
1261 pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
1262 pTxFwInfo->RtsBandwidth = 0;
1263 pTxFwInfo->RtsSubcarrier = tcb_desc->RTSSC;
1264 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ? (tcb_desc->bRTSUseShortPreamble ? 1 : 0) : (tcb_desc->bRTSUseShortGI? 1 : 0);
1265
1266 /* Set Bandwidth and sub-channel settings. */
1267 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1268 if (tcb_desc->bPacketBW) {
1269 pTxFwInfo->TxBandwidth = 1;
067ba6cf
MM		 1270 /* use duplicated mode */
1271 pTxFwInfo->TxSubCarrier = 0;
067ba6cf
MM		 1272 } else {
1273 pTxFwInfo->TxBandwidth = 0;
1274 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1275 }
1276 } else {
1277 pTxFwInfo->TxBandwidth = 0;
1278 pTxFwInfo->TxSubCarrier = 0;
1279 }
ecdfa446 1280
067ba6cf
MM		 1281 spin_lock_irqsave(&priv->irq_th_lock, flags);
1282 ring = &priv->tx_ring[tcb_desc->queue_index];
1283 if (tcb_desc->queue_index != BEACON_QUEUE)
1284 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
1285 else
1286 idx = 0;
1287
1288 pdesc = &ring->desc[idx];
1289 if ((pdesc->OWN == 1) && (tcb_desc->queue_index != BEACON_QUEUE)) {
703fdcc3 1290 RT_TRACE(COMP_ERR, "No more TX desc@%d, ring->idx = %d,idx = %d,%x\n",
067ba6cf
MM		 1291 tcb_desc->queue_index, ring->idx, idx, skb->len);
1292 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
1293 return skb->len;
1294 }
ecdfa446 1295
067ba6cf
MM		 1296 /* fill tx descriptor */
1297 memset(pdesc, 0, 12);
1298
1299 /*DWORD 0*/
1300 pdesc->LINIP = 0;
1301 pdesc->CmdInit = 1;
1302 pdesc->Offset = sizeof(TX_FWINFO_8190PCI) + 8; /* We must add 8!! */
1303 pdesc->PktSize = (u16)skb->len-sizeof(TX_FWINFO_8190PCI);
1304
1305 /*DWORD 1*/
1306 pdesc->SecCAMID = 0;
1307 pdesc->RATid = tcb_desc->RATRIndex;
1308
1309 pdesc->NoEnc = 1;
1310 pdesc->SecType = 0x0;
1311 if (tcb_desc->bHwSec) {
1312 switch (priv->ieee80211->pairwise_key_type) {
1313 case KEY_TYPE_WEP40:
1314 case KEY_TYPE_WEP104:
1315 pdesc->SecType = 0x1;
1316 pdesc->NoEnc = 0;
1317 break;
1318 case KEY_TYPE_TKIP:
1319 pdesc->SecType = 0x2;
1320 pdesc->NoEnc = 0;
1321 break;
1322 case KEY_TYPE_CCMP:
1323 pdesc->SecType = 0x3;
1324 pdesc->NoEnc = 0;
1325 break;
1326 case KEY_TYPE_NA:
1327 pdesc->SecType = 0x0;
1328 pdesc->NoEnc = 1;
1329 break;
1330 }
1331 }
ecdfa446 1332
067ba6cf
MM		 1333 /* Set Packet ID */
1334 pdesc->PktId = 0x0;
ecdfa446 1335
067ba6cf
MM		 1336 pdesc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
1337 pdesc->TxFWInfoSize = sizeof(TX_FWINFO_8190PCI);
ecdfa446 1338
067ba6cf
MM		 1339 pdesc->DISFB = tcb_desc->bTxDisableRateFallBack;
1340 pdesc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
ecdfa446 1341
067ba6cf
MM		 1342 pdesc->FirstSeg = 1;
1343 pdesc->LastSeg = 1;
1344 pdesc->TxBufferSize = skb->len;
ecdfa446 1345
067ba6cf
MM		 1346 pdesc->TxBuffAddr = cpu_to_le32(mapping);
1347 __skb_queue_tail(&ring->queue, skb);
1348 pdesc->OWN = 1;
1349 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
af59c39d 1350 priv->ieee80211->dev->trans_start = jiffies;
3f9ab1ee 1351 write_nic_word(priv, TPPoll, 0x01<<tcb_desc->queue_index);
067ba6cf 1352 return 0;
ecdfa446
GKH		 1353}
1354
af59c39d 1355static short rtl8192_alloc_rx_desc_ring(struct r8192_priv *priv)
ecdfa446 1356{
ecdfa446
GKH		 1357 rx_desc_819x_pci *entry = NULL;
1358 int i;
1359
1360 priv->rx_ring = pci_alloc_consistent(priv->pdev,
1361 sizeof(*priv->rx_ring) * priv->rxringcount, &priv->rx_ring_dma);
1362
1363 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
1364 RT_TRACE(COMP_ERR,"Cannot allocate RX ring\n");
1365 return -ENOMEM;
1366 }
1367
1368 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * priv->rxringcount);
1369 priv->rx_idx = 0;
1370
1371 for (i = 0; i < priv->rxringcount; i++) {
1372 struct sk_buff *skb = dev_alloc_skb(priv->rxbuffersize);
1373 dma_addr_t *mapping;
1374 entry = &priv->rx_ring[i];
1375 if (!skb)
1376 return 0;
1377 priv->rx_buf[i] = skb;
1378 mapping = (dma_addr_t *)skb->cb;
1c7ec2e8 1379 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
ecdfa446
GKH		 1380 priv->rxbuffersize, PCI_DMA_FROMDEVICE);
1381
1382 entry->BufferAddress = cpu_to_le32(*mapping);
1383
1384 entry->Length = priv->rxbuffersize;
1385 entry->OWN = 1;
1386 }
1387
1388 entry->EOR = 1;
1389 return 0;
1390}
1391
af59c39d 1392static int rtl8192_alloc_tx_desc_ring(struct r8192_priv *priv,
ecdfa446
GKH		 1393 unsigned int prio, unsigned int entries)
1394{
ecdfa446
GKH		 1395 tx_desc_819x_pci *ring;
1396 dma_addr_t dma;
1397 int i;
1398
1399 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
1400 if (!ring || (unsigned long)ring & 0xFF) {
1401 RT_TRACE(COMP_ERR, "Cannot allocate TX ring (prio = %d)\n", prio);
1402 return -ENOMEM;
1403 }
1404
1405 memset(ring, 0, sizeof(*ring)*entries);
1406 priv->tx_ring[prio].desc = ring;
1407 priv->tx_ring[prio].dma = dma;
1408 priv->tx_ring[prio].idx = 0;
1409 priv->tx_ring[prio].entries = entries;
1410 skb_queue_head_init(&priv->tx_ring[prio].queue);
1411
1412 for (i = 0; i < entries; i++)
1413 ring[i].NextDescAddress =
1414 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
1415
1416 return 0;
1417}
1418
af59c39d 1419static short rtl8192_pci_initdescring(struct r8192_priv *priv)
ecdfa446 1420{
1f1f19ff
MM		 1421 u32 ret;
1422 int i;
ecdfa446 1423
af59c39d 1424 ret = rtl8192_alloc_rx_desc_ring(priv);
1f1f19ff
MM		 1425 if (ret)
1426 return ret;
ecdfa446 1427
1f1f19ff
MM		 1428 /* general process for other queue */
1429 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) {
af59c39d 1430 ret = rtl8192_alloc_tx_desc_ring(priv, i, priv->txringcount);
1f1f19ff
MM		 1431 if (ret)
1432 goto err_free_rings;
1433 }
ecdfa446 1434
1f1f19ff 1435 return 0;
ecdfa446
GKH		 1436
1437err_free_rings:
af59c39d 1438 rtl8192_free_rx_ring(priv);
1f1f19ff
MM		 1439 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
1440 if (priv->tx_ring[i].desc)
af59c39d 1441 rtl8192_free_tx_ring(priv, i);
1f1f19ff 1442 return 1;
ecdfa446
GKH		 1443}
1444
480ab9dc 1445static void rtl8192_pci_resetdescring(struct r8192_priv *priv)
ecdfa446 1446{
ecdfa446
GKH		 1447 int i;
1448
1449 /* force the rx_idx to the first one */
1450 if(priv->rx_ring) {
1451 rx_desc_819x_pci *entry = NULL;
1452 for (i = 0; i < priv->rxringcount; i++) {
1453 entry = &priv->rx_ring[i];
1454 entry->OWN = 1;
1455 }
1456 priv->rx_idx = 0;
1457 }
1458
1459 /* after reset, release previous pending packet, and force the
1460 * tx idx to the first one */
1461 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) {
1462 if (priv->tx_ring[i].desc) {
1463 struct rtl8192_tx_ring *ring = &priv->tx_ring[i];
1464
1465 while (skb_queue_len(&ring->queue)) {
1466 tx_desc_819x_pci *entry = &ring->desc[ring->idx];
1467 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1468
1469 pci_unmap_single(priv->pdev, le32_to_cpu(entry->TxBuffAddr),
1470 skb->len, PCI_DMA_TODEVICE);
1471 kfree_skb(skb);
1472 ring->idx = (ring->idx + 1) % ring->entries;
1473 }
1474 ring->idx = 0;
1475 }
1476 }
1477}
1478
5e1ad18a 1479static void rtl8192_link_change(struct net_device *dev)
ecdfa446 1480{
ecdfa446
GKH		 1481 struct r8192_priv *priv = ieee80211_priv(dev);
1482 struct ieee80211_device* ieee = priv->ieee80211;
11a861d9 1483
ecdfa446
GKH		 1484 if (ieee->state == IEEE80211_LINKED)
1485 {
480ab9dc
MM		 1486 rtl8192_net_update(priv);
1487 rtl8192_update_ratr_table(priv);
11aacc28 1488
ecdfa446
GKH		 1489 //add this as in pure N mode, wep encryption will use software way, but there is no chance to set this as wep will not set group key in wext. WB.2008.07.08
1490 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
282fa9f3 1491 EnableHWSecurityConfig8192(priv);
ecdfa446
GKH		 1492 }
1493 else
1494 {
3f9ab1ee 1495 write_nic_byte(priv, 0x173, 0);
ecdfa446 1496 }
11a861d9 1497
480ab9dc 1498 rtl8192_update_msr(priv);
ecdfa446
GKH		 1499
1500 // 2007/10/16 MH MAC Will update TSF according to all received beacon, so we have
1501 // // To set CBSSID bit when link with any AP or STA.
1502 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC)
1503 {
1504 u32 reg = 0;
3f9ab1ee 1505 reg = read_nic_dword(priv, RCR);
ecdfa446
GKH		 1506 if (priv->ieee80211->state == IEEE80211_LINKED)
1507 priv->ReceiveConfig = reg |= RCR_CBSSID;
1508 else
1509 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
3f9ab1ee 1510 write_nic_dword(priv, RCR, reg);
ecdfa446
GKH		 1511 }
1512}
ecdfa446
GKH		 1513
1514
5b3b1a7b 1515static const struct ieee80211_qos_parameters def_qos_parameters = {
ecdfa446
GKH		 1516 {3,3,3,3},/* cw_min */
1517 {7,7,7,7},/* cw_max */
1518 {2,2,2,2},/* aifs */
1519 {0,0,0,0},/* flags */
1520 {0,0,0,0} /* tx_op_limit */
1521};
1522
5e1ad18a 1523static void rtl8192_update_beacon(struct work_struct * work)
ecdfa446
GKH		 1524{
1525 struct r8192_priv *priv = container_of(work, struct r8192_priv, update_beacon_wq.work);
ecdfa446
GKH		 1526 struct ieee80211_device* ieee = priv->ieee80211;
1527 struct ieee80211_network* net = &ieee->current_network;
1528
1529 if (ieee->pHTInfo->bCurrentHTSupport)
1530 HTUpdateSelfAndPeerSetting(ieee, net);
1531 ieee->pHTInfo->bCurrentRT2RTLongSlotTime = net->bssht.bdRT2RTLongSlotTime;
480ab9dc 1532 rtl8192_update_cap(priv, net->capability);
ecdfa446 1533}
214985a6 1534
ecdfa446
GKH		 1535/*
1536* background support to run QoS activate functionality
1537*/
881a975b 1538static const int WDCAPARA_ADD[] = {EDCAPARA_BE,EDCAPARA_BK,EDCAPARA_VI,EDCAPARA_VO};
5e1ad18a 1539static void rtl8192_qos_activate(struct work_struct * work)
ecdfa446
GKH		 1540{
1541 struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate);
ecdfa446
GKH		 1542 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
1543 u8 mode = priv->ieee80211->current_network.mode;
ecdfa446
GKH		 1544 u8 u1bAIFS;
1545 u32 u4bAcParam;
1546 int i;
ecdfa446 1547
ecdfa446 1548 mutex_lock(&priv->mutex);
ecdfa446
GKH		 1549 if(priv->ieee80211->state != IEEE80211_LINKED)
1550 goto success;
1551 RT_TRACE(COMP_QOS,"qos active process with associate response received\n");
1552 /* It better set slot time at first */
1553 /* For we just support b/g mode at present, let the slot time at 9/20 selection */
1554 /* update the ac parameter to related registers */
1555 for(i = 0; i < QOS_QUEUE_NUM; i++) {
1556 //Mode G/A: slotTimeTimer = 9; Mode B: 20
1557 u1bAIFS = qos_parameters->aifs[i] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
1558 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[i]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
1559 (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)|
1560 (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)|
1561 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
3f9ab1ee 1562 write_nic_dword(priv, WDCAPARA_ADD[i], u4bAcParam);
ecdfa446
GKH		 1563 }
1564
1565success:
ecdfa446 1566 mutex_unlock(&priv->mutex);
ecdfa446
GKH		 1567}
1568
1569static int rtl8192_qos_handle_probe_response(struct r8192_priv *priv,
1570 int active_network,
1571 struct ieee80211_network *network)
1572{
1573 int ret = 0;
1574 u32 size = sizeof(struct ieee80211_qos_parameters);
1575
1576 if(priv->ieee80211->state !=IEEE80211_LINKED)
1577 return ret;
1578
1579 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
1580 return ret;
1581
1582 if (network->flags & NETWORK_HAS_QOS_MASK) {
1583 if (active_network &&
1584 (network->flags & NETWORK_HAS_QOS_PARAMETERS))
1585 network->qos_data.active = network->qos_data.supported;
1586
1587 if ((network->qos_data.active == 1) && (active_network == 1) &&
1588 (network->flags & NETWORK_HAS_QOS_PARAMETERS) &&
1589 (network->qos_data.old_param_count !=
1590 network->qos_data.param_count)) {
1591 network->qos_data.old_param_count =
1592 network->qos_data.param_count;
ecdfa446 1593 queue_work(priv->priv_wq, &priv->qos_activate);
ecdfa446
GKH		 1594 RT_TRACE (COMP_QOS, "QoS parameters change call "
1595 "qos_activate\n");
1596 }
1597 } else {
207b58fb 1598 memcpy(&priv->ieee80211->current_network.qos_data.parameters,
ecdfa446
GKH		 1599 &def_qos_parameters, size);
1600
1601 if ((network->qos_data.active == 1) && (active_network == 1)) {
ecdfa446 1602 queue_work(priv->priv_wq, &priv->qos_activate);
703fdcc3 1603 RT_TRACE(COMP_QOS, "QoS was disabled call qos_activate\n");
ecdfa446
GKH		 1604 }
1605 network->qos_data.active = 0;
1606 network->qos_data.supported = 0;
1607 }
1608
1609 return 0;
1610}
1611
1612/* handle manage frame frame beacon and probe response */
1613static int rtl8192_handle_beacon(struct net_device * dev,
1614 struct ieee80211_beacon * beacon,
1615 struct ieee80211_network * network)
1616{
1617 struct r8192_priv *priv = ieee80211_priv(dev);
1618
1619 rtl8192_qos_handle_probe_response(priv,1,network);
1620
ecdfa446 1621 queue_delayed_work(priv->priv_wq, &priv->update_beacon_wq, 0);
ecdfa446
GKH		 1622 return 0;
1623
1624}
1625
1626/*
214985a6
MM		 1627 * handling the beaconing responses. if we get different QoS setting
1628 * off the network from the associated setting, adjust the QoS setting
1629 */
ecdfa446
GKH		 1630static int rtl8192_qos_association_resp(struct r8192_priv *priv,
1631 struct ieee80211_network *network)
1632{
b72cb94f
MM		 1633 int ret = 0;
1634 unsigned long flags;
1635 u32 size = sizeof(struct ieee80211_qos_parameters);
1636 int set_qos_param = 0;
ecdfa446 1637
b72cb94f
MM		 1638 if ((priv == NULL) || (network == NULL))
1639 return ret;
ecdfa446 1640
b72cb94f
MM		 1641 if (priv->ieee80211->state != IEEE80211_LINKED)
1642 return ret;
ecdfa446 1643
b72cb94f
MM		 1644 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
1645 return ret;
ecdfa446 1646
b72cb94f
MM		 1647 spin_lock_irqsave(&priv->ieee80211->lock, flags);
1648 if (network->flags & NETWORK_HAS_QOS_PARAMETERS) {
207b58fb
MM		 1649 memcpy(&priv->ieee80211->current_network.qos_data.parameters,
1650 &network->qos_data.parameters,
ecdfa446
GKH		 1651 sizeof(struct ieee80211_qos_parameters));
1652 priv->ieee80211->current_network.qos_data.active = 1;
b72cb94f
MM		 1653 set_qos_param = 1;
1654 /* update qos parameter for current network */
1655 priv->ieee80211->current_network.qos_data.old_param_count =
1656 priv->ieee80211->current_network.qos_data.param_count;
1657 priv->ieee80211->current_network.qos_data.param_count =
1658 network->qos_data.param_count;
1659
1660 } else {
207b58fb 1661 memcpy(&priv->ieee80211->current_network.qos_data.parameters,
ecdfa446
GKH		 1662 &def_qos_parameters, size);
1663 priv->ieee80211->current_network.qos_data.active = 0;
1664 priv->ieee80211->current_network.qos_data.supported = 0;
b72cb94f
MM		 1665 set_qos_param = 1;
1666 }
ecdfa446 1667
b72cb94f 1668 spin_unlock_irqrestore(&priv->ieee80211->lock, flags);
ecdfa446 1669
b72cb94f
MM		 1670 RT_TRACE(COMP_QOS, "%s: network->flags = %d,%d\n", __FUNCTION__,
1671 network->flags, priv->ieee80211->current_network.qos_data.active);
ecdfa446 1672 if (set_qos_param == 1)
ecdfa446 1673 queue_work(priv->priv_wq, &priv->qos_activate);
ecdfa446 1674
b72cb94f 1675 return ret;
ecdfa446
GKH		 1676}
1677
1678
1679static int rtl8192_handle_assoc_response(struct net_device *dev,
1680 struct ieee80211_assoc_response_frame *resp,
1681 struct ieee80211_network *network)
1682{
1683 struct r8192_priv *priv = ieee80211_priv(dev);
1684 rtl8192_qos_association_resp(priv, network);
1685 return 0;
1686}
1687
1688
214985a6 1689/* updateRATRTabel for MCS only. Basic rate is not implemented. */
480ab9dc 1690static void rtl8192_update_ratr_table(struct r8192_priv* priv)
ecdfa446 1691{
ecdfa446
GKH		 1692 struct ieee80211_device* ieee = priv->ieee80211;
1693 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
ecdfa446
GKH		 1694 u32 ratr_value = 0;
1695 u8 rate_index = 0;
1696
480ab9dc 1697 rtl8192_config_rate(priv, (u16*)(&ratr_value));
ecdfa446 1698 ratr_value |= (*(u16*)(pMcsRate)) << 12;
16d74da0 1699
ecdfa446
GKH		 1700 switch (ieee->mode)
1701 {
1702 case IEEE_A:
1703 ratr_value &= 0x00000FF0;
1704 break;
1705 case IEEE_B:
1706 ratr_value &= 0x0000000F;
1707 break;
1708 case IEEE_G:
1709 ratr_value &= 0x00000FF7;
1710 break;
1711 case IEEE_N_24G:
1712 case IEEE_N_5G:
1713 if (ieee->pHTInfo->PeerMimoPs == 0) //MIMO_PS_STATIC
1714 ratr_value &= 0x0007F007;
1715 else{
1716 if (priv->rf_type == RF_1T2R)
1717 ratr_value &= 0x000FF007;
1718 else
1719 ratr_value &= 0x0F81F007;
1720 }
1721 break;
1722 default:
1723 break;
1724 }
1725 ratr_value &= 0x0FFFFFFF;
1726 if(ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI40MHz){
1727 ratr_value |= 0x80000000;
1728 }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){
1729 ratr_value |= 0x80000000;
1730 }
3f9ab1ee
MM		 1731 write_nic_dword(priv, RATR0+rate_index*4, ratr_value);
1732 write_nic_byte(priv, UFWP, 1);
ecdfa446
GKH		 1733}
1734
5e1ad18a 1735static bool GetNmodeSupportBySecCfg8190Pci(struct net_device*dev)
ecdfa446 1736{
65a43784 1737 struct r8192_priv *priv = ieee80211_priv(dev);
1738 struct ieee80211_device *ieee = priv->ieee80211;
ecdfa446 1739
f8acdc3d
MM		 1740 return !(ieee->rtllib_ap_sec_type &&
1741 (ieee->rtllib_ap_sec_type(ieee)&(SEC_ALG_WEP|SEC_ALG_TKIP)));
ecdfa446
GKH		 1742}
1743
5e1ad18a 1744static void rtl8192_refresh_supportrate(struct r8192_priv* priv)
ecdfa446
GKH		 1745{
1746 struct ieee80211_device* ieee = priv->ieee80211;
1747 //we donot consider set support rate for ABG mode, only HT MCS rate is set here.
1748 if (ieee->mode == WIRELESS_MODE_N_24G || ieee->mode == WIRELESS_MODE_N_5G)
1749 {
1750 memcpy(ieee->Regdot11HTOperationalRateSet, ieee->RegHTSuppRateSet, 16);
ecdfa446
GKH		 1751 }
1752 else
1753 memset(ieee->Regdot11HTOperationalRateSet, 0, 16);
ecdfa446
GKH		 1754}
1755
af59c39d 1756static u8 rtl8192_getSupportedWireleeMode(void)
ecdfa446 1757{
6f304eb2 1758 return (WIRELESS_MODE_N_24G|WIRELESS_MODE_G|WIRELESS_MODE_B);
ecdfa446 1759}
5e1ad18a
GKH		 1760
1761static void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode)
ecdfa446
GKH		 1762{
1763 struct r8192_priv *priv = ieee80211_priv(dev);
af59c39d 1764 u8 bSupportMode = rtl8192_getSupportedWireleeMode();
ecdfa446 1765
ecdfa446
GKH		 1766 if ((wireless_mode == WIRELESS_MODE_AUTO) || ((wireless_mode&bSupportMode)==0))
1767 {
1768 if(bSupportMode & WIRELESS_MODE_N_24G)
1769 {
1770 wireless_mode = WIRELESS_MODE_N_24G;
1771 }
1772 else if(bSupportMode & WIRELESS_MODE_N_5G)
1773 {
1774 wireless_mode = WIRELESS_MODE_N_5G;
1775 }
1776 else if((bSupportMode & WIRELESS_MODE_A))
1777 {
1778 wireless_mode = WIRELESS_MODE_A;
1779 }
1780 else if((bSupportMode & WIRELESS_MODE_G))
1781 {
1782 wireless_mode = WIRELESS_MODE_G;
1783 }
1784 else if((bSupportMode & WIRELESS_MODE_B))
1785 {
1786 wireless_mode = WIRELESS_MODE_B;
1787 }
1788 else{
1789 RT_TRACE(COMP_ERR, "%s(), No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n", __FUNCTION__,bSupportMode);
1790 wireless_mode = WIRELESS_MODE_B;
1791 }
1792 }
ecdfa446
GKH		 1793 priv->ieee80211->mode = wireless_mode;
1794
1795 if ((wireless_mode == WIRELESS_MODE_N_24G) || (wireless_mode == WIRELESS_MODE_N_5G))
1796 priv->ieee80211->pHTInfo->bEnableHT = 1;
1797 else
1798 priv->ieee80211->pHTInfo->bEnableHT = 0;
1799 RT_TRACE(COMP_INIT, "Current Wireless Mode is %x\n", wireless_mode);
1800 rtl8192_refresh_supportrate(priv);
ecdfa446 1801}
ecdfa446 1802
5e1ad18a 1803static bool GetHalfNmodeSupportByAPs819xPci(struct net_device* dev)
ecdfa446 1804{
ecdfa446
GKH		 1805 struct r8192_priv* priv = ieee80211_priv(dev);
1806 struct ieee80211_device* ieee = priv->ieee80211;
1807
285f660c 1808 return ieee->bHalfWirelessN24GMode;
ecdfa446
GKH		 1809}
1810
9f17b076 1811static short rtl8192_is_tx_queue_empty(struct net_device *dev)
ecdfa446
GKH		 1812{
1813 int i=0;
1814 struct r8192_priv *priv = ieee80211_priv(dev);
1815 for (i=0; i<=MGNT_QUEUE; i++)
1816 {
1817 if ((i== TXCMD_QUEUE) || (i == HCCA_QUEUE) )
1818 continue;
1819 if (skb_queue_len(&(&priv->tx_ring[i])->queue) > 0){
1820 printk("===>tx queue is not empty:%d, %d\n", i, skb_queue_len(&(&priv->tx_ring[i])->queue));
1821 return 0;
1822 }
1823 }
1824 return 1;
1825}
16d74da0 1826
176e8dc1 1827static void rtl8192_hw_sleep_down(struct r8192_priv *priv)
ecdfa446 1828{
262cd816 1829 MgntActSet_RF_State(priv, eRfSleep, RF_CHANGE_BY_PS);
ecdfa446 1830}
16d74da0 1831
5e1ad18a 1832static void rtl8192_hw_wakeup(struct net_device* dev)
ecdfa446 1833{
262cd816
MM		 1834 struct r8192_priv *priv = ieee80211_priv(dev);
1835 MgntActSet_RF_State(priv, eRfOn, RF_CHANGE_BY_PS);
ecdfa446 1836}
65a43784 1837
9f17b076 1838static void rtl8192_hw_wakeup_wq (struct work_struct *work)
ecdfa446 1839{
ecdfa446
GKH		 1840 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1841 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
1842 struct net_device *dev = ieee->dev;
ecdfa446
GKH		 1843 rtl8192_hw_wakeup(dev);
1844
1845}
1846
1847#define MIN_SLEEP_TIME 50
1848#define MAX_SLEEP_TIME 10000
5e1ad18a 1849static void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl)
ecdfa446 1850{
ecdfa446 1851 struct r8192_priv *priv = ieee80211_priv(dev);
9236928f 1852 u32 tmp;
ecdfa446 1853 u32 rb = jiffies;
ecdfa446 1854
65a43784 1855 // Writing HW register with 0 equals to disable
1856 // the timer, that is not really what we want
1857 //
1858 tl -= MSECS(8+16+7);
ecdfa446 1859
65a43784 1860 // If the interval in witch we are requested to sleep is too
1861 // short then give up and remain awake
1862 // when we sleep after send null frame, the timer will be too short to sleep.
1863 //
ecdfa446 1864 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
65a43784 1865 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
65a43784 1866 printk("too short to sleep::%x, %x, %lx\n",tl, rb, MSECS(MIN_SLEEP_TIME));
0d65112a 1867 return;
ecdfa446
GKH		 1868 }
1869
ecdfa446 1870 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
65a43784 1871 ((tl < rb) && (tl>MSECS(69)) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))||
1872 ((tl<rb)&&(tl<MSECS(69))&&((tl+0xffffffff-rb)>MSECS(MAX_SLEEP_TIME)))) {
ecdfa446 1873 printk("========>too long to sleep:%x, %x, %lx\n", tl, rb, MSECS(MAX_SLEEP_TIME));
0d65112a 1874 return;
65a43784 1875 }
9236928f
MM		 1876
1877 tmp = (tl>rb)?(tl-rb):(rb-tl);
65a43784 1878 queue_delayed_work(priv->ieee80211->wq,
9236928f 1879 &priv->ieee80211->hw_wakeup_wq,tmp);
65a43784 1880
176e8dc1 1881 rtl8192_hw_sleep_down(priv);
ecdfa446 1882}
214985a6 1883
af59c39d 1884static void rtl8192_init_priv_variable(struct r8192_priv *priv)
ecdfa446 1885{
ecdfa446 1886 u8 i;
31d664e5 1887 PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
65a43784 1888
1889 // Default Halt the NIC if RF is OFF.
1890 pPSC->RegRfPsLevel |= RT_RF_OFF_LEVL_HALT_NIC;
1891 pPSC->RegRfPsLevel |= RT_RF_OFF_LEVL_CLK_REQ;
1892 pPSC->RegRfPsLevel |= RT_RF_OFF_LEVL_ASPM;
1893 pPSC->RegRfPsLevel |= RT_RF_LPS_LEVEL_ASPM;
1894 pPSC->bLeisurePs = true;
774dee1c 1895 priv->ieee80211->RegMaxLPSAwakeIntvl = 5;
65a43784 1896 priv->bHwRadioOff = false;
1897
ecdfa446 1898 priv->being_init_adapter = false;
ecdfa446 1899 priv->txringcount = 64;//32;
ecdfa446
GKH		 1900 priv->rxbuffersize = 9100;//2048;//1024;
1901 priv->rxringcount = MAX_RX_COUNT;//64;
ecdfa446
GKH		 1902 priv->chan = 1; //set to channel 1
1903 priv->RegWirelessMode = WIRELESS_MODE_AUTO;
1904 priv->RegChannelPlan = 0xf;
ecdfa446
GKH		 1905 priv->ieee80211->mode = WIRELESS_MODE_AUTO; //SET AUTO
1906 priv->ieee80211->iw_mode = IW_MODE_INFRA;
1907 priv->ieee80211->ieee_up=0;
1908 priv->retry_rts = DEFAULT_RETRY_RTS;
1909 priv->retry_data = DEFAULT_RETRY_DATA;
1910 priv->ieee80211->rts = DEFAULT_RTS_THRESHOLD;
1911 priv->ieee80211->rate = 110; //11 mbps
1912 priv->ieee80211->short_slot = 1;
af59c39d 1913 priv->promisc = (priv->ieee80211->dev->flags & IFF_PROMISC) ? 1:0;
ecdfa446 1914 priv->bcck_in_ch14 = false;
ecdfa446
GKH		 1915 priv->CCKPresentAttentuation = 0;
1916 priv->rfa_txpowertrackingindex = 0;
1917 priv->rfc_txpowertrackingindex = 0;
1918 priv->CckPwEnl = 6;
ecdfa446
GKH		 1919 //added by amy for silent reset
1920 priv->ResetProgress = RESET_TYPE_NORESET;
1921 priv->bForcedSilentReset = 0;
1922 priv->bDisableNormalResetCheck = false;
1923 priv->force_reset = false;
1924 //added by amy for power save
181d1dff 1925 priv->RfOffReason = 0;
ecdfa446 1926 priv->bHwRfOffAction = 0;
31d664e5
MM		 1927 priv->PowerSaveControl.bInactivePs = true;
1928 priv->PowerSaveControl.bIPSModeBackup = false;
ecdfa446
GKH		 1929
1930 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
1931 priv->ieee80211->iw_mode = IW_MODE_INFRA;
1932 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
1933 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
1934 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;/* |
1935 IEEE_SOFTMAC_BEACONS;*///added by amy 080604 //| //IEEE_SOFTMAC_SINGLE_QUEUE;
1936
1937 priv->ieee80211->active_scan = 1;
1938 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION | IEEE80211_OFDM_MODULATION;
1939 priv->ieee80211->host_encrypt = 1;
1940 priv->ieee80211->host_decrypt = 1;
ecdfa446
GKH		 1941 priv->ieee80211->start_send_beacons = rtl8192_start_beacon;//+by david 081107
1942 priv->ieee80211->stop_send_beacons = rtl8192_stop_beacon;//+by david 081107
1943 priv->ieee80211->softmac_hard_start_xmit = rtl8192_hard_start_xmit;
1944 priv->ieee80211->set_chan = rtl8192_set_chan;
1945 priv->ieee80211->link_change = rtl8192_link_change;
1946 priv->ieee80211->softmac_data_hard_start_xmit = rtl8192_hard_data_xmit;
1947 priv->ieee80211->data_hard_stop = rtl8192_data_hard_stop;
1948 priv->ieee80211->data_hard_resume = rtl8192_data_hard_resume;
1949 priv->ieee80211->init_wmmparam_flag = 0;
1950 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
1951 priv->ieee80211->check_nic_enough_desc = check_nic_enough_desc;
1952 priv->ieee80211->tx_headroom = sizeof(TX_FWINFO_8190PCI);
1953 priv->ieee80211->qos_support = 1;
ecdfa446
GKH		 1954 priv->ieee80211->SetBWModeHandler = rtl8192_SetBWMode;
1955 priv->ieee80211->handle_assoc_response = rtl8192_handle_assoc_response;
1956 priv->ieee80211->handle_beacon = rtl8192_handle_beacon;
1957
1958 priv->ieee80211->sta_wake_up = rtl8192_hw_wakeup;
ecdfa446
GKH		 1959 priv->ieee80211->enter_sleep_state = rtl8192_hw_to_sleep;
1960 priv->ieee80211->ps_is_queue_empty = rtl8192_is_tx_queue_empty;
ecdfa446
GKH		 1961 priv->ieee80211->GetNmodeSupportBySecCfg = GetNmodeSupportBySecCfg8190Pci;
1962 priv->ieee80211->SetWirelessMode = rtl8192_SetWirelessMode;
1963 priv->ieee80211->GetHalfNmodeSupportByAPsHandler = GetHalfNmodeSupportByAPs819xPci;
1964
ecdfa446
GKH		 1965 priv->ieee80211->InitialGainHandler = InitialGain819xPci;
1966
65a43784 1967#ifdef ENABLE_IPS
1968 priv->ieee80211->ieee80211_ips_leave_wq = ieee80211_ips_leave_wq;
1969 priv->ieee80211->ieee80211_ips_leave = ieee80211_ips_leave;
1970#endif
1971#ifdef ENABLE_LPS
1972 priv->ieee80211->LeisurePSLeave = LeisurePSLeave;
16d74da0 1973#endif
65a43784 1974
1975 priv->ieee80211->SetHwRegHandler = rtl8192e_SetHwReg;
1976 priv->ieee80211->rtllib_ap_sec_type = rtl8192e_ap_sec_type;
1977
395aa640
MM		 1978 priv->ShortRetryLimit = 0x30;
1979 priv->LongRetryLimit = 0x30;
ecdfa446
GKH		 1980
1981 priv->ReceiveConfig = RCR_ADD3 |
1982 RCR_AMF | RCR_ADF | //accept management/data
1983 RCR_AICV | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
1984 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
1985 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
1986 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
1987
5b84cc78 1988 priv->pFirmware = vzalloc(sizeof(rt_firmware));
ecdfa446
GKH		 1989
1990 /* rx related queue */
ecdfa446
GKH		 1991 skb_queue_head_init(&priv->skb_queue);
1992
1993 /* Tx related queue */
1994 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
1995 skb_queue_head_init(&priv->ieee80211->skb_waitQ [i]);
1996 }
1997 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
1998 skb_queue_head_init(&priv->ieee80211->skb_aggQ [i]);
1999 }
2000 priv->rf_set_chan = rtl8192_phy_SwChnl;
2001}
2002
ecdfa446
GKH		 2003static void rtl8192_init_priv_lock(struct r8192_priv* priv)
2004{
ecdfa446
GKH		 2005 spin_lock_init(&priv->irq_th_lock);
2006 spin_lock_init(&priv->rf_ps_lock);
ecdfa446
GKH		 2007 sema_init(&priv->wx_sem,1);
2008 sema_init(&priv->rf_sem,1);
ecdfa446 2009 mutex_init(&priv->mutex);
ecdfa446
GKH		 2010}
2011
214985a6 2012/* init tasklet and wait_queue here */
ecdfa446 2013#define DRV_NAME "wlan0"
af59c39d 2014static void rtl8192_init_priv_task(struct r8192_priv *priv)
ecdfa446 2015{
ecdfa446 2016 priv->priv_wq = create_workqueue(DRV_NAME);
ecdfa446 2017
65a43784 2018#ifdef ENABLE_IPS
80a4dead 2019 INIT_WORK(&priv->ieee80211->ips_leave_wq, IPSLeave_wq);
65a43784 2020#endif
2021
ecdfa446 2022 INIT_WORK(&priv->reset_wq, rtl8192_restart);
ecdfa446
GKH		 2023 INIT_DELAYED_WORK(&priv->watch_dog_wq, rtl819x_watchdog_wqcallback);
2024 INIT_DELAYED_WORK(&priv->txpower_tracking_wq, dm_txpower_trackingcallback);
2025 INIT_DELAYED_WORK(&priv->rfpath_check_wq, dm_rf_pathcheck_workitemcallback);
2026 INIT_DELAYED_WORK(&priv->update_beacon_wq, rtl8192_update_beacon);
ecdfa446 2027 INIT_WORK(&priv->qos_activate, rtl8192_qos_activate);
80a4dead 2028 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq, rtl8192_hw_wakeup_wq);
ecdfa446 2029
80a4dead
MM		 2030 tasklet_init(&priv->irq_rx_tasklet, rtl8192_irq_rx_tasklet,
2031 (unsigned long) priv);
2032 tasklet_init(&priv->irq_tx_tasklet, rtl8192_irq_tx_tasklet,
2033 (unsigned long) priv);
2034 tasklet_init(&priv->irq_prepare_beacon_tasklet, rtl8192_prepare_beacon,
2035 (unsigned long) priv);
ecdfa446
GKH		 2036}
2037
af59c39d 2038static void rtl8192_get_eeprom_size(struct r8192_priv *priv)
ecdfa446
GKH		 2039{
2040 u16 curCR = 0;
ecdfa446 2041 RT_TRACE(COMP_INIT, "===========>%s()\n", __FUNCTION__);
3f9ab1ee 2042 curCR = read_nic_dword(priv, EPROM_CMD);
ecdfa446
GKH		 2043 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, curCR);
2044 //whether need I consider BIT5?
2045 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EPROM_93c56 : EPROM_93c46;
2046 RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __FUNCTION__, priv->epromtype);
2047}
2048
ecdfa446 2049/*
214985a6
MM		 2050 * Adapter->EEPROMAddressSize should be set before this function call.
2051 * EEPROM address size can be got through GetEEPROMSize8185()
2052 */
3f9ab1ee 2053static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
ecdfa446 2054{
3f9ab1ee 2055 struct net_device *dev = priv->ieee80211->dev;
ecdfa446 2056 u8 tempval;
ecdfa446 2057 u8 ICVer8192, ICVer8256;
ecdfa446
GKH		 2058 u16 i,usValue, IC_Version;
2059 u16 EEPROMId;
ecdfa446
GKH		 2060 u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
2061 RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
2062
2063
2064 // TODO: I don't know if we need to apply EF function to EEPROM read function
2065
2066 //2 Read EEPROM ID to make sure autoload is success
5aa68752 2067 EEPROMId = eprom_read(priv, 0);
ecdfa446
GKH		 2068 if( EEPROMId != RTL8190_EEPROM_ID )
2069 {
2070 RT_TRACE(COMP_ERR, "EEPROM ID is invalid:%x, %x\n", EEPROMId, RTL8190_EEPROM_ID);
2071 priv->AutoloadFailFlag=true;
2072 }
2073 else
2074 {
2075 priv->AutoloadFailFlag=false;
2076 }
2077
2078 //
2079 // Assign Chip Version ID
2080 //
2081 // Read IC Version && Channel Plan
2082 if(!priv->AutoloadFailFlag)
2083 {
2084 // VID, PID
5aa68752
MM		 2085 priv->eeprom_vid = eprom_read(priv, (EEPROM_VID >> 1));
2086 priv->eeprom_did = eprom_read(priv, (EEPROM_DID >> 1));
ecdfa446 2087
5aa68752 2088 usValue = eprom_read(priv, (u16)(EEPROM_Customer_ID>>1)) >> 8 ;
ecdfa446 2089 priv->eeprom_CustomerID = (u8)( usValue & 0xff);
5aa68752 2090 usValue = eprom_read(priv, (EEPROM_ICVersion_ChannelPlan>>1));
ecdfa446
GKH		 2091 priv->eeprom_ChannelPlan = usValue&0xff;
2092 IC_Version = ((usValue&0xff00)>>8);
2093
ecdfa446
GKH		 2094 ICVer8192 = (IC_Version&0xf); //bit0~3; 1:A cut, 2:B cut, 3:C cut...
2095 ICVer8256 = ((IC_Version&0xf0)>>4);//bit4~6, bit7 reserved for other RF chip; 1:A cut, 2:B cut, 3:C cut...
703fdcc3
MM		 2096 RT_TRACE(COMP_INIT, "ICVer8192 = 0x%x\n", ICVer8192);
2097 RT_TRACE(COMP_INIT, "ICVer8256 = 0x%x\n", ICVer8256);
ecdfa446
GKH		 2098 if(ICVer8192 == 0x2) //B-cut
2099 {
2100 if(ICVer8256 == 0x5) //E-cut
2101 priv->card_8192_version= VERSION_8190_BE;
2102 }
4803ef77 2103
ecdfa446
GKH		 2104 switch(priv->card_8192_version)
2105 {
2106 case VERSION_8190_BD:
2107 case VERSION_8190_BE:
2108 break;
2109 default:
2110 priv->card_8192_version = VERSION_8190_BD;
2111 break;
2112 }
2113 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", priv->card_8192_version);
2114 }
2115 else
2116 {
2117 priv->card_8192_version = VERSION_8190_BD;
2118 priv->eeprom_vid = 0;
2119 priv->eeprom_did = 0;
2120 priv->eeprom_CustomerID = 0;
2121 priv->eeprom_ChannelPlan = 0;
703fdcc3 2122 RT_TRACE(COMP_INIT, "IC Version = 0x%x\n", 0xff);
ecdfa446
GKH		 2123 }
2124
2125 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
2126 RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
2127 RT_TRACE(COMP_INIT,"EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
2128
2129 //2 Read Permanent MAC address
2130 if(!priv->AutoloadFailFlag)
2131 {
2132 for(i = 0; i < 6; i += 2)
2133 {
5aa68752 2134 usValue = eprom_read(priv, (u16) ((EEPROM_NODE_ADDRESS_BYTE_0+i)>>1));
ecdfa446
GKH		 2135 *(u16*)(&dev->dev_addr[i]) = usValue;
2136 }
2137 } else {
2138 // when auto load failed, the last address byte set to be a random one.
2139 // added by david woo.2007/11/7
2140 memcpy(dev->dev_addr, bMac_Tmp_Addr, 6);
ecdfa446
GKH		 2141 }
2142
820793c3 2143 RT_TRACE(COMP_INIT, "Permanent Address = %pM\n", dev->dev_addr);
ecdfa446
GKH		 2144
2145 //2 TX Power Check EEPROM Fail or not
2146 if(priv->card_8192_version > VERSION_8190_BD) {
2147 priv->bTXPowerDataReadFromEEPORM = true;
2148 } else {
2149 priv->bTXPowerDataReadFromEEPORM = false;
2150 }
2151
bbc9a991 2152 // 2007/11/15 MH 8190PCI Default=2T4R, 8192PCIE default=1T2R
ecdfa446
GKH		 2153 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
2154
2155 if(priv->card_8192_version > VERSION_8190_BD)
2156 {
2157 // Read RF-indication and Tx Power gain index diff of legacy to HT OFDM rate.
2158 if(!priv->AutoloadFailFlag)
2159 {
5aa68752 2160 tempval = (eprom_read(priv, (EEPROM_RFInd_PowerDiff>>1))) & 0xff;
ecdfa446
GKH		 2161 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf; // bit[3:0]
2162
2163 if (tempval&0x80) //RF-indication, bit[7]
2164 priv->rf_type = RF_1T2R;
2165 else
2166 priv->rf_type = RF_2T4R;
2167 }
2168 else
2169 {
2170 priv->EEPROMLegacyHTTxPowerDiff = EEPROM_Default_LegacyHTTxPowerDiff;
2171 }
2172 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
2173 priv->EEPROMLegacyHTTxPowerDiff);
2174
2175 // Read ThermalMeter from EEPROM
2176 if(!priv->AutoloadFailFlag)
2177 {
5aa68752 2178 priv->EEPROMThermalMeter = (u8)(((eprom_read(priv, (EEPROM_ThermalMeter>>1))) & 0xff00)>>8);
ecdfa446
GKH		 2179 }
2180 else
2181 {
2182 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
2183 }
2184 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n", priv->EEPROMThermalMeter);
2185 //vivi, for tx power track
2186 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
2187
2188 if(priv->epromtype == EPROM_93c46)
2189 {
2190 // Read antenna tx power offset of B/C/D to A and CrystalCap from EEPROM
2191 if(!priv->AutoloadFailFlag)
2192 {
5aa68752 2193 usValue = eprom_read(priv, (EEPROM_TxPwDiff_CrystalCap>>1));
ecdfa446
GKH		 2194 priv->EEPROMAntPwDiff = (usValue&0x0fff);
2195 priv->EEPROMCrystalCap = (u8)((usValue&0xf000)>>12);
2196 }
2197 else
2198 {
2199 priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff;
2200 priv->EEPROMCrystalCap = EEPROM_Default_TxPwDiff_CrystalCap;
2201 }
2202 RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n", priv->EEPROMAntPwDiff);
2203 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", priv->EEPROMCrystalCap);
2204
2205 //
2206 // Get per-channel Tx Power Level
2207 //
2208 for(i=0; i<14; i+=2)
2209 {
2210 if(!priv->AutoloadFailFlag)
2211 {
5aa68752 2212 usValue = eprom_read(priv, (u16) ((EEPROM_TxPwIndex_CCK+i)>>1) );
ecdfa446
GKH		 2213 }
2214 else
2215 {
2216 usValue = EEPROM_Default_TxPower;
2217 }
2218 *((u16*)(&priv->EEPROMTxPowerLevelCCK[i])) = usValue;
2219 RT_TRACE(COMP_INIT,"CCK Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK[i]);
2220 RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index %d = 0x%02x\n", i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
2221 }
2222 for(i=0; i<14; i+=2)
2223 {
2224 if(!priv->AutoloadFailFlag)
2225 {
5aa68752 2226 usValue = eprom_read(priv, (u16) ((EEPROM_TxPwIndex_OFDM_24G+i)>>1) );
ecdfa446
GKH		 2227 }
2228 else
2229 {
2230 usValue = EEPROM_Default_TxPower;
2231 }
2232 *((u16*)(&priv->EEPROMTxPowerLevelOFDM24G[i])) = usValue;
2233 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelOFDM24G[i]);
2234 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i+1, priv->EEPROMTxPowerLevelOFDM24G[i+1]);
2235 }
2236 }
ecdfa446 2237
ecdfa446
GKH		 2238 //
2239 // Update HAL variables.
2240 //
2241 if(priv->epromtype == EPROM_93c46)
2242 {
2243 for(i=0; i<14; i++)
2244 {
2245 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK[i];
2246 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
2247 }
2248 priv->LegacyHTTxPowerDiff = priv->EEPROMLegacyHTTxPowerDiff;
2249 // Antenna B gain offset to antenna A, bit0~3
2250 priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff & 0xf);
2251 // Antenna C gain offset to antenna A, bit4~7
2252 priv->AntennaTxPwDiff[1] = ((priv->EEPROMAntPwDiff & 0xf0)>>4);
2253 // Antenna D gain offset to antenna A, bit8~11
2254 priv->AntennaTxPwDiff[2] = ((priv->EEPROMAntPwDiff & 0xf00)>>8);
2255 // CrystalCap, bit12~15
2256 priv->CrystalCap = priv->EEPROMCrystalCap;
2257 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
2258 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter & 0xf);
2259 priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter & 0xf0)>>4);
2260 }
2261 else if(priv->epromtype == EPROM_93c56)
2262 {
ecdfa446
GKH		 2263 for(i=0; i<3; i++) // channel 1~3 use the same Tx Power Level.
2264 {
2265 priv->TxPowerLevelCCK_A[i] = priv->EEPROMRfACCKChnl1TxPwLevel[0];
2266 priv->TxPowerLevelOFDM24G_A[i] = priv->EEPROMRfAOfdmChnlTxPwLevel[0];
2267 priv->TxPowerLevelCCK_C[i] = priv->EEPROMRfCCCKChnl1TxPwLevel[0];
2268 priv->TxPowerLevelOFDM24G_C[i] = priv->EEPROMRfCOfdmChnlTxPwLevel[0];
2269 }
2270 for(i=3; i<9; i++) // channel 4~9 use the same Tx Power Level
2271 {
2272 priv->TxPowerLevelCCK_A[i] = priv->EEPROMRfACCKChnl1TxPwLevel[1];
2273 priv->TxPowerLevelOFDM24G_A[i] = priv->EEPROMRfAOfdmChnlTxPwLevel[1];
2274 priv->TxPowerLevelCCK_C[i] = priv->EEPROMRfCCCKChnl1TxPwLevel[1];
2275 priv->TxPowerLevelOFDM24G_C[i] = priv->EEPROMRfCOfdmChnlTxPwLevel[1];
2276 }
2277 for(i=9; i<14; i++) // channel 10~14 use the same Tx Power Level
2278 {
2279 priv->TxPowerLevelCCK_A[i] = priv->EEPROMRfACCKChnl1TxPwLevel[2];
2280 priv->TxPowerLevelOFDM24G_A[i] = priv->EEPROMRfAOfdmChnlTxPwLevel[2];
2281 priv->TxPowerLevelCCK_C[i] = priv->EEPROMRfCCCKChnl1TxPwLevel[2];
2282 priv->TxPowerLevelOFDM24G_C[i] = priv->EEPROMRfCOfdmChnlTxPwLevel[2];
2283 }
2284 for(i=0; i<14; i++)
2285 RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_A[%d] = 0x%x\n", i, priv->TxPowerLevelCCK_A[i]);
2286 for(i=0; i<14; i++)
2287 RT_TRACE(COMP_INIT,"priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n", i, priv->TxPowerLevelOFDM24G_A[i]);
2288 for(i=0; i<14; i++)
2289 RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_C[%d] = 0x%x\n", i, priv->TxPowerLevelCCK_C[i]);
2290 for(i=0; i<14; i++)
2291 RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n", i, priv->TxPowerLevelOFDM24G_C[i]);
2292 priv->LegacyHTTxPowerDiff = priv->EEPROMLegacyHTTxPowerDiff;
2293 priv->AntennaTxPwDiff[0] = 0;
2294 priv->AntennaTxPwDiff[1] = 0;
2295 priv->AntennaTxPwDiff[2] = 0;
2296 priv->CrystalCap = priv->EEPROMCrystalCap;
2297 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
2298 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter & 0xf);
2299 priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter & 0xf0)>>4);
2300 }
2301 }
2302
2303 if(priv->rf_type == RF_1T2R)
2304 {
703fdcc3 2305 RT_TRACE(COMP_INIT, "1T2R config\n");
ecdfa446
GKH		 2306 }
2307 else if (priv->rf_type == RF_2T4R)
2308 {
703fdcc3 2309 RT_TRACE(COMP_INIT, "2T4R config\n");
ecdfa446
GKH		 2310 }
2311
2312 // 2008/01/16 MH We can only know RF type in the function. So we have to init
2313 // DIG RATR table again.
2314 init_rate_adaptive(dev);
2315
2316 //1 Make a copy for following variables and we can change them if we want
2317
ecdfa446
GKH		 2318 if(priv->RegChannelPlan == 0xf)
2319 {
2320 priv->ChannelPlan = priv->eeprom_ChannelPlan;
2321 }
2322 else
2323 {
2324 priv->ChannelPlan = priv->RegChannelPlan;
2325 }
2326
2327 //
2328 // Used PID and DID to Set CustomerID
2329 //
2330 if( priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304 )
2331 {
2332 priv->CustomerID = RT_CID_DLINK;
2333 }
2334
2335 switch(priv->eeprom_CustomerID)
2336 {
2337 case EEPROM_CID_DEFAULT:
2338 priv->CustomerID = RT_CID_DEFAULT;
2339 break;
2340 case EEPROM_CID_CAMEO:
2341 priv->CustomerID = RT_CID_819x_CAMEO;
2342 break;
2343 case EEPROM_CID_RUNTOP:
2344 priv->CustomerID = RT_CID_819x_RUNTOP;
2345 break;
2346 case EEPROM_CID_NetCore:
2347 priv->CustomerID = RT_CID_819x_Netcore;
2348 break;
2349 case EEPROM_CID_TOSHIBA: // Merge by Jacken, 2008/01/31
2350 priv->CustomerID = RT_CID_TOSHIBA;
2351 if(priv->eeprom_ChannelPlan&0x80)
2352 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
2353 else
2354 priv->ChannelPlan = 0x0;
2355 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
2356 priv->ChannelPlan);
2357 break;
2358 case EEPROM_CID_Nettronix:
ecdfa446
GKH		 2359 priv->CustomerID = RT_CID_Nettronix;
2360 break;
2361 case EEPROM_CID_Pronet:
2362 priv->CustomerID = RT_CID_PRONET;
2363 break;
2364 case EEPROM_CID_DLINK:
2365 priv->CustomerID = RT_CID_DLINK;
2366 break;
2367
2368 case EEPROM_CID_WHQL:
ecdfa446
GKH		 2369 break;
2370 default:
2371 // value from RegCustomerID
2372 break;
2373 }
2374
2375 //Avoid the channel plan array overflow, by Bruce, 2007-08-27.
2376 if(priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
2377 priv->ChannelPlan = 0; //FCC
2378
ecdfa446 2379 if( priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
65a43784 2380 priv->ieee80211->bSupportRemoteWakeUp = true;
ecdfa446 2381 else
65a43784 2382 priv->ieee80211->bSupportRemoteWakeUp = false;
2383
2384
ecdfa446 2385 RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
703fdcc3 2386 RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
ecdfa446 2387 RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
ecdfa446
GKH		 2388}
2389
2390
af59c39d 2391static short rtl8192_get_channel_map(struct r8192_priv *priv)
ecdfa446 2392{
ecdfa446
GKH		 2393#ifdef ENABLE_DOT11D
2394 if(priv->ChannelPlan> COUNTRY_CODE_GLOBAL_DOMAIN){
2395 printk("rtl8180_init:Error channel plan! Set to default.\n");
2396 priv->ChannelPlan= 0;
2397 }
2398 RT_TRACE(COMP_INIT, "Channel plan is %d\n",priv->ChannelPlan);
2399
2400 rtl819x_set_channel_map(priv->ChannelPlan, priv);
2401#else
2402 int ch,i;
2403 //Set Default Channel Plan
2404 if(!channels){
2405 DMESG("No channels, aborting");
2406 return -1;
2407 }
2408 ch=channels;
2409 priv->ChannelPlan= 0;//hikaru
2410 // set channels 1..14 allowed in given locale
2411 for (i=1; i<=14; i++) {
2412 (priv->ieee80211->channel_map)[i] = (u8)(ch & 0x01);
2413 ch >>= 1;
2414 }
2415#endif
2416 return 0;
2417}
5e1ad18a 2418
c62fdce2 2419static short rtl8192_init(struct r8192_priv *priv)
ecdfa446 2420{
c62fdce2
MM		 2421 struct net_device *dev = priv->ieee80211->dev;
2422
ecdfa446 2423 memset(&(priv->stats),0,sizeof(struct Stats));
af59c39d 2424 rtl8192_init_priv_variable(priv);
ecdfa446 2425 rtl8192_init_priv_lock(priv);
af59c39d
MM		 2426 rtl8192_init_priv_task(priv);
2427 rtl8192_get_eeprom_size(priv);
3f9ab1ee 2428 rtl8192_read_eeprom_info(priv);
af59c39d 2429 rtl8192_get_channel_map(priv);
ecdfa446
GKH		 2430 init_hal_dm(dev);
2431 init_timer(&priv->watch_dog_timer);
1f0e4270 2432 priv->watch_dog_timer.data = (unsigned long)priv;
ecdfa446 2433 priv->watch_dog_timer.function = watch_dog_timer_callback;
7bb5e823 2434 if (request_irq(dev->irq, rtl8192_interrupt, IRQF_SHARED, dev->name, dev)) {
ecdfa446
GKH		 2435 printk("Error allocating IRQ %d",dev->irq);
2436 return -1;
2437 }else{
2438 priv->irq=dev->irq;
2439 printk("IRQ %d",dev->irq);
2440 }
af59c39d 2441 if (rtl8192_pci_initdescring(priv) != 0){
ecdfa446
GKH		 2442 printk("Endopoints initialization failed");
2443 return -1;
2444 }
2445
ecdfa446
GKH		 2446 return 0;
2447}
2448
214985a6
MM		 2449/*
2450 * Actually only set RRSR, RATR and BW_OPMODE registers
2451 * not to do all the hw config as its name says
2452 * This part need to modified according to the rate set we filtered
2453 */
480ab9dc 2454static void rtl8192_hwconfig(struct r8192_priv *priv)
ecdfa446
GKH		 2455{
2456 u32 regRATR = 0, regRRSR = 0;
2457 u8 regBwOpMode = 0, regTmp = 0;
ecdfa446
GKH		 2458
2459// Set RRSR, RATR, and BW_OPMODE registers
2460 //
480ab9dc 2461 switch (priv->ieee80211->mode)
ecdfa446
GKH		 2462 {
2463 case WIRELESS_MODE_B:
2464 regBwOpMode = BW_OPMODE_20MHZ;
2465 regRATR = RATE_ALL_CCK;
2466 regRRSR = RATE_ALL_CCK;
2467 break;
2468 case WIRELESS_MODE_A:
2469 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
2470 regRATR = RATE_ALL_OFDM_AG;
2471 regRRSR = RATE_ALL_OFDM_AG;
2472 break;
2473 case WIRELESS_MODE_G:
2474 regBwOpMode = BW_OPMODE_20MHZ;
2475 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
2476 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
2477 break;
2478 case WIRELESS_MODE_AUTO:
2479 case WIRELESS_MODE_N_24G:
2480 // It support CCK rate by default.
2481 // CCK rate will be filtered out only when associated AP does not support it.
2482 regBwOpMode = BW_OPMODE_20MHZ;
2483 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
2484 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
2485 break;
2486 case WIRELESS_MODE_N_5G:
2487 regBwOpMode = BW_OPMODE_5G;
2488 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
2489 regRRSR = RATE_ALL_OFDM_AG;
2490 break;
2491 }
2492
3f9ab1ee 2493 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
ecdfa446
GKH		 2494 {
2495 u32 ratr_value = 0;
2496 ratr_value = regRATR;
2497 if (priv->rf_type == RF_1T2R)
2498 {
2499 ratr_value &= ~(RATE_ALL_OFDM_2SS);
2500 }
3f9ab1ee
MM		 2501 write_nic_dword(priv, RATR0, ratr_value);
2502 write_nic_byte(priv, UFWP, 1);
ecdfa446 2503 }
3f9ab1ee 2504 regTmp = read_nic_byte(priv, 0x313);
ecdfa446 2505 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
3f9ab1ee 2506 write_nic_dword(priv, RRSR, regRRSR);
ecdfa446
GKH		 2507
2508 //
2509 // Set Retry Limit here
2510 //
3f9ab1ee 2511 write_nic_word(priv, RETRY_LIMIT,
207b58fb 2512 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
ecdfa446
GKH		 2513 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
2514 // Set Contention Window here
2515
2516 // Set Tx AGC
2517
2518 // Set Tx Antenna including Feedback control
2519
2520 // Set Auto Rate fallback control
2521
2522
2523}
2524
2525
af59c39d 2526static RT_STATUS rtl8192_adapter_start(struct r8192_priv *priv)
ecdfa446 2527{
af59c39d 2528 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 2529 u32 ulRegRead;
2530 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
ecdfa446 2531 u8 tmpvalue;
ecdfa446 2532 u8 ICVersion,SwitchingRegulatorOutput;
ecdfa446 2533 bool bfirmwareok = true;
ecdfa446
GKH		 2534 u32 tmpRegA, tmpRegC, TempCCk;
2535 int i =0;
ecdfa446
GKH		 2536
2537 RT_TRACE(COMP_INIT, "====>%s()\n", __FUNCTION__);
2538 priv->being_init_adapter = true;
480ab9dc 2539 rtl8192_pci_resetdescring(priv);
ecdfa446
GKH		 2540 // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W.
2541 priv->Rf_Mode = RF_OP_By_SW_3wire;
4803ef77 2542
ecdfa446
GKH		 2543 //dPLL on
2544 if(priv->ResetProgress == RESET_TYPE_NORESET)
2545 {
3f9ab1ee 2546 write_nic_byte(priv, ANAPAR, 0x37);
ecdfa446
GKH		 2547 // Accordign to designer's explain, LBUS active will never > 10ms. We delay 10ms
2548 // Joseph increae the time to prevent firmware download fail
2549 mdelay(500);
2550 }
4803ef77 2551
ecdfa446
GKH		 2552 //PlatformSleepUs(10000);
2553 // For any kind of InitializeAdapter process, we shall use system now!!
2554 priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
2555
ecdfa446
GKH		 2556 //
2557 //3 //Config CPUReset Register
2558 //3//
2559 //3 Firmware Reset Or Not
3f9ab1ee 2560 ulRegRead = read_nic_dword(priv, CPU_GEN);
ecdfa446
GKH		 2561 if(priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
2562 { //called from MPInitialized. do nothing
2563 ulRegRead |= CPU_GEN_SYSTEM_RESET;
2564 }else if(priv->pFirmware->firmware_status == FW_STATUS_5_READY)
2565 ulRegRead |= CPU_GEN_FIRMWARE_RESET; // Called from MPReset
2566 else
2567 RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status);
2568
3f9ab1ee 2569 write_nic_dword(priv, CPU_GEN, ulRegRead);
ecdfa446 2570
ecdfa446
GKH		 2571 //3//
2572 //3 //Fix the issue of E-cut high temperature issue
2573 //3//
2574 // TODO: E cut only
3f9ab1ee 2575 ICVersion = read_nic_byte(priv, IC_VERRSION);
ecdfa446
GKH		 2576 if(ICVersion >= 0x4) //E-cut only
2577 {
2578 // HW SD suggest that we should not wirte this register too often, so driver
2579 // should readback this register. This register will be modified only when
2580 // power on reset
3f9ab1ee 2581 SwitchingRegulatorOutput = read_nic_byte(priv, SWREGULATOR);
ecdfa446
GKH		 2582 if(SwitchingRegulatorOutput != 0xb8)
2583 {
3f9ab1ee 2584 write_nic_byte(priv, SWREGULATOR, 0xa8);
ecdfa446 2585 mdelay(1);
3f9ab1ee 2586 write_nic_byte(priv, SWREGULATOR, 0xb8);
ecdfa446
GKH		 2587 }
2588 }
ecdfa446
GKH		 2589
2590 //3//
2591 //3// Initialize BB before MAC
2592 //3//
ecdfa446 2593 RT_TRACE(COMP_INIT, "BB Config Start!\n");
d9ffa6c2 2594 rtStatus = rtl8192_BBConfig(priv);
ecdfa446
GKH		 2595 if(rtStatus != RT_STATUS_SUCCESS)
2596 {
2597 RT_TRACE(COMP_ERR, "BB Config failed\n");
2598 return rtStatus;
2599 }
2600 RT_TRACE(COMP_INIT,"BB Config Finished!\n");
2601
ecdfa446
GKH		 2602 //3//Set Loopback mode or Normal mode
2603 //3//
2604 //2006.12.13 by emily. Note!We should not merge these two CPU_GEN register writings
2605 // because setting of System_Reset bit reset MAC to default transmission mode.
2606 //Loopback mode or not
2607 priv->LoopbackMode = RTL819X_NO_LOOPBACK;
ecdfa446
GKH		 2608 if(priv->ResetProgress == RESET_TYPE_NORESET)
2609 {
3f9ab1ee 2610 ulRegRead = read_nic_dword(priv, CPU_GEN);
ecdfa446
GKH		 2611 if(priv->LoopbackMode == RTL819X_NO_LOOPBACK)
2612 {
2613 ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET);
2614 }
2615 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK )
2616 {
2617 ulRegRead |= CPU_CCK_LOOPBACK;
2618 }
2619 else
2620 {
2621 RT_TRACE(COMP_ERR,"Serious error: wrong loopback mode setting\n");
2622 }
2623
2624 //2008.06.03, for WOL
2625 //ulRegRead &= (~(CPU_GEN_GPIO_UART));
3f9ab1ee 2626 write_nic_dword(priv, CPU_GEN, ulRegRead);
ecdfa446
GKH		 2627
2628 // 2006.11.29. After reset cpu, we sholud wait for a second, otherwise, it may fail to write registers. Emily
2629 udelay(500);
2630 }
2631 //3Set Hardware(Do nothing now)
480ab9dc 2632 rtl8192_hwconfig(priv);
ecdfa446
GKH		 2633 //2=======================================================
2634 // Common Setting for all of the FPGA platform. (part 1)
2635 //2=======================================================
2636 // If there is changes, please make sure it applies to all of the FPGA version
2637 //3 Turn on Tx/Rx
3f9ab1ee 2638 write_nic_byte(priv, CMDR, CR_RE|CR_TE);
ecdfa446
GKH		 2639
2640 //2Set Tx dma burst
3f9ab1ee 2641 write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
ecdfa446 2642 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) ));
4803ef77 2643
ecdfa446 2644 //set IDR0 here
3f9ab1ee
MM		 2645 write_nic_dword(priv, MAC0, ((u32*)dev->dev_addr)[0]);
2646 write_nic_word(priv, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
ecdfa446 2647 //set RCR
3f9ab1ee 2648 write_nic_dword(priv, RCR, priv->ReceiveConfig);
ecdfa446
GKH		 2649
2650 //3 Initialize Number of Reserved Pages in Firmware Queue
3f9ab1ee 2651 write_nic_dword(priv, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |
207b58fb
MM		 2652 NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT |
2653 NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT |
ecdfa446 2654 NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT);
3f9ab1ee
MM		 2655 write_nic_dword(priv, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
2656 write_nic_dword(priv, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW|
207b58fb 2657 NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
ecdfa446 2658 NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
ecdfa446 2659
480ab9dc
MM		 2660 rtl8192_tx_enable(priv);
2661 rtl8192_rx_enable(priv);
ecdfa446
GKH		 2662 //3Set Response Rate Setting Register
2663 // CCK rate is supported by default.
2664 // CCK rate will be filtered out only when associated AP does not support it.
3f9ab1ee
MM		 2665 ulRegRead = (0xFFF00000 & read_nic_dword(priv, RRSR)) | RATE_ALL_OFDM_AG | RATE_ALL_CCK;
2666 write_nic_dword(priv, RRSR, ulRegRead);
2667 write_nic_dword(priv, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
ecdfa446
GKH		 2668
2669 //2Set AckTimeout
2670 // TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily
3f9ab1ee 2671 write_nic_byte(priv, ACK_TIMEOUT, 0x30);
ecdfa446 2672
ecdfa446
GKH		 2673 if(priv->ResetProgress == RESET_TYPE_NORESET)
2674 rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);
2675 //-----------------------------------------------------------------------------
2676 // Set up security related. 070106, by rcnjko:
2677 // 1. Clear all H/W keys.
2678 // 2. Enable H/W encryption/decryption.
2679 //-----------------------------------------------------------------------------
480ab9dc 2680 CamResetAllEntry(priv);
ecdfa446
GKH		 2681 {
2682 u8 SECR_value = 0x0;
2683 SECR_value |= SCR_TxEncEnable;
2684 SECR_value |= SCR_RxDecEnable;
2685 SECR_value |= SCR_NoSKMC;
3f9ab1ee 2686 write_nic_byte(priv, SECR, SECR_value);
ecdfa446
GKH		 2687 }
2688 //3Beacon related
3f9ab1ee
MM		 2689 write_nic_word(priv, ATIMWND, 2);
2690 write_nic_word(priv, BCN_INTERVAL, 100);
5e1ad18a 2691 for (i=0; i<QOS_QUEUE_NUM; i++)
3f9ab1ee 2692 write_nic_dword(priv, WDCAPARA_ADD[i], 0x005e4332);
ecdfa446
GKH		 2693 //
2694 // Switching regulator controller: This is set temporarily.
2695 // It's not sure if this can be removed in the future.
2696 // PJ advised to leave it by default.
2697 //
3f9ab1ee 2698 write_nic_byte(priv, 0xbe, 0xc0);
ecdfa446
GKH		 2699
2700 //2=======================================================
2701 // Set PHY related configuration defined in MAC register bank
2702 //2=======================================================
d9ffa6c2 2703 rtl8192_phy_configmac(priv);
ecdfa446
GKH		 2704
2705 if (priv->card_8192_version > (u8) VERSION_8190_BD) {
d9ffa6c2
MM		 2706 rtl8192_phy_getTxPower(priv);
2707 rtl8192_phy_setTxPower(priv, priv->chan);
ecdfa446
GKH		 2708 }
2709
2710 //if D or C cut
3f9ab1ee 2711 tmpvalue = read_nic_byte(priv, IC_VERRSION);
ecdfa446
GKH		 2712 priv->IC_Cut = tmpvalue;
2713 RT_TRACE(COMP_INIT, "priv->IC_Cut = 0x%x\n", priv->IC_Cut);
2714 if(priv->IC_Cut >= IC_VersionCut_D)
2715 {
2716 //pHalData->bDcut = TRUE;
2717 if(priv->IC_Cut == IC_VersionCut_D)
2718 RT_TRACE(COMP_INIT, "D-cut\n");
2719 if(priv->IC_Cut == IC_VersionCut_E)
2720 {
2721 RT_TRACE(COMP_INIT, "E-cut\n");
2722 // HW SD suggest that we should not wirte this register too often, so driver
2723 // should readback this register. This register will be modified only when
2724 // power on reset
2725 }
2726 }
2727 else
2728 {
2729 //pHalData->bDcut = FALSE;
2730 RT_TRACE(COMP_INIT, "Before C-cut\n");
2731 }
2732
ecdfa446
GKH		 2733 //Firmware download
2734 RT_TRACE(COMP_INIT, "Load Firmware!\n");
2735 bfirmwareok = init_firmware(dev);
2736 if(bfirmwareok != true) {
2737 rtStatus = RT_STATUS_FAILURE;
2738 return rtStatus;
2739 }
2740 RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
11aacc28 2741
ecdfa446
GKH		 2742 //RF config
2743 if(priv->ResetProgress == RESET_TYPE_NORESET)
2744 {
2745 RT_TRACE(COMP_INIT, "RF Config Started!\n");
d9ffa6c2 2746 rtStatus = rtl8192_phy_RFConfig(priv);
ecdfa446
GKH		 2747 if(rtStatus != RT_STATUS_SUCCESS)
2748 {
2749 RT_TRACE(COMP_ERR, "RF Config failed\n");
2750 return rtStatus;
2751 }
2752 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
2753 }
d9ffa6c2 2754 rtl8192_phy_updateInitGain(priv);
ecdfa446
GKH		 2755
2756 /*---- Set CCK and OFDM Block "ON"----*/
d9ffa6c2
MM		 2757 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bCCKEn, 0x1);
2758 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bOFDMEn, 0x1);
ecdfa446 2759
ecdfa446 2760 //Enable Led
3f9ab1ee 2761 write_nic_byte(priv, 0x87, 0x0);
ecdfa446
GKH		 2762
2763 //2=======================================================
2764 // RF Power Save
2765 //2=======================================================
2766#ifdef ENABLE_IPS
2767
2768{
181d1dff 2769 if(priv->RfOffReason > RF_CHANGE_BY_PS)
ecdfa446 2770 { // H/W or S/W RF OFF before sleep.
181d1dff 2771 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for RfOffReason(%d)\n", __FUNCTION__,priv->RfOffReason);
262cd816 2772 MgntActSet_RF_State(priv, eRfOff, priv->RfOffReason);
ecdfa446 2773 }
181d1dff 2774 else if(priv->RfOffReason >= RF_CHANGE_BY_IPS)
ecdfa446 2775 { // H/W or S/W RF OFF before sleep.
181d1dff 2776 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for RfOffReason(%d)\n", __FUNCTION__, priv->RfOffReason);
262cd816 2777 MgntActSet_RF_State(priv, eRfOff, priv->RfOffReason);
ecdfa446
GKH		 2778 }
2779 else
2780 {
2781 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON \n",__FUNCTION__);
4559854d 2782 priv->eRFPowerState = eRfOn;
181d1dff 2783 priv->RfOffReason = 0;
ecdfa446
GKH		 2784 }
2785}
2786#endif
4803ef77
MM		 2787 // We can force firmware to do RF-R/W
2788 if(priv->ieee80211->FwRWRF)
2789 priv->Rf_Mode = RF_OP_By_FW;
2790 else
2791 priv->Rf_Mode = RF_OP_By_SW_3wire;
ecdfa446 2792
ecdfa446
GKH		 2793 if(priv->ResetProgress == RESET_TYPE_NORESET)
2794 {
7088dfb6 2795 dm_initialize_txpower_tracking(priv);
ecdfa446
GKH		 2796
2797 if(priv->IC_Cut >= IC_VersionCut_D)
2798 {
d9ffa6c2
MM		 2799 tmpRegA = rtl8192_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord);
2800 tmpRegC = rtl8192_QueryBBReg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord);
ecdfa446
GKH		 2801 for(i = 0; i<TxBBGainTableLength; i++)
2802 {
2803 if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
2804 {
2805 priv->rfa_txpowertrackingindex= (u8)i;
2806 priv->rfa_txpowertrackingindex_real= (u8)i;
2807 priv->rfa_txpowertracking_default = priv->rfa_txpowertrackingindex;
2808 break;
2809 }
2810 }
2811
d9ffa6c2 2812 TempCCk = rtl8192_QueryBBReg(priv, rCCK0_TxFilter1, bMaskByte2);
ecdfa446
GKH		 2813
2814 for(i=0 ; i<CCKTxBBGainTableLength ; i++)
2815 {
2816 if(TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0])
2817 {
2818 priv->CCKPresentAttentuation_20Mdefault =(u8) i;
2819 break;
2820 }
2821 }
2822 priv->CCKPresentAttentuation_40Mdefault = 0;
2823 priv->CCKPresentAttentuation_difference = 0;
2824 priv->CCKPresentAttentuation = priv->CCKPresentAttentuation_20Mdefault;
2825 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_initial = %d\n", priv->rfa_txpowertrackingindex);
2826 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real__initial = %d\n", priv->rfa_txpowertrackingindex_real);
2827 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference_initial = %d\n", priv->CCKPresentAttentuation_difference);
2828 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_initial = %d\n", priv->CCKPresentAttentuation);
2829 priv->btxpower_tracking = FALSE;//TEMPLY DISABLE
2830 }
2831 }
4803ef77 2832
480ab9dc 2833 rtl8192_irq_enable(priv);
ecdfa446
GKH		 2834 priv->being_init_adapter = false;
2835 return rtStatus;
2836
2837}
2838
80a4dead 2839static void rtl8192_prepare_beacon(unsigned long arg)
ecdfa446 2840{
80a4dead 2841 struct r8192_priv *priv = (struct r8192_priv*) arg;
ecdfa446 2842 struct sk_buff *skb;
ecdfa446
GKH		 2843 cb_desc *tcb_desc;
2844
2845 skb = ieee80211_get_beacon(priv->ieee80211);
2846 tcb_desc = (cb_desc *)(skb->cb + 8);
ecdfa446
GKH		 2847 /* prepare misc info for the beacon xmit */
2848 tcb_desc->queue_index = BEACON_QUEUE;
bbc9a991 2849 /* IBSS does not support HT yet, use 1M defaultly */
ecdfa446
GKH		 2850 tcb_desc->data_rate = 2;
2851 tcb_desc->RATRIndex = 7;
2852 tcb_desc->bTxDisableRateFallBack = 1;
2853 tcb_desc->bTxUseDriverAssingedRate = 1;
2854
2855 skb_push(skb, priv->ieee80211->tx_headroom);
2856 if(skb){
af59c39d 2857 rtl8192_tx(priv, skb);
ecdfa446 2858 }
ecdfa446
GKH		 2859}
2860
ecdfa446 2861
214985a6
MM		 2862/*
2863 * configure registers for beacon tx and enables it via
ecdfa446
GKH		 2864 * rtl8192_beacon_tx_enable(). rtl8192_beacon_tx_disable() might
2865 * be used to stop beacon transmission
2866 */
559fba5e 2867static void rtl8192_start_beacon(struct net_device *dev)
ecdfa446
GKH		 2868{
2869 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
2870 struct ieee80211_network *net = &priv->ieee80211->current_network;
2871 u16 BcnTimeCfg = 0;
2872 u16 BcnCW = 6;
2873 u16 BcnIFS = 0xf;
2874
2875 DMESG("Enabling beacon TX");
af59c39d 2876 rtl8192_irq_disable(priv);
ecdfa446
GKH		 2877 //rtl8192_beacon_tx_enable(dev);
2878
2879 /* ATIM window */
3f9ab1ee 2880 write_nic_word(priv, ATIMWND, 2);
ecdfa446
GKH		 2881
2882 /* Beacon interval (in unit of TU) */
3f9ab1ee 2883 write_nic_word(priv, BCN_INTERVAL, net->beacon_interval);
ecdfa446
GKH		 2884
2885 /*
2886 * DrvErlyInt (in unit of TU).
2887 * (Time to send interrupt to notify driver to c
2888 * hange beacon content)
2889 * */
3f9ab1ee 2890 write_nic_word(priv, BCN_DRV_EARLY_INT, 10);
ecdfa446
GKH		 2891
2892 /*
2893 * BcnDMATIM(in unit of us).
2894 * Indicates the time before TBTT to perform beacon queue DMA
2895 * */
3f9ab1ee 2896 write_nic_word(priv, BCN_DMATIME, 256);
ecdfa446
GKH		 2897
2898 /*
2899 * Force beacon frame transmission even after receiving
2900 * beacon frame from other ad hoc STA
2901 * */
3f9ab1ee 2902 write_nic_byte(priv, BCN_ERR_THRESH, 100);
ecdfa446
GKH		 2903
2904 /* Set CW and IFS */
2905 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
2906 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
3f9ab1ee 2907 write_nic_word(priv, BCN_TCFG, BcnTimeCfg);
ecdfa446
GKH		 2908
2909
2910 /* enable the interrupt for ad-hoc process */
480ab9dc 2911 rtl8192_irq_enable(priv);
ecdfa446 2912}
ecdfa446 2913
af59c39d 2914static bool HalRxCheckStuck8190Pci(struct r8192_priv *priv)
ecdfa446 2915{
3f9ab1ee 2916 u16 RegRxCounter = read_nic_word(priv, 0x130);
ecdfa446 2917 bool bStuck = FALSE;
935ce899 2918
ecdfa446
GKH		 2919 RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter);
2920 // If rssi is small, we should check rx for long time because of bad rx.
2921 // or maybe it will continuous silent reset every 2 seconds.
935ce899 2922 priv->rx_chk_cnt++;
ecdfa446
GKH		 2923 if(priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5))
2924 {
935ce899 2925 priv->rx_chk_cnt = 0; /* high rssi, check rx stuck right now. */
ecdfa446
GKH		 2926 }
2927 else if(priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High+5) &&
2928 ((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_40M) ||
2929 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_20M)) )
2930
2931 {
935ce899 2932 if(priv->rx_chk_cnt < 2)
ecdfa446
GKH		 2933 {
2934 return bStuck;
2935 }
2936 else
2937 {
935ce899 2938 priv->rx_chk_cnt = 0;
ecdfa446
GKH		 2939 }
2940 }
2941 else if(((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_40M) ||
2942 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_20M)) &&
2943 priv->undecorated_smoothed_pwdb >= VeryLowRSSI)
2944 {
935ce899 2945 if(priv->rx_chk_cnt < 4)
ecdfa446 2946 {
ecdfa446
GKH		 2947 return bStuck;
2948 }
2949 else
2950 {
935ce899 2951 priv->rx_chk_cnt = 0;
ecdfa446
GKH		 2952 }
2953 }
2954 else
2955 {
935ce899 2956 if(priv->rx_chk_cnt < 8)
ecdfa446 2957 {
ecdfa446
GKH		 2958 return bStuck;
2959 }
2960 else
2961 {
935ce899 2962 priv->rx_chk_cnt = 0;
ecdfa446
GKH		 2963 }
2964 }
ecdfa446
GKH		 2965 if(priv->RxCounter==RegRxCounter)
2966 bStuck = TRUE;
2967
2968 priv->RxCounter = RegRxCounter;
2969
2970 return bStuck;
2971}
2972
af59c39d 2973static RESET_TYPE RxCheckStuck(struct r8192_priv *priv)
ecdfa446
GKH		 2974{
2975
af59c39d 2976 if(HalRxCheckStuck8190Pci(priv))
ecdfa446
GKH		 2977 {
2978 RT_TRACE(COMP_RESET, "RxStuck Condition\n");
2979 return RESET_TYPE_SILENT;
2980 }
2981
2982 return RESET_TYPE_NORESET;
2983}
2984
5e1ad18a 2985static RESET_TYPE
af59c39d 2986rtl819x_ifcheck_resetornot(struct r8192_priv *priv)
ecdfa446 2987{
ecdfa446
GKH		 2988 RESET_TYPE TxResetType = RESET_TYPE_NORESET;
2989 RESET_TYPE RxResetType = RESET_TYPE_NORESET;
2990 RT_RF_POWER_STATE rfState;
2991
4559854d 2992 rfState = priv->eRFPowerState;
ecdfa446 2993
ecdfa446
GKH		 2994 if( rfState != eRfOff &&
2995 /*ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FW_DOWNLOAD_FAILURE)) &&*/
2996 (priv->ieee80211->iw_mode != IW_MODE_ADHOC))
2997 {
2998 // If driver is in the status of firmware download failure , driver skips RF initialization and RF is
2999 // in turned off state. Driver should check whether Rx stuck and do silent reset. And
3000 // if driver is in firmware download failure status, driver should initialize RF in the following
3001 // silent reset procedure Emily, 2008.01.21
3002
3003 // Driver should not check RX stuck in IBSS mode because it is required to
3004 // set Check BSSID in order to send beacon, however, if check BSSID is
3005 // set, STA cannot hear any packet a all. Emily, 2008.04.12
af59c39d 3006 RxResetType = RxCheckStuck(priv);
ecdfa446 3007 }
ecdfa446
GKH		 3008
3009 RT_TRACE(COMP_RESET,"%s(): TxResetType is %d, RxResetType is %d\n",__FUNCTION__,TxResetType,RxResetType);
3010 if(TxResetType==RESET_TYPE_NORMAL || RxResetType==RESET_TYPE_NORMAL)
3011 return RESET_TYPE_NORMAL;
3012 else if(TxResetType==RESET_TYPE_SILENT || RxResetType==RESET_TYPE_SILENT)
3013 return RESET_TYPE_SILENT;
3014 else
3015 return RESET_TYPE_NORESET;
3016
3017}
3018
ecdfa446 3019#ifdef ENABLE_IPS
af59c39d 3020static void InactivePsWorkItemCallback(struct r8192_priv *priv)
ecdfa446 3021{
31d664e5 3022 PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
ecdfa446 3023
703fdcc3 3024 RT_TRACE(COMP_POWER, "InactivePsWorkItemCallback() --------->\n");
ecdfa446
GKH		 3025 //
3026 // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
3027 // is really scheduled.
3028 // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
3029 // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
3030 // blocks the IPS procedure of switching RF.
3031 // By Bruce, 2007-12-25.
3032 //
3033 pPSC->bSwRfProcessing = TRUE;
3034
207b58fb 3035 RT_TRACE(COMP_RF, "InactivePsWorkItemCallback(): Set RF to %s.\n",
ecdfa446
GKH		 3036 pPSC->eInactivePowerState == eRfOff?"OFF":"ON");
3037
3038
262cd816 3039 MgntActSet_RF_State(priv, pPSC->eInactivePowerState, RF_CHANGE_BY_IPS);
ecdfa446
GKH		 3040
3041 //
3042 // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
3043 //
ecdfa446 3044 pPSC->bSwRfProcessing = FALSE;
703fdcc3 3045 RT_TRACE(COMP_POWER, "InactivePsWorkItemCallback() <---------\n");
ecdfa446
GKH		 3046}
3047
65a43784 3048#ifdef ENABLE_LPS
214985a6 3049/* Change current and default preamble mode. */
679a2494 3050bool MgntActSet_802_11_PowerSaveMode(struct r8192_priv *priv, u8 rtPsMode)
65a43784 3051{
65a43784 3052
3053 // Currently, we do not change power save mode on IBSS mode.
3054 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
3055 {
3056 return false;
3057 }
3058
3059 //
3060 // <RJ_NOTE> If we make HW to fill up the PwrMgt bit for us,
3061 // some AP will not response to our mgnt frames with PwrMgt bit set,
3062 // e.g. cannot associate the AP.
3063 // So I commented out it. 2005.02.16, by rcnjko.
3064 //
3065// // Change device's power save mode.
3066// Adapter->HalFunc.SetPSModeHandler( Adapter, rtPsMode );
3067
3068 // Update power save mode configured.
3069 //RT_TRACE(COMP_LPS,"%s(): set ieee->ps = %x\n",__FUNCTION__,rtPsMode);
3070 if(!priv->ps_force) {
3071 priv->ieee80211->ps = rtPsMode;
3072 }
3073
3074 // Awake immediately
3075 if(priv->ieee80211->sta_sleep != 0 && rtPsMode == IEEE80211_PS_DISABLED)
3076 {
65a43784 3077 // Notify the AP we awke.
679a2494 3078 rtl8192_hw_wakeup(priv->ieee80211->dev);
65a43784 3079 priv->ieee80211->sta_sleep = 0;
3080
0cfc6185 3081 spin_lock(&priv->ieee80211->mgmt_tx_lock);
65a43784 3082 printk("LPS leave: notify AP we are awaked ++++++++++ SendNullFunctionData\n");
3083 ieee80211_sta_ps_send_null_frame(priv->ieee80211, 0);
0cfc6185 3084 spin_unlock(&priv->ieee80211->mgmt_tx_lock);
65a43784 3085 }
3086
3087 return true;
3088}
3089
214985a6 3090/* Enter the leisure power save mode. */
65a43784 3091void LeisurePSEnter(struct net_device *dev)
3092{
3093 struct r8192_priv *priv = ieee80211_priv(dev);
31d664e5 3094 PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
65a43784 3095
65a43784 3096 if(!((priv->ieee80211->iw_mode == IW_MODE_INFRA) &&
3097 (priv->ieee80211->state == IEEE80211_LINKED)) ||
3098 (priv->ieee80211->iw_mode == IW_MODE_ADHOC) ||
3099 (priv->ieee80211->iw_mode == IW_MODE_MASTER))
3100 return;
3101
3102 if (pPSC->bLeisurePs)
3103 {
3104 // Idle for a while if we connect to AP a while ago.
3105 if(pPSC->LpsIdleCount >= RT_CHECK_FOR_HANG_PERIOD) // 4 Sec
3106 {
3107
3108 if(priv->ieee80211->ps == IEEE80211_PS_DISABLED)
3109 {
679a2494 3110 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST);
65a43784 3111
3112 }
3113 }
3114 else
3115 pPSC->LpsIdleCount++;
3116 }
3117}
3118
3119
214985a6 3120/* Leave leisure power save mode. */
65a43784 3121void LeisurePSLeave(struct net_device *dev)
3122{
3123 struct r8192_priv *priv = ieee80211_priv(dev);
31d664e5 3124 PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
65a43784 3125
65a43784 3126 if (pPSC->bLeisurePs)
3127 {
3128 if(priv->ieee80211->ps != IEEE80211_PS_DISABLED)
3129 {
3130 // move to lps_wakecomplete()
679a2494 3131 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED);
65a43784 3132
3133 }
3134 }
3135}
3136#endif
3137
3138
214985a6 3139/* Enter the inactive power save mode. RF will be off */
e676ae58 3140void IPSEnter(struct r8192_priv *priv)
ecdfa446 3141{
31d664e5 3142 PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
ecdfa446
GKH		 3143 RT_RF_POWER_STATE rtState;
3144
3145 if (pPSC->bInactivePs)
3146 {
4559854d 3147 rtState = priv->eRFPowerState;
ecdfa446
GKH		 3148 //
3149 // Added by Bruce, 2007-12-25.
3150 // Do not enter IPS in the following conditions:
3151 // (1) RF is already OFF or Sleep
3152 // (2) bSwRfProcessing (indicates the IPS is still under going)
3153 // (3) Connectted (only disconnected can trigger IPS)
3154 // (4) IBSS (send Beacon)
3155 // (5) AP mode (send Beacon)
3156 //
3157 if (rtState == eRfOn && !pPSC->bSwRfProcessing
3158 && (priv->ieee80211->state != IEEE80211_LINKED) )
3159 {
3160 RT_TRACE(COMP_RF,"IPSEnter(): Turn off RF.\n");
3161 pPSC->eInactivePowerState = eRfOff;
3162// queue_work(priv->priv_wq,&(pPSC->InactivePsWorkItem));
af59c39d 3163 InactivePsWorkItemCallback(priv);
ecdfa446
GKH		 3164 }
3165 }
3166}
3167
3168//
3169// Description:
3170// Leave the inactive power save mode, RF will be on.
3171// 2007.08.17, by shien chang.
3172//
58f6b58e 3173void IPSLeave(struct r8192_priv *priv)
ecdfa446 3174{
31d664e5 3175 PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
ecdfa446
GKH		 3176 RT_RF_POWER_STATE rtState;
3177
3178 if (pPSC->bInactivePs)
3179 {
4559854d 3180 rtState = priv->eRFPowerState;
181d1dff 3181 if (rtState != eRfOn && !pPSC->bSwRfProcessing && priv->RfOffReason <= RF_CHANGE_BY_IPS)
ecdfa446
GKH		 3182 {
3183 RT_TRACE(COMP_POWER, "IPSLeave(): Turn on RF.\n");
3184 pPSC->eInactivePowerState = eRfOn;
af59c39d 3185 InactivePsWorkItemCallback(priv);
ecdfa446
GKH		 3186 }
3187 }
3188}
65a43784 3189
80a4dead 3190void IPSLeave_wq(struct work_struct *work)
65a43784 3191{
80a4dead 3192 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, ips_leave_wq);
65a43784 3193 struct net_device *dev = ieee->dev;
3194
3195 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
3196 down(&priv->ieee80211->ips_sem);
58f6b58e 3197 IPSLeave(priv);
65a43784 3198 up(&priv->ieee80211->ips_sem);
3199}
3200
3201void ieee80211_ips_leave_wq(struct net_device *dev)
3202{
3203 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
3204 RT_RF_POWER_STATE rtState;
4559854d 3205 rtState = priv->eRFPowerState;
65a43784 3206
31d664e5 3207 if (priv->PowerSaveControl.bInactivePs){
65a43784 3208 if(rtState == eRfOff){
181d1dff 3209 if(priv->RfOffReason > RF_CHANGE_BY_IPS)
65a43784 3210 {
3211 RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__);
3212 return;
3213 }
3214 else{
3215 printk("=========>%s(): IPSLeave\n",__FUNCTION__);
3216 queue_work(priv->ieee80211->wq,&priv->ieee80211->ips_leave_wq);
3217 }
3218 }
3219 }
3220}
3221//added by amy 090331 end
3222void ieee80211_ips_leave(struct net_device *dev)
3223{
3224 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
3225 down(&priv->ieee80211->ips_sem);
58f6b58e 3226 IPSLeave(priv);
65a43784 3227 up(&priv->ieee80211->ips_sem);
3228}
ecdfa446 3229#endif
ecdfa446 3230
5e1ad18a 3231static void rtl819x_update_rxcounts(
ecdfa446
GKH		 3232 struct r8192_priv *priv,
3233 u32* TotalRxBcnNum,
3234 u32* TotalRxDataNum
3235)
3236{
3237 u16 SlotIndex;
3238 u8 i;
3239
3240 *TotalRxBcnNum = 0;
3241 *TotalRxDataNum = 0;
3242
3243 SlotIndex = (priv->ieee80211->LinkDetectInfo.SlotIndex++)%(priv->ieee80211->LinkDetectInfo.SlotNum);
3244 priv->ieee80211->LinkDetectInfo.RxBcnNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod;
3245 priv->ieee80211->LinkDetectInfo.RxDataNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod;
3246 for( i=0; i<priv->ieee80211->LinkDetectInfo.SlotNum; i++ ){
3247 *TotalRxBcnNum += priv->ieee80211->LinkDetectInfo.RxBcnNum[i];
3248 *TotalRxDataNum += priv->ieee80211->LinkDetectInfo.RxDataNum[i];
3249 }
3250}
3251
3252
559fba5e 3253static void rtl819x_watchdog_wqcallback(struct work_struct *work)
ecdfa446
GKH		 3254{
3255 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3256 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,watch_dog_wq);
af59c39d 3257 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 3258 struct ieee80211_device* ieee = priv->ieee80211;
3259 RESET_TYPE ResetType = RESET_TYPE_NORESET;
ecdfa446 3260 bool bBusyTraffic = false;
65a43784 3261 bool bEnterPS = false;
3262
f500e256 3263 if ((!priv->up) || priv->bHwRadioOff)
65a43784 3264 return;
3265
ecdfa446
GKH		 3266 if(!priv->up)
3267 return;
3268 hal_dm_watchdog(dev);
3269#ifdef ENABLE_IPS
ecdfa446 3270 if(ieee->actscanning == false){
207b58fb 3271 if((ieee->iw_mode == IW_MODE_INFRA) && (ieee->state == IEEE80211_NOLINK) &&
4559854d 3272 (priv->eRFPowerState == eRfOn) && !ieee->is_set_key &&
65a43784 3273 (!ieee->proto_stoppping) && !ieee->wx_set_enc){
31d664e5 3274 if (priv->PowerSaveControl.ReturnPoint == IPS_CALLBACK_NONE){
e676ae58 3275 IPSEnter(priv);
ecdfa446
GKH		 3276 }
3277 }
3278 }
3279#endif
3280 {//to get busy traffic condition
3281 if(ieee->state == IEEE80211_LINKED)
3282 {
65a43784 3283 if( ieee->LinkDetectInfo.NumRxOkInPeriod> 100 ||
3284 ieee->LinkDetectInfo.NumTxOkInPeriod> 100 ) {
ecdfa446
GKH		 3285 bBusyTraffic = true;
3286 }
3287
65a43784 3288#ifdef ENABLE_LPS
3289 //added by amy for Leisure PS
3290 if( ((ieee->LinkDetectInfo.NumRxUnicastOkInPeriod + ieee->LinkDetectInfo.NumTxOkInPeriod) > 8 ) ||
3291 (ieee->LinkDetectInfo.NumRxUnicastOkInPeriod > 2) )
3292 {
65a43784 3293 bEnterPS= false;
3294 }
3295 else
3296 {
3297 bEnterPS= true;
3298 }
3299
65a43784 3300 // LeisurePS only work in infra mode.
3301 if(bEnterPS)
3302 {
3303 LeisurePSEnter(dev);
3304 }
3305 else
3306 {
3307 LeisurePSLeave(dev);
3308 }
3309#endif
3310
3311 }
3312 else
3313 {
3314#ifdef ENABLE_LPS
65a43784 3315 LeisurePSLeave(dev);
3316#endif
ecdfa446 3317 }
65a43784 3318
ecdfa446
GKH		 3319 ieee->LinkDetectInfo.NumRxOkInPeriod = 0;
3320 ieee->LinkDetectInfo.NumTxOkInPeriod = 0;
65a43784 3321 ieee->LinkDetectInfo.NumRxUnicastOkInPeriod = 0;
ecdfa446
GKH		 3322 ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
3323 }
3324
3325
3326 //added by amy for AP roaming
ecdfa446
GKH		 3327 if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA)
3328 {
3329 u32 TotalRxBcnNum = 0;
3330 u32 TotalRxDataNum = 0;
3331
3332 rtl819x_update_rxcounts(priv, &TotalRxBcnNum, &TotalRxDataNum);
3333 if((TotalRxBcnNum+TotalRxDataNum) == 0)
3334 {
4559854d 3335 if (priv->eRFPowerState == eRfOff)
ecdfa446
GKH		 3336 RT_TRACE(COMP_ERR,"========>%s()\n",__FUNCTION__);
3337 printk("===>%s(): AP is power off,connect another one\n",__FUNCTION__);
65a43784 3338 // Dot11d_Reset(dev);
ecdfa446
GKH		 3339 ieee->state = IEEE80211_ASSOCIATING;
3340 notify_wx_assoc_event(priv->ieee80211);
65a43784 3341 RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid);
ecdfa446
GKH		 3342 ieee->is_roaming = true;
3343 ieee->is_set_key = false;
65a43784 3344 ieee->link_change(dev);
3345 queue_work(ieee->wq, &ieee->associate_procedure_wq);
ecdfa446
GKH		 3346 }
3347 }
3348 ieee->LinkDetectInfo.NumRecvBcnInPeriod=0;
3349 ieee->LinkDetectInfo.NumRecvDataInPeriod=0;
3350
ecdfa446 3351 //check if reset the driver
d5fdaa3a
MM		 3352 if (priv->watchdog_check_reset_cnt++ >= 3 && !ieee->is_roaming &&
3353 priv->watchdog_last_time != 1)
ecdfa446 3354 {
af59c39d 3355 ResetType = rtl819x_ifcheck_resetornot(priv);
d5fdaa3a 3356 priv->watchdog_check_reset_cnt = 3;
ecdfa446 3357 }
ecdfa446
GKH		 3358 if(!priv->bDisableNormalResetCheck && ResetType == RESET_TYPE_NORMAL)
3359 {
3360 priv->ResetProgress = RESET_TYPE_NORMAL;
3361 RT_TRACE(COMP_RESET,"%s(): NOMAL RESET\n",__FUNCTION__);
3362 return;
3363 }
3364 /* disable silent reset temply 2008.9.11*/
11aacc28 3365
ecdfa446
GKH		 3366 if( ((priv->force_reset) || (!priv->bDisableNormalResetCheck && ResetType==RESET_TYPE_SILENT))) // This is control by OID set in Pomelo
3367 {
d5fdaa3a 3368 priv->watchdog_last_time = 1;
ecdfa446
GKH		 3369 }
3370 else
d5fdaa3a 3371 priv->watchdog_last_time = 0;
11aacc28 3372
ecdfa446
GKH		 3373 priv->force_reset = false;
3374 priv->bForcedSilentReset = false;
3375 priv->bResetInProgress = false;
3376 RT_TRACE(COMP_TRACE, " <==RtUsbCheckForHangWorkItemCallback()\n");
3377
3378}
3379
3380void watch_dog_timer_callback(unsigned long data)
3381{
1f0e4270 3382 struct r8192_priv *priv = (struct r8192_priv *) data;
ecdfa446 3383 queue_delayed_work(priv->priv_wq,&priv->watch_dog_wq,0);
ecdfa446
GKH		 3384 mod_timer(&priv->watch_dog_timer, jiffies + MSECS(IEEE80211_WATCH_DOG_TIME));
3385
3386}
5b3b1a7b 3387
af59c39d 3388static int _rtl8192_up(struct r8192_priv *priv)
ecdfa446 3389{
ecdfa446 3390 RT_STATUS init_status = RT_STATUS_SUCCESS;
af59c39d
MM		 3391 struct net_device *dev = priv->ieee80211->dev;
3392
ecdfa446
GKH		 3393 priv->up=1;
3394 priv->ieee80211->ieee_up=1;
65a43784 3395 priv->bdisable_nic = false; //YJ,add,091111
703fdcc3 3396 RT_TRACE(COMP_INIT, "Bringing up iface\n");
ecdfa446 3397
af59c39d 3398 init_status = rtl8192_adapter_start(priv);
ecdfa446
GKH		 3399 if(init_status != RT_STATUS_SUCCESS)
3400 {
3401 RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n",__FUNCTION__);
3402 return -1;
3403 }
3404 RT_TRACE(COMP_INIT, "start adapter finished\n");
4803ef77 3405
4559854d 3406 if (priv->eRFPowerState != eRfOn)
262cd816 3407 MgntActSet_RF_State(priv, eRfOn, priv->RfOffReason);
4803ef77 3408
ecdfa446
GKH		 3409 if(priv->ieee80211->state != IEEE80211_LINKED)
3410 ieee80211_softmac_start_protocol(priv->ieee80211);
3411 ieee80211_reset_queue(priv->ieee80211);
1f0e4270 3412 watch_dog_timer_callback((unsigned long) priv);
ecdfa446
GKH		 3413 if(!netif_queue_stopped(dev))
3414 netif_start_queue(dev);
3415 else
3416 netif_wake_queue(dev);
3417
3418 return 0;
3419}
3420
3421
5e1ad18a 3422static int rtl8192_open(struct net_device *dev)
ecdfa446
GKH		 3423{
3424 struct r8192_priv *priv = ieee80211_priv(dev);
3425 int ret;
3426
3427 down(&priv->wx_sem);
3428 ret = rtl8192_up(dev);
3429 up(&priv->wx_sem);
3430 return ret;
3431
3432}
3433
3434
3435int rtl8192_up(struct net_device *dev)
3436{
3437 struct r8192_priv *priv = ieee80211_priv(dev);
3438
3439 if (priv->up == 1) return -1;
3440
af59c39d 3441 return _rtl8192_up(priv);
ecdfa446
GKH		 3442}
3443
3444
5e1ad18a 3445static int rtl8192_close(struct net_device *dev)
ecdfa446
GKH		 3446{
3447 struct r8192_priv *priv = ieee80211_priv(dev);
3448 int ret;
3449
3450 down(&priv->wx_sem);
3451
3452 ret = rtl8192_down(dev);
3453
3454 up(&priv->wx_sem);
3455
3456 return ret;
3457
3458}
3459
3460int rtl8192_down(struct net_device *dev)
3461{
3462 struct r8192_priv *priv = ieee80211_priv(dev);
16d74da0 3463
ecdfa446
GKH		 3464 if (priv->up == 0) return -1;
3465
65a43784 3466#ifdef ENABLE_LPS
3467 //LZM for PS-Poll AID issue. 090429
3468 if(priv->ieee80211->state == IEEE80211_LINKED)
3469 LeisurePSLeave(dev);
3470#endif
3471
ecdfa446
GKH		 3472 priv->up=0;
3473 priv->ieee80211->ieee_up = 0;
3474 RT_TRACE(COMP_DOWN, "==========>%s()\n", __FUNCTION__);
3475/* FIXME */
3476 if (!netif_queue_stopped(dev))
3477 netif_stop_queue(dev);
3478
af59c39d 3479 rtl8192_irq_disable(priv);
ecdfa446
GKH		 3480 rtl8192_cancel_deferred_work(priv);
3481 deinit_hal_dm(dev);
3482 del_timer_sync(&priv->watch_dog_timer);
3483
65a43784 3484 ieee80211_softmac_stop_protocol(priv->ieee80211,true);
3485
af59c39d 3486 rtl8192_halt_adapter(priv, false);
ecdfa446
GKH		 3487 memset(&priv->ieee80211->current_network, 0 , offsetof(struct ieee80211_network, list));
3488
3489 RT_TRACE(COMP_DOWN, "<==========%s()\n", __FUNCTION__);
3490
16d74da0 3491 return 0;
ecdfa446
GKH		 3492}
3493
3494
af59c39d 3495void rtl8192_commit(struct r8192_priv *priv)
ecdfa446 3496{
ecdfa446
GKH		 3497 if (priv->up == 0) return ;
3498
3499
65a43784 3500 ieee80211_softmac_stop_protocol(priv->ieee80211,true);
ecdfa446 3501
af59c39d
MM		 3502 rtl8192_irq_disable(priv);
3503 rtl8192_halt_adapter(priv, true);
3504 _rtl8192_up(priv);
ecdfa446
GKH		 3505}
3506
5b3b1a7b 3507static void rtl8192_restart(struct work_struct *work)
ecdfa446
GKH		 3508{
3509 struct r8192_priv *priv = container_of(work, struct r8192_priv, reset_wq);
ecdfa446
GKH		 3510
3511 down(&priv->wx_sem);
3512
af59c39d 3513 rtl8192_commit(priv);
ecdfa446
GKH		 3514
3515 up(&priv->wx_sem);
3516}
3517
3518static void r8192_set_multicast(struct net_device *dev)
3519{
3520 struct r8192_priv *priv = ieee80211_priv(dev);
ecdfa446 3521
109ded2b 3522 priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
ecdfa446
GKH		 3523}
3524
3525
5e1ad18a 3526static int r8192_set_mac_adr(struct net_device *dev, void *mac)
ecdfa446
GKH		 3527{
3528 struct r8192_priv *priv = ieee80211_priv(dev);
3529 struct sockaddr *addr = mac;
3530
3531 down(&priv->wx_sem);
3532
3533 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3534
ecdfa446 3535 schedule_work(&priv->reset_wq);
ecdfa446
GKH		 3536 up(&priv->wx_sem);
3537
3538 return 0;
3539}
3540
4573d145
MM		 3541static void r8192e_set_hw_key(struct r8192_priv *priv, struct ieee_param *ipw)
3542{
3543 struct ieee80211_device *ieee = priv->ieee80211;
4573d145
MM		 3544 u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
3545 u32 key[4];
3546
3547 if (ipw->u.crypt.set_tx) {
3548 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
3549 ieee->pairwise_key_type = KEY_TYPE_CCMP;
3550 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
3551 ieee->pairwise_key_type = KEY_TYPE_TKIP;
3552 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) {
3553 if (ipw->u.crypt.key_len == 13)
3554 ieee->pairwise_key_type = KEY_TYPE_WEP104;
3555 else if (ipw->u.crypt.key_len == 5)
3556 ieee->pairwise_key_type = KEY_TYPE_WEP40;
3557 } else
3558 ieee->pairwise_key_type = KEY_TYPE_NA;
3559
3560 if (ieee->pairwise_key_type) {
3561 memcpy(key, ipw->u.crypt.key, 16);
282fa9f3 3562 EnableHWSecurityConfig8192(priv);
4573d145
MM		 3563 /*
3564 * We fill both index entry and 4th entry for pairwise
3565 * key as in IPW interface, adhoc will only get here,
3566 * so we need index entry for its default key serching!
3567 */
043dfdd3 3568 setKey(priv, 4, ipw->u.crypt.idx,
4573d145
MM		 3569 ieee->pairwise_key_type,
3570 (u8*)ieee->ap_mac_addr, 0, key);
3571
3572 /* LEAP WEP will never set this. */
3573 if (ieee->auth_mode != 2)
043dfdd3 3574 setKey(priv, ipw->u.crypt.idx, ipw->u.crypt.idx,
4573d145
MM		 3575 ieee->pairwise_key_type,
3576 (u8*)ieee->ap_mac_addr, 0, key);
3577 }
3578 if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) &&
3579 ieee->pHTInfo->bCurrentHTSupport) {
3580 write_nic_byte(priv, 0x173, 1); /* fix aes bug */
3581 }
3582 } else {
3583 memcpy(key, ipw->u.crypt.key, 16);
3584 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
3585 ieee->group_key_type= KEY_TYPE_CCMP;
3586 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
3587 ieee->group_key_type = KEY_TYPE_TKIP;
3588 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) {
3589 if (ipw->u.crypt.key_len == 13)
3590 ieee->group_key_type = KEY_TYPE_WEP104;
3591 else if (ipw->u.crypt.key_len == 5)
3592 ieee->group_key_type = KEY_TYPE_WEP40;
3593 } else
3594 ieee->group_key_type = KEY_TYPE_NA;
3595
3596 if (ieee->group_key_type) {
043dfdd3 3597 setKey(priv, ipw->u.crypt.idx, ipw->u.crypt.idx,
4573d145
MM		 3598 ieee->group_key_type, broadcast_addr, 0, key);
3599 }
3600 }
3601}
3602
ecdfa446 3603/* based on ipw2200 driver */
5e1ad18a 3604static int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
ecdfa446
GKH		 3605{
3606 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
3607 struct iwreq *wrq = (struct iwreq *)rq;
3608 int ret=-1;
ecdfa446
GKH		 3609 struct iw_point *p = &wrq->u.data;
3610 struct ieee_param *ipw = NULL;//(struct ieee_param *)wrq->u.data.pointer;
3611
3612 down(&priv->wx_sem);
3613
3614
3615 if (p->length < sizeof(struct ieee_param) || !p->pointer){
3616 ret = -EINVAL;
3617 goto out;
3618 }
3619
32414878 3620 ipw = kmalloc(p->length, GFP_KERNEL);
ecdfa446
GKH		 3621 if (ipw == NULL){
3622 ret = -ENOMEM;
3623 goto out;
3624 }
3625 if (copy_from_user(ipw, p->pointer, p->length)) {
3626 kfree(ipw);
3627 ret = -EFAULT;
3628 goto out;
3629 }
3630
3631 switch (cmd) {
4573d145
MM		 3632 case RTL_IOCTL_WPA_SUPPLICANT:
3633 /* parse here for HW security */
3634 if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION)
3635 r8192e_set_hw_key(priv, ipw);
ecdfa446
GKH		 3636 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
3637 break;
3638
4573d145 3639 default:
ecdfa446
GKH		 3640 ret = -EOPNOTSUPP;
3641 break;
3642 }
3643
3644 kfree(ipw);
3645out:
3646 up(&priv->wx_sem);
3647
3648 return ret;
3649}
3650
5e1ad18a 3651static u8 HwRateToMRate90(bool bIsHT, u8 rate)
ecdfa446
GKH		 3652{
3653 u8 ret_rate = 0x02;
3654
3655 if(!bIsHT) {
3656 switch(rate) {
3657 case DESC90_RATE1M: ret_rate = MGN_1M; break;
3658 case DESC90_RATE2M: ret_rate = MGN_2M; break;
3659 case DESC90_RATE5_5M: ret_rate = MGN_5_5M; break;
3660 case DESC90_RATE11M: ret_rate = MGN_11M; break;
3661 case DESC90_RATE6M: ret_rate = MGN_6M; break;
3662 case DESC90_RATE9M: ret_rate = MGN_9M; break;
3663 case DESC90_RATE12M: ret_rate = MGN_12M; break;
3664 case DESC90_RATE18M: ret_rate = MGN_18M; break;
3665 case DESC90_RATE24M: ret_rate = MGN_24M; break;
3666 case DESC90_RATE36M: ret_rate = MGN_36M; break;
3667 case DESC90_RATE48M: ret_rate = MGN_48M; break;
3668 case DESC90_RATE54M: ret_rate = MGN_54M; break;
3669
3670 default:
3671 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
3672 break;
3673 }
3674
3675 } else {
3676 switch(rate) {
3677 case DESC90_RATEMCS0: ret_rate = MGN_MCS0; break;
3678 case DESC90_RATEMCS1: ret_rate = MGN_MCS1; break;
3679 case DESC90_RATEMCS2: ret_rate = MGN_MCS2; break;
3680 case DESC90_RATEMCS3: ret_rate = MGN_MCS3; break;
3681 case DESC90_RATEMCS4: ret_rate = MGN_MCS4; break;
3682 case DESC90_RATEMCS5: ret_rate = MGN_MCS5; break;
3683 case DESC90_RATEMCS6: ret_rate = MGN_MCS6; break;
3684 case DESC90_RATEMCS7: ret_rate = MGN_MCS7; break;
3685 case DESC90_RATEMCS8: ret_rate = MGN_MCS8; break;
3686 case DESC90_RATEMCS9: ret_rate = MGN_MCS9; break;
3687 case DESC90_RATEMCS10: ret_rate = MGN_MCS10; break;
3688 case DESC90_RATEMCS11: ret_rate = MGN_MCS11; break;
3689 case DESC90_RATEMCS12: ret_rate = MGN_MCS12; break;
3690 case DESC90_RATEMCS13: ret_rate = MGN_MCS13; break;
3691 case DESC90_RATEMCS14: ret_rate = MGN_MCS14; break;
3692 case DESC90_RATEMCS15: ret_rate = MGN_MCS15; break;
3693 case DESC90_RATEMCS32: ret_rate = (0x80|0x20); break;
3694
3695 default:
3696 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT);
3697 break;
3698 }
3699 }
3700
3701 return ret_rate;
3702}
3703
214985a6 3704/* Record the TSF time stamp when receiving a packet */
95a9a653 3705static void UpdateRxPktTimeStamp8190(struct r8192_priv *priv, struct ieee80211_rx_stats *stats)
ecdfa446 3706{
ecdfa446
GKH		 3707
3708 if(stats->bIsAMPDU && !stats->bFirstMPDU) {
3709 stats->mac_time[0] = priv->LastRxDescTSFLow;
3710 stats->mac_time[1] = priv->LastRxDescTSFHigh;
3711 } else {
3712 priv->LastRxDescTSFLow = stats->mac_time[0];
3713 priv->LastRxDescTSFHigh = stats->mac_time[1];
3714 }
3715}
3716
5e1ad18a 3717static long rtl819x_translate_todbm(u8 signal_strength_index)// 0-100 index.
ecdfa446
GKH		 3718{
3719 long signal_power; // in dBm.
3720
3721 // Translate to dBm (x=0.5y-95).
3722 signal_power = (long)((signal_strength_index + 1) >> 1);
3723 signal_power -= 95;
3724
3725 return signal_power;
3726}
3727
ecdfa446
GKH		 3728/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to
3729 be a local static. Otherwise, it may increase when we return from S3/S4. The
3730 value will be kept in memory or disk. We must delcare the value in adapter
3731 and it will be reinitialized when return from S3/S4. */
5e1ad18a 3732static void rtl8192_process_phyinfo(struct r8192_priv * priv, u8* buffer,struct ieee80211_rx_stats * pprevious_stats, struct ieee80211_rx_stats * pcurrent_stats)
ecdfa446
GKH		 3733{
3734 bool bcheck = false;
3735 u8 rfpath;
3736 u32 nspatial_stream, tmp_val;
ecdfa446
GKH		 3737 static u32 slide_rssi_index=0, slide_rssi_statistics=0;
3738 static u32 slide_evm_index=0, slide_evm_statistics=0;
3739 static u32 last_rssi=0, last_evm=0;
ecdfa446
GKH		 3740 //cosa add for beacon rssi smoothing
3741 static u32 slide_beacon_adc_pwdb_index=0, slide_beacon_adc_pwdb_statistics=0;
3742 static u32 last_beacon_adc_pwdb=0;
3743
3744 struct ieee80211_hdr_3addr *hdr;
3745 u16 sc ;
3746 unsigned int frag,seq;
3747 hdr = (struct ieee80211_hdr_3addr *)buffer;
3748 sc = le16_to_cpu(hdr->seq_ctl);
3749 frag = WLAN_GET_SEQ_FRAG(sc);
3750 seq = WLAN_GET_SEQ_SEQ(sc);
3751 //cosa add 04292008 to record the sequence number
3752 pcurrent_stats->Seq_Num = seq;
3753 //
3754 // Check whether we should take the previous packet into accounting
3755 //
3756 if(!pprevious_stats->bIsAMPDU)
3757 {
3758 // if previous packet is not aggregated packet
3759 bcheck = true;
ecdfa446
GKH		 3760 }
3761
3762 if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX)
3763 {
3764 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
3765 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
3766 priv->stats.slide_rssi_total -= last_rssi;
3767 }
3768 priv->stats.slide_rssi_total += pprevious_stats->SignalStrength;
3769
3770 priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength;
3771 if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
3772 slide_rssi_index = 0;
3773
3774 // <1> Showed on UI for user, in dbm
3775 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
3776 priv->stats.signal_strength = rtl819x_translate_todbm((u8)tmp_val);
3777 pcurrent_stats->rssi = priv->stats.signal_strength;
3778 //
3779 // If the previous packet does not match the criteria, neglect it
3780 //
3781 if(!pprevious_stats->bPacketMatchBSSID)
3782 {
3783 if(!pprevious_stats->bToSelfBA)
3784 return;
3785 }
3786
3787 if(!bcheck)
3788 return;
3789
ecdfa446
GKH		 3790 // <2> Showed on UI for engineering
3791 // hardware does not provide rssi information for each rf path in CCK
3792 if(!pprevious_stats->bIsCCK && pprevious_stats->bPacketToSelf)
3793 {
3794 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++)
3795 {
d9ffa6c2 3796 if (!rtl8192_phy_CheckIsLegalRFPath(priv, rfpath))
ecdfa446 3797 continue;
703fdcc3 3798 RT_TRACE(COMP_DBG, "pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n", pprevious_stats->RxMIMOSignalStrength[rfpath]);
ecdfa446
GKH		 3799 //Fixed by Jacken 2008-03-20
3800 if(priv->stats.rx_rssi_percentage[rfpath] == 0)
3801 {
3802 priv->stats.rx_rssi_percentage[rfpath] = pprevious_stats->RxMIMOSignalStrength[rfpath];
ecdfa446
GKH		 3803 }
3804 if(pprevious_stats->RxMIMOSignalStrength[rfpath] > priv->stats.rx_rssi_percentage[rfpath])
3805 {
3806 priv->stats.rx_rssi_percentage[rfpath] =
3807 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
3808 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
3809 priv->stats.rx_rssi_percentage[rfpath] = priv->stats.rx_rssi_percentage[rfpath] + 1;
3810 }
3811 else
3812 {
3813 priv->stats.rx_rssi_percentage[rfpath] =
3814 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
3815 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
3816 }
703fdcc3 3817 RT_TRACE(COMP_DBG, "priv->RxStats.RxRSSIPercentage[rfPath] = %d \n" , priv->stats.rx_rssi_percentage[rfpath]);
ecdfa446
GKH		 3818 }
3819 }
3820
3821
3822 //
3823 // Check PWDB.
3824 //
3825 //cosa add for beacon rssi smoothing by average.
3826 if(pprevious_stats->bPacketBeacon)
3827 {
3828 /* record the beacon pwdb to the sliding window. */
3829 if(slide_beacon_adc_pwdb_statistics++ >= PHY_Beacon_RSSI_SLID_WIN_MAX)
3830 {
3831 slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX;
3832 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index];
3833 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
ecdfa446
GKH		 3834 // slide_beacon_adc_pwdb_index, last_beacon_adc_pwdb, Adapter->RxStats.Slide_Beacon_Total);
3835 }
3836 priv->stats.Slide_Beacon_Total += pprevious_stats->RxPWDBAll;
3837 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = pprevious_stats->RxPWDBAll;
ecdfa446
GKH		 3838 slide_beacon_adc_pwdb_index++;
3839 if(slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
3840 slide_beacon_adc_pwdb_index = 0;
3841 pprevious_stats->RxPWDBAll = priv->stats.Slide_Beacon_Total/slide_beacon_adc_pwdb_statistics;
3842 if(pprevious_stats->RxPWDBAll >= 3)
3843 pprevious_stats->RxPWDBAll -= 3;
3844 }
3845
3846 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
3847 pprevious_stats->bIsCCK? "CCK": "OFDM",
3848 pprevious_stats->RxPWDBAll);
3849
3850 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
3851 {
3852 if(priv->undecorated_smoothed_pwdb < 0) // initialize
3853 {
3854 priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll;
ecdfa446 3855 }
11aacc28 3856
ecdfa446
GKH		 3857 if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb)
3858 {
3859 priv->undecorated_smoothed_pwdb =
3860 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
3861 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
3862 priv->undecorated_smoothed_pwdb = priv->undecorated_smoothed_pwdb + 1;
3863 }
3864 else
3865 {
3866 priv->undecorated_smoothed_pwdb =
3867 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
3868 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
3869 }
ecdfa446
GKH		 3870 }
3871
3872 //
3873 // Check EVM
3874 //
3875 /* record the general EVM to the sliding window. */
3876 if(pprevious_stats->SignalQuality == 0)
3877 {
3878 }
3879 else
3880 {
3881 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA){
3882 if(slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX){
3883 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
3884 last_evm = priv->stats.slide_evm[slide_evm_index];
3885 priv->stats.slide_evm_total -= last_evm;
3886 }
3887
3888 priv->stats.slide_evm_total += pprevious_stats->SignalQuality;
3889
3890 priv->stats.slide_evm[slide_evm_index++] = pprevious_stats->SignalQuality;
3891 if(slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
3892 slide_evm_index = 0;
3893
3894 // <1> Showed on UI for user, in percentage.
3895 tmp_val = priv->stats.slide_evm_total/slide_evm_statistics;
ecdfa446 3896 //cosa add 10/11/2007, Showed on UI for user in Windows Vista, for Link quality.
ecdfa446
GKH		 3897 }
3898
3899 // <2> Showed on UI for engineering
3900 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
3901 {
3902 for(nspatial_stream = 0; nspatial_stream<2 ; nspatial_stream++) // 2 spatial stream
3903 {
3904 if(pprevious_stats->RxMIMOSignalQuality[nspatial_stream] != -1)
3905 {
3906 if(priv->stats.rx_evm_percentage[nspatial_stream] == 0) // initialize
3907 {
3908 priv->stats.rx_evm_percentage[nspatial_stream] = pprevious_stats->RxMIMOSignalQuality[nspatial_stream];
3909 }
3910 priv->stats.rx_evm_percentage[nspatial_stream] =
3911 ( (priv->stats.rx_evm_percentage[nspatial_stream]* (Rx_Smooth_Factor-1)) +
3912 (pprevious_stats->RxMIMOSignalQuality[nspatial_stream]* 1)) / (Rx_Smooth_Factor);
3913 }
3914 }
3915 }
3916 }
3917
3918}
3919
ecdfa446
GKH		 3920static u8 rtl819x_query_rxpwrpercentage(
3921 char antpower
3922 )
3923{
3924 if ((antpower <= -100) || (antpower >= 20))
3925 {
3926 return 0;
3927 }
3928 else if (antpower >= 0)
3929 {
3930 return 100;
3931 }
3932 else
3933 {
3934 return (100+antpower);
3935 }
3936
d5abdf72 3937}
ecdfa446
GKH		 3938
3939static u8
3940rtl819x_evm_dbtopercentage(
3941 char value
3942 )
3943{
3944 char ret_val;
3945
3946 ret_val = value;
3947
3948 if(ret_val >= 0)
3949 ret_val = 0;
3950 if(ret_val <= -33)
3951 ret_val = -33;
3952 ret_val = 0 - ret_val;
3953 ret_val*=3;
3954 if(ret_val == 99)
3955 ret_val = 100;
c6eae677 3956 return ret_val;
ecdfa446
GKH		 3957}
3958
214985a6 3959/* We want good-looking for signal strength/quality */
5e1ad18a 3960static long rtl819x_signal_scale_mapping(long currsig)
ecdfa446
GKH		 3961{
3962 long retsig;
3963
3964 // Step 1. Scale mapping.
3965 if(currsig >= 61 && currsig <= 100)
3966 {
3967 retsig = 90 + ((currsig - 60) / 4);
3968 }
3969 else if(currsig >= 41 && currsig <= 60)
3970 {
3971 retsig = 78 + ((currsig - 40) / 2);
3972 }
3973 else if(currsig >= 31 && currsig <= 40)
3974 {
3975 retsig = 66 + (currsig - 30);
3976 }
3977 else if(currsig >= 21 && currsig <= 30)
3978 {
3979 retsig = 54 + (currsig - 20);
3980 }
3981 else if(currsig >= 5 && currsig <= 20)
3982 {
3983 retsig = 42 + (((currsig - 5) * 2) / 3);
3984 }
3985 else if(currsig == 4)
3986 {
3987 retsig = 36;
3988 }
3989 else if(currsig == 3)
3990 {
3991 retsig = 27;
3992 }
3993 else if(currsig == 2)
3994 {
3995 retsig = 18;
3996 }
3997 else if(currsig == 1)
3998 {
3999 retsig = 9;
4000 }
4001 else
4002 {
4003 retsig = currsig;
4004 }
4005
4006 return retsig;
4007}
4008
4009static void rtl8192_query_rxphystatus(
4010 struct r8192_priv * priv,
4011 struct ieee80211_rx_stats * pstats,
4012 prx_desc_819x_pci pdesc,
4013 prx_fwinfo_819x_pci pdrvinfo,
4014 struct ieee80211_rx_stats * precord_stats,
4015 bool bpacket_match_bssid,
4016 bool bpacket_toself,
4017 bool bPacketBeacon,
4018 bool bToSelfBA
4019 )
4020{
4021 //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status);
4022 phy_sts_ofdm_819xpci_t* pofdm_buf;
4023 phy_sts_cck_819xpci_t * pcck_buf;
4024 phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc;
4025 u8 *prxpkt;
4026 u8 i,max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
4027 char rx_pwr[4], rx_pwr_all=0;
4028 //long rx_avg_pwr = 0;
4029 char rx_snrX, rx_evmX;
4030 u8 evm, pwdb_all;
4031 u32 RSSI, total_rssi=0;//, total_evm=0;
4032// long signal_strength_index = 0;
4033 u8 is_cck_rate=0;
4034 u8 rf_rx_num = 0;
4035
ecdfa446
GKH		 4036 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
4037
4038 // Record it for next packet processing
4039 memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats));
4040 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid;
4041 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
4042 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo);
4043 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
4044 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
4045 /*2007.08.30 requested by SD3 Jerry */
d163f324 4046 if (priv->phy_check_reg824 == 0)
ecdfa446 4047 {
d9ffa6c2 4048 priv->phy_reg824_bit9 = rtl8192_QueryBBReg(priv, rFPGA0_XA_HSSIParameter2, 0x200);
d163f324 4049 priv->phy_check_reg824 = 1;
ecdfa446
GKH		 4050 }
4051
4052
4053 prxpkt = (u8*)pdrvinfo;
4054
4055 /* Move pointer to the 16th bytes. Phy status start address. */
4056 prxpkt += sizeof(rx_fwinfo_819x_pci);
4057
4058 /* Initial the cck and ofdm buffer pointer */
4059 pcck_buf = (phy_sts_cck_819xpci_t *)prxpkt;
4060 pofdm_buf = (phy_sts_ofdm_819xpci_t *)prxpkt;
4061
4062 pstats->RxMIMOSignalQuality[0] = -1;
4063 pstats->RxMIMOSignalQuality[1] = -1;
4064 precord_stats->RxMIMOSignalQuality[0] = -1;
4065 precord_stats->RxMIMOSignalQuality[1] = -1;
4066
4067 if(is_cck_rate)
4068 {
4069 //
4070 // (1)Hardware does not provide RSSI for CCK
4071 //
4072
4073 //
4074 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
4075 //
4076 u8 report;//, cck_agc_rpt;
ecdfa446 4077
d163f324 4078 if (!priv->phy_reg824_bit9)
ecdfa446
GKH		 4079 {
4080 report = pcck_buf->cck_agc_rpt & 0xc0;
4081 report = report>>6;
4082 switch(report)
4083 {
4084 //Fixed by Jacken from Bryant 2008-03-20
4085 //Original value is -38 , -26 , -14 , -2
4086 //Fixed value is -35 , -23 , -11 , 6
4087 case 0x3:
4088 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e);
4089 break;
4090 case 0x2:
4091 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e);
4092 break;
4093 case 0x1:
4094 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e);
4095 break;
4096 case 0x0:
4097 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
4098 break;
4099 }
4100 }
4101 else
4102 {
4103 report = pcck_buf->cck_agc_rpt & 0x60;
4104 report = report>>5;
4105 switch(report)
4106 {
4107 case 0x3:
4108 rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
4109 break;
4110 case 0x2:
4111 rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1);
4112 break;
4113 case 0x1:
4114 rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
4115 break;
4116 case 0x0:
4117 rx_pwr_all = -8 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
4118 break;
4119 }
4120 }
4121
4122 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
4123 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
4124 pstats->RecvSignalPower = rx_pwr_all;
4125
4126 //
4127 // (3) Get Signal Quality (EVM)
4128 //
4129 if(bpacket_match_bssid)
4130 {
4131 u8 sq;
4132
4133 if(pstats->RxPWDBAll > 40)
4134 {
4135 sq = 100;
4136 }else
4137 {
4138 sq = pcck_buf->sq_rpt;
4139
4140 if(pcck_buf->sq_rpt > 64)
4141 sq = 0;
4142 else if (pcck_buf->sq_rpt < 20)
4143 sq = 100;
4144 else
4145 sq = ((64-sq) * 100) / 44;
4146 }
4147 pstats->SignalQuality = precord_stats->SignalQuality = sq;
4148 pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq;
4149 pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1;
4150 }
4151 }
4152 else
4153 {
ecdfa446
GKH		 4154 //
4155 // (1)Get RSSI for HT rate
4156 //
4157 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
4158 {
4159 // 2008/01/30 MH we will judge RF RX path now.
4160 if (priv->brfpath_rxenable[i])
4161 rf_rx_num++;
4162 //else
4163 //continue;
4164
4165 //Fixed by Jacken from Bryant 2008-03-20
4166 //Original value is 106
ecdfa446 4167 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 110;
ecdfa446
GKH		 4168
4169 //Get Rx snr value in DB
4170 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
4171 rx_snrX = (char)(tmp_rxsnr);
4172 rx_snrX /= 2;
ecdfa446
GKH		 4173
4174 /* Translate DBM to percentage. */
4175 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
4176 if (priv->brfpath_rxenable[i])
4177 total_rssi += RSSI;
4178
4179 /* Record Signal Strength for next packet */
4180 if(bpacket_match_bssid)
4181 {
4182 pstats->RxMIMOSignalStrength[i] =(u8) RSSI;
4183 precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI;
4184 }
4185 }
4186
4187
4188 //
4189 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
4190 //
4191 //Fixed by Jacken from Bryant 2008-03-20
4192 //Original value is 106
4193 rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106;
4194 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
4195
4196 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
4197 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
4198 pstats->RecvSignalPower = rx_pwr_all;
4199 //
4200 // (3)EVM of HT rate
4201 //
4202 if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 &&
4203 pdrvinfo->RxRate<=DESC90_RATEMCS15)
4204 max_spatial_stream = 2; //both spatial stream make sense
4205 else
4206 max_spatial_stream = 1; //only spatial stream 1 makes sense
4207
4208 for(i=0; i<max_spatial_stream; i++)
4209 {
4210 tmp_rxevm = pofdm_buf->rxevm_X[i];
4211 rx_evmX = (char)(tmp_rxevm);
4212
4213 // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
4214 // fill most significant bit to "zero" when doing shifting operation which may change a negative
4215 // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
4216 rx_evmX /= 2; //dbm
4217
4218 evm = rtl819x_evm_dbtopercentage(rx_evmX);
ecdfa446
GKH		 4219 if(bpacket_match_bssid)
4220 {
4221 if(i==0) // Fill value in RFD, Get the first spatial stream only
4222 pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff);
4223 pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff);
4224 }
4225 }
4226
4227
4228 /* record rx statistics for debug */
4229 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
4230 prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg;
ecdfa446
GKH		 4231 }
4232
4233 //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
4234 //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
4235 if(is_cck_rate)
4236 {
4237 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;
4238
4239 }
4240 else
4241 {
4242 //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u1Byte)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u1Byte)(total_rssi/=RF90_PATH_MAX);
4243 // We can judge RX path number now.
4244 if (rf_rx_num != 0)
4245 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num)));
4246 }
d5abdf72 4247}
ecdfa446 4248
5e1ad18a 4249static void
ecdfa446
GKH		 4250rtl8192_record_rxdesc_forlateruse(
4251 struct ieee80211_rx_stats * psrc_stats,
4252 struct ieee80211_rx_stats * ptarget_stats
4253)
4254{
4255 ptarget_stats->bIsAMPDU = psrc_stats->bIsAMPDU;
4256 ptarget_stats->bFirstMPDU = psrc_stats->bFirstMPDU;
4257 //ptarget_stats->Seq_Num = psrc_stats->Seq_Num;
4258}
4259
4260
4261
9633608f 4262static void TranslateRxSignalStuff819xpci(struct r8192_priv *priv,
ecdfa446
GKH		 4263 struct sk_buff *skb,
4264 struct ieee80211_rx_stats * pstats,
4265 prx_desc_819x_pci pdesc,
4266 prx_fwinfo_819x_pci pdrvinfo)
4267{
4268 // TODO: We must only check packet for current MAC address. Not finish
ecdfa446
GKH		 4269 bool bpacket_match_bssid, bpacket_toself;
4270 bool bPacketBeacon=false, bToSelfBA=false;
ecdfa446
GKH		 4271 struct ieee80211_hdr_3addr *hdr;
4272 u16 fc,type;
4273
4274 // Get Signal Quality for only RX data queue (but not command queue)
4275
4276 u8* tmp_buf;
4277 u8 *praddr;
4278
4279 /* Get MAC frame start address. */
4280 tmp_buf = skb->data;
4281
4282 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
4283 fc = le16_to_cpu(hdr->frame_ctl);
4284 type = WLAN_FC_GET_TYPE(fc);
4285 praddr = hdr->addr1;
4286
4287 /* Check if the received packet is acceptabe. */
4288 bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) &&
03996954 4289 (!compare_ether_addr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
ecdfa446 4290 && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
03996954 4291 bpacket_toself = bpacket_match_bssid & (!compare_ether_addr(praddr, priv->ieee80211->dev->dev_addr));
11aacc28 4292
ecdfa446
GKH		 4293 if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
4294 {
4295 bPacketBeacon = true;
ecdfa446
GKH		 4296 }
4297 if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK)
4298 {
9633608f 4299 if (!compare_ether_addr(praddr, priv->ieee80211->dev->dev_addr))
ecdfa446 4300 bToSelfBA = true;
ecdfa446
GKH		 4301 }
4302
ecdfa446
GKH		 4303 //
4304 // Process PHY information for previous packet (RSSI/PWDB/EVM)
4305 //
4306 // Because phy information is contained in the last packet of AMPDU only, so driver
4307 // should process phy information of previous packet
83184e69
MM		 4308 rtl8192_process_phyinfo(priv, tmp_buf, &priv->previous_stats, pstats);
4309 rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, &priv->previous_stats, bpacket_match_bssid,
ecdfa446 4310 bpacket_toself ,bPacketBeacon, bToSelfBA);
83184e69 4311 rtl8192_record_rxdesc_forlateruse(pstats, &priv->previous_stats);
ecdfa446
GKH		 4312
4313}
4314
4315
7703f04d 4316static void rtl8192_tx_resume(struct r8192_priv *priv)
ecdfa446 4317{
ecdfa446 4318 struct ieee80211_device *ieee = priv->ieee80211;
7703f04d 4319 struct net_device *dev = priv->ieee80211->dev;
ecdfa446
GKH		 4320 struct sk_buff *skb;
4321 int queue_index;
4322
4323 for(queue_index = BK_QUEUE; queue_index < TXCMD_QUEUE;queue_index++) {
4324 while((!skb_queue_empty(&ieee->skb_waitQ[queue_index]))&&
4325 (priv->ieee80211->check_nic_enough_desc(dev,queue_index) > 0)) {
4326 /* 1. dequeue the packet from the wait queue */
4327 skb = skb_dequeue(&ieee->skb_waitQ[queue_index]);
4328 /* 2. tx the packet directly */
4329 ieee->softmac_data_hard_start_xmit(skb,dev,0/* rate useless now*/);
ecdfa446
GKH		 4330 }
4331 }
4332}
4333
80a4dead 4334static void rtl8192_irq_tx_tasklet(unsigned long arg)
ecdfa446 4335{
80a4dead 4336 struct r8192_priv *priv = (struct r8192_priv*) arg;
1348dc08
MM		 4337 struct rtl8192_tx_ring *mgnt_ring = &priv->tx_ring[MGNT_QUEUE];
4338 struct net_device *dev = priv->ieee80211->dev;
4339 unsigned long flags;
4340
4341 /* check if we need to report that the management queue is drained */
4342 spin_lock_irqsave(&priv->irq_th_lock, flags);
4343
4344 if (!skb_queue_len(&mgnt_ring->queue) &&
4345 priv->ieee80211->ack_tx_to_ieee &&
4346 rtl8192_is_tx_queue_empty(dev)) {
4347 priv->ieee80211->ack_tx_to_ieee = 0;
4348 ieee80211_ps_tx_ack(priv->ieee80211, 1);
4349 }
4350
4351 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
4352
7703f04d 4353 rtl8192_tx_resume(priv);
ecdfa446
GKH		 4354}
4355
214985a6 4356/* Record the received data rate */
5e1ad18a 4357static void UpdateReceivedRateHistogramStatistics8190(
e2617486 4358 struct r8192_priv *priv,
ecdfa446
GKH		 4359 struct ieee80211_rx_stats* pstats
4360 )
4361{
ecdfa446
GKH		 4362 u32 rcvType=1; //0: Total, 1:OK, 2:CRC, 3:ICV
4363 u32 rateIndex;
4364 u32 preamble_guardinterval; //1: short preamble/GI, 0: long preamble/GI
4365
ecdfa446
GKH		 4366 if(pstats->bCRC)
4367 rcvType = 2;
4368 else if(pstats->bICV)
4369 rcvType = 3;
4370
4371 if(pstats->bShortPreamble)
4372 preamble_guardinterval = 1;// short
4373 else
4374 preamble_guardinterval = 0;// long
4375
4376 switch(pstats->rate)
4377 {
4378 //
4379 // CCK rate
4380 //
4381 case MGN_1M: rateIndex = 0; break;
4382 case MGN_2M: rateIndex = 1; break;
4383 case MGN_5_5M: rateIndex = 2; break;
4384 case MGN_11M: rateIndex = 3; break;
4385 //
4386 // Legacy OFDM rate
4387 //
4388 case MGN_6M: rateIndex = 4; break;
4389 case MGN_9M: rateIndex = 5; break;
4390 case MGN_12M: rateIndex = 6; break;
4391 case MGN_18M: rateIndex = 7; break;
4392 case MGN_24M: rateIndex = 8; break;
4393 case MGN_36M: rateIndex = 9; break;
4394 case MGN_48M: rateIndex = 10; break;
4395 case MGN_54M: rateIndex = 11; break;
4396 //
4397 // 11n High throughput rate
4398 //
4399 case MGN_MCS0: rateIndex = 12; break;
4400 case MGN_MCS1: rateIndex = 13; break;
4401 case MGN_MCS2: rateIndex = 14; break;
4402 case MGN_MCS3: rateIndex = 15; break;
4403 case MGN_MCS4: rateIndex = 16; break;
4404 case MGN_MCS5: rateIndex = 17; break;
4405 case MGN_MCS6: rateIndex = 18; break;
4406 case MGN_MCS7: rateIndex = 19; break;
4407 case MGN_MCS8: rateIndex = 20; break;
4408 case MGN_MCS9: rateIndex = 21; break;
4409 case MGN_MCS10: rateIndex = 22; break;
4410 case MGN_MCS11: rateIndex = 23; break;
4411 case MGN_MCS12: rateIndex = 24; break;
4412 case MGN_MCS13: rateIndex = 25; break;
4413 case MGN_MCS14: rateIndex = 26; break;
4414 case MGN_MCS15: rateIndex = 27; break;
4415 default: rateIndex = 28; break;
4416 }
ecdfa446
GKH		 4417 priv->stats.received_rate_histogram[0][rateIndex]++; //total
4418 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
4419}
4420
ddd877b2 4421static void rtl8192_rx(struct r8192_priv *priv)
ecdfa446 4422{
ecdfa446
GKH		 4423 struct ieee80211_hdr_1addr *ieee80211_hdr = NULL;
4424 bool unicast_packet = false;
4425 struct ieee80211_rx_stats stats = {
4426 .signal = 0,
4427 .noise = -98,
4428 .rate = 0,
4429 .freq = IEEE80211_24GHZ_BAND,
4430 };
4431 unsigned int count = priv->rxringcount;
79b03af6
MM		 4432 prx_fwinfo_819x_pci pDrvInfo = NULL;
4433 struct sk_buff *new_skb;
ecdfa446 4434
ecdfa446
GKH		 4435 while (count--) {
4436 rx_desc_819x_pci *pdesc = &priv->rx_ring[priv->rx_idx];//rx descriptor
4437 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];//rx pkt
4438
79b03af6 4439 if (pdesc->OWN)
ecdfa446
GKH		 4440 /* wait data to be filled by hardware */
4441 return;
79b03af6 4442
ecdfa446
GKH		 4443 stats.bICV = pdesc->ICV;
4444 stats.bCRC = pdesc->CRC32;
4445 stats.bHwError = pdesc->CRC32 | pdesc->ICV;
4446
4447 stats.Length = pdesc->Length;
4448 if(stats.Length < 24)
4449 stats.bHwError |= 1;
4450
4451 if(stats.bHwError) {
4452 stats.bShift = false;
ecdfa446 4453 goto done;
79b03af6
MM		 4454 }
4455 pDrvInfo = NULL;
4456 new_skb = dev_alloc_skb(priv->rxbuffersize);
ecdfa446 4457
79b03af6 4458 if (unlikely(!new_skb))
ecdfa446 4459 goto done;
ecdfa446
GKH		 4460
4461 stats.RxDrvInfoSize = pdesc->RxDrvInfoSize;
4462 stats.RxBufShift = ((pdesc->Shift)&0x03);
4463 stats.Decrypted = !pdesc->SWDec;
4464
ecdfa446 4465 pci_dma_sync_single_for_cpu(priv->pdev,
ecdfa446
GKH		 4466 *((dma_addr_t *)skb->cb),
4467 priv->rxbuffersize,
4468 PCI_DMA_FROMDEVICE);
4469 skb_put(skb, pdesc->Length);
4470 pDrvInfo = (rx_fwinfo_819x_pci *)(skb->data + stats.RxBufShift);
4471 skb_reserve(skb, stats.RxDrvInfoSize + stats.RxBufShift);
4472
4473 stats.rate = HwRateToMRate90((bool)pDrvInfo->RxHT, (u8)pDrvInfo->RxRate);
4474 stats.bShortPreamble = pDrvInfo->SPLCP;
4475
4476 /* it is debug only. It should be disabled in released driver.
4477 * 2007.1.11 by Emily
4478 * */
e2617486 4479 UpdateReceivedRateHistogramStatistics8190(priv, &stats);
ecdfa446
GKH		 4480
4481 stats.bIsAMPDU = (pDrvInfo->PartAggr==1);
4482 stats.bFirstMPDU = (pDrvInfo->PartAggr==1) && (pDrvInfo->FirstAGGR==1);
4483
4484 stats.TimeStampLow = pDrvInfo->TSFL;
3f9ab1ee 4485 stats.TimeStampHigh = read_nic_dword(priv, TSFR+4);
ecdfa446 4486
95a9a653 4487 UpdateRxPktTimeStamp8190(priv, &stats);
ecdfa446
GKH		 4488
4489 //
4490 // Get Total offset of MPDU Frame Body
4491 //
4492 if((stats.RxBufShift + stats.RxDrvInfoSize) > 0)
4493 stats.bShift = 1;
4494
4495 stats.RxIs40MHzPacket = pDrvInfo->BW;
4496
4497 /* ???? */
9633608f 4498 TranslateRxSignalStuff819xpci(priv, skb, &stats, pdesc, pDrvInfo);
ecdfa446
GKH		 4499
4500 /* Rx A-MPDU */
4501 if(pDrvInfo->FirstAGGR==1 || pDrvInfo->PartAggr == 1)
4502 RT_TRACE(COMP_RXDESC, "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
4503 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
4504 skb_trim(skb, skb->len - 4/*sCrcLng*/);
4505 /* rx packets statistics */
4506 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
4507 unicast_packet = false;
4508
4509 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
4510 //TODO
4511 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
4512 //TODO
4513 }else {
4514 /* unicast packet */
4515 unicast_packet = true;
4516 }
4517
4518 stats.packetlength = stats.Length-4;
4519 stats.fraglength = stats.packetlength;
4520 stats.fragoffset = 0;
4521 stats.ntotalfrag = 1;
4522
fb5fe277 4523 if(!ieee80211_rtl_rx(priv->ieee80211, skb, &stats)){
ecdfa446
GKH		 4524 dev_kfree_skb_any(skb);
4525 } else {
4526 priv->stats.rxok++;
4527 if(unicast_packet) {
4528 priv->stats.rxbytesunicast += skb->len;
4529 }
4530 }
4531
43f88d53
DL		 4532 pci_unmap_single(priv->pdev, *((dma_addr_t *) skb->cb),
4533 priv->rxbuffersize, PCI_DMA_FROMDEVICE);
4534
ecdfa446
GKH		 4535 skb = new_skb;
4536 priv->rx_buf[priv->rx_idx] = skb;
1c7ec2e8 4537 *((dma_addr_t *) skb->cb) = pci_map_single(priv->pdev, skb_tail_pointer(skb), priv->rxbuffersize, PCI_DMA_FROMDEVICE);
ecdfa446 4538
ecdfa446
GKH		 4539done:
4540 pdesc->BufferAddress = cpu_to_le32(*((dma_addr_t *)skb->cb));
4541 pdesc->OWN = 1;
4542 pdesc->Length = priv->rxbuffersize;
4543 if (priv->rx_idx == priv->rxringcount-1)
4544 pdesc->EOR = 1;
4545 priv->rx_idx = (priv->rx_idx + 1) % priv->rxringcount;
4546 }
4547
4548}
4549
80a4dead 4550static void rtl8192_irq_rx_tasklet(unsigned long arg)
ecdfa446 4551{
80a4dead 4552 struct r8192_priv *priv = (struct r8192_priv*) arg;
ddd877b2 4553 rtl8192_rx(priv);
ecdfa446 4554 /* unmask RDU */
3f9ab1ee 4555 write_nic_dword(priv, INTA_MASK, read_nic_dword(priv, INTA_MASK) | IMR_RDU);
ecdfa446
GKH		 4556}
4557
4558static const struct net_device_ops rtl8192_netdev_ops = {
4559 .ndo_open = rtl8192_open,
4560 .ndo_stop = rtl8192_close,
ecdfa446
GKH		 4561 .ndo_tx_timeout = tx_timeout,
4562 .ndo_do_ioctl = rtl8192_ioctl,
4563 .ndo_set_multicast_list = r8192_set_multicast,
4564 .ndo_set_mac_address = r8192_set_mac_adr,
fb5fe277 4565 .ndo_start_xmit = ieee80211_rtl_xmit,
ecdfa446
GKH		 4566};
4567
ecdfa446
GKH		 4568static int __devinit rtl8192_pci_probe(struct pci_dev *pdev,
4569 const struct pci_device_id *id)
4570{
4571 unsigned long ioaddr = 0;
4572 struct net_device *dev = NULL;
4573 struct r8192_priv *priv= NULL;
4574 u8 unit = 0;
3a8f2d3c 4575 int ret = -ENODEV;
ecdfa446 4576 unsigned long pmem_start, pmem_len, pmem_flags;
ecdfa446 4577
703fdcc3 4578 RT_TRACE(COMP_INIT,"Configuring chip resources\n");
ecdfa446
GKH		 4579
4580 if( pci_enable_device (pdev) ){
4581 RT_TRACE(COMP_ERR,"Failed to enable PCI device");
4582 return -EIO;
4583 }
4584
4585 pci_set_master(pdev);
4586 //pci_set_wmi(pdev);
4587 pci_set_dma_mask(pdev, 0xffffff00ULL);
ecdfa446 4588 pci_set_consistent_dma_mask(pdev,0xffffff00ULL);
ecdfa446 4589 dev = alloc_ieee80211(sizeof(struct r8192_priv));
3a8f2d3c
KV		 4590 if (!dev) {
4591 ret = -ENOMEM;
4592 goto fail_free;
4593 }
ecdfa446 4594
ecdfa446 4595 pci_set_drvdata(pdev, dev);
ecdfa446 4596 SET_NETDEV_DEV(dev, &pdev->dev);
ecdfa446 4597 priv = ieee80211_priv(dev);
ecdfa446 4598 priv->ieee80211 = netdev_priv(dev);
ecdfa446 4599 priv->pdev=pdev;
ecdfa446
GKH		 4600 if((pdev->subsystem_vendor == PCI_VENDOR_ID_DLINK)&&(pdev->subsystem_device == 0x3304)){
4601 priv->ieee80211->bSupportRemoteWakeUp = 1;
4602 } else
ecdfa446
GKH		 4603 {
4604 priv->ieee80211->bSupportRemoteWakeUp = 0;
4605 }
4606
ecdfa446
GKH		 4607 pmem_start = pci_resource_start(pdev, 1);
4608 pmem_len = pci_resource_len(pdev, 1);
4609 pmem_flags = pci_resource_flags (pdev, 1);
4610
4611 if (!(pmem_flags & IORESOURCE_MEM)) {
703fdcc3 4612 RT_TRACE(COMP_ERR, "region #1 not a MMIO resource, aborting\n");
ecdfa446
GKH		 4613 goto fail;
4614 }
4615
4616 //DMESG("Memory mapped space @ 0x%08lx ", pmem_start);
4617 if( ! request_mem_region(pmem_start, pmem_len, RTL819xE_MODULE_NAME)) {
703fdcc3 4618 RT_TRACE(COMP_ERR,"request_mem_region failed!\n");
ecdfa446
GKH		 4619 goto fail;
4620 }
4621
4622
4623 ioaddr = (unsigned long)ioremap_nocache( pmem_start, pmem_len);
4624 if( ioaddr == (unsigned long)NULL ){
703fdcc3 4625 RT_TRACE(COMP_ERR,"ioremap failed!\n");
ecdfa446
GKH		 4626 // release_mem_region( pmem_start, pmem_len );
4627 goto fail1;
4628 }
4629
4630 dev->mem_start = ioaddr; // shared mem start
4631 dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end
4632
ecdfa446
GKH		 4633 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4634 * PCI Tx retries from interfering with C3 CPU state */
4635 pci_write_config_byte(pdev, 0x41, 0x00);
4636
4637
4638 pci_read_config_byte(pdev, 0x05, &unit);
4639 pci_write_config_byte(pdev, 0x05, unit & (~0x04));
4640
4641 dev->irq = pdev->irq;
4642 priv->irq = 0;
4643
4644 dev->netdev_ops = &rtl8192_netdev_ops;
ecdfa446 4645
890a6850 4646 dev->wireless_handlers = &r8192_wx_handlers_def;
ecdfa446
GKH		 4647 dev->type=ARPHRD_ETHER;
4648
890a6850 4649 dev->watchdog_timeo = HZ*3;
ecdfa446
GKH		 4650
4651 if (dev_alloc_name(dev, ifname) < 0){
4652 RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying wlan%%d...\n");
dca41306 4653 strcpy(ifname, "wlan%d");
ecdfa446
GKH		 4654 dev_alloc_name(dev, ifname);
4655 }
4656
4657 RT_TRACE(COMP_INIT, "Driver probe completed1\n");
c62fdce2 4658 if (rtl8192_init(priv)!=0) {
703fdcc3 4659 RT_TRACE(COMP_ERR, "Initialization failed\n");
ecdfa446
GKH		 4660 goto fail;
4661 }
4662
ecdfa446
GKH		 4663 register_netdev(dev);
4664 RT_TRACE(COMP_INIT, "dev name=======> %s\n",dev->name);
af59c39d 4665 rtl8192_proc_init_one(priv);
ecdfa446
GKH		 4666
4667
4668 RT_TRACE(COMP_INIT, "Driver probe completed\n");
ecdfa446 4669 return 0;
ecdfa446
GKH		 4670
4671fail1:
4672
ecdfa446
GKH		 4673 if( dev->mem_start != (unsigned long)NULL ){
4674 iounmap( (void *)dev->mem_start );
4675 release_mem_region( pci_resource_start(pdev, 1),
4676 pci_resource_len(pdev, 1) );
4677 }
ecdfa446
GKH		 4678
4679fail:
4680 if(dev){
4681
4682 if (priv->irq) {
4683 free_irq(dev->irq, dev);
4684 dev->irq=0;
4685 }
4686 free_ieee80211(dev);
4687 }
4688
3a8f2d3c 4689fail_free:
ecdfa446
GKH		 4690 pci_disable_device(pdev);
4691
4692 DMESG("wlan driver load failed\n");
4693 pci_set_drvdata(pdev, NULL);
3a8f2d3c 4694 return ret;
ecdfa446
GKH		 4695
4696}
4697
4698/* detach all the work and timer structure declared or inititialized
4699 * in r8192_init function.
4700 * */
5b3b1a7b 4701static void rtl8192_cancel_deferred_work(struct r8192_priv* priv)
ecdfa446
GKH		 4702{
4703 /* call cancel_work_sync instead of cancel_delayed_work if and only if Linux_version_code
4704 * is or is newer than 2.6.20 and work structure is defined to be struct work_struct.
4705 * Otherwise call cancel_delayed_work is enough.
39cfb97b 4706 * FIXME (2.6.20 should 2.6.22, work_struct should not cancel)
ecdfa446 4707 * */
ecdfa446
GKH		 4708 cancel_delayed_work(&priv->watch_dog_wq);
4709 cancel_delayed_work(&priv->update_beacon_wq);
4710 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
ecdfa446 4711 cancel_delayed_work(&priv->gpio_change_rf_wq);
ecdfa446
GKH		 4712 cancel_work_sync(&priv->reset_wq);
4713 cancel_work_sync(&priv->qos_activate);
ecdfa446
GKH		 4714}
4715
4716
4717static void __devexit rtl8192_pci_disconnect(struct pci_dev *pdev)
4718{
4719 struct net_device *dev = pci_get_drvdata(pdev);
4720 struct r8192_priv *priv ;
fb53c2b7 4721 u32 i;
ecdfa446 4722
fb53c2b7 4723 if (dev) {
ecdfa446
GKH		 4724
4725 unregister_netdev(dev);
4726
fb53c2b7 4727 priv = ieee80211_priv(dev);
ecdfa446 4728
af59c39d 4729 rtl8192_proc_remove_one(priv);
ecdfa446
GKH		 4730
4731 rtl8192_down(dev);
4732 if (priv->pFirmware)
4733 {
4734 vfree(priv->pFirmware);
4735 priv->pFirmware = NULL;
4736 }
ecdfa446 4737 destroy_workqueue(priv->priv_wq);
ecdfa446 4738
fb53c2b7 4739 /* free tx/rx rings */
af59c39d 4740 rtl8192_free_rx_ring(priv);
fb53c2b7 4741 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
af59c39d 4742 rtl8192_free_tx_ring(priv, i);
fb53c2b7
MM		 4743
4744 if (priv->irq) {
ecdfa446
GKH		 4745 printk("Freeing irq %d\n",dev->irq);
4746 free_irq(dev->irq, dev);
4747 priv->irq=0;
ecdfa446
GKH		 4748 }
4749
ecdfa446
GKH		 4750 if( dev->mem_start != (unsigned long)NULL ){
4751 iounmap( (void *)dev->mem_start );
4752 release_mem_region( pci_resource_start(pdev, 1),
4753 pci_resource_len(pdev, 1) );
4754 }
ecdfa446 4755
97a6688a 4756 free_ieee80211(dev);
ecdfa446
GKH		 4757 }
4758
4759 pci_disable_device(pdev);
4760 RT_TRACE(COMP_DOWN, "wlan driver removed\n");
4761}
4762
fb5fe277
GK		 4763extern int ieee80211_rtl_init(void);
4764extern void ieee80211_rtl_exit(void);
ecdfa446
GKH		 4765
4766static int __init rtl8192_pci_module_init(void)
4767{
4768 int retval;
4769
fb5fe277 4770 retval = ieee80211_rtl_init();
ecdfa446
GKH		 4771 if (retval)
4772 return retval;
4773
4774 printk(KERN_INFO "\nLinux kernel driver for RTL8192 based WLAN cards\n");
4775 printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan\n");
703fdcc3 4776 RT_TRACE(COMP_INIT, "Initializing module\n");
ecdfa446 4777 rtl8192_proc_module_init();
ecdfa446 4778 if(0!=pci_register_driver(&rtl8192_pci_driver))
ecdfa446
GKH		 4779 {
4780 DMESG("No device found");
4781 /*pci_unregister_driver (&rtl8192_pci_driver);*/
4782 return -ENODEV;
4783 }
4784 return 0;
4785}
4786
4787
4788static void __exit rtl8192_pci_module_exit(void)
4789{
4790 pci_unregister_driver(&rtl8192_pci_driver);
4791
703fdcc3 4792 RT_TRACE(COMP_DOWN, "Exiting\n");
ecdfa446 4793 rtl8192_proc_module_remove();
fb5fe277 4794 ieee80211_rtl_exit();
ecdfa446
GKH		 4795}
4796
559fba5e 4797static irqreturn_t rtl8192_interrupt(int irq, void *netdev)
ecdfa446 4798{
b2cf8d48
MM		 4799 struct net_device *dev = (struct net_device *) netdev;
4800 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
4801 unsigned long flags;
4802 u32 inta;
f8129a95
MM		 4803 irqreturn_t ret = IRQ_HANDLED;
4804
4805 spin_lock_irqsave(&priv->irq_th_lock, flags);
ecdfa446 4806
b2cf8d48 4807 /* ISR: 4bytes */
ecdfa446 4808
3f9ab1ee
MM		 4809 inta = read_nic_dword(priv, ISR); /* & priv->IntrMask; */
4810 write_nic_dword(priv, ISR, inta); /* reset int situation */
ecdfa446 4811
b2cf8d48 4812 if (!inta) {
b2cf8d48
MM		 4813 /*
4814 * most probably we can safely return IRQ_NONE,
4815 * but for now is better to avoid problems
4816 */
f8129a95 4817 goto out_unlock;
b2cf8d48 4818 }
ecdfa446 4819
b2cf8d48
MM		 4820 if (inta == 0xffff) {
4821 /* HW disappared */
f8129a95 4822 goto out_unlock;
b2cf8d48
MM		 4823 }
4824
f8129a95
MM		 4825 if (!netif_running(dev))
4826 goto out_unlock;
ecdfa446 4827
b2cf8d48
MM		 4828 if (inta & IMR_TBDOK) {
4829 RT_TRACE(COMP_INTR, "beacon ok interrupt!\n");
af59c39d 4830 rtl8192_tx_isr(priv, BEACON_QUEUE);
b2cf8d48
MM		 4831 priv->stats.txbeaconokint++;
4832 }
ecdfa446 4833
b2cf8d48
MM		 4834 if (inta & IMR_TBDER) {
4835 RT_TRACE(COMP_INTR, "beacon ok interrupt!\n");
af59c39d 4836 rtl8192_tx_isr(priv, BEACON_QUEUE);
b2cf8d48
MM		 4837 priv->stats.txbeaconerr++;
4838 }
ecdfa446 4839
b2cf8d48
MM		 4840 if (inta & IMR_MGNTDOK ) {
4841 RT_TRACE(COMP_INTR, "Manage ok interrupt!\n");
4842 priv->stats.txmanageokint++;
af59c39d 4843 rtl8192_tx_isr(priv, MGNT_QUEUE);
b2cf8d48 4844 }
ecdfa446 4845
b2cf8d48
MM		 4846 if (inta & IMR_COMDOK)
4847 {
4848 priv->stats.txcmdpktokint++;
af59c39d 4849 rtl8192_tx_isr(priv, TXCMD_QUEUE);
b2cf8d48 4850 }
ecdfa446 4851
b2cf8d48 4852 if (inta & IMR_ROK) {
b2cf8d48
MM		 4853 priv->stats.rxint++;
4854 tasklet_schedule(&priv->irq_rx_tasklet);
4855 }
ecdfa446 4856
b2cf8d48
MM		 4857 if (inta & IMR_BcnInt) {
4858 RT_TRACE(COMP_INTR, "prepare beacon for interrupt!\n");
4859 tasklet_schedule(&priv->irq_prepare_beacon_tasklet);
4860 }
ecdfa446 4861
b2cf8d48
MM		 4862 if (inta & IMR_RDU) {
4863 RT_TRACE(COMP_INTR, "rx descriptor unavailable!\n");
4864 priv->stats.rxrdu++;
4865 /* reset int situation */
3f9ab1ee 4866 write_nic_dword(priv, INTA_MASK, read_nic_dword(priv, INTA_MASK) & ~IMR_RDU);
b2cf8d48
MM		 4867 tasklet_schedule(&priv->irq_rx_tasklet);
4868 }
ecdfa446 4869
b2cf8d48
MM		 4870 if (inta & IMR_RXFOVW) {
4871 RT_TRACE(COMP_INTR, "rx overflow !\n");
4872 priv->stats.rxoverflow++;
4873 tasklet_schedule(&priv->irq_rx_tasklet);
4874 }
ecdfa446 4875
b2cf8d48
MM		 4876 if (inta & IMR_TXFOVW)
4877 priv->stats.txoverflow++;
ecdfa446 4878
b2cf8d48
MM		 4879 if (inta & IMR_BKDOK) {
4880 RT_TRACE(COMP_INTR, "BK Tx OK interrupt!\n");
4881 priv->stats.txbkokint++;
4882 priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++;
af59c39d 4883 rtl8192_tx_isr(priv, BK_QUEUE);
b2cf8d48 4884 }
ecdfa446 4885
b2cf8d48
MM		 4886 if (inta & IMR_BEDOK) {
4887 RT_TRACE(COMP_INTR, "BE TX OK interrupt!\n");
4888 priv->stats.txbeokint++;
4889 priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++;
af59c39d 4890 rtl8192_tx_isr(priv, BE_QUEUE);
b2cf8d48 4891 }
ecdfa446 4892
b2cf8d48
MM		 4893 if (inta & IMR_VIDOK) {
4894 RT_TRACE(COMP_INTR, "VI TX OK interrupt!\n");
4895 priv->stats.txviokint++;
4896 priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++;
af59c39d 4897 rtl8192_tx_isr(priv, VI_QUEUE);
b2cf8d48 4898 }
ecdfa446 4899
b2cf8d48
MM		 4900 if (inta & IMR_VODOK) {
4901 priv->stats.txvookint++;
4902 priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++;
af59c39d 4903 rtl8192_tx_isr(priv, VO_QUEUE);
b2cf8d48 4904 }
ecdfa446 4905
f8129a95 4906out_unlock:
b2cf8d48 4907 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
ecdfa446 4908
f8129a95 4909 return ret;
ecdfa446
GKH		 4910}
4911
282fa9f3 4912void EnableHWSecurityConfig8192(struct r8192_priv *priv)
ecdfa446
GKH		 4913{
4914 u8 SECR_value = 0x0;
16d74da0
MM		 4915 struct ieee80211_device* ieee = priv->ieee80211;
4916
ecdfa446 4917 SECR_value = SCR_TxEncEnable | SCR_RxDecEnable;
11aacc28 4918
ecdfa446
GKH		 4919 if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2))
4920 {
4921 SECR_value |= SCR_RxUseDK;
4922 SECR_value |= SCR_TxUseDK;
4923 }
4924 else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP)))
4925 {
4926 SECR_value |= SCR_RxUseDK;
4927 SECR_value |= SCR_TxUseDK;
4928 }
4929
ecdfa446
GKH		 4930 //add HWSec active enable here.
4931//default using hwsec. when peer AP is in N mode only and pairwise_key_type is none_aes(which HT_IOT_ACT_PURE_N_MODE indicates it), use software security. when peer AP is in b,g,n mode mixed and pairwise_key_type is none_aes, use g mode hw security. WB on 2008.7.4
4932 ieee->hwsec_active = 1;
4933
4934 if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep)//!ieee->hwsec_support) //add hwsec_support flag to totol control hw_sec on/off
4935 {
4936 ieee->hwsec_active = 0;
4937 SECR_value &= ~SCR_RxDecEnable;
4938 }
4939
207b58fb 4940 RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__,
ecdfa446
GKH		 4941 ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);
4942 {
3f9ab1ee 4943 write_nic_byte(priv, SECR, SECR_value);//SECR_value | SCR_UseDK );
ecdfa446
GKH		 4944 }
4945
4946}
4947#define TOTAL_CAM_ENTRY 32
4948//#define CAM_CONTENT_COUNT 8
043dfdd3
MM		 4949void setKey(struct r8192_priv *priv, u8 EntryNo, u8 KeyIndex, u16 KeyType,
4950 const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent)
ecdfa446
GKH		 4951{
4952 u32 TargetCommand = 0;
4953 u32 TargetContent = 0;
4954 u16 usConfig = 0;
4955 u8 i;
4956#ifdef ENABLE_IPS
ecdfa446 4957 RT_RF_POWER_STATE rtState;
043dfdd3 4958
4559854d 4959 rtState = priv->eRFPowerState;
31d664e5 4960 if (priv->PowerSaveControl.bInactivePs){
ecdfa446 4961 if(rtState == eRfOff){
181d1dff 4962 if(priv->RfOffReason > RF_CHANGE_BY_IPS)
ecdfa446
GKH		 4963 {
4964 RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__);
65a43784 4965 //up(&priv->wx_sem);
ecdfa446
GKH		 4966 return ;
4967 }
4968 else{
65a43784 4969 down(&priv->ieee80211->ips_sem);
58f6b58e 4970 IPSLeave(priv);
65a43784 4971 up(&priv->ieee80211->ips_sem);
ecdfa446
GKH		 4972 }
4973 }
4974 }
4975 priv->ieee80211->is_set_key = true;
4976#endif
4977 if (EntryNo >= TOTAL_CAM_ENTRY)
4978 RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n");
4979
043dfdd3 4980 RT_TRACE(COMP_SEC, "====>to setKey(), priv:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr%pM\n", priv, EntryNo, KeyIndex, KeyType, MacAddr);
ecdfa446
GKH		 4981
4982 if (DefaultKey)
4983 usConfig |= BIT15 | (KeyType<<2);
4984 else
4985 usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
4986// usConfig |= BIT15 | (KeyType<<2) | (DefaultKey<<5) | KeyIndex;
4987
4988
4989 for(i=0 ; i<CAM_CONTENT_COUNT; i++){
4990 TargetCommand = i+CAM_CONTENT_COUNT*EntryNo;
4991 TargetCommand |= BIT31|BIT16;
4992
4993 if(i==0){//MAC|Config
4994 TargetContent = (u32)(*(MacAddr+0)) << 16|
4995 (u32)(*(MacAddr+1)) << 24|
4996 (u32)usConfig;
4997
3f9ab1ee
MM		 4998 write_nic_dword(priv, WCAMI, TargetContent);
4999 write_nic_dword(priv, RWCAM, TargetCommand);
ecdfa446
GKH		 5000 }
5001 else if(i==1){//MAC
5002 TargetContent = (u32)(*(MacAddr+2)) |
5003 (u32)(*(MacAddr+3)) << 8|
5004 (u32)(*(MacAddr+4)) << 16|
5005 (u32)(*(MacAddr+5)) << 24;
3f9ab1ee
MM		 5006 write_nic_dword(priv, WCAMI, TargetContent);
5007 write_nic_dword(priv, RWCAM, TargetCommand);
ecdfa446
GKH		 5008 }
5009 else { //Key Material
5010 if(KeyContent != NULL)
5011 {
3f9ab1ee
MM		 5012 write_nic_dword(priv, WCAMI, (u32)(*(KeyContent+i-2)) );
5013 write_nic_dword(priv, RWCAM, TargetCommand);
ecdfa446
GKH		 5014 }
5015 }
5016 }
5017 RT_TRACE(COMP_SEC,"=========>after set key, usconfig:%x\n", usConfig);
ecdfa446 5018}
ecdfa446 5019
480ab9dc 5020bool NicIFEnableNIC(struct r8192_priv *priv)
65a43784 5021{
5022 RT_STATUS init_status = RT_STATUS_SUCCESS;
31d664e5 5023 PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
65a43784 5024
5025 //YJ,add,091109
5026 if (priv->up == 0){
5027 RT_TRACE(COMP_ERR, "ERR!!! %s(): Driver is already down!\n",__FUNCTION__);
5028 priv->bdisable_nic = false; //YJ,add,091111
5029 return false;
5030 }
5031 // <1> Reset memory: descriptor, buffer,..
5032 //NicIFResetMemory(Adapter);
5033
5034 // <2> Enable Adapter
65a43784 5035 //priv->bfirst_init = true;
af59c39d 5036 init_status = rtl8192_adapter_start(priv);
65a43784 5037 if (init_status != RT_STATUS_SUCCESS) {
5038 RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n",__FUNCTION__);
5039 priv->bdisable_nic = false; //YJ,add,091111
5040 return -1;
5041 }
65a43784 5042 RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
5043 //priv->bfirst_init = false;
5044
5045 // <3> Enable Interrupt
480ab9dc 5046 rtl8192_irq_enable(priv);
65a43784 5047 priv->bdisable_nic = false;
16d74da0 5048
c6eae677 5049 return (init_status == RT_STATUS_SUCCESS);
65a43784 5050}
214985a6 5051
480ab9dc 5052bool NicIFDisableNIC(struct r8192_priv *priv)
65a43784 5053{
5054 bool status = true;
65a43784 5055 u8 tmp_state = 0;
5056 // <1> Disable Interrupt
16d74da0 5057
65a43784 5058 priv->bdisable_nic = true; //YJ,move,091109
5059 tmp_state = priv->ieee80211->state;
5060
5061 ieee80211_softmac_stop_protocol(priv->ieee80211, false);
5062
5063 priv->ieee80211->state = tmp_state;
5064 rtl8192_cancel_deferred_work(priv);
af59c39d 5065 rtl8192_irq_disable(priv);
65a43784 5066 // <2> Stop all timer
5067
5068 // <3> Disable Adapter
af59c39d 5069 rtl8192_halt_adapter(priv, false);
65a43784 5070// priv->bdisable_nic = true;
65a43784 5071
5072 return status;
5073}
5074
ecdfa446
GKH		 5075module_init(rtl8192_pci_module_init);
5076module_exit(rtl8192_pci_module_exit);
Linux kernel - Deliverables
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