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rtl8192e: reject rtl8192se cards with same PCI ID
[deliverable/linux.git] / drivers / staging / rtl8192e / r8192E_phy.c
CommitLineData
94a79942
LF		 1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7 * more details.
8 *
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12 *
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
15 *
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18******************************************************************************/
19#if (defined(RTL8192E) || defined(RTL8190P))
20
21
22#include "rtl_core.h"
23#include "r8192E_hw.h"
24#include "r8192E_phyreg.h"
25#include "r8190P_rtl8256.h"
26#include "r8192E_phy.h"
27#include "rtl_dm.h"
28#ifdef ENABLE_DOT11D
29#include "dot11d.h"
30#endif
31
32#ifdef RTL8190P
33#include "r8190P_hwimg.h"
34#endif
35
36#ifdef RTL8192E
37#include "r8192E_hwimg.h"
38#endif
39
40static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
41 0,
42 0x085c,
43 0x08dc,
44 0x095c,
45 0x09dc,
46 0x0a5c,
47 0x0adc,
48 0x0b5c,
49 0x0bdc,
50 0x0c5c,
51 0x0cdc,
52 0x0d5c,
53 0x0ddc,
54 0x0e5c,
55 0x0f72,
56};
57
58/*************************Define local function prototype**********************/
59
60static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
61static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
62u32 rtl8192_CalculateBitShift(u32 dwBitMask)
63{
64 u32 i;
65 for (i=0; i<=31; i++)
66 {
67 if (((dwBitMask>>i)&0x1) == 1)
68 break;
69 }
70 return i;
71}
72u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
73{
74 u8 ret = 1;
75 struct r8192_priv *priv = rtllib_priv(dev);
76#ifdef RTL8190P
77 if (priv->rf_type == RF_2T4R)
78 {
79 ret= 1;
80 }
81 else if (priv->rf_type == RF_1T2R)
82 {
83 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
84 ret = 0;
85 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
86 ret = 1;
87 }
88#else
89 #ifdef RTL8192E
90 if (priv->rf_type == RF_2T4R)
91 ret = 0;
92 else if (priv->rf_type == RF_1T2R)
93 {
94 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
95 ret = 1;
96 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
97 ret = 0;
98 }
99 #endif
100#endif
101 return ret;
102}
103void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
104{
105
106 u32 OriginalValue, BitShift, NewValue;
107
108 if (dwBitMask!= bMaskDWord)
109 {
110 OriginalValue = read_nic_dword(dev, dwRegAddr);
111 BitShift = rtl8192_CalculateBitShift(dwBitMask);
112 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
113 write_nic_dword(dev, dwRegAddr, NewValue);
114 }else
115 write_nic_dword(dev, dwRegAddr, dwData);
116 return;
117}
118u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
119{
120 u32 Ret = 0, OriginalValue, BitShift;
121
122 OriginalValue = read_nic_dword(dev, dwRegAddr);
123 BitShift = rtl8192_CalculateBitShift(dwBitMask);
124 Ret = (OriginalValue & dwBitMask) >> BitShift;
125
126 return (Ret);
127}
128u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
129{
130 struct r8192_priv *priv = rtllib_priv(dev);
131 u32 ret = 0;
132 u32 NewOffset = 0;
133 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
134 Offset &= 0x3f;
135
136 if (priv->rf_chip == RF_8256)
137 {
138#ifdef RTL8190P
139 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
140#else
141 #ifdef RTL8192E
142 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
143 #endif
144#endif
145 if (Offset >= 31)
146 {
147 priv->RfReg0Value[eRFPath] |= 0x140;
148 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
149 NewOffset = Offset -30;
150 }
151 else if (Offset >= 16)
152 {
153 priv->RfReg0Value[eRFPath] |= 0x100;
154 priv->RfReg0Value[eRFPath] &= (~0x40);
155 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
156
157 NewOffset = Offset - 15;
158 }
159 else
160 NewOffset = Offset;
161 }
162 else
163 {
164 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
165 NewOffset = Offset;
166 }
167 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
168 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
169 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
170
171
172 msleep(1);
173
174 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
175
176
177 if (priv->rf_chip == RF_8256)
178 {
179 priv->RfReg0Value[eRFPath] &= 0xebf;
180
181 rtl8192_setBBreg(
182 dev,
183 pPhyReg->rf3wireOffset,
184 bMaskDWord,
185 (priv->RfReg0Value[eRFPath] << 16));
186
187#ifdef RTL8190P
188 if (priv->rf_type == RF_2T4R)
189 {
190 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);
191 }
192 else if (priv->rf_type == RF_1T2R)
193 {
194 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);
195 }
196#else
197 #ifdef RTL8192E
198 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
199 #endif
200#endif
201 }
202
203
204 return ret;
205
206}
207
208void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
209{
210 struct r8192_priv *priv = rtllib_priv(dev);
211 u32 DataAndAddr = 0, NewOffset = 0;
212 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
213
214 Offset &= 0x3f;
215 if (priv->rf_chip == RF_8256)
216 {
217
218#ifdef RTL8190P
219 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
220#else
221 #ifdef RTL8192E
222 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
223 #endif
224#endif
225
226 if (Offset >= 31)
227 {
228 priv->RfReg0Value[eRFPath] |= 0x140;
229 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
230 NewOffset = Offset - 30;
231 }
232 else if (Offset >= 16)
233 {
234 priv->RfReg0Value[eRFPath] |= 0x100;
235 priv->RfReg0Value[eRFPath] &= (~0x40);
236 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
237 NewOffset = Offset - 15;
238 }
239 else
240 NewOffset = Offset;
241 }
242 else
243 {
244 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
245 NewOffset = Offset;
246 }
247
248 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
249
250 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
251
252
253 if (Offset==0x0)
254 priv->RfReg0Value[eRFPath] = Data;
255
256 if (priv->rf_chip == RF_8256)
257 {
258 if (Offset != 0)
259 {
260 priv->RfReg0Value[eRFPath] &= 0xebf;
261 rtl8192_setBBreg(
262 dev,
263 pPhyReg->rf3wireOffset,
264 bMaskDWord,
265 (priv->RfReg0Value[eRFPath] << 16));
266 }
267#ifdef RTL8190P
268 if (priv->rf_type == RF_2T4R)
269 {
270 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);
271 }
272 else if (priv->rf_type == RF_1T2R)
273 {
274 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);
275 }
276#else
277 #ifdef RTL8192E
278 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
279 #endif
280#endif
281 }
282
283 return;
284}
285
286void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
287{
288 struct r8192_priv *priv = rtllib_priv(dev);
289 u32 Original_Value, BitShift, New_Value;
290
291 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
292 return;
293#ifdef RTL8192E
294 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
295 return;
296#endif
297
298 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
299 if (priv->Rf_Mode == RF_OP_By_FW)
300 {
301 if (BitMask != bMask12Bits)
302 {
303 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
304 BitShift = rtl8192_CalculateBitShift(BitMask);
305 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
306
307 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
308 }else
309 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
310 udelay(200);
311
312 }
313 else
314 {
315 if (BitMask != bMask12Bits)
316 {
317 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
318 BitShift = rtl8192_CalculateBitShift(BitMask);
319 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
320
321 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
322 }else
323 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
324 }
325 return;
326}
327
328u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
329{
330 u32 Original_Value, Readback_Value, BitShift;
331 struct r8192_priv *priv = rtllib_priv(dev);
332 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
333 return 0;
334#ifdef RTL8192E
335 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
336 return 0;
337#endif
338 down(&priv->rf_sem);
339 if (priv->Rf_Mode == RF_OP_By_FW)
340 {
341 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
342 udelay(200);
343 }
344 else
345 {
346 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
347
348 }
349 BitShift = rtl8192_CalculateBitShift(BitMask);
350 Readback_Value = (Original_Value & BitMask) >> BitShift;
351 up(&priv->rf_sem);
352 return (Readback_Value);
353}
354
355static u32 phy_FwRFSerialRead(
356 struct net_device* dev,
357 RF90_RADIO_PATH_E eRFPath,
358 u32 Offset )
359{
360 u32 retValue = 0;
361 u32 Data = 0;
362 u8 time = 0;
363 Data |= ((Offset&0xFF)<<12);
364 Data |= ((eRFPath&0x3)<<20);
365 Data |= 0x80000000;
366 while (read_nic_dword(dev, QPNR)&0x80000000)
367 {
368 if (time++ < 100)
369 {
370 udelay(10);
371 }
372 else
373 break;
374 }
375 write_nic_dword(dev, QPNR, Data);
376 while (read_nic_dword(dev, QPNR)&0x80000000)
377 {
378 if (time++ < 100)
379 {
380 udelay(10);
381 }
382 else
383 return (0);
384 }
385 retValue = read_nic_dword(dev, RF_DATA);
386
387 return (retValue);
388
389} /* phy_FwRFSerialRead */
390
391static void
392phy_FwRFSerialWrite(
393 struct net_device* dev,
394 RF90_RADIO_PATH_E eRFPath,
395 u32 Offset,
396 u32 Data )
397{
398 u8 time = 0;
399
400
401 Data |= ((Offset&0xFF)<<12);
402 Data |= ((eRFPath&0x3)<<20);
403 Data |= 0x400000;
404 Data |= 0x80000000;
405
406 while (read_nic_dword(dev, QPNR)&0x80000000)
407 {
408 if (time++ < 100)
409 {
410 udelay(10);
411 }
412 else
413 break;
414 }
415 write_nic_dword(dev, QPNR, Data);
416
417} /* phy_FwRFSerialWrite */
418
419
420void rtl8192_phy_configmac(struct net_device* dev)
421{
422 u32 dwArrayLen = 0, i = 0;
423 u32* pdwArray = NULL;
424 struct r8192_priv *priv = rtllib_priv(dev);
425#ifdef TO_DO_LIST
426if (dev->bInHctTest)
427 {
428 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
429 dwArrayLen = MACPHY_ArrayLengthDTM;
430 pdwArray = Rtl819XMACPHY_ArrayDTM;
431 }
432 else if (priv->bTXPowerDataReadFromEEPORM)
433#endif
434 if (priv->bTXPowerDataReadFromEEPORM)
435 {
436 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
437 dwArrayLen = MACPHY_Array_PGLength;
438 pdwArray = Rtl819XMACPHY_Array_PG;
439
440 }
441 else
442 {
443 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
444 dwArrayLen = MACPHY_ArrayLength;
445 pdwArray = Rtl819XMACPHY_Array;
446 }
447 for (i = 0; i<dwArrayLen; i=i+3){
448 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
449 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
450 if (pdwArray[i] == 0x318)
451 {
452 pdwArray[i+2] = 0x00000800;
453 }
454 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
455 }
456 return;
457
458}
459
460void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
461{
462 int i;
463 u32* Rtl819XPHY_REGArray_Table = NULL;
464 u32* Rtl819XAGCTAB_Array_Table = NULL;
465 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
466 struct r8192_priv *priv = rtllib_priv(dev);
467#ifdef TO_DO_LIST
468 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
469 if (dev->bInHctTest)
470 {
471 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
472 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
473
474 if (priv->RF_Type == RF_2T4R)
475 {
476 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
477 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
478 }
479 else if (priv->RF_Type == RF_1T2R)
480 {
481 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
482 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
483 }
484 }
485 else
486#endif
487 {
488 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
489 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
490 if (priv->rf_type == RF_2T4R)
491 {
492 PHY_REGArrayLen = PHY_REGArrayLength;
493 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
494 }
495 else if (priv->rf_type == RF_1T2R)
496 {
497 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
498 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
499 }
500 }
501
502 if (ConfigType == BaseBand_Config_PHY_REG)
503 {
504 for (i=0; i<PHY_REGArrayLen; i+=2)
505 {
506 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
507 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
508 }
509 }
510 else if (ConfigType == BaseBand_Config_AGC_TAB)
511 {
512 for (i=0; i<AGCTAB_ArrayLen; i+=2)
513 {
514 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
515 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
516 }
517 }
518 return;
519
520
521}
522void rtl8192_InitBBRFRegDef(struct net_device* dev)
523{
524 struct r8192_priv *priv = rtllib_priv(dev);
525 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
526 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
527 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
528 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
529
530 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
531 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
532 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
533 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
534
535 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
536 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
537 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
538 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
539
540 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
541 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
542 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
543 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
544
545 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
546 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
547 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
548 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
549
550 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
551 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
552 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
553 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
554
555 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
556 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
557 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
558 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
559
560 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
561 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
562 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
563 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
564
565 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
566 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
567 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
568 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
569
570 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
571 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
572 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
573 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
574
575 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
576 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
577 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
578 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
579
580 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
581 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
582 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
583 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
584
585 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
586 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
587 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
588 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
589
590 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
591 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
592 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
593 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
594
595 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
596 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
597 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
598 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
599
600 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
601 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
602 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
603 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
604
605 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
606 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
607 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
608 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
609
610}
611bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
612{
613 bool ret = true;
614 u32 i, CheckTimes = 4, dwRegRead = 0;
615 u32 WriteAddr[4];
616 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
617 WriteAddr[HW90_BLOCK_MAC] = 0x100;
618 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
619 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
620 WriteAddr[HW90_BLOCK_RF] = 0x3;
621 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, CheckBlock);
622 for (i=0 ; i < CheckTimes ; i++)
623 {
624
625 switch (CheckBlock)
626 {
627 case HW90_BLOCK_MAC:
628 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
629 break;
630
631 case HW90_BLOCK_PHY0:
632 case HW90_BLOCK_PHY1:
633 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
634 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
635 break;
636
637 case HW90_BLOCK_RF:
638 WriteData[i] &= 0xfff;
639 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
640 mdelay(10);
641 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
642 mdelay(10);
643 break;
644
645 default:
646 ret = false;
647 break;
648 }
649
650
651 if (dwRegRead != WriteData[i])
652 {
653 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
654 ret = false;
655 break;
656 }
657 }
658
659 return ret;
660}
661
662bool rtl8192_BB_Config_ParaFile(struct net_device* dev)
663{
664 struct r8192_priv *priv = rtllib_priv(dev);
665 bool rtStatus = true;
666 u8 bRegValue = 0, eCheckItem = 0;
667 u32 dwRegValue = 0;
668 /**************************************
669 **************************************/
670
671 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
672 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
673
674 dwRegValue = read_nic_dword(dev, CPU_GEN);
675 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
676
677 for (eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
678 {
679 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0);
680 if (rtStatus != true)
681 {
682 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
683 return rtStatus;
684 }
685 }
686 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
687 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
688
689 dwRegValue = read_nic_dword(dev, CPU_GEN);
690 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
691
692 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
693
694 if (priv->IC_Cut > VERSION_8190_BD)
695 {
696 if (priv->rf_type == RF_2T4R)
697 {
698 dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 |
699 priv->AntennaTxPwDiff[1]<<4 |
700 priv->AntennaTxPwDiff[0]);
701 }
702 else
703 dwRegValue = 0x0;
704 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
705 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
706
707
708#ifdef RTL8190P
709 dwRegValue = priv->CrystalCap & 0x3;
710 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
711 dwRegValue = ((priv->CrystalCap & 0xc)>>2);
712 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
713#else
714 #ifdef RTL8192E
715 dwRegValue = priv->CrystalCap;
716 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
717 #endif
718#endif
719
720 }
721
722 return rtStatus;
723}
724bool rtl8192_BBConfig(struct net_device* dev)
725{
726 bool rtStatus = true;
727 rtl8192_InitBBRFRegDef(dev);
728 rtStatus = rtl8192_BB_Config_ParaFile(dev);
729 return rtStatus;
730}
731
732void rtl8192_phy_getTxPower(struct net_device* dev)
733{
734 struct r8192_priv *priv = rtllib_priv(dev);
735#ifdef RTL8190P
736 priv->MCSTxPowerLevelOriginalOffset[0] =
737 read_nic_dword(dev, MCS_TXAGC);
738 priv->MCSTxPowerLevelOriginalOffset[1] =
739 read_nic_dword(dev, (MCS_TXAGC+4));
740 priv->CCKTxPowerLevelOriginalOffset =
741 read_nic_dword(dev, CCK_TXAGC);
742#else
743 #ifdef RTL8192E
744 priv->MCSTxPowerLevelOriginalOffset[0] =
745 read_nic_dword(dev, rTxAGC_Rate18_06);
746 priv->MCSTxPowerLevelOriginalOffset[1] =
747 read_nic_dword(dev, rTxAGC_Rate54_24);
748 priv->MCSTxPowerLevelOriginalOffset[2] =
749 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
750 priv->MCSTxPowerLevelOriginalOffset[3] =
751 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
752 priv->MCSTxPowerLevelOriginalOffset[4] =
753 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
754 priv->MCSTxPowerLevelOriginalOffset[5] =
755 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
756 #endif
757#endif
758
759 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
760 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
761 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
762 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
763 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
764 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
765 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
766
767 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
768 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
769 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
770 rOFDM0_RxDetector3, priv->framesync);
771 priv->SifsTime = read_nic_word(dev, SIFS);
772 return;
773}
774
775void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
776{
777 struct r8192_priv *priv = rtllib_priv(dev);
778 u8 powerlevel = 0,powerlevelOFDM24G = 0;
779 char ant_pwr_diff;
780 u32 u4RegValue;
781
782 if (priv->epromtype == EEPROM_93C46)
783 {
784 powerlevel = priv->TxPowerLevelCCK[channel-1];
785 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
786 }
787 else if (priv->epromtype == EEPROM_93C56)
788 {
789 if (priv->rf_type == RF_1T2R)
790 {
791 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
792 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
793 }
794 else if (priv->rf_type == RF_2T4R)
795 {
796 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
797 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
798
799 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
800 -priv->TxPowerLevelOFDM24G_A[channel-1];
801
802 priv->RF_C_TxPwDiff = ant_pwr_diff;
803
804 ant_pwr_diff &= 0xf;
805
806 priv->AntennaTxPwDiff[2] = 0;
807 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
808 priv->AntennaTxPwDiff[0] = 0;
809
810 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
811 priv->AntennaTxPwDiff[1]<<4 |
812 priv->AntennaTxPwDiff[0]);
813
814 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
815 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
816 }
817 }
818#ifdef TODO
819 if ( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
820 pMgntInfo->bWithCcxCellPwr &&
821 channel == pMgntInfo->dot11CurrentChannelNumber)
822 {
823 u8 CckCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
824 u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
825 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
826
827 RT_TRACE(COMP_TXAGC, DBG_LOUD,
828 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
829 pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
830 RT_TRACE(COMP_TXAGC, DBG_LOUD,
831 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
832 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
833
834 if (powerlevel > CckCellPwrIdx)
835 powerlevel = CckCellPwrIdx;
836 if (powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
837 {
838 if ((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
839 {
840 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
841 }
842 else
843 {
844 LegacyOfdmCellPwrIdx = 0;
845 }
846 }
847
848 RT_TRACE(COMP_TXAGC, DBG_LOUD,
849 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
850 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
851 }
852
853 pHalData->CurrentCckTxPwrIdx = powerlevel;
854 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
855
856 RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_GET_CHANNEL, &channel, &pChannelInfo);
857
858 if (pChannelInfo)
859 {
860 if (pChannelInfo->MaxTxPwrDbm != UNSPECIFIED_PWR_DBM)
861 {
862 u1Byte CckMaxPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pChannelInfo->MaxTxPwrDbm);
863 u1Byte LegacyOfdmMaxPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pChannelInfo->MaxTxPwrDbm);
864 u1Byte OfdmMaxPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pChannelInfo->MaxTxPwrDbm);
865
866 RT_TRACE(COMP_TXAGC, DBG_LOUD,
867 ("CCX Cell Limit: %ld dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
868 pChannelInfo->MaxTxPwrDbm, CckMaxPwrIdx, LegacyOfdmMaxPwrIdx, OfdmMaxPwrIdx));
869 RT_TRACE(COMP_TXAGC, DBG_LOUD,
870 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
871 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
872
873 if (powerlevel > CckMaxPwrIdx)
874 powerlevel = CckMaxPwrIdx;
875 if (powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmMaxPwrIdx)
876 {
877 if ((OfdmMaxPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
878 {
879 powerlevelOFDM24G = OfdmMaxPwrIdx - pHalData->LegacyHTTxPowerDiff;
880 }
881 else
882 {
883 LegacyOfdmMaxPwrIdx = 0;
884 }
885 }
886
887 RT_TRACE(COMP_TXAGC, DBG_LOUD,
888 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
889 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
890 }
891 }
892#endif
893 switch (priv->rf_chip)
894 {
895 case RF_8225:
896 break;
897 case RF_8256:
898 PHY_SetRF8256CCKTxPower(dev, powerlevel);
899 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
900 break;
901 case RF_8258:
902 break;
903 default:
904 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __func__);
905 break;
906 }
907 return;
908}
909
910bool rtl8192_phy_RFConfig(struct net_device* dev)
911{
912 struct r8192_priv *priv = rtllib_priv(dev);
913 bool rtStatus = true;
914 switch (priv->rf_chip)
915 {
916 case RF_8225:
917 break;
918 case RF_8256:
919 rtStatus = PHY_RF8256_Config(dev);
920 break;
921
922 case RF_8258:
923 break;
924 case RF_PSEUDO_11N:
925 break;
926
927 default:
928 RT_TRACE(COMP_ERR, "error chip id\n");
929 break;
930 }
931 return rtStatus;
932}
933
934void rtl8192_phy_updateInitGain(struct net_device* dev)
935{
936 return;
937}
938
939u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
940{
941
942 int i;
943 u8 ret = 0;
944
945 switch (eRFPath){
946 case RF90_PATH_A:
947 for (i = 0;i<RadioA_ArrayLength; i=i+2){
948
949 if (Rtl819XRadioA_Array[i] == 0xfe){
950 msleep(100);
951 continue;
952 }
953 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
954
955 }
956 break;
957 case RF90_PATH_B:
958 for (i = 0;i<RadioB_ArrayLength; i=i+2){
959
960 if (Rtl819XRadioB_Array[i] == 0xfe){
961 msleep(100);
962 continue;
963 }
964 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
965
966 }
967 break;
968 case RF90_PATH_C:
969 for (i = 0;i<RadioC_ArrayLength; i=i+2){
970
971 if (Rtl819XRadioC_Array[i] == 0xfe){
972 msleep(100);
973 continue;
974 }
975 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
976
977 }
978 break;
979 case RF90_PATH_D:
980 for (i = 0;i<RadioD_ArrayLength; i=i+2){
981
982 if (Rtl819XRadioD_Array[i] == 0xfe){
983 msleep(100);
984 continue;
985 }
986 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
987
988 }
989 break;
990 default:
991 break;
992 }
993
994 return ret;;
995
996}
997void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
998{
999 struct r8192_priv *priv = rtllib_priv(dev);
1000 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1001 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1002
1003 switch (priv->rf_chip)
1004 {
1005 case RF_8225:
1006#ifdef TO_DO_LIST
1007 PHY_SetRF8225CckTxPower(dev, powerlevel);
1008 PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
1009#endif
1010 break;
1011
1012 case RF_8256:
1013 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1014 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1015 break;
1016
1017 case RF_8258:
1018 break;
1019 default:
1020 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
1021 break;
1022 }
1023 return;
1024}
1025u8 rtl8192_phy_SetSwChnlCmdArray(
1026 SwChnlCmd* CmdTable,
1027 u32 CmdTableIdx,
1028 u32 CmdTableSz,
1029 SwChnlCmdID CmdID,
1030 u32 Para1,
1031 u32 Para2,
1032 u32 msDelay
1033 )
1034{
1035 SwChnlCmd* pCmd;
1036
1037 if (CmdTable == NULL)
1038 {
1039 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1040 return false;
1041 }
1042 if (CmdTableIdx >= CmdTableSz)
1043 {
1044 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1045 CmdTableIdx, CmdTableSz);
1046 return false;
1047 }
1048
1049 pCmd = CmdTable + CmdTableIdx;
1050 pCmd->CmdID = CmdID;
1051 pCmd->Para1 = Para1;
1052 pCmd->Para2 = Para2;
1053 pCmd->msDelay = msDelay;
1054
1055 return true;
1056}
1057u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
1058{
1059 struct r8192_priv *priv = rtllib_priv(dev);
1060 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1061 u32 PreCommonCmdCnt;
1062 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1063 u32 PostCommonCmdCnt;
1064 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1065 u32 RfDependCmdCnt;
1066 SwChnlCmd *CurrentCmd = NULL;
1067 u8 eRFPath;
1068
1069 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __func__, *stage, *step, channel);
1070
1071#ifdef ENABLE_DOT11D
1072 if (!IsLegalChannel(priv->rtllib, channel))
1073 {
1074 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1075 return true;
1076 }
1077#endif
1078
1079 {
1080 PreCommonCmdCnt = 0;
1081 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1082 CmdID_SetTxPowerLevel, 0, 0, 0);
1083 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1084 CmdID_End, 0, 0, 0);
1085
1086 PostCommonCmdCnt = 0;
1087
1088 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1089 CmdID_End, 0, 0, 0);
1090
1091 RfDependCmdCnt = 0;
1092 switch ( priv->rf_chip )
1093 {
1094 case RF_8225:
1095 if (!(channel >= 1 && channel <= 14))
1096 {
1097 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
1098 return false;
1099 }
1100 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1101 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
1102 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1103 CmdID_End, 0, 0, 0);
1104 break;
1105
1106 case RF_8256:
1107 if (!(channel >= 1 && channel <= 14))
1108 {
1109 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
1110 return false;
1111 }
1112 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1113 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1114 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1115 CmdID_End, 0, 0, 0);
1116 break;
1117
1118 case RF_8258:
1119 break;
1120
1121 default:
1122 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1123 return false;
1124 break;
1125 }
1126
1127
1128 do{
1129 switch (*stage)
1130 {
1131 case 0:
1132 CurrentCmd=&PreCommonCmd[*step];
1133 break;
1134 case 1:
1135 CurrentCmd=&RfDependCmd[*step];
1136 break;
1137 case 2:
1138 CurrentCmd=&PostCommonCmd[*step];
1139 break;
1140 }
1141
1142 if (CurrentCmd->CmdID==CmdID_End)
1143 {
1144 if ((*stage)==2)
1145 {
1146 return true;
1147 }
1148 else
1149 {
1150 (*stage)++;
1151 (*step)=0;
1152 continue;
1153 }
1154 }
1155
1156 switch (CurrentCmd->CmdID)
1157 {
1158 case CmdID_SetTxPowerLevel:
1159 if (priv->IC_Cut > (u8)VERSION_8190_BD)
1160 rtl8192_SetTxPowerLevel(dev,channel);
1161 break;
1162 case CmdID_WritePortUlong:
1163 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
1164 break;
1165 case CmdID_WritePortUshort:
1166 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
1167 break;
1168 case CmdID_WritePortUchar:
1169 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1170 break;
1171 case CmdID_RF_WriteReg:
1172 for (eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
1173 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
1174 break;
1175 default:
1176 break;
1177 }
1178
1179 break;
1180 }while(true);
1181 }/*for (Number of RF paths)*/
1182
1183 (*delay)=CurrentCmd->msDelay;
1184 (*step)++;
1185 return false;
1186}
1187
1188void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1189{
1190 struct r8192_priv *priv = rtllib_priv(dev);
1191 u32 delay = 0;
1192
1193 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
1194 {
1195 if (delay>0)
1196 msleep(delay);
1197 if (IS_NIC_DOWN(priv))
1198 break;
1199 }
1200}
1201void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1202{
1203
1204 struct r8192_priv *priv = rtllib_priv(dev);
1205
1206 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1207
1208 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, priv->chan, priv);
1209
1210 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1211
1212 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1213}
1214
1215u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
1216{
1217 struct r8192_priv *priv = rtllib_priv(dev);
1218 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1219 if (IS_NIC_DOWN(priv))
1220 {
1221 RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n",__func__);
1222 return false;
1223 }
1224 if (priv->SwChnlInProgress)
1225 return false;
1226
1227
1228 switch (priv->rtllib->mode)
1229 {
1230 case WIRELESS_MODE_A:
1231 case WIRELESS_MODE_N_5G:
1232 if (channel<=14){
1233 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1234 return false;
1235 }
1236 break;
1237 case WIRELESS_MODE_B:
1238 if (channel>14){
1239 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1240 return false;
1241 }
1242 break;
1243 case WIRELESS_MODE_G:
1244 case WIRELESS_MODE_N_24G:
1245 if (channel>14){
1246 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1247 return false;
1248 }
1249 break;
1250 }
1251
1252 priv->SwChnlInProgress = true;
1253 if (channel == 0)
1254 channel = 1;
1255
1256 priv->chan=channel;
1257
1258 priv->SwChnlStage=0;
1259 priv->SwChnlStep=0;
1260
1261 if (!IS_NIC_DOWN(priv)){
1262 rtl8192_SwChnl_WorkItem(dev);
1263 }
1264 priv->SwChnlInProgress = false;
1265 return true;
1266}
1267
1268static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
1269{
1270 struct r8192_priv *priv = rtllib_priv(dev);
1271
1272 switch (priv->CurrentChannelBW)
1273 {
1274 case HT_CHANNEL_WIDTH_20:
1275 priv->CCKPresentAttentuation =
1276 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
1277
1278 if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1279 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1280 if (priv->CCKPresentAttentuation < 0)
1281 priv->CCKPresentAttentuation = 0;
1282
1283 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1284
1285 if (priv->rtllib->current_network.channel== 14 && !priv->bcck_in_ch14)
1286 {
1287 priv->bcck_in_ch14 = true;
1288 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1289 }
1290 else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14)
1291 {
1292 priv->bcck_in_ch14 = false;
1293 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1294 }
1295 else
1296 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1297 break;
1298
1299 case HT_CHANNEL_WIDTH_20_40:
1300 priv->CCKPresentAttentuation =
1301 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
1302
1303 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1304 if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1305 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1306 if (priv->CCKPresentAttentuation < 0)
1307 priv->CCKPresentAttentuation = 0;
1308
1309 if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14)
1310 {
1311 priv->bcck_in_ch14 = true;
1312 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1313 }
1314 else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14)
1315 {
1316 priv->bcck_in_ch14 = false;
1317 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1318 }
1319 else
1320 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1321 break;
1322 }
1323}
1324
1325#ifndef RTL8190P
1326static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1327{
1328 struct r8192_priv *priv = rtllib_priv(dev);
1329
1330 if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14)
1331 priv->bcck_in_ch14 = true;
1332 else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14)
1333 priv->bcck_in_ch14 = false;
1334
1335 switch (priv->CurrentChannelBW)
1336 {
1337 case HT_CHANNEL_WIDTH_20:
1338 if (priv->Record_CCK_20Mindex == 0)
1339 priv->Record_CCK_20Mindex = 6;
1340 priv->CCK_index = priv->Record_CCK_20Mindex;
1341 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
1342 break;
1343
1344 case HT_CHANNEL_WIDTH_20_40:
1345 priv->CCK_index = priv->Record_CCK_40Mindex;
1346 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
1347 break;
1348 }
1349 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1350}
1351#endif
1352
1353static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
1354{
1355#ifdef RTL8192E
1356 struct r8192_priv *priv = rtllib_priv(dev);
1357#endif
1358
1359#ifdef RTL8190P
1360 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1361#else
1362 if (priv->IC_Cut >= IC_VersionCut_D)
1363 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1364 else
1365 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
1366#endif
1367}
1368
1369void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1370{
1371
1372 struct r8192_priv *priv = rtllib_priv(dev);
1373 u8 regBwOpMode;
1374
1375 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \
1376 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
1377
1378
1379 if (priv->rf_chip== RF_PSEUDO_11N)
1380 {
1381 priv->SetBWModeInProgress= false;
1382 return;
1383 }
1384 if (IS_NIC_DOWN(priv)){
1385 RT_TRACE(COMP_ERR,"%s(): ERR!! driver is not up\n",__func__);
1386 return;
1387 }
1388 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
1389
1390 switch (priv->CurrentChannelBW)
1391 {
1392 case HT_CHANNEL_WIDTH_20:
1393 regBwOpMode |= BW_OPMODE_20MHZ;
1394 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1395 break;
1396
1397 case HT_CHANNEL_WIDTH_20_40:
1398 regBwOpMode &= ~BW_OPMODE_20MHZ;
1399 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1400 break;
1401
1402 default:
1403 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
1404 break;
1405 }
1406
1407 switch (priv->CurrentChannelBW)
1408 {
1409 case HT_CHANNEL_WIDTH_20:
1410 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1411 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1412
1413 if (!priv->btxpower_tracking)
1414 {
1415 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
1416 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
1417 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
1418 }
1419 else
1420 CCK_Tx_Power_Track_BW_Switch(dev);
1421
1422#ifdef RTL8190P
1423 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
1424 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44);
1425#else
1426 #ifdef RTL8192E
1427 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1428 #endif
1429#endif
1430
1431 break;
1432 case HT_CHANNEL_WIDTH_20_40:
1433 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1434 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1435
1436 if (!priv->btxpower_tracking)
1437 {
1438 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
1439 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
1440 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
1441 }
1442 else
1443 CCK_Tx_Power_Track_BW_Switch(dev);
1444
1445 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
1446 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
1447
1448
1449#ifdef RTL8190P
1450 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
1451 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42);
1452
1453 if (priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1454 {
1455 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
1456 }else if (priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1457 {
1458 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
1459 }
1460
1461#else
1462 #ifdef RTL8192E
1463 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1464 #endif
1465#endif
1466 break;
1467 default:
1468 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
1469 break;
1470
1471 }
1472
1473#if 1
1474 switch ( priv->rf_chip )
1475 {
1476 case RF_8225:
1477#ifdef TO_DO_LIST
1478 PHY_SetRF8225Bandwidth(dev, pHalData->CurrentChannelBW);
1479#endif
1480 break;
1481
1482 case RF_8256:
1483 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1484 break;
1485
1486 case RF_8258:
1487 break;
1488
1489 case RF_PSEUDO_11N:
1490 break;
1491
1492 default:
1493 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1494 break;
1495 }
1496#endif
1497 atomic_dec(&(priv->rtllib->atm_swbw));
1498 priv->SetBWModeInProgress= false;
1499
1500 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1501}
1502
1503void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
1504{
1505 struct r8192_priv *priv = rtllib_priv(dev);
1506
1507
1508 if (priv->SetBWModeInProgress)
1509 return;
1510
1511 atomic_inc(&(priv->rtllib->atm_swbw));
1512 priv->SetBWModeInProgress= true;
1513
1514 priv->CurrentChannelBW = Bandwidth;
1515
1516 if (Offset==HT_EXTCHNL_OFFSET_LOWER)
1517 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1518 else if (Offset==HT_EXTCHNL_OFFSET_UPPER)
1519 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1520 else
1521 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1522
1523 rtl8192_SetBWModeWorkItem(dev);
1524
1525}
1526
1527
1528void InitialGain819xPci(struct net_device *dev, u8 Operation)
1529{
1530#define SCAN_RX_INITIAL_GAIN 0x17
1531#define POWER_DETECTION_TH 0x08
1532 struct r8192_priv *priv = rtllib_priv(dev);
1533 u32 BitMask;
1534 u8 initial_gain;
1535
1536 if (!IS_NIC_DOWN(priv)){
1537 switch (Operation)
1538 {
1539 case IG_Backup:
1540 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1541 initial_gain = SCAN_RX_INITIAL_GAIN;
1542 BitMask = bMaskByte0;
1543 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1544 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1545 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
1546 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
1547 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
1548 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
1549 BitMask = bMaskByte2;
1550 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
1551
1552 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1553 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1554 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1555 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1556 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1557
1558 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
1559 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1560 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1561 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1562 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1563 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
1564 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1565 break;
1566 case IG_Restore:
1567 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1568 BitMask = 0x7f;
1569 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1570 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1571
1572 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
1573 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
1574 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
1575 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
1576 BitMask = bMaskByte2;
1577 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
1578
1579 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1580 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1581 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1582 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1583 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1584
1585 rtl8192_phy_setTxPower(dev,priv->rtllib->current_network.channel);
1586
1587
1588 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1589 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1590 break;
1591 default:
1592 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1593 break;
1594 }
1595 }
1596}
1597
1598#if defined RTL8190P
1599extern void
1600PHY_SetRtl8190pRfOff(struct net_device* dev )
1601{
1602 struct r8192_priv *priv = rtllib_priv(dev);
1603
1604 if (priv->rf_type == RF_2T4R)
1605 {
1606 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1607 }
1608 rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x0);
1609 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
1610 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0x0);
1611 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1612 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1613 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0x0);
1614
1615}
1616#endif
1617
1618#if defined RTL8192E
1619extern void
1620PHY_SetRtl8192eRfOff(struct net_device* dev )
1621{
1622
1623 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1624 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1625 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1626 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1627 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1628 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1629 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1630 write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
1631
1632}
1633#endif
1634
1635#ifndef RTL8192SE
1636bool
1637SetRFPowerState8190(
1638 struct net_device* dev,
1639 RT_RF_POWER_STATE eRFPowerState
1640 )
1641{
1642 struct r8192_priv *priv = rtllib_priv(dev);
1643#if defined RTL8192E
1644 PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
1645#endif
1646 bool bResult = true;
1647 u8 i = 0, QueueID = 0;
1648 struct rtl8192_tx_ring *ring = NULL;
1649
1650 if (priv->SetRFPowerStateInProgress == true)
1651 return false;
1652 RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
1653 priv->SetRFPowerStateInProgress = true;
1654
1655 switch (priv->rf_chip)
1656 {
1657 case RF_8256:
1658 switch ( eRFPowerState )
1659 {
1660 case eRfOn:
1661 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n");
1662 #ifdef RTL8190P
1663 if (priv->rf_type == RF_2T4R)
1664 {
1665 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);
1666 rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1);
1667 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);
1668 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf);
1669 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf);
1670 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf);
1671 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf);
1672 }
1673 else if (priv->rf_type == RF_1T2R)
1674 {
1675 rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1);
1676 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);
1677 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3);
1678 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3);
1679 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3);
1680 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3);
1681 }
1682 else if (priv->rf_type == RF_1T1R)
1683 {
1684 rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1);
1685 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x400, 0x1);
1686 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1);
1687 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x4, 0x1);
1688 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x4, 0x1);
1689 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1);
1690 }
1691
1692#elif defined RTL8192E
1693 if ((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
1694 {
1695 bool rtstatus = true;
1696 u32 InitilizeCount = 3;
1697 do
1698 {
1699 InitilizeCount--;
1700 priv->RegRfOff = false;
1701 rtstatus = NicIFEnableNIC(dev);
1702 }while( (rtstatus != true) &&(InitilizeCount >0) );
1703
1704 if (rtstatus != true)
1705 {
1706 RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__func__);
1707 priv->SetRFPowerStateInProgress = false;
1708 return false;
1709 }
1710
1711 RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1712 } else {
1713 write_nic_byte(dev, ANAPAR, 0x37);
1714 mdelay(1);
1715 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1);
1716 priv->bHwRfOffAction = 0;
1717
1718 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);
1719 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
1720 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3);
1721 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1722 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1723 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3);
1724
1725 }
1726
1727 #endif
1728 break;
1729
1730 case eRfSleep:
1731 {
1732 if (priv->rtllib->eRFPowerState == eRfOff)
1733 break;
1734
1735
1736 {
1737 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
1738 {
1739 ring = &priv->tx_ring[QueueID];
1740
1741 if (skb_queue_len(&ring->queue) == 0) {
1742 QueueID++;
1743 continue;
1744 }
1745#ifdef TO_DO_LIST
1746 else if (IsLowPowerState(Adapter))
1747 {
1748 RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID);
1749 break;
1750 }
1751#endif
1752 else
1753 {
1754 RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1755 udelay(10);
1756 i++;
1757 }
1758
1759 if (i >= MAX_DOZE_WAITING_TIMES_9x)
1760 {
1761 RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
1762 break;
1763 }
1764 }
1765 }
1766
1767#ifdef RTL8190P
1768 {
1769 PHY_SetRtl8190pRfOff(dev);
1770 }
1771#elif defined RTL8192E
1772 {
1773 PHY_SetRtl8192eRfOff(dev);
1774 }
1775#endif
1776 }
1777 break;
1778
1779 case eRfOff:
1780 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/Sleep !\n");
1781
1782
1783 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1784 ring = &priv->tx_ring[QueueID];
1785
1786 if (skb_queue_len(&ring->queue) == 0) {
1787 QueueID++;
1788 continue;
1789 }
1790#ifdef TO_DO_LIST
1791 else if (IsLowPowerState(Adapter))
1792 {
1793 RT_TRACE(COMP_POWER,
1794 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID);
1795 break;
1796 }
1797#endif
1798 else
1799 {
1800 RT_TRACE(COMP_POWER,
1801 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1802 udelay(10);
1803 i++;
1804 }
1805
1806 if (i >= MAX_DOZE_WAITING_TIMES_9x)
1807 {
1808 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
1809 break;
1810 }
1811 }
1812
1813#if defined RTL8190P
1814 {
1815 PHY_SetRtl8190pRfOff(dev);
1816 }
1817#elif defined RTL8192E
1818 {
1819 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
1820 {
1821
1822 NicIFDisableNIC(dev);
1823 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1824 }
1825 else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
1826 {
1827 PHY_SetRtl8192eRfOff(dev);
1828 }
1829#ifdef TO_DO_LIST
1830 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS )
1831 {
1832 Adapter->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
1833 }
1834 else
1835 {
1836 Adapter->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
1837 }
1838#endif
1839 }
1840#else
1841 else
1842 {
1843 RT_TRACE(COMP_DBG,DBG_TRACE,("It is not 8190Pci and 8192PciE \n"));
1844 }
1845 #endif
1846
1847 break;
1848
1849 default:
1850 bResult = false;
1851 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1852 break;
1853 }
1854
1855 break;
1856
1857 default:
1858 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1859 break;
1860 }
1861
1862 if (bResult) {
1863 priv->rtllib->eRFPowerState = eRFPowerState;
1864
1865 switch (priv->rf_chip )
1866 {
1867 case RF_8256:
1868 switch (priv->rtllib->eRFPowerState)
1869 {
1870 case eRfOff:
1871 if (priv->rtllib->RfOffReason==RF_CHANGE_BY_IPS ) {
1872 #ifdef TO_DO
1873 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
1874 #endif
1875 } else {
1876 #ifdef TO_DO
1877 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
1878 #endif
1879 }
1880 break;
1881
1882 case eRfOn:
1883 if ( priv->rtllib->state == RTLLIB_LINKED) {
1884 #ifdef TO_DO
1885 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
1886 #endif
1887 } else {
1888 #ifdef TO_DO
1889 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
1890 #endif
1891 }
1892 break;
1893
1894 default:
1895 break;
1896 }
1897
1898 break;
1899
1900 default:
1901 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1902 break;
1903 }
1904 }
1905
1906 priv->SetRFPowerStateInProgress = false;
1907 RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult);
1908 return bResult;
1909}
1910
1911
1912
1913bool
1914SetRFPowerState(
1915 struct net_device* dev,
1916 RT_RF_POWER_STATE eRFPowerState
1917 )
1918{
1919 struct r8192_priv *priv = rtllib_priv(dev);
1920
1921 bool bResult = false;
1922
1923 RT_TRACE(COMP_PS,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1924 if (eRFPowerState == priv->rtllib->eRFPowerState && priv->bHwRfOffAction == 0) {
1925 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
1926 return bResult;
1927 }
1928
1929 bResult = SetRFPowerState8190(dev, eRFPowerState);
1930
1931 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", bResult);
1932
1933 return bResult;
1934}
1935#endif
1936
1937extern void
1938PHY_ScanOperationBackup8192(
1939 struct net_device* dev,
1940 u8 Operation
1941 )
1942{
1943 struct r8192_priv *priv = rtllib_priv(dev);
1944
1945 if (priv->up) {
1946 switch (Operation) {
1947 case SCAN_OPT_BACKUP:
1948 priv->rtllib->InitialGainHandler(dev,IG_Backup);
1949 break;
1950
1951 case SCAN_OPT_RESTORE:
1952 priv->rtllib->InitialGainHandler(dev,IG_Restore);
1953 break;
1954
1955 default:
1956 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation. \n");
1957 break;
1958 }
1959 }
1960
1961}
1962
1963#endif
Linux kernel - Deliverables
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