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94a79942 LF |
1 | /****************************************************************************** |
2 | * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. | |
3 | * | |
4 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
5 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
6 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
7 | * more details. | |
8 | * | |
9 | * You should have received a copy of the GNU General Public License along with | |
10 | * this program; if not, write to the Free Software Foundation, Inc., | |
11 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in the | |
14 | * file called LICENSE. | |
15 | * | |
16 | * Contact Information: | |
17 | * wlanfae <wlanfae@realtek.com> | |
18 | ******************************************************************************/ | |
94a79942 LF |
19 | |
20 | #include "rtl_core.h" | |
21 | #include "r8192E_hw.h" | |
22 | #include "r8192E_phyreg.h" | |
23 | #include "r8190P_rtl8256.h" | |
24 | #include "r8192E_phy.h" | |
25 | #include "rtl_dm.h" | |
94a79942 | 26 | #include "dot11d.h" |
94a79942 | 27 | |
94a79942 | 28 | #include "r8192E_hwimg.h" |
94a79942 LF |
29 | |
30 | static u32 RF_CHANNEL_TABLE_ZEBRA[] = { | |
31 | 0, | |
32 | 0x085c, | |
33 | 0x08dc, | |
34 | 0x095c, | |
35 | 0x09dc, | |
36 | 0x0a5c, | |
37 | 0x0adc, | |
38 | 0x0b5c, | |
39 | 0x0bdc, | |
40 | 0x0c5c, | |
41 | 0x0cdc, | |
42 | 0x0d5c, | |
43 | 0x0ddc, | |
44 | 0x0e5c, | |
45 | 0x0f72, | |
46 | }; | |
47 | ||
48 | /*************************Define local function prototype**********************/ | |
49 | ||
547d0c34 LF |
50 | static u32 phy_FwRFSerialRead(struct net_device *dev, |
51 | enum rf90_radio_path eRFPath, | |
52 | u32 Offset); | |
53 | static void phy_FwRFSerialWrite(struct net_device *dev, | |
54 | enum rf90_radio_path eRFPath, | |
55 | u32 Offset, u32 Data); | |
49aab5fd LF |
56 | |
57 | static u32 rtl8192_CalculateBitShift(u32 dwBitMask) | |
94a79942 LF |
58 | { |
59 | u32 i; | |
547d0c34 LF |
60 | for (i = 0; i <= 31; i++) { |
61 | if (((dwBitMask >> i) & 0x1) == 1) | |
94a79942 LF |
62 | break; |
63 | } | |
64 | return i; | |
65 | } | |
547d0c34 LF |
66 | |
67 | u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) | |
94a79942 LF |
68 | { |
69 | u8 ret = 1; | |
70 | struct r8192_priv *priv = rtllib_priv(dev); | |
94a79942 LF |
71 | if (priv->rf_type == RF_2T4R) |
72 | ret = 0; | |
547d0c34 | 73 | else if (priv->rf_type == RF_1T2R) { |
94a79942 LF |
74 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) |
75 | ret = 1; | |
76 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) | |
77 | ret = 0; | |
78 | } | |
94a79942 LF |
79 | return ret; |
80 | } | |
547d0c34 LF |
81 | |
82 | void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, | |
83 | u32 dwData) | |
94a79942 LF |
84 | { |
85 | ||
86 | u32 OriginalValue, BitShift, NewValue; | |
87 | ||
547d0c34 | 88 | if (dwBitMask != bMaskDWord) { |
94a79942 LF |
89 | OriginalValue = read_nic_dword(dev, dwRegAddr); |
90 | BitShift = rtl8192_CalculateBitShift(dwBitMask); | |
547d0c34 LF |
91 | NewValue = (((OriginalValue) & (~dwBitMask)) | |
92 | (dwData << BitShift)); | |
94a79942 | 93 | write_nic_dword(dev, dwRegAddr, NewValue); |
547d0c34 | 94 | } else |
94a79942 LF |
95 | write_nic_dword(dev, dwRegAddr, dwData); |
96 | return; | |
97 | } | |
547d0c34 LF |
98 | |
99 | u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) | |
94a79942 LF |
100 | { |
101 | u32 Ret = 0, OriginalValue, BitShift; | |
102 | ||
103 | OriginalValue = read_nic_dword(dev, dwRegAddr); | |
104 | BitShift = rtl8192_CalculateBitShift(dwBitMask); | |
105 | Ret = (OriginalValue & dwBitMask) >> BitShift; | |
106 | ||
547d0c34 | 107 | return Ret; |
94a79942 | 108 | } |
49aab5fd LF |
109 | static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, |
110 | enum rf90_radio_path eRFPath, u32 Offset) | |
94a79942 LF |
111 | { |
112 | struct r8192_priv *priv = rtllib_priv(dev); | |
113 | u32 ret = 0; | |
114 | u32 NewOffset = 0; | |
547d0c34 | 115 | struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; |
94a79942 LF |
116 | Offset &= 0x3f; |
117 | ||
547d0c34 | 118 | if (priv->rf_chip == RF_8256) { |
94a79942 | 119 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
547d0c34 | 120 | if (Offset >= 31) { |
94a79942 | 121 | priv->RfReg0Value[eRFPath] |= 0x140; |
547d0c34 LF |
122 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
123 | bMaskDWord, | |
124 | (priv->RfReg0Value[eRFPath]<<16)); | |
125 | NewOffset = Offset - 30; | |
126 | } else if (Offset >= 16) { | |
94a79942 LF |
127 | priv->RfReg0Value[eRFPath] |= 0x100; |
128 | priv->RfReg0Value[eRFPath] &= (~0x40); | |
547d0c34 LF |
129 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
130 | bMaskDWord, | |
131 | (priv->RfReg0Value[eRFPath]<<16)); | |
94a79942 LF |
132 | |
133 | NewOffset = Offset - 15; | |
547d0c34 | 134 | } else |
94a79942 | 135 | NewOffset = Offset; |
547d0c34 LF |
136 | } else { |
137 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need" | |
138 | " to be 8256\n"); | |
94a79942 LF |
139 | NewOffset = Offset; |
140 | } | |
547d0c34 LF |
141 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, |
142 | NewOffset); | |
94a79942 LF |
143 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); |
144 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); | |
145 | ||
547d0c34 | 146 | mdelay(1); |
94a79942 | 147 | |
547d0c34 LF |
148 | ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, |
149 | bLSSIReadBackData); | |
94a79942 | 150 | |
547d0c34 | 151 | if (priv->rf_chip == RF_8256) { |
94a79942 LF |
152 | priv->RfReg0Value[eRFPath] &= 0xebf; |
153 | ||
547d0c34 LF |
154 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, |
155 | (priv->RfReg0Value[eRFPath] << 16)); | |
94a79942 | 156 | |
94a79942 | 157 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); |
94a79942 LF |
158 | } |
159 | ||
160 | ||
161 | return ret; | |
162 | ||
163 | } | |
164 | ||
49aab5fd LF |
165 | static void rtl8192_phy_RFSerialWrite(struct net_device *dev, |
166 | enum rf90_radio_path eRFPath, u32 Offset, | |
167 | u32 Data) | |
94a79942 LF |
168 | { |
169 | struct r8192_priv *priv = rtllib_priv(dev); | |
170 | u32 DataAndAddr = 0, NewOffset = 0; | |
9bf6e4c1 | 171 | struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; |
94a79942 LF |
172 | |
173 | Offset &= 0x3f; | |
547d0c34 | 174 | if (priv->rf_chip == RF_8256) { |
94a79942 | 175 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
94a79942 | 176 | |
547d0c34 | 177 | if (Offset >= 31) { |
94a79942 | 178 | priv->RfReg0Value[eRFPath] |= 0x140; |
547d0c34 LF |
179 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
180 | bMaskDWord, | |
181 | (priv->RfReg0Value[eRFPath] << 16)); | |
94a79942 | 182 | NewOffset = Offset - 30; |
547d0c34 | 183 | } else if (Offset >= 16) { |
94a79942 LF |
184 | priv->RfReg0Value[eRFPath] |= 0x100; |
185 | priv->RfReg0Value[eRFPath] &= (~0x40); | |
547d0c34 LF |
186 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
187 | bMaskDWord, | |
188 | (priv->RfReg0Value[eRFPath] << 16)); | |
94a79942 | 189 | NewOffset = Offset - 15; |
547d0c34 | 190 | } else |
94a79942 | 191 | NewOffset = Offset; |
547d0c34 LF |
192 | } else { |
193 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be" | |
194 | " 8256\n"); | |
94a79942 LF |
195 | NewOffset = Offset; |
196 | } | |
197 | ||
198 | DataAndAddr = (Data<<16) | (NewOffset&0x3f); | |
199 | ||
200 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); | |
201 | ||
547d0c34 | 202 | if (Offset == 0x0) |
94a79942 LF |
203 | priv->RfReg0Value[eRFPath] = Data; |
204 | ||
547d0c34 LF |
205 | if (priv->rf_chip == RF_8256) { |
206 | if (Offset != 0) { | |
94a79942 LF |
207 | priv->RfReg0Value[eRFPath] &= 0xebf; |
208 | rtl8192_setBBreg( | |
209 | dev, | |
210 | pPhyReg->rf3wireOffset, | |
211 | bMaskDWord, | |
212 | (priv->RfReg0Value[eRFPath] << 16)); | |
213 | } | |
94a79942 | 214 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); |
94a79942 | 215 | } |
94a79942 LF |
216 | return; |
217 | } | |
218 | ||
547d0c34 LF |
219 | void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, |
220 | u32 RegAddr, u32 BitMask, u32 Data) | |
94a79942 LF |
221 | { |
222 | struct r8192_priv *priv = rtllib_priv(dev); | |
223 | u32 Original_Value, BitShift, New_Value; | |
224 | ||
225 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | |
226 | return; | |
94a79942 LF |
227 | if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) |
228 | return; | |
94a79942 LF |
229 | |
230 | RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); | |
547d0c34 LF |
231 | if (priv->Rf_Mode == RF_OP_By_FW) { |
232 | if (BitMask != bMask12Bits) { | |
233 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, | |
234 | RegAddr); | |
94a79942 | 235 | BitShift = rtl8192_CalculateBitShift(BitMask); |
547d0c34 LF |
236 | New_Value = (((Original_Value) & (~BitMask)) | |
237 | (Data << BitShift)); | |
94a79942 LF |
238 | |
239 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); | |
547d0c34 | 240 | } else |
94a79942 LF |
241 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); |
242 | udelay(200); | |
243 | ||
547d0c34 LF |
244 | } else { |
245 | if (BitMask != bMask12Bits) { | |
246 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, | |
247 | RegAddr); | |
94a79942 | 248 | BitShift = rtl8192_CalculateBitShift(BitMask); |
547d0c34 LF |
249 | New_Value = (((Original_Value) & (~BitMask)) | |
250 | (Data << BitShift)); | |
94a79942 | 251 | |
547d0c34 LF |
252 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, |
253 | New_Value); | |
254 | } else | |
94a79942 LF |
255 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); |
256 | } | |
257 | return; | |
258 | } | |
259 | ||
547d0c34 LF |
260 | u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, |
261 | u32 RegAddr, u32 BitMask) | |
94a79942 LF |
262 | { |
263 | u32 Original_Value, Readback_Value, BitShift; | |
264 | struct r8192_priv *priv = rtllib_priv(dev); | |
265 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | |
266 | return 0; | |
94a79942 LF |
267 | if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) |
268 | return 0; | |
94a79942 | 269 | down(&priv->rf_sem); |
547d0c34 | 270 | if (priv->Rf_Mode == RF_OP_By_FW) { |
94a79942 LF |
271 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); |
272 | udelay(200); | |
547d0c34 LF |
273 | } else { |
274 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, | |
275 | RegAddr); | |
94a79942 LF |
276 | } |
277 | BitShift = rtl8192_CalculateBitShift(BitMask); | |
278 | Readback_Value = (Original_Value & BitMask) >> BitShift; | |
279 | up(&priv->rf_sem); | |
547d0c34 | 280 | return Readback_Value; |
94a79942 LF |
281 | } |
282 | ||
547d0c34 LF |
283 | static u32 phy_FwRFSerialRead(struct net_device *dev, |
284 | enum rf90_radio_path eRFPath, u32 Offset) | |
94a79942 LF |
285 | { |
286 | u32 retValue = 0; | |
287 | u32 Data = 0; | |
288 | u8 time = 0; | |
547d0c34 LF |
289 | Data |= ((Offset & 0xFF) << 12); |
290 | Data |= ((eRFPath & 0x3) << 20); | |
94a79942 | 291 | Data |= 0x80000000; |
547d0c34 | 292 | while (read_nic_dword(dev, QPNR)&0x80000000) { |
94a79942 | 293 | if (time++ < 100) |
94a79942 | 294 | udelay(10); |
94a79942 LF |
295 | else |
296 | break; | |
297 | } | |
298 | write_nic_dword(dev, QPNR, Data); | |
547d0c34 | 299 | while (read_nic_dword(dev, QPNR) & 0x80000000) { |
94a79942 | 300 | if (time++ < 100) |
94a79942 | 301 | udelay(10); |
94a79942 | 302 | else |
547d0c34 | 303 | return 0; |
94a79942 LF |
304 | } |
305 | retValue = read_nic_dword(dev, RF_DATA); | |
306 | ||
547d0c34 | 307 | return retValue; |
94a79942 LF |
308 | |
309 | } /* phy_FwRFSerialRead */ | |
310 | ||
547d0c34 LF |
311 | static void phy_FwRFSerialWrite(struct net_device *dev, |
312 | enum rf90_radio_path eRFPath, | |
313 | u32 Offset, u32 Data) | |
94a79942 LF |
314 | { |
315 | u8 time = 0; | |
316 | ||
547d0c34 LF |
317 | Data |= ((Offset & 0xFF) << 12); |
318 | Data |= ((eRFPath & 0x3) << 20); | |
94a79942 LF |
319 | Data |= 0x400000; |
320 | Data |= 0x80000000; | |
321 | ||
547d0c34 | 322 | while (read_nic_dword(dev, QPNR) & 0x80000000) { |
94a79942 | 323 | if (time++ < 100) |
94a79942 | 324 | udelay(10); |
94a79942 LF |
325 | else |
326 | break; | |
327 | } | |
328 | write_nic_dword(dev, QPNR, Data); | |
329 | ||
330 | } /* phy_FwRFSerialWrite */ | |
331 | ||
332 | ||
547d0c34 | 333 | void rtl8192_phy_configmac(struct net_device *dev) |
94a79942 LF |
334 | { |
335 | u32 dwArrayLen = 0, i = 0; | |
547d0c34 | 336 | u32 *pdwArray = NULL; |
94a79942 | 337 | struct r8192_priv *priv = rtllib_priv(dev); |
547d0c34 LF |
338 | |
339 | if (priv->bTXPowerDataReadFromEEPORM) { | |
94a79942 LF |
340 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); |
341 | dwArrayLen = MACPHY_Array_PGLength; | |
342 | pdwArray = Rtl819XMACPHY_Array_PG; | |
343 | ||
547d0c34 LF |
344 | } else { |
345 | RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n"); | |
94a79942 LF |
346 | dwArrayLen = MACPHY_ArrayLength; |
347 | pdwArray = Rtl819XMACPHY_Array; | |
348 | } | |
547d0c34 LF |
349 | for (i = 0; i < dwArrayLen; i += 3) { |
350 | RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC" | |
351 | "PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", | |
352 | pdwArray[i], pdwArray[i+1], pdwArray[i+2]); | |
94a79942 | 353 | if (pdwArray[i] == 0x318) |
94a79942 | 354 | pdwArray[i+2] = 0x00000800; |
547d0c34 LF |
355 | rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], |
356 | pdwArray[i+2]); | |
94a79942 LF |
357 | } |
358 | return; | |
359 | ||
360 | } | |
361 | ||
547d0c34 | 362 | void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) |
94a79942 LF |
363 | { |
364 | int i; | |
547d0c34 LF |
365 | u32 *Rtl819XPHY_REGArray_Table = NULL; |
366 | u32 *Rtl819XAGCTAB_Array_Table = NULL; | |
367 | u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; | |
94a79942 | 368 | struct r8192_priv *priv = rtllib_priv(dev); |
547d0c34 LF |
369 | |
370 | AGCTAB_ArrayLen = AGCTAB_ArrayLength; | |
371 | Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; | |
372 | if (priv->rf_type == RF_2T4R) { | |
373 | PHY_REGArrayLen = PHY_REGArrayLength; | |
374 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; | |
375 | } else if (priv->rf_type == RF_1T2R) { | |
376 | PHY_REGArrayLen = PHY_REG_1T2RArrayLength; | |
377 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; | |
94a79942 LF |
378 | } |
379 | ||
547d0c34 LF |
380 | if (ConfigType == BaseBand_Config_PHY_REG) { |
381 | for (i = 0; i < PHY_REGArrayLen; i += 2) { | |
382 | rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], | |
383 | bMaskDWord, | |
384 | Rtl819XPHY_REGArray_Table[i+1]); | |
385 | RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray" | |
386 | "[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n", | |
387 | i, Rtl819XPHY_REGArray_Table[i], | |
388 | Rtl819XPHY_REGArray_Table[i+1]); | |
94a79942 | 389 | } |
547d0c34 LF |
390 | } else if (ConfigType == BaseBand_Config_AGC_TAB) { |
391 | for (i = 0; i < AGCTAB_ArrayLen; i += 2) { | |
392 | rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], | |
393 | bMaskDWord, | |
394 | Rtl819XAGCTAB_Array_Table[i+1]); | |
395 | RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] " | |
396 | "is %x rtl819XAGCTAB_Array[1] is %x\n", i, | |
397 | Rtl819XAGCTAB_Array_Table[i], | |
398 | Rtl819XAGCTAB_Array_Table[i+1]); | |
94a79942 LF |
399 | } |
400 | } | |
401 | return; | |
94a79942 | 402 | } |
547d0c34 | 403 | |
49aab5fd | 404 | static void rtl8192_InitBBRFRegDef(struct net_device *dev) |
94a79942 LF |
405 | { |
406 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 | 407 | |
94a79942 LF |
408 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; |
409 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; | |
410 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; | |
411 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; | |
412 | ||
413 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; | |
414 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; | |
415 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; | |
416 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; | |
417 | ||
418 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; | |
419 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; | |
420 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; | |
421 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; | |
422 | ||
423 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; | |
424 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; | |
425 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; | |
426 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; | |
427 | ||
428 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; | |
429 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; | |
430 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; | |
431 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; | |
432 | ||
433 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; | |
434 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; | |
435 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; | |
436 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; | |
437 | ||
438 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; | |
439 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; | |
440 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; | |
441 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; | |
442 | ||
443 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; | |
444 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; | |
445 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; | |
446 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; | |
447 | ||
448 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; | |
449 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; | |
450 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; | |
451 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; | |
452 | ||
453 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; | |
454 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; | |
455 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; | |
456 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; | |
457 | ||
458 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; | |
459 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; | |
460 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; | |
461 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; | |
462 | ||
463 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; | |
464 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; | |
465 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; | |
466 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; | |
467 | ||
468 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; | |
469 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; | |
470 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; | |
471 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; | |
472 | ||
473 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; | |
474 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; | |
475 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; | |
476 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; | |
477 | ||
478 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; | |
479 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; | |
480 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; | |
481 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; | |
482 | ||
483 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; | |
484 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; | |
485 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; | |
486 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; | |
487 | ||
488 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; | |
489 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; | |
490 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; | |
491 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; | |
492 | ||
493 | } | |
547d0c34 LF |
494 | |
495 | bool rtl8192_phy_checkBBAndRF(struct net_device *dev, | |
496 | enum hw90_block CheckBlock, | |
497 | enum rf90_radio_path eRFPath) | |
94a79942 LF |
498 | { |
499 | bool ret = true; | |
500 | u32 i, CheckTimes = 4, dwRegRead = 0; | |
501 | u32 WriteAddr[4]; | |
502 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; | |
547d0c34 | 503 | |
94a79942 LF |
504 | WriteAddr[HW90_BLOCK_MAC] = 0x100; |
505 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; | |
506 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; | |
507 | WriteAddr[HW90_BLOCK_RF] = 0x3; | |
547d0c34 LF |
508 | RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, |
509 | CheckBlock); | |
510 | for (i = 0; i < CheckTimes; i++) { | |
511 | switch (CheckBlock) { | |
94a79942 | 512 | case HW90_BLOCK_MAC: |
547d0c34 LF |
513 | RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write " |
514 | "0x100 here!"); | |
94a79942 LF |
515 | break; |
516 | ||
517 | case HW90_BLOCK_PHY0: | |
518 | case HW90_BLOCK_PHY1: | |
547d0c34 LF |
519 | write_nic_dword(dev, WriteAddr[CheckBlock], |
520 | WriteData[i]); | |
94a79942 LF |
521 | dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); |
522 | break; | |
523 | ||
524 | case HW90_BLOCK_RF: | |
525 | WriteData[i] &= 0xfff; | |
547d0c34 LF |
526 | rtl8192_phy_SetRFReg(dev, eRFPath, |
527 | WriteAddr[HW90_BLOCK_RF], | |
528 | bMask12Bits, WriteData[i]); | |
94a79942 | 529 | mdelay(10); |
547d0c34 LF |
530 | dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, |
531 | WriteAddr[HW90_BLOCK_RF], | |
532 | bMaskDWord); | |
94a79942 LF |
533 | mdelay(10); |
534 | break; | |
535 | ||
536 | default: | |
537 | ret = false; | |
538 | break; | |
539 | } | |
540 | ||
541 | ||
547d0c34 LF |
542 | if (dwRegRead != WriteData[i]) { |
543 | RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, " | |
544 | "WriteData: %x\n", dwRegRead, WriteData[i]); | |
94a79942 LF |
545 | ret = false; |
546 | break; | |
547 | } | |
548 | } | |
549 | ||
550 | return ret; | |
551 | } | |
552 | ||
49aab5fd | 553 | static bool rtl8192_BB_Config_ParaFile(struct net_device *dev) |
94a79942 LF |
554 | { |
555 | struct r8192_priv *priv = rtllib_priv(dev); | |
556 | bool rtStatus = true; | |
557 | u8 bRegValue = 0, eCheckItem = 0; | |
558 | u32 dwRegValue = 0; | |
94a79942 LF |
559 | |
560 | bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); | |
547d0c34 | 561 | write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); |
94a79942 LF |
562 | |
563 | dwRegValue = read_nic_dword(dev, CPU_GEN); | |
564 | write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); | |
565 | ||
547d0c34 LF |
566 | for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; |
567 | eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { | |
568 | rtStatus = rtl8192_phy_checkBBAndRF(dev, | |
569 | (enum hw90_block)eCheckItem, | |
570 | (enum rf90_radio_path)0); | |
571 | if (rtStatus != true) { | |
572 | RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():" | |
573 | "Check PHY%d Fail!!\n", eCheckItem-1); | |
94a79942 LF |
574 | return rtStatus; |
575 | } | |
576 | } | |
577 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); | |
578 | rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); | |
579 | ||
580 | dwRegValue = read_nic_dword(dev, CPU_GEN); | |
581 | write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); | |
582 | ||
583 | rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); | |
584 | ||
547d0c34 | 585 | if (priv->IC_Cut > VERSION_8190_BD) { |
94a79942 | 586 | if (priv->rf_type == RF_2T4R) |
547d0c34 LF |
587 | dwRegValue = (priv->AntennaTxPwDiff[2]<<8 | |
588 | priv->AntennaTxPwDiff[1]<<4 | | |
589 | priv->AntennaTxPwDiff[0]); | |
94a79942 LF |
590 | else |
591 | dwRegValue = 0x0; | |
592 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, | |
593 | (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); | |
594 | ||
595 | ||
94a79942 | 596 | dwRegValue = priv->CrystalCap; |
547d0c34 LF |
597 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, |
598 | dwRegValue); | |
94a79942 LF |
599 | } |
600 | ||
601 | return rtStatus; | |
602 | } | |
547d0c34 | 603 | bool rtl8192_BBConfig(struct net_device *dev) |
94a79942 LF |
604 | { |
605 | bool rtStatus = true; | |
547d0c34 | 606 | |
94a79942 LF |
607 | rtl8192_InitBBRFRegDef(dev); |
608 | rtStatus = rtl8192_BB_Config_ParaFile(dev); | |
609 | return rtStatus; | |
610 | } | |
611 | ||
547d0c34 | 612 | void rtl8192_phy_getTxPower(struct net_device *dev) |
94a79942 LF |
613 | { |
614 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 | 615 | |
94a79942 LF |
616 | priv->MCSTxPowerLevelOriginalOffset[0] = |
617 | read_nic_dword(dev, rTxAGC_Rate18_06); | |
618 | priv->MCSTxPowerLevelOriginalOffset[1] = | |
619 | read_nic_dword(dev, rTxAGC_Rate54_24); | |
620 | priv->MCSTxPowerLevelOriginalOffset[2] = | |
621 | read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); | |
622 | priv->MCSTxPowerLevelOriginalOffset[3] = | |
623 | read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); | |
624 | priv->MCSTxPowerLevelOriginalOffset[4] = | |
625 | read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); | |
626 | priv->MCSTxPowerLevelOriginalOffset[5] = | |
627 | read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); | |
94a79942 LF |
628 | |
629 | priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); | |
630 | priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); | |
631 | priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); | |
632 | priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); | |
547d0c34 LF |
633 | RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, " |
634 | "c60=0x%x, c68=0x%x)\n", | |
94a79942 LF |
635 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], |
636 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); | |
637 | ||
638 | priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); | |
639 | priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); | |
547d0c34 | 640 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", |
94a79942 LF |
641 | rOFDM0_RxDetector3, priv->framesync); |
642 | priv->SifsTime = read_nic_word(dev, SIFS); | |
643 | return; | |
644 | } | |
645 | ||
547d0c34 | 646 | void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) |
94a79942 LF |
647 | { |
648 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 | 649 | u8 powerlevel = 0, powerlevelOFDM24G = 0; |
94a79942 LF |
650 | char ant_pwr_diff; |
651 | u32 u4RegValue; | |
652 | ||
547d0c34 | 653 | if (priv->epromtype == EEPROM_93C46) { |
94a79942 LF |
654 | powerlevel = priv->TxPowerLevelCCK[channel-1]; |
655 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | |
547d0c34 LF |
656 | } else if (priv->epromtype == EEPROM_93C56) { |
657 | if (priv->rf_type == RF_1T2R) { | |
94a79942 LF |
658 | powerlevel = priv->TxPowerLevelCCK_C[channel-1]; |
659 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; | |
547d0c34 | 660 | } else if (priv->rf_type == RF_2T4R) { |
94a79942 LF |
661 | powerlevel = priv->TxPowerLevelCCK_A[channel-1]; |
662 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; | |
663 | ||
664 | ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] | |
547d0c34 | 665 | - priv->TxPowerLevelOFDM24G_A[channel-1]; |
94a79942 LF |
666 | |
667 | priv->RF_C_TxPwDiff = ant_pwr_diff; | |
668 | ||
669 | ant_pwr_diff &= 0xf; | |
670 | ||
671 | priv->AntennaTxPwDiff[2] = 0; | |
672 | priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); | |
673 | priv->AntennaTxPwDiff[0] = 0; | |
674 | ||
547d0c34 LF |
675 | u4RegValue = (priv->AntennaTxPwDiff[2]<<8 | |
676 | priv->AntennaTxPwDiff[1]<<4 | | |
677 | priv->AntennaTxPwDiff[0]); | |
94a79942 LF |
678 | |
679 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, | |
680 | (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); | |
681 | } | |
682 | } | |
cb762154 | 683 | switch (priv->rf_chip) { |
94a79942 LF |
684 | case RF_8225: |
685 | break; | |
686 | case RF_8256: | |
687 | PHY_SetRF8256CCKTxPower(dev, powerlevel); | |
688 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); | |
689 | break; | |
690 | case RF_8258: | |
691 | break; | |
692 | default: | |
547d0c34 LF |
693 | RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", |
694 | __func__); | |
94a79942 LF |
695 | break; |
696 | } | |
697 | return; | |
698 | } | |
699 | ||
547d0c34 | 700 | bool rtl8192_phy_RFConfig(struct net_device *dev) |
94a79942 LF |
701 | { |
702 | struct r8192_priv *priv = rtllib_priv(dev); | |
703 | bool rtStatus = true; | |
547d0c34 LF |
704 | switch (priv->rf_chip) { |
705 | case RF_8225: | |
706 | break; | |
707 | case RF_8256: | |
708 | rtStatus = PHY_RF8256_Config(dev); | |
709 | break; | |
94a79942 | 710 | |
547d0c34 LF |
711 | case RF_8258: |
712 | break; | |
713 | case RF_PSEUDO_11N: | |
94a79942 LF |
714 | break; |
715 | ||
547d0c34 LF |
716 | default: |
717 | RT_TRACE(COMP_ERR, "error chip id\n"); | |
718 | break; | |
94a79942 LF |
719 | } |
720 | return rtStatus; | |
721 | } | |
722 | ||
547d0c34 | 723 | void rtl8192_phy_updateInitGain(struct net_device *dev) |
94a79942 LF |
724 | { |
725 | return; | |
726 | } | |
727 | ||
547d0c34 LF |
728 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, |
729 | enum rf90_radio_path eRFPath) | |
94a79942 LF |
730 | { |
731 | ||
732 | int i; | |
733 | u8 ret = 0; | |
734 | ||
547d0c34 LF |
735 | switch (eRFPath) { |
736 | case RF90_PATH_A: | |
737 | for (i = 0; i < RadioA_ArrayLength; i += 2) { | |
738 | if (Rtl819XRadioA_Array[i] == 0xfe) { | |
739 | msleep(100); | |
740 | continue; | |
94a79942 | 741 | } |
547d0c34 LF |
742 | rtl8192_phy_SetRFReg(dev, eRFPath, |
743 | Rtl819XRadioA_Array[i], | |
744 | bMask12Bits, | |
745 | Rtl819XRadioA_Array[i+1]); | |
94a79942 | 746 | |
547d0c34 LF |
747 | } |
748 | break; | |
749 | case RF90_PATH_B: | |
750 | for (i = 0; i < RadioB_ArrayLength; i += 2) { | |
751 | if (Rtl819XRadioB_Array[i] == 0xfe) { | |
752 | msleep(100); | |
753 | continue; | |
94a79942 | 754 | } |
547d0c34 LF |
755 | rtl8192_phy_SetRFReg(dev, eRFPath, |
756 | Rtl819XRadioB_Array[i], | |
757 | bMask12Bits, | |
758 | Rtl819XRadioB_Array[i+1]); | |
94a79942 | 759 | |
547d0c34 LF |
760 | } |
761 | break; | |
762 | case RF90_PATH_C: | |
763 | for (i = 0; i < RadioC_ArrayLength; i += 2) { | |
764 | if (Rtl819XRadioC_Array[i] == 0xfe) { | |
765 | msleep(100); | |
766 | continue; | |
94a79942 | 767 | } |
547d0c34 LF |
768 | rtl8192_phy_SetRFReg(dev, eRFPath, |
769 | Rtl819XRadioC_Array[i], | |
770 | bMask12Bits, | |
771 | Rtl819XRadioC_Array[i+1]); | |
94a79942 | 772 | |
547d0c34 LF |
773 | } |
774 | break; | |
775 | case RF90_PATH_D: | |
776 | for (i = 0; i < RadioD_ArrayLength; i += 2) { | |
777 | if (Rtl819XRadioD_Array[i] == 0xfe) { | |
778 | msleep(100); | |
779 | continue; | |
94a79942 | 780 | } |
547d0c34 LF |
781 | rtl8192_phy_SetRFReg(dev, eRFPath, |
782 | Rtl819XRadioD_Array[i], bMask12Bits, | |
783 | Rtl819XRadioD_Array[i+1]); | |
784 | ||
785 | } | |
786 | break; | |
787 | default: | |
788 | break; | |
94a79942 LF |
789 | } |
790 | ||
547d0c34 | 791 | return ret; |
94a79942 LF |
792 | |
793 | } | |
49aab5fd | 794 | static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) |
94a79942 LF |
795 | { |
796 | struct r8192_priv *priv = rtllib_priv(dev); | |
797 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; | |
798 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | |
799 | ||
547d0c34 | 800 | switch (priv->rf_chip) { |
94a79942 | 801 | case RF_8225: |
94a79942 LF |
802 | break; |
803 | ||
804 | case RF_8256: | |
805 | PHY_SetRF8256CCKTxPower(dev, powerlevel); | |
806 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); | |
807 | break; | |
808 | ||
809 | case RF_8258: | |
810 | break; | |
811 | default: | |
547d0c34 LF |
812 | RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower" |
813 | "Level()\n"); | |
94a79942 LF |
814 | break; |
815 | } | |
816 | return; | |
817 | } | |
547d0c34 | 818 | |
49aab5fd LF |
819 | static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, |
820 | u32 CmdTableIdx, u32 CmdTableSz, | |
821 | enum sw_chnl_cmd_id CmdID, | |
822 | u32 Para1, u32 Para2, u32 msDelay) | |
94a79942 | 823 | { |
547d0c34 | 824 | struct sw_chnl_cmd *pCmd; |
94a79942 | 825 | |
547d0c34 LF |
826 | if (CmdTable == NULL) { |
827 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot " | |
828 | "be NULL.\n"); | |
94a79942 LF |
829 | return false; |
830 | } | |
547d0c34 LF |
831 | if (CmdTableIdx >= CmdTableSz) { |
832 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid" | |
833 | " index, please check size of the table, CmdTableIdx:" | |
834 | "%d, CmdTableSz:%d\n", | |
94a79942 LF |
835 | CmdTableIdx, CmdTableSz); |
836 | return false; | |
837 | } | |
838 | ||
839 | pCmd = CmdTable + CmdTableIdx; | |
840 | pCmd->CmdID = CmdID; | |
841 | pCmd->Para1 = Para1; | |
842 | pCmd->Para2 = Para2; | |
843 | pCmd->msDelay = msDelay; | |
844 | ||
845 | return true; | |
846 | } | |
547d0c34 | 847 | |
49aab5fd LF |
848 | static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, |
849 | u8 *stage, u8 *step, u32 *delay) | |
94a79942 LF |
850 | { |
851 | struct r8192_priv *priv = rtllib_priv(dev); | |
51ce231f | 852 | struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT]; |
94a79942 | 853 | u32 PreCommonCmdCnt; |
51ce231f | 854 | struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT]; |
94a79942 | 855 | u32 PostCommonCmdCnt; |
51ce231f | 856 | struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; |
94a79942 | 857 | u32 RfDependCmdCnt; |
51ce231f | 858 | struct sw_chnl_cmd *CurrentCmd = NULL; |
94a79942 LF |
859 | u8 eRFPath; |
860 | ||
547d0c34 LF |
861 | RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", |
862 | __func__, *stage, *step, channel); | |
94a79942 | 863 | |
547d0c34 LF |
864 | if (!IsLegalChannel(priv->rtllib, channel)) { |
865 | RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", | |
866 | channel); | |
94a79942 LF |
867 | return true; |
868 | } | |
94a79942 LF |
869 | |
870 | { | |
871 | PreCommonCmdCnt = 0; | |
547d0c34 LF |
872 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, |
873 | MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, | |
874 | 0, 0, 0); | |
875 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, | |
876 | MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); | |
94a79942 LF |
877 | |
878 | PostCommonCmdCnt = 0; | |
879 | ||
547d0c34 LF |
880 | rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, |
881 | MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); | |
94a79942 LF |
882 | |
883 | RfDependCmdCnt = 0; | |
547d0c34 | 884 | switch (priv->rf_chip) { |
94a79942 | 885 | case RF_8225: |
547d0c34 LF |
886 | if (!(channel >= 1 && channel <= 14)) { |
887 | RT_TRACE(COMP_ERR, "illegal channel for Zebra " | |
888 | "8225: %d\n", channel); | |
94a79942 LF |
889 | return false; |
890 | } | |
547d0c34 LF |
891 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, |
892 | RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, | |
893 | CmdID_RF_WriteReg, rZebra1_Channel, | |
894 | RF_CHANNEL_TABLE_ZEBRA[channel], 10); | |
895 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, | |
896 | RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, | |
94a79942 LF |
897 | CmdID_End, 0, 0, 0); |
898 | break; | |
899 | ||
900 | case RF_8256: | |
547d0c34 LF |
901 | if (!(channel >= 1 && channel <= 14)) { |
902 | RT_TRACE(COMP_ERR, "illegal channel for Zebra" | |
903 | " 8256: %d\n", channel); | |
94a79942 LF |
904 | return false; |
905 | } | |
547d0c34 LF |
906 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, |
907 | RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, | |
908 | CmdID_RF_WriteReg, rZebra1_Channel, channel, | |
909 | 10); | |
910 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, | |
911 | RfDependCmdCnt++, | |
912 | MAX_RFDEPENDCMD_CNT, | |
94a79942 LF |
913 | CmdID_End, 0, 0, 0); |
914 | break; | |
915 | ||
916 | case RF_8258: | |
917 | break; | |
918 | ||
919 | default: | |
547d0c34 LF |
920 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", |
921 | priv->rf_chip); | |
94a79942 LF |
922 | return false; |
923 | break; | |
924 | } | |
925 | ||
926 | ||
547d0c34 LF |
927 | do { |
928 | switch (*stage) { | |
94a79942 | 929 | case 0: |
547d0c34 | 930 | CurrentCmd = &PreCommonCmd[*step]; |
94a79942 LF |
931 | break; |
932 | case 1: | |
547d0c34 | 933 | CurrentCmd = &RfDependCmd[*step]; |
94a79942 LF |
934 | break; |
935 | case 2: | |
547d0c34 | 936 | CurrentCmd = &PostCommonCmd[*step]; |
94a79942 LF |
937 | break; |
938 | } | |
939 | ||
52a7fb09 | 940 | if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) { |
547d0c34 | 941 | if ((*stage) == 2) { |
94a79942 | 942 | return true; |
547d0c34 | 943 | } else { |
94a79942 | 944 | (*stage)++; |
547d0c34 | 945 | (*step) = 0; |
94a79942 LF |
946 | continue; |
947 | } | |
948 | } | |
949 | ||
52a7fb09 LF |
950 | if (!CurrentCmd) |
951 | continue; | |
547d0c34 | 952 | switch (CurrentCmd->CmdID) { |
94a79942 LF |
953 | case CmdID_SetTxPowerLevel: |
954 | if (priv->IC_Cut > (u8)VERSION_8190_BD) | |
547d0c34 | 955 | rtl8192_SetTxPowerLevel(dev, channel); |
94a79942 LF |
956 | break; |
957 | case CmdID_WritePortUlong: | |
547d0c34 LF |
958 | write_nic_dword(dev, CurrentCmd->Para1, |
959 | CurrentCmd->Para2); | |
94a79942 LF |
960 | break; |
961 | case CmdID_WritePortUshort: | |
547d0c34 LF |
962 | write_nic_word(dev, CurrentCmd->Para1, |
963 | (u16)CurrentCmd->Para2); | |
94a79942 LF |
964 | break; |
965 | case CmdID_WritePortUchar: | |
547d0c34 LF |
966 | write_nic_byte(dev, CurrentCmd->Para1, |
967 | (u8)CurrentCmd->Para2); | |
94a79942 LF |
968 | break; |
969 | case CmdID_RF_WriteReg: | |
547d0c34 LF |
970 | for (eRFPath = 0; eRFPath < |
971 | priv->NumTotalRFPath; eRFPath++) | |
972 | rtl8192_phy_SetRFReg(dev, | |
973 | (enum rf90_radio_path)eRFPath, | |
974 | CurrentCmd->Para1, bMask12Bits, | |
975 | CurrentCmd->Para2<<7); | |
94a79942 LF |
976 | break; |
977 | default: | |
978 | break; | |
979 | } | |
980 | ||
981 | break; | |
547d0c34 LF |
982 | } while (true); |
983 | } /*for (Number of RF paths)*/ | |
94a79942 | 984 | |
547d0c34 | 985 | (*delay) = CurrentCmd->msDelay; |
94a79942 LF |
986 | (*step)++; |
987 | return false; | |
988 | } | |
989 | ||
49aab5fd | 990 | static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) |
94a79942 LF |
991 | { |
992 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 | 993 | u32 delay = 0; |
94a79942 | 994 | |
547d0c34 LF |
995 | while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, |
996 | &priv->SwChnlStep, &delay)) { | |
997 | if (delay > 0) | |
94a79942 LF |
998 | msleep(delay); |
999 | if (IS_NIC_DOWN(priv)) | |
547d0c34 | 1000 | break; |
94a79942 LF |
1001 | } |
1002 | } | |
1003 | void rtl8192_SwChnl_WorkItem(struct net_device *dev) | |
1004 | { | |
1005 | ||
1006 | struct r8192_priv *priv = rtllib_priv(dev); | |
1007 | ||
1008 | RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); | |
1009 | ||
547d0c34 LF |
1010 | RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, |
1011 | priv->chan, priv); | |
94a79942 LF |
1012 | |
1013 | rtl8192_phy_FinishSwChnlNow(dev , priv->chan); | |
1014 | ||
1015 | RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); | |
1016 | } | |
1017 | ||
547d0c34 | 1018 | u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) |
94a79942 LF |
1019 | { |
1020 | struct r8192_priv *priv = rtllib_priv(dev); | |
1021 | RT_TRACE(COMP_PHY, "=====>%s()\n", __func__); | |
547d0c34 LF |
1022 | if (IS_NIC_DOWN(priv)) { |
1023 | RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__); | |
94a79942 LF |
1024 | return false; |
1025 | } | |
1026 | if (priv->SwChnlInProgress) | |
1027 | return false; | |
1028 | ||
1029 | ||
547d0c34 | 1030 | switch (priv->rtllib->mode) { |
94a79942 LF |
1031 | case WIRELESS_MODE_A: |
1032 | case WIRELESS_MODE_N_5G: | |
547d0c34 | 1033 | if (channel <= 14) { |
94a79942 LF |
1034 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); |
1035 | return false; | |
1036 | } | |
1037 | break; | |
1038 | case WIRELESS_MODE_B: | |
547d0c34 | 1039 | if (channel > 14) { |
94a79942 LF |
1040 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); |
1041 | return false; | |
1042 | } | |
1043 | break; | |
1044 | case WIRELESS_MODE_G: | |
1045 | case WIRELESS_MODE_N_24G: | |
547d0c34 | 1046 | if (channel > 14) { |
94a79942 LF |
1047 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); |
1048 | return false; | |
1049 | } | |
1050 | break; | |
1051 | } | |
1052 | ||
1053 | priv->SwChnlInProgress = true; | |
1054 | if (channel == 0) | |
1055 | channel = 1; | |
1056 | ||
547d0c34 | 1057 | priv->chan = channel; |
94a79942 | 1058 | |
547d0c34 LF |
1059 | priv->SwChnlStage = 0; |
1060 | priv->SwChnlStep = 0; | |
94a79942 | 1061 | |
547d0c34 | 1062 | if (!IS_NIC_DOWN(priv)) |
94a79942 | 1063 | rtl8192_SwChnl_WorkItem(dev); |
94a79942 LF |
1064 | priv->SwChnlInProgress = false; |
1065 | return true; | |
1066 | } | |
1067 | ||
547d0c34 | 1068 | static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev) |
94a79942 LF |
1069 | { |
1070 | struct r8192_priv *priv = rtllib_priv(dev); | |
1071 | ||
547d0c34 LF |
1072 | switch (priv->CurrentChannelBW) { |
1073 | case HT_CHANNEL_WIDTH_20: | |
1074 | priv->CCKPresentAttentuation = | |
1075 | priv->CCKPresentAttentuation_20Mdefault + | |
1076 | priv->CCKPresentAttentuation_difference; | |
94a79942 | 1077 | |
547d0c34 LF |
1078 | if (priv->CCKPresentAttentuation > |
1079 | (CCKTxBBGainTableLength-1)) | |
1080 | priv->CCKPresentAttentuation = | |
1081 | CCKTxBBGainTableLength-1; | |
1082 | if (priv->CCKPresentAttentuation < 0) | |
1083 | priv->CCKPresentAttentuation = 0; | |
1084 | ||
1085 | RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent" | |
1086 | "Attentuation = %d\n", | |
1087 | priv->CCKPresentAttentuation); | |
1088 | ||
1089 | if (priv->rtllib->current_network.channel == 14 && | |
1090 | !priv->bcck_in_ch14) { | |
1091 | priv->bcck_in_ch14 = true; | |
1092 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1093 | } else if (priv->rtllib->current_network.channel != | |
1094 | 14 && priv->bcck_in_ch14) { | |
1095 | priv->bcck_in_ch14 = false; | |
1096 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1097 | } else { | |
1098 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1099 | } | |
94a79942 LF |
1100 | break; |
1101 | ||
547d0c34 LF |
1102 | case HT_CHANNEL_WIDTH_20_40: |
1103 | priv->CCKPresentAttentuation = | |
1104 | priv->CCKPresentAttentuation_40Mdefault + | |
1105 | priv->CCKPresentAttentuation_difference; | |
1106 | ||
1107 | RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent" | |
1108 | "Attentuation = %d\n", | |
1109 | priv->CCKPresentAttentuation); | |
1110 | if (priv->CCKPresentAttentuation > | |
1111 | (CCKTxBBGainTableLength - 1)) | |
94a79942 | 1112 | priv->CCKPresentAttentuation = |
547d0c34 LF |
1113 | CCKTxBBGainTableLength-1; |
1114 | if (priv->CCKPresentAttentuation < 0) | |
1115 | priv->CCKPresentAttentuation = 0; | |
1116 | ||
1117 | if (priv->rtllib->current_network.channel == 14 && | |
1118 | !priv->bcck_in_ch14) { | |
1119 | priv->bcck_in_ch14 = true; | |
1120 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1121 | } else if (priv->rtllib->current_network.channel != 14 | |
1122 | && priv->bcck_in_ch14) { | |
1123 | priv->bcck_in_ch14 = false; | |
1124 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1125 | } else { | |
1126 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1127 | } | |
94a79942 LF |
1128 | break; |
1129 | } | |
1130 | } | |
1131 | ||
94a79942 LF |
1132 | static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) |
1133 | { | |
1134 | struct r8192_priv *priv = rtllib_priv(dev); | |
1135 | ||
547d0c34 LF |
1136 | if (priv->rtllib->current_network.channel == 14 && |
1137 | !priv->bcck_in_ch14) | |
94a79942 | 1138 | priv->bcck_in_ch14 = true; |
547d0c34 LF |
1139 | else if (priv->rtllib->current_network.channel != 14 && |
1140 | priv->bcck_in_ch14) | |
94a79942 LF |
1141 | priv->bcck_in_ch14 = false; |
1142 | ||
547d0c34 LF |
1143 | switch (priv->CurrentChannelBW) { |
1144 | case HT_CHANNEL_WIDTH_20: | |
1145 | if (priv->Record_CCK_20Mindex == 0) | |
1146 | priv->Record_CCK_20Mindex = 6; | |
1147 | priv->CCK_index = priv->Record_CCK_20Mindex; | |
1148 | RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_" | |
1149 | "Switch_ThermalMeter(),CCK_index = %d\n", | |
1150 | priv->CCK_index); | |
1151 | break; | |
1152 | ||
1153 | case HT_CHANNEL_WIDTH_20_40: | |
1154 | priv->CCK_index = priv->Record_CCK_40Mindex; | |
1155 | RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_" | |
1156 | "Switch_ThermalMeter(), CCK_index = %d\n", | |
1157 | priv->CCK_index); | |
1158 | break; | |
94a79942 LF |
1159 | } |
1160 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1161 | } | |
94a79942 LF |
1162 | |
1163 | static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) | |
1164 | { | |
94a79942 | 1165 | struct r8192_priv *priv = rtllib_priv(dev); |
94a79942 | 1166 | |
94a79942 LF |
1167 | if (priv->IC_Cut >= IC_VersionCut_D) |
1168 | CCK_Tx_Power_Track_BW_Switch_TSSI(dev); | |
1169 | else | |
1170 | CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); | |
94a79942 LF |
1171 | } |
1172 | ||
1173 | void rtl8192_SetBWModeWorkItem(struct net_device *dev) | |
1174 | { | |
1175 | ||
1176 | struct r8192_priv *priv = rtllib_priv(dev); | |
1177 | u8 regBwOpMode; | |
1178 | ||
547d0c34 LF |
1179 | RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s " |
1180 | "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? | |
1181 | "20MHz" : "40MHz") | |
94a79942 LF |
1182 | |
1183 | ||
547d0c34 LF |
1184 | if (priv->rf_chip == RF_PSEUDO_11N) { |
1185 | priv->SetBWModeInProgress = false; | |
94a79942 LF |
1186 | return; |
1187 | } | |
547d0c34 LF |
1188 | if (IS_NIC_DOWN(priv)) { |
1189 | RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__); | |
94a79942 LF |
1190 | return; |
1191 | } | |
1192 | regBwOpMode = read_nic_byte(dev, BW_OPMODE); | |
1193 | ||
547d0c34 LF |
1194 | switch (priv->CurrentChannelBW) { |
1195 | case HT_CHANNEL_WIDTH_20: | |
1196 | regBwOpMode |= BW_OPMODE_20MHZ; | |
1197 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); | |
1198 | break; | |
94a79942 | 1199 | |
547d0c34 LF |
1200 | case HT_CHANNEL_WIDTH_20_40: |
1201 | regBwOpMode &= ~BW_OPMODE_20MHZ; | |
1202 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); | |
1203 | break; | |
94a79942 | 1204 | |
547d0c34 LF |
1205 | default: |
1206 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown " | |
1207 | "Bandwidth: %#X\n", priv->CurrentChannelBW); | |
1208 | break; | |
94a79942 LF |
1209 | } |
1210 | ||
547d0c34 LF |
1211 | switch (priv->CurrentChannelBW) { |
1212 | case HT_CHANNEL_WIDTH_20: | |
1213 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); | |
1214 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); | |
1215 | ||
1216 | if (!priv->btxpower_tracking) { | |
1217 | write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); | |
1218 | write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); | |
1219 | write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); | |
1220 | } else { | |
1221 | CCK_Tx_Power_Track_BW_Switch(dev); | |
1222 | } | |
94a79942 | 1223 | |
547d0c34 | 1224 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); |
94a79942 | 1225 | |
547d0c34 LF |
1226 | break; |
1227 | case HT_CHANNEL_WIDTH_20_40: | |
1228 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); | |
1229 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); | |
1230 | ||
1231 | if (!priv->btxpower_tracking) { | |
1232 | write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); | |
1233 | write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); | |
1234 | write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); | |
1235 | } else { | |
1236 | CCK_Tx_Power_Track_BW_Switch(dev); | |
1237 | } | |
94a79942 | 1238 | |
547d0c34 LF |
1239 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, |
1240 | (priv->nCur40MhzPrimeSC>>1)); | |
1241 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, | |
1242 | priv->nCur40MhzPrimeSC); | |
94a79942 | 1243 | |
547d0c34 LF |
1244 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); |
1245 | break; | |
1246 | default: | |
1247 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown " | |
1248 | "Bandwidth: %#X\n", priv->CurrentChannelBW); | |
1249 | break; | |
94a79942 LF |
1250 | |
1251 | } | |
1252 | ||
547d0c34 LF |
1253 | switch (priv->rf_chip) { |
1254 | case RF_8225: | |
1255 | break; | |
94a79942 | 1256 | |
547d0c34 LF |
1257 | case RF_8256: |
1258 | PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); | |
1259 | break; | |
94a79942 | 1260 | |
547d0c34 LF |
1261 | case RF_8258: |
1262 | break; | |
94a79942 | 1263 | |
547d0c34 LF |
1264 | case RF_PSEUDO_11N: |
1265 | break; | |
94a79942 | 1266 | |
547d0c34 LF |
1267 | default: |
1268 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); | |
1269 | break; | |
94a79942 | 1270 | } |
4f6807e8 | 1271 | |
94a79942 | 1272 | atomic_dec(&(priv->rtllib->atm_swbw)); |
547d0c34 | 1273 | priv->SetBWModeInProgress = false; |
94a79942 LF |
1274 | |
1275 | RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); | |
1276 | } | |
1277 | ||
547d0c34 LF |
1278 | void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, |
1279 | enum ht_extchnl_offset Offset) | |
94a79942 LF |
1280 | { |
1281 | struct r8192_priv *priv = rtllib_priv(dev); | |
1282 | ||
1283 | ||
1284 | if (priv->SetBWModeInProgress) | |
1285 | return; | |
1286 | ||
547d0c34 LF |
1287 | atomic_inc(&(priv->rtllib->atm_swbw)); |
1288 | priv->SetBWModeInProgress = true; | |
94a79942 LF |
1289 | |
1290 | priv->CurrentChannelBW = Bandwidth; | |
1291 | ||
547d0c34 | 1292 | if (Offset == HT_EXTCHNL_OFFSET_LOWER) |
94a79942 | 1293 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; |
547d0c34 | 1294 | else if (Offset == HT_EXTCHNL_OFFSET_UPPER) |
94a79942 LF |
1295 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; |
1296 | else | |
1297 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; | |
1298 | ||
1299 | rtl8192_SetBWModeWorkItem(dev); | |
1300 | ||
1301 | } | |
1302 | ||
94a79942 LF |
1303 | void InitialGain819xPci(struct net_device *dev, u8 Operation) |
1304 | { | |
1305 | #define SCAN_RX_INITIAL_GAIN 0x17 | |
1306 | #define POWER_DETECTION_TH 0x08 | |
1307 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 LF |
1308 | u32 BitMask; |
1309 | u8 initial_gain; | |
1310 | ||
1311 | if (!IS_NIC_DOWN(priv)) { | |
1312 | switch (Operation) { | |
1313 | case IG_Backup: | |
1314 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial" | |
1315 | " gain.\n"); | |
1316 | initial_gain = SCAN_RX_INITIAL_GAIN; | |
1317 | BitMask = bMaskByte0; | |
1318 | if (dm_digtable.dig_algorithm == | |
1319 | DIG_ALGO_BY_FALSE_ALARM) | |
1320 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); | |
1321 | priv->initgain_backup.xaagccore1 = | |
1322 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, | |
1323 | BitMask); | |
1324 | priv->initgain_backup.xbagccore1 = | |
1325 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, | |
1326 | BitMask); | |
1327 | priv->initgain_backup.xcagccore1 = | |
1328 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, | |
1329 | BitMask); | |
1330 | priv->initgain_backup.xdagccore1 = | |
1331 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, | |
1332 | BitMask); | |
1333 | BitMask = bMaskByte2; | |
1334 | priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, | |
1335 | rCCK0_CCA, BitMask); | |
1336 | ||
1337 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is" | |
1338 | " %x\n", priv->initgain_backup.xaagccore1); | |
1339 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is" | |
1340 | " %x\n", priv->initgain_backup.xbagccore1); | |
1341 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is" | |
1342 | " %x\n", priv->initgain_backup.xcagccore1); | |
1343 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is" | |
1344 | " %x\n", priv->initgain_backup.xdagccore1); | |
1345 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is" | |
1346 | " %x\n", priv->initgain_backup.cca); | |
1347 | ||
1348 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", | |
1349 | initial_gain); | |
1350 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); | |
1351 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); | |
1352 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); | |
1353 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); | |
1354 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", | |
1355 | POWER_DETECTION_TH); | |
1356 | write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); | |
1357 | break; | |
1358 | case IG_Restore: | |
1359 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial " | |
1360 | "gain.\n"); | |
1361 | BitMask = 0x7f; | |
1362 | if (dm_digtable.dig_algorithm == | |
1363 | DIG_ALGO_BY_FALSE_ALARM) | |
1364 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); | |
1365 | ||
1366 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, | |
1367 | (u32)priv->initgain_backup.xaagccore1); | |
1368 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, | |
1369 | (u32)priv->initgain_backup.xbagccore1); | |
1370 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, | |
1371 | (u32)priv->initgain_backup.xcagccore1); | |
1372 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, | |
1373 | (u32)priv->initgain_backup.xdagccore1); | |
1374 | BitMask = bMaskByte2; | |
1375 | rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, | |
1376 | (u32)priv->initgain_backup.cca); | |
1377 | ||
1378 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50" | |
1379 | " is %x\n", priv->initgain_backup.xaagccore1); | |
1380 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58" | |
1381 | " is %x\n", priv->initgain_backup.xbagccore1); | |
1382 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60" | |
1383 | " is %x\n", priv->initgain_backup.xcagccore1); | |
1384 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68" | |
1385 | " is %x\n", priv->initgain_backup.xdagccore1); | |
1386 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a" | |
1387 | " is %x\n", priv->initgain_backup.cca); | |
1388 | ||
1389 | rtl8192_phy_setTxPower(dev, | |
1390 | priv->rtllib->current_network.channel); | |
1391 | ||
1392 | if (dm_digtable.dig_algorithm == | |
1393 | DIG_ALGO_BY_FALSE_ALARM) | |
1394 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); | |
1395 | break; | |
1396 | default: | |
1397 | RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); | |
1398 | break; | |
94a79942 LF |
1399 | } |
1400 | } | |
1401 | } | |
1402 | ||
547d0c34 | 1403 | void PHY_SetRtl8192eRfOff(struct net_device *dev) |
94a79942 LF |
1404 | { |
1405 | ||
1406 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); | |
1407 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); | |
1408 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); | |
1409 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); | |
1410 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); | |
1411 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); | |
1412 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); | |
1413 | write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07); | |
1414 | ||
1415 | } | |
94a79942 | 1416 | |
49aab5fd LF |
1417 | static bool SetRFPowerState8190(struct net_device *dev, |
1418 | enum rt_rf_power_state eRFPowerState) | |
94a79942 LF |
1419 | { |
1420 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 LF |
1421 | struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) |
1422 | (&(priv->rtllib->PowerSaveControl)); | |
94a79942 LF |
1423 | bool bResult = true; |
1424 | u8 i = 0, QueueID = 0; | |
1425 | struct rtl8192_tx_ring *ring = NULL; | |
1426 | ||
1427 | if (priv->SetRFPowerStateInProgress == true) | |
1428 | return false; | |
1429 | RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); | |
1430 | priv->SetRFPowerStateInProgress = true; | |
1431 | ||
547d0c34 LF |
1432 | switch (priv->rf_chip) { |
1433 | case RF_8256: | |
1434 | switch (eRFPowerState) { | |
1435 | case eRfOn: | |
1436 | RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n"); | |
1437 | if ((priv->rtllib->eRFPowerState == eRfOff) && | |
1438 | RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { | |
1439 | bool rtstatus = true; | |
1440 | u32 InitilizeCount = 3; | |
1441 | do { | |
1442 | InitilizeCount--; | |
1443 | priv->RegRfOff = false; | |
1444 | rtstatus = NicIFEnableNIC(dev); | |
1445 | } while ((rtstatus != true) && | |
1446 | (InitilizeCount > 0)); | |
1447 | ||
1448 | if (rtstatus != true) { | |
1449 | RT_TRACE(COMP_ERR, "%s():Initialize Ada" | |
1450 | "pter fail,return\n", | |
1451 | __func__); | |
1452 | priv->SetRFPowerStateInProgress = false; | |
1453 | return false; | |
1454 | } | |
1455 | ||
1456 | RT_CLEAR_PS_LEVEL(pPSC, | |
1457 | RT_RF_OFF_LEVL_HALT_NIC); | |
1458 | } else { | |
94a79942 LF |
1459 | write_nic_byte(dev, ANAPAR, 0x37); |
1460 | mdelay(1); | |
547d0c34 LF |
1461 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, |
1462 | 0x4, 0x1); | |
94a79942 LF |
1463 | priv->bHwRfOffAction = 0; |
1464 | ||
547d0c34 LF |
1465 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, |
1466 | BIT4, 0x1); | |
1467 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, | |
1468 | 0x300, 0x3); | |
1469 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, | |
1470 | 0x18, 0x3); | |
1471 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, | |
1472 | 0x3); | |
1473 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, | |
1474 | 0x3); | |
1475 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, | |
1476 | 0x60, 0x3); | |
94a79942 | 1477 | |
547d0c34 | 1478 | } |
94a79942 | 1479 | |
547d0c34 LF |
1480 | break; |
1481 | ||
1482 | case eRfSleep: | |
1483 | if (priv->rtllib->eRFPowerState == eRfOff) | |
1484 | break; | |
94a79942 | 1485 | |
94a79942 | 1486 | |
547d0c34 LF |
1487 | for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { |
1488 | ring = &priv->tx_ring[QueueID]; | |
94a79942 | 1489 | |
547d0c34 LF |
1490 | if (skb_queue_len(&ring->queue) == 0) { |
1491 | QueueID++; | |
1492 | continue; | |
1493 | } else { | |
1494 | RT_TRACE((COMP_POWER|COMP_RF), "eRf Off" | |
1495 | "/Sleep: %d times TcbBusyQueue" | |
1496 | "[%d] !=0 before doze!\n", | |
1497 | (i+1), QueueID); | |
1498 | udelay(10); | |
1499 | i++; | |
94a79942 LF |
1500 | } |
1501 | ||
547d0c34 LF |
1502 | if (i >= MAX_DOZE_WAITING_TIMES_9x) { |
1503 | RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! " | |
1504 | "SetRFPowerState8190(): eRfOff" | |
1505 | ": %d times TcbBusyQueue[%d] " | |
1506 | "!= 0 !!!\n", | |
1507 | MAX_DOZE_WAITING_TIMES_9x, | |
1508 | QueueID); | |
1509 | break; | |
94a79942 | 1510 | } |
94a79942 | 1511 | } |
547d0c34 LF |
1512 | PHY_SetRtl8192eRfOff(dev); |
1513 | break; | |
1514 | ||
1515 | case eRfOff: | |
1516 | RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/" | |
1517 | "Sleep !\n"); | |
1518 | ||
1519 | for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { | |
1520 | ring = &priv->tx_ring[QueueID]; | |
1521 | ||
1522 | if (skb_queue_len(&ring->queue) == 0) { | |
1523 | QueueID++; | |
1524 | continue; | |
1525 | } else { | |
1526 | RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d" | |
1527 | " times TcbBusyQueue[%d] !=0 b" | |
1528 | "efore doze!\n", (i+1), | |
1529 | QueueID); | |
1530 | udelay(10); | |
1531 | i++; | |
94a79942 | 1532 | } |
94a79942 | 1533 | |
547d0c34 LF |
1534 | if (i >= MAX_DOZE_WAITING_TIMES_9x) { |
1535 | RT_TRACE(COMP_POWER, "\n\n\n SetZebra: " | |
1536 | "RFPowerState8185B(): eRfOff:" | |
1537 | " %d times TcbBusyQueue[%d] " | |
1538 | "!= 0 !!!\n", | |
1539 | MAX_DOZE_WAITING_TIMES_9x, | |
1540 | QueueID); | |
94a79942 | 1541 | break; |
547d0c34 LF |
1542 | } |
1543 | } | |
94a79942 | 1544 | |
547d0c34 LF |
1545 | if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && |
1546 | !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { | |
1547 | NicIFDisableNIC(dev); | |
1548 | RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); | |
1549 | } else if (!(pPSC->RegRfPsLevel & | |
1550 | RT_RF_OFF_LEVL_HALT_NIC)) { | |
1551 | PHY_SetRtl8192eRfOff(dev); | |
1552 | } | |
94a79942 | 1553 | |
547d0c34 | 1554 | break; |
94a79942 LF |
1555 | |
1556 | default: | |
547d0c34 LF |
1557 | bResult = false; |
1558 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state" | |
1559 | " to set: 0x%X!!!\n", eRFPowerState); | |
94a79942 | 1560 | break; |
547d0c34 LF |
1561 | } |
1562 | ||
1563 | break; | |
1564 | ||
1565 | default: | |
1566 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); | |
1567 | break; | |
94a79942 LF |
1568 | } |
1569 | ||
1570 | if (bResult) { | |
1571 | priv->rtllib->eRFPowerState = eRFPowerState; | |
1572 | ||
d064307a LF |
1573 | switch (priv->rf_chip) { |
1574 | case RF_8256: | |
94a79942 LF |
1575 | break; |
1576 | ||
d064307a | 1577 | default: |
547d0c34 LF |
1578 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown " |
1579 | "RF type\n"); | |
d064307a | 1580 | break; |
94a79942 LF |
1581 | } |
1582 | } | |
1583 | ||
1584 | priv->SetRFPowerStateInProgress = false; | |
547d0c34 LF |
1585 | RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", |
1586 | bResult); | |
94a79942 LF |
1587 | return bResult; |
1588 | } | |
1589 | ||
547d0c34 LF |
1590 | bool SetRFPowerState(struct net_device *dev, |
1591 | enum rt_rf_power_state eRFPowerState) | |
94a79942 LF |
1592 | { |
1593 | struct r8192_priv *priv = rtllib_priv(dev); | |
1594 | ||
1595 | bool bResult = false; | |
1596 | ||
547d0c34 LF |
1597 | RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n", |
1598 | eRFPowerState); | |
1599 | if (eRFPowerState == priv->rtllib->eRFPowerState && | |
1600 | priv->bHwRfOffAction == 0) { | |
1601 | RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the " | |
1602 | "request for eRFPowerState(%d) is the same.\n", | |
1603 | eRFPowerState); | |
94a79942 LF |
1604 | return bResult; |
1605 | } | |
1606 | ||
1607 | bResult = SetRFPowerState8190(dev, eRFPowerState); | |
1608 | ||
547d0c34 LF |
1609 | RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", |
1610 | bResult); | |
94a79942 LF |
1611 | |
1612 | return bResult; | |
1613 | } | |
94a79942 | 1614 | |
49aab5fd | 1615 | void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation) |
94a79942 LF |
1616 | { |
1617 | struct r8192_priv *priv = rtllib_priv(dev); | |
1618 | ||
1619 | if (priv->up) { | |
1620 | switch (Operation) { | |
547d0c34 LF |
1621 | case SCAN_OPT_BACKUP: |
1622 | priv->rtllib->InitialGainHandler(dev, IG_Backup); | |
1623 | break; | |
94a79942 | 1624 | |
547d0c34 LF |
1625 | case SCAN_OPT_RESTORE: |
1626 | priv->rtllib->InitialGainHandler(dev, IG_Restore); | |
1627 | break; | |
94a79942 | 1628 | |
547d0c34 LF |
1629 | default: |
1630 | RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n"); | |
1631 | break; | |
94a79942 LF |
1632 | } |
1633 | } | |
1634 | ||
1635 | } |