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94a79942 LF |
1 | /****************************************************************************** |
2 | * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. | |
3 | * | |
4 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
5 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
6 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
7 | * more details. | |
8 | * | |
9 | * You should have received a copy of the GNU General Public License along with | |
10 | * this program; if not, write to the Free Software Foundation, Inc., | |
11 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in the | |
14 | * file called LICENSE. | |
15 | * | |
16 | * Contact Information: | |
17 | * wlanfae <wlanfae@realtek.com> | |
18 | ******************************************************************************/ | |
94a79942 LF |
19 | |
20 | #include "rtl_core.h" | |
21 | #include "r8192E_hw.h" | |
22 | #include "r8192E_phyreg.h" | |
23 | #include "r8190P_rtl8256.h" | |
24 | #include "r8192E_phy.h" | |
25 | #include "rtl_dm.h" | |
94a79942 | 26 | |
94a79942 | 27 | #include "r8192E_hwimg.h" |
94a79942 LF |
28 | |
29 | static u32 RF_CHANNEL_TABLE_ZEBRA[] = { | |
30 | 0, | |
31 | 0x085c, | |
32 | 0x08dc, | |
33 | 0x095c, | |
34 | 0x09dc, | |
35 | 0x0a5c, | |
36 | 0x0adc, | |
37 | 0x0b5c, | |
38 | 0x0bdc, | |
39 | 0x0c5c, | |
40 | 0x0cdc, | |
41 | 0x0d5c, | |
42 | 0x0ddc, | |
43 | 0x0e5c, | |
44 | 0x0f72, | |
45 | }; | |
46 | ||
47 | /*************************Define local function prototype**********************/ | |
48 | ||
547d0c34 LF |
49 | static u32 phy_FwRFSerialRead(struct net_device *dev, |
50 | enum rf90_radio_path eRFPath, | |
51 | u32 Offset); | |
52 | static void phy_FwRFSerialWrite(struct net_device *dev, | |
53 | enum rf90_radio_path eRFPath, | |
54 | u32 Offset, u32 Data); | |
49aab5fd LF |
55 | |
56 | static u32 rtl8192_CalculateBitShift(u32 dwBitMask) | |
94a79942 LF |
57 | { |
58 | u32 i; | |
547d0c34 LF |
59 | for (i = 0; i <= 31; i++) { |
60 | if (((dwBitMask >> i) & 0x1) == 1) | |
94a79942 LF |
61 | break; |
62 | } | |
63 | return i; | |
64 | } | |
547d0c34 LF |
65 | |
66 | u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) | |
94a79942 LF |
67 | { |
68 | u8 ret = 1; | |
69 | struct r8192_priv *priv = rtllib_priv(dev); | |
94a79942 LF |
70 | if (priv->rf_type == RF_2T4R) |
71 | ret = 0; | |
547d0c34 | 72 | else if (priv->rf_type == RF_1T2R) { |
94a79942 LF |
73 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) |
74 | ret = 1; | |
75 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) | |
76 | ret = 0; | |
77 | } | |
94a79942 LF |
78 | return ret; |
79 | } | |
547d0c34 LF |
80 | |
81 | void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, | |
82 | u32 dwData) | |
94a79942 LF |
83 | { |
84 | ||
85 | u32 OriginalValue, BitShift, NewValue; | |
86 | ||
547d0c34 | 87 | if (dwBitMask != bMaskDWord) { |
94a79942 LF |
88 | OriginalValue = read_nic_dword(dev, dwRegAddr); |
89 | BitShift = rtl8192_CalculateBitShift(dwBitMask); | |
547d0c34 LF |
90 | NewValue = (((OriginalValue) & (~dwBitMask)) | |
91 | (dwData << BitShift)); | |
94a79942 | 92 | write_nic_dword(dev, dwRegAddr, NewValue); |
547d0c34 | 93 | } else |
94a79942 LF |
94 | write_nic_dword(dev, dwRegAddr, dwData); |
95 | return; | |
96 | } | |
547d0c34 LF |
97 | |
98 | u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) | |
94a79942 LF |
99 | { |
100 | u32 Ret = 0, OriginalValue, BitShift; | |
101 | ||
102 | OriginalValue = read_nic_dword(dev, dwRegAddr); | |
103 | BitShift = rtl8192_CalculateBitShift(dwBitMask); | |
104 | Ret = (OriginalValue & dwBitMask) >> BitShift; | |
105 | ||
547d0c34 | 106 | return Ret; |
94a79942 | 107 | } |
49aab5fd LF |
108 | static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, |
109 | enum rf90_radio_path eRFPath, u32 Offset) | |
94a79942 LF |
110 | { |
111 | struct r8192_priv *priv = rtllib_priv(dev); | |
112 | u32 ret = 0; | |
113 | u32 NewOffset = 0; | |
547d0c34 | 114 | struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; |
94a79942 LF |
115 | Offset &= 0x3f; |
116 | ||
547d0c34 | 117 | if (priv->rf_chip == RF_8256) { |
94a79942 | 118 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
547d0c34 | 119 | if (Offset >= 31) { |
94a79942 | 120 | priv->RfReg0Value[eRFPath] |= 0x140; |
547d0c34 LF |
121 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
122 | bMaskDWord, | |
123 | (priv->RfReg0Value[eRFPath]<<16)); | |
124 | NewOffset = Offset - 30; | |
125 | } else if (Offset >= 16) { | |
94a79942 LF |
126 | priv->RfReg0Value[eRFPath] |= 0x100; |
127 | priv->RfReg0Value[eRFPath] &= (~0x40); | |
547d0c34 LF |
128 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
129 | bMaskDWord, | |
130 | (priv->RfReg0Value[eRFPath]<<16)); | |
94a79942 LF |
131 | |
132 | NewOffset = Offset - 15; | |
547d0c34 | 133 | } else |
94a79942 | 134 | NewOffset = Offset; |
547d0c34 LF |
135 | } else { |
136 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need" | |
137 | " to be 8256\n"); | |
94a79942 LF |
138 | NewOffset = Offset; |
139 | } | |
547d0c34 LF |
140 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, |
141 | NewOffset); | |
94a79942 LF |
142 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); |
143 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); | |
144 | ||
547d0c34 | 145 | mdelay(1); |
94a79942 | 146 | |
547d0c34 LF |
147 | ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, |
148 | bLSSIReadBackData); | |
94a79942 | 149 | |
547d0c34 | 150 | if (priv->rf_chip == RF_8256) { |
94a79942 LF |
151 | priv->RfReg0Value[eRFPath] &= 0xebf; |
152 | ||
547d0c34 LF |
153 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, |
154 | (priv->RfReg0Value[eRFPath] << 16)); | |
94a79942 | 155 | |
94a79942 | 156 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); |
94a79942 LF |
157 | } |
158 | ||
159 | ||
160 | return ret; | |
161 | ||
162 | } | |
163 | ||
49aab5fd LF |
164 | static void rtl8192_phy_RFSerialWrite(struct net_device *dev, |
165 | enum rf90_radio_path eRFPath, u32 Offset, | |
166 | u32 Data) | |
94a79942 LF |
167 | { |
168 | struct r8192_priv *priv = rtllib_priv(dev); | |
169 | u32 DataAndAddr = 0, NewOffset = 0; | |
9bf6e4c1 | 170 | struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; |
94a79942 LF |
171 | |
172 | Offset &= 0x3f; | |
547d0c34 | 173 | if (priv->rf_chip == RF_8256) { |
94a79942 | 174 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); |
94a79942 | 175 | |
547d0c34 | 176 | if (Offset >= 31) { |
94a79942 | 177 | priv->RfReg0Value[eRFPath] |= 0x140; |
547d0c34 LF |
178 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
179 | bMaskDWord, | |
180 | (priv->RfReg0Value[eRFPath] << 16)); | |
94a79942 | 181 | NewOffset = Offset - 30; |
547d0c34 | 182 | } else if (Offset >= 16) { |
94a79942 LF |
183 | priv->RfReg0Value[eRFPath] |= 0x100; |
184 | priv->RfReg0Value[eRFPath] &= (~0x40); | |
547d0c34 LF |
185 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, |
186 | bMaskDWord, | |
187 | (priv->RfReg0Value[eRFPath] << 16)); | |
94a79942 | 188 | NewOffset = Offset - 15; |
547d0c34 | 189 | } else |
94a79942 | 190 | NewOffset = Offset; |
547d0c34 LF |
191 | } else { |
192 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be" | |
193 | " 8256\n"); | |
94a79942 LF |
194 | NewOffset = Offset; |
195 | } | |
196 | ||
197 | DataAndAddr = (Data<<16) | (NewOffset&0x3f); | |
198 | ||
199 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); | |
200 | ||
547d0c34 | 201 | if (Offset == 0x0) |
94a79942 LF |
202 | priv->RfReg0Value[eRFPath] = Data; |
203 | ||
547d0c34 LF |
204 | if (priv->rf_chip == RF_8256) { |
205 | if (Offset != 0) { | |
94a79942 LF |
206 | priv->RfReg0Value[eRFPath] &= 0xebf; |
207 | rtl8192_setBBreg( | |
208 | dev, | |
209 | pPhyReg->rf3wireOffset, | |
210 | bMaskDWord, | |
211 | (priv->RfReg0Value[eRFPath] << 16)); | |
212 | } | |
94a79942 | 213 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); |
94a79942 | 214 | } |
94a79942 LF |
215 | return; |
216 | } | |
217 | ||
547d0c34 LF |
218 | void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, |
219 | u32 RegAddr, u32 BitMask, u32 Data) | |
94a79942 LF |
220 | { |
221 | struct r8192_priv *priv = rtllib_priv(dev); | |
222 | u32 Original_Value, BitShift, New_Value; | |
223 | ||
224 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | |
225 | return; | |
94a79942 LF |
226 | if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) |
227 | return; | |
94a79942 LF |
228 | |
229 | RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); | |
547d0c34 LF |
230 | if (priv->Rf_Mode == RF_OP_By_FW) { |
231 | if (BitMask != bMask12Bits) { | |
232 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, | |
233 | RegAddr); | |
94a79942 | 234 | BitShift = rtl8192_CalculateBitShift(BitMask); |
547d0c34 LF |
235 | New_Value = (((Original_Value) & (~BitMask)) | |
236 | (Data << BitShift)); | |
94a79942 LF |
237 | |
238 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); | |
547d0c34 | 239 | } else |
94a79942 LF |
240 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); |
241 | udelay(200); | |
242 | ||
547d0c34 LF |
243 | } else { |
244 | if (BitMask != bMask12Bits) { | |
245 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, | |
246 | RegAddr); | |
94a79942 | 247 | BitShift = rtl8192_CalculateBitShift(BitMask); |
547d0c34 LF |
248 | New_Value = (((Original_Value) & (~BitMask)) | |
249 | (Data << BitShift)); | |
94a79942 | 250 | |
547d0c34 LF |
251 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, |
252 | New_Value); | |
253 | } else | |
94a79942 LF |
254 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); |
255 | } | |
256 | return; | |
257 | } | |
258 | ||
547d0c34 LF |
259 | u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, |
260 | u32 RegAddr, u32 BitMask) | |
94a79942 LF |
261 | { |
262 | u32 Original_Value, Readback_Value, BitShift; | |
263 | struct r8192_priv *priv = rtllib_priv(dev); | |
264 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) | |
265 | return 0; | |
94a79942 LF |
266 | if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) |
267 | return 0; | |
94a79942 | 268 | down(&priv->rf_sem); |
547d0c34 | 269 | if (priv->Rf_Mode == RF_OP_By_FW) { |
94a79942 LF |
270 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); |
271 | udelay(200); | |
547d0c34 LF |
272 | } else { |
273 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, | |
274 | RegAddr); | |
94a79942 LF |
275 | } |
276 | BitShift = rtl8192_CalculateBitShift(BitMask); | |
277 | Readback_Value = (Original_Value & BitMask) >> BitShift; | |
278 | up(&priv->rf_sem); | |
547d0c34 | 279 | return Readback_Value; |
94a79942 LF |
280 | } |
281 | ||
547d0c34 LF |
282 | static u32 phy_FwRFSerialRead(struct net_device *dev, |
283 | enum rf90_radio_path eRFPath, u32 Offset) | |
94a79942 LF |
284 | { |
285 | u32 retValue = 0; | |
286 | u32 Data = 0; | |
287 | u8 time = 0; | |
547d0c34 LF |
288 | Data |= ((Offset & 0xFF) << 12); |
289 | Data |= ((eRFPath & 0x3) << 20); | |
94a79942 | 290 | Data |= 0x80000000; |
547d0c34 | 291 | while (read_nic_dword(dev, QPNR)&0x80000000) { |
94a79942 | 292 | if (time++ < 100) |
94a79942 | 293 | udelay(10); |
94a79942 LF |
294 | else |
295 | break; | |
296 | } | |
297 | write_nic_dword(dev, QPNR, Data); | |
547d0c34 | 298 | while (read_nic_dword(dev, QPNR) & 0x80000000) { |
94a79942 | 299 | if (time++ < 100) |
94a79942 | 300 | udelay(10); |
94a79942 | 301 | else |
547d0c34 | 302 | return 0; |
94a79942 LF |
303 | } |
304 | retValue = read_nic_dword(dev, RF_DATA); | |
305 | ||
547d0c34 | 306 | return retValue; |
94a79942 LF |
307 | |
308 | } /* phy_FwRFSerialRead */ | |
309 | ||
547d0c34 LF |
310 | static void phy_FwRFSerialWrite(struct net_device *dev, |
311 | enum rf90_radio_path eRFPath, | |
312 | u32 Offset, u32 Data) | |
94a79942 LF |
313 | { |
314 | u8 time = 0; | |
315 | ||
547d0c34 LF |
316 | Data |= ((Offset & 0xFF) << 12); |
317 | Data |= ((eRFPath & 0x3) << 20); | |
94a79942 LF |
318 | Data |= 0x400000; |
319 | Data |= 0x80000000; | |
320 | ||
547d0c34 | 321 | while (read_nic_dword(dev, QPNR) & 0x80000000) { |
94a79942 | 322 | if (time++ < 100) |
94a79942 | 323 | udelay(10); |
94a79942 LF |
324 | else |
325 | break; | |
326 | } | |
327 | write_nic_dword(dev, QPNR, Data); | |
328 | ||
329 | } /* phy_FwRFSerialWrite */ | |
330 | ||
331 | ||
547d0c34 | 332 | void rtl8192_phy_configmac(struct net_device *dev) |
94a79942 LF |
333 | { |
334 | u32 dwArrayLen = 0, i = 0; | |
547d0c34 | 335 | u32 *pdwArray = NULL; |
94a79942 | 336 | struct r8192_priv *priv = rtllib_priv(dev); |
547d0c34 LF |
337 | |
338 | if (priv->bTXPowerDataReadFromEEPORM) { | |
94a79942 LF |
339 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); |
340 | dwArrayLen = MACPHY_Array_PGLength; | |
341 | pdwArray = Rtl819XMACPHY_Array_PG; | |
342 | ||
547d0c34 LF |
343 | } else { |
344 | RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n"); | |
94a79942 LF |
345 | dwArrayLen = MACPHY_ArrayLength; |
346 | pdwArray = Rtl819XMACPHY_Array; | |
347 | } | |
547d0c34 LF |
348 | for (i = 0; i < dwArrayLen; i += 3) { |
349 | RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC" | |
350 | "PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", | |
351 | pdwArray[i], pdwArray[i+1], pdwArray[i+2]); | |
94a79942 | 352 | if (pdwArray[i] == 0x318) |
94a79942 | 353 | pdwArray[i+2] = 0x00000800; |
547d0c34 LF |
354 | rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], |
355 | pdwArray[i+2]); | |
94a79942 LF |
356 | } |
357 | return; | |
358 | ||
359 | } | |
360 | ||
547d0c34 | 361 | void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) |
94a79942 LF |
362 | { |
363 | int i; | |
547d0c34 LF |
364 | u32 *Rtl819XPHY_REGArray_Table = NULL; |
365 | u32 *Rtl819XAGCTAB_Array_Table = NULL; | |
366 | u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; | |
94a79942 | 367 | struct r8192_priv *priv = rtllib_priv(dev); |
547d0c34 LF |
368 | |
369 | AGCTAB_ArrayLen = AGCTAB_ArrayLength; | |
370 | Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; | |
371 | if (priv->rf_type == RF_2T4R) { | |
372 | PHY_REGArrayLen = PHY_REGArrayLength; | |
373 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; | |
374 | } else if (priv->rf_type == RF_1T2R) { | |
375 | PHY_REGArrayLen = PHY_REG_1T2RArrayLength; | |
376 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; | |
94a79942 LF |
377 | } |
378 | ||
547d0c34 LF |
379 | if (ConfigType == BaseBand_Config_PHY_REG) { |
380 | for (i = 0; i < PHY_REGArrayLen; i += 2) { | |
381 | rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], | |
382 | bMaskDWord, | |
383 | Rtl819XPHY_REGArray_Table[i+1]); | |
384 | RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray" | |
385 | "[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n", | |
386 | i, Rtl819XPHY_REGArray_Table[i], | |
387 | Rtl819XPHY_REGArray_Table[i+1]); | |
94a79942 | 388 | } |
547d0c34 LF |
389 | } else if (ConfigType == BaseBand_Config_AGC_TAB) { |
390 | for (i = 0; i < AGCTAB_ArrayLen; i += 2) { | |
391 | rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], | |
392 | bMaskDWord, | |
393 | Rtl819XAGCTAB_Array_Table[i+1]); | |
394 | RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] " | |
395 | "is %x rtl819XAGCTAB_Array[1] is %x\n", i, | |
396 | Rtl819XAGCTAB_Array_Table[i], | |
397 | Rtl819XAGCTAB_Array_Table[i+1]); | |
94a79942 LF |
398 | } |
399 | } | |
400 | return; | |
94a79942 | 401 | } |
547d0c34 | 402 | |
49aab5fd | 403 | static void rtl8192_InitBBRFRegDef(struct net_device *dev) |
94a79942 LF |
404 | { |
405 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 | 406 | |
94a79942 LF |
407 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; |
408 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; | |
409 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; | |
410 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; | |
411 | ||
412 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; | |
413 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; | |
414 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; | |
415 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; | |
416 | ||
417 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; | |
418 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; | |
419 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; | |
420 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; | |
421 | ||
422 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; | |
423 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; | |
424 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; | |
425 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; | |
426 | ||
427 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; | |
428 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; | |
429 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; | |
430 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; | |
431 | ||
432 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; | |
433 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; | |
434 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; | |
435 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; | |
436 | ||
437 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; | |
438 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; | |
439 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; | |
440 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; | |
441 | ||
442 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; | |
443 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; | |
444 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; | |
445 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; | |
446 | ||
447 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; | |
448 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; | |
449 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; | |
450 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; | |
451 | ||
452 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; | |
453 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; | |
454 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; | |
455 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; | |
456 | ||
457 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; | |
458 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; | |
459 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; | |
460 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; | |
461 | ||
462 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; | |
463 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; | |
464 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; | |
465 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; | |
466 | ||
467 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; | |
468 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; | |
469 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; | |
470 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; | |
471 | ||
472 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; | |
473 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; | |
474 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; | |
475 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; | |
476 | ||
477 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; | |
478 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; | |
479 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; | |
480 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; | |
481 | ||
482 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; | |
483 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; | |
484 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; | |
485 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; | |
486 | ||
487 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; | |
488 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; | |
489 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; | |
490 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; | |
491 | ||
492 | } | |
547d0c34 LF |
493 | |
494 | bool rtl8192_phy_checkBBAndRF(struct net_device *dev, | |
495 | enum hw90_block CheckBlock, | |
496 | enum rf90_radio_path eRFPath) | |
94a79942 LF |
497 | { |
498 | bool ret = true; | |
499 | u32 i, CheckTimes = 4, dwRegRead = 0; | |
500 | u32 WriteAddr[4]; | |
501 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; | |
547d0c34 | 502 | |
94a79942 LF |
503 | WriteAddr[HW90_BLOCK_MAC] = 0x100; |
504 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; | |
505 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; | |
506 | WriteAddr[HW90_BLOCK_RF] = 0x3; | |
547d0c34 LF |
507 | RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, |
508 | CheckBlock); | |
509 | for (i = 0; i < CheckTimes; i++) { | |
510 | switch (CheckBlock) { | |
94a79942 | 511 | case HW90_BLOCK_MAC: |
547d0c34 LF |
512 | RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write " |
513 | "0x100 here!"); | |
94a79942 LF |
514 | break; |
515 | ||
516 | case HW90_BLOCK_PHY0: | |
517 | case HW90_BLOCK_PHY1: | |
547d0c34 LF |
518 | write_nic_dword(dev, WriteAddr[CheckBlock], |
519 | WriteData[i]); | |
94a79942 LF |
520 | dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); |
521 | break; | |
522 | ||
523 | case HW90_BLOCK_RF: | |
524 | WriteData[i] &= 0xfff; | |
547d0c34 LF |
525 | rtl8192_phy_SetRFReg(dev, eRFPath, |
526 | WriteAddr[HW90_BLOCK_RF], | |
527 | bMask12Bits, WriteData[i]); | |
94a79942 | 528 | mdelay(10); |
547d0c34 LF |
529 | dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, |
530 | WriteAddr[HW90_BLOCK_RF], | |
531 | bMaskDWord); | |
94a79942 LF |
532 | mdelay(10); |
533 | break; | |
534 | ||
535 | default: | |
536 | ret = false; | |
537 | break; | |
538 | } | |
539 | ||
540 | ||
547d0c34 LF |
541 | if (dwRegRead != WriteData[i]) { |
542 | RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, " | |
543 | "WriteData: %x\n", dwRegRead, WriteData[i]); | |
94a79942 LF |
544 | ret = false; |
545 | break; | |
546 | } | |
547 | } | |
548 | ||
549 | return ret; | |
550 | } | |
551 | ||
49aab5fd | 552 | static bool rtl8192_BB_Config_ParaFile(struct net_device *dev) |
94a79942 LF |
553 | { |
554 | struct r8192_priv *priv = rtllib_priv(dev); | |
555 | bool rtStatus = true; | |
556 | u8 bRegValue = 0, eCheckItem = 0; | |
557 | u32 dwRegValue = 0; | |
94a79942 LF |
558 | |
559 | bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); | |
547d0c34 | 560 | write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); |
94a79942 LF |
561 | |
562 | dwRegValue = read_nic_dword(dev, CPU_GEN); | |
563 | write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); | |
564 | ||
547d0c34 LF |
565 | for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; |
566 | eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { | |
567 | rtStatus = rtl8192_phy_checkBBAndRF(dev, | |
568 | (enum hw90_block)eCheckItem, | |
569 | (enum rf90_radio_path)0); | |
4bb01423 | 570 | if (!rtStatus) { |
547d0c34 LF |
571 | RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():" |
572 | "Check PHY%d Fail!!\n", eCheckItem-1); | |
94a79942 LF |
573 | return rtStatus; |
574 | } | |
575 | } | |
576 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); | |
577 | rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); | |
578 | ||
579 | dwRegValue = read_nic_dword(dev, CPU_GEN); | |
580 | write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); | |
581 | ||
582 | rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); | |
583 | ||
547d0c34 | 584 | if (priv->IC_Cut > VERSION_8190_BD) { |
94a79942 | 585 | if (priv->rf_type == RF_2T4R) |
547d0c34 LF |
586 | dwRegValue = (priv->AntennaTxPwDiff[2]<<8 | |
587 | priv->AntennaTxPwDiff[1]<<4 | | |
588 | priv->AntennaTxPwDiff[0]); | |
94a79942 LF |
589 | else |
590 | dwRegValue = 0x0; | |
591 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, | |
592 | (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); | |
593 | ||
594 | ||
94a79942 | 595 | dwRegValue = priv->CrystalCap; |
547d0c34 LF |
596 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, |
597 | dwRegValue); | |
94a79942 LF |
598 | } |
599 | ||
600 | return rtStatus; | |
601 | } | |
547d0c34 | 602 | bool rtl8192_BBConfig(struct net_device *dev) |
94a79942 LF |
603 | { |
604 | bool rtStatus = true; | |
547d0c34 | 605 | |
94a79942 LF |
606 | rtl8192_InitBBRFRegDef(dev); |
607 | rtStatus = rtl8192_BB_Config_ParaFile(dev); | |
608 | return rtStatus; | |
609 | } | |
610 | ||
547d0c34 | 611 | void rtl8192_phy_getTxPower(struct net_device *dev) |
94a79942 LF |
612 | { |
613 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 | 614 | |
94a79942 LF |
615 | priv->MCSTxPowerLevelOriginalOffset[0] = |
616 | read_nic_dword(dev, rTxAGC_Rate18_06); | |
617 | priv->MCSTxPowerLevelOriginalOffset[1] = | |
618 | read_nic_dword(dev, rTxAGC_Rate54_24); | |
619 | priv->MCSTxPowerLevelOriginalOffset[2] = | |
620 | read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); | |
621 | priv->MCSTxPowerLevelOriginalOffset[3] = | |
622 | read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); | |
623 | priv->MCSTxPowerLevelOriginalOffset[4] = | |
624 | read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); | |
625 | priv->MCSTxPowerLevelOriginalOffset[5] = | |
626 | read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); | |
94a79942 LF |
627 | |
628 | priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); | |
629 | priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); | |
630 | priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); | |
631 | priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); | |
547d0c34 LF |
632 | RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, " |
633 | "c60=0x%x, c68=0x%x)\n", | |
94a79942 LF |
634 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], |
635 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); | |
636 | ||
637 | priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); | |
638 | priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); | |
547d0c34 | 639 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", |
94a79942 LF |
640 | rOFDM0_RxDetector3, priv->framesync); |
641 | priv->SifsTime = read_nic_word(dev, SIFS); | |
642 | return; | |
643 | } | |
644 | ||
547d0c34 | 645 | void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) |
94a79942 LF |
646 | { |
647 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 | 648 | u8 powerlevel = 0, powerlevelOFDM24G = 0; |
94a79942 LF |
649 | char ant_pwr_diff; |
650 | u32 u4RegValue; | |
651 | ||
547d0c34 | 652 | if (priv->epromtype == EEPROM_93C46) { |
94a79942 LF |
653 | powerlevel = priv->TxPowerLevelCCK[channel-1]; |
654 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | |
547d0c34 LF |
655 | } else if (priv->epromtype == EEPROM_93C56) { |
656 | if (priv->rf_type == RF_1T2R) { | |
94a79942 LF |
657 | powerlevel = priv->TxPowerLevelCCK_C[channel-1]; |
658 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; | |
547d0c34 | 659 | } else if (priv->rf_type == RF_2T4R) { |
94a79942 LF |
660 | powerlevel = priv->TxPowerLevelCCK_A[channel-1]; |
661 | powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; | |
662 | ||
663 | ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] | |
547d0c34 | 664 | - priv->TxPowerLevelOFDM24G_A[channel-1]; |
94a79942 LF |
665 | |
666 | priv->RF_C_TxPwDiff = ant_pwr_diff; | |
667 | ||
668 | ant_pwr_diff &= 0xf; | |
669 | ||
670 | priv->AntennaTxPwDiff[2] = 0; | |
671 | priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); | |
672 | priv->AntennaTxPwDiff[0] = 0; | |
673 | ||
547d0c34 LF |
674 | u4RegValue = (priv->AntennaTxPwDiff[2]<<8 | |
675 | priv->AntennaTxPwDiff[1]<<4 | | |
676 | priv->AntennaTxPwDiff[0]); | |
94a79942 LF |
677 | |
678 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, | |
679 | (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); | |
680 | } | |
681 | } | |
cb762154 | 682 | switch (priv->rf_chip) { |
94a79942 LF |
683 | case RF_8225: |
684 | break; | |
685 | case RF_8256: | |
686 | PHY_SetRF8256CCKTxPower(dev, powerlevel); | |
687 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); | |
688 | break; | |
689 | case RF_8258: | |
690 | break; | |
691 | default: | |
73e29189 | 692 | RT_TRACE(COMP_ERR, "unknown rf chip in function %s()\n", |
547d0c34 | 693 | __func__); |
94a79942 LF |
694 | break; |
695 | } | |
696 | return; | |
697 | } | |
698 | ||
547d0c34 | 699 | bool rtl8192_phy_RFConfig(struct net_device *dev) |
94a79942 LF |
700 | { |
701 | struct r8192_priv *priv = rtllib_priv(dev); | |
702 | bool rtStatus = true; | |
547d0c34 LF |
703 | switch (priv->rf_chip) { |
704 | case RF_8225: | |
705 | break; | |
706 | case RF_8256: | |
707 | rtStatus = PHY_RF8256_Config(dev); | |
708 | break; | |
94a79942 | 709 | |
547d0c34 LF |
710 | case RF_8258: |
711 | break; | |
712 | case RF_PSEUDO_11N: | |
94a79942 LF |
713 | break; |
714 | ||
547d0c34 LF |
715 | default: |
716 | RT_TRACE(COMP_ERR, "error chip id\n"); | |
717 | break; | |
94a79942 LF |
718 | } |
719 | return rtStatus; | |
720 | } | |
721 | ||
547d0c34 | 722 | void rtl8192_phy_updateInitGain(struct net_device *dev) |
94a79942 LF |
723 | { |
724 | return; | |
725 | } | |
726 | ||
547d0c34 LF |
727 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, |
728 | enum rf90_radio_path eRFPath) | |
94a79942 LF |
729 | { |
730 | ||
731 | int i; | |
732 | u8 ret = 0; | |
733 | ||
547d0c34 LF |
734 | switch (eRFPath) { |
735 | case RF90_PATH_A: | |
736 | for (i = 0; i < RadioA_ArrayLength; i += 2) { | |
737 | if (Rtl819XRadioA_Array[i] == 0xfe) { | |
738 | msleep(100); | |
739 | continue; | |
94a79942 | 740 | } |
547d0c34 LF |
741 | rtl8192_phy_SetRFReg(dev, eRFPath, |
742 | Rtl819XRadioA_Array[i], | |
743 | bMask12Bits, | |
744 | Rtl819XRadioA_Array[i+1]); | |
94a79942 | 745 | |
547d0c34 LF |
746 | } |
747 | break; | |
748 | case RF90_PATH_B: | |
749 | for (i = 0; i < RadioB_ArrayLength; i += 2) { | |
750 | if (Rtl819XRadioB_Array[i] == 0xfe) { | |
751 | msleep(100); | |
752 | continue; | |
94a79942 | 753 | } |
547d0c34 LF |
754 | rtl8192_phy_SetRFReg(dev, eRFPath, |
755 | Rtl819XRadioB_Array[i], | |
756 | bMask12Bits, | |
757 | Rtl819XRadioB_Array[i+1]); | |
94a79942 | 758 | |
547d0c34 LF |
759 | } |
760 | break; | |
761 | case RF90_PATH_C: | |
762 | for (i = 0; i < RadioC_ArrayLength; i += 2) { | |
763 | if (Rtl819XRadioC_Array[i] == 0xfe) { | |
764 | msleep(100); | |
765 | continue; | |
94a79942 | 766 | } |
547d0c34 LF |
767 | rtl8192_phy_SetRFReg(dev, eRFPath, |
768 | Rtl819XRadioC_Array[i], | |
769 | bMask12Bits, | |
770 | Rtl819XRadioC_Array[i+1]); | |
94a79942 | 771 | |
547d0c34 LF |
772 | } |
773 | break; | |
774 | case RF90_PATH_D: | |
775 | for (i = 0; i < RadioD_ArrayLength; i += 2) { | |
776 | if (Rtl819XRadioD_Array[i] == 0xfe) { | |
777 | msleep(100); | |
778 | continue; | |
94a79942 | 779 | } |
547d0c34 LF |
780 | rtl8192_phy_SetRFReg(dev, eRFPath, |
781 | Rtl819XRadioD_Array[i], bMask12Bits, | |
782 | Rtl819XRadioD_Array[i+1]); | |
783 | ||
784 | } | |
785 | break; | |
786 | default: | |
787 | break; | |
94a79942 LF |
788 | } |
789 | ||
547d0c34 | 790 | return ret; |
94a79942 LF |
791 | |
792 | } | |
49aab5fd | 793 | static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) |
94a79942 LF |
794 | { |
795 | struct r8192_priv *priv = rtllib_priv(dev); | |
796 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; | |
797 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; | |
798 | ||
547d0c34 | 799 | switch (priv->rf_chip) { |
94a79942 | 800 | case RF_8225: |
94a79942 LF |
801 | break; |
802 | ||
803 | case RF_8256: | |
804 | PHY_SetRF8256CCKTxPower(dev, powerlevel); | |
805 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); | |
806 | break; | |
807 | ||
808 | case RF_8258: | |
809 | break; | |
810 | default: | |
547d0c34 LF |
811 | RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower" |
812 | "Level()\n"); | |
94a79942 LF |
813 | break; |
814 | } | |
815 | return; | |
816 | } | |
547d0c34 | 817 | |
49aab5fd LF |
818 | static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, |
819 | u32 CmdTableIdx, u32 CmdTableSz, | |
820 | enum sw_chnl_cmd_id CmdID, | |
821 | u32 Para1, u32 Para2, u32 msDelay) | |
94a79942 | 822 | { |
547d0c34 | 823 | struct sw_chnl_cmd *pCmd; |
94a79942 | 824 | |
547d0c34 LF |
825 | if (CmdTable == NULL) { |
826 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot " | |
827 | "be NULL.\n"); | |
94a79942 LF |
828 | return false; |
829 | } | |
547d0c34 LF |
830 | if (CmdTableIdx >= CmdTableSz) { |
831 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid" | |
832 | " index, please check size of the table, CmdTableIdx:" | |
833 | "%d, CmdTableSz:%d\n", | |
94a79942 LF |
834 | CmdTableIdx, CmdTableSz); |
835 | return false; | |
836 | } | |
837 | ||
838 | pCmd = CmdTable + CmdTableIdx; | |
839 | pCmd->CmdID = CmdID; | |
840 | pCmd->Para1 = Para1; | |
841 | pCmd->Para2 = Para2; | |
842 | pCmd->msDelay = msDelay; | |
843 | ||
844 | return true; | |
845 | } | |
547d0c34 | 846 | |
49aab5fd LF |
847 | static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, |
848 | u8 *stage, u8 *step, u32 *delay) | |
94a79942 LF |
849 | { |
850 | struct r8192_priv *priv = rtllib_priv(dev); | |
2eed3dee | 851 | struct rtllib_device *ieee = priv->rtllib; |
94a79942 | 852 | u32 PreCommonCmdCnt; |
94a79942 | 853 | u32 PostCommonCmdCnt; |
94a79942 | 854 | u32 RfDependCmdCnt; |
51ce231f | 855 | struct sw_chnl_cmd *CurrentCmd = NULL; |
94a79942 LF |
856 | u8 eRFPath; |
857 | ||
547d0c34 LF |
858 | RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", |
859 | __func__, *stage, *step, channel); | |
94a79942 | 860 | |
976d5341 | 861 | if (!rtllib_legal_channel(priv->rtllib, channel)) { |
547d0c34 LF |
862 | RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", |
863 | channel); | |
94a79942 LF |
864 | return true; |
865 | } | |
94a79942 LF |
866 | |
867 | { | |
868 | PreCommonCmdCnt = 0; | |
2eed3dee LF |
869 | rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd, |
870 | PreCommonCmdCnt++, | |
547d0c34 LF |
871 | MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, |
872 | 0, 0, 0); | |
2eed3dee LF |
873 | rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd, |
874 | PreCommonCmdCnt++, | |
547d0c34 | 875 | MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); |
94a79942 LF |
876 | |
877 | PostCommonCmdCnt = 0; | |
878 | ||
2eed3dee LF |
879 | rtl8192_phy_SetSwChnlCmdArray(ieee->PostCommonCmd, |
880 | PostCommonCmdCnt++, | |
547d0c34 | 881 | MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); |
94a79942 LF |
882 | |
883 | RfDependCmdCnt = 0; | |
547d0c34 | 884 | switch (priv->rf_chip) { |
94a79942 | 885 | case RF_8225: |
547d0c34 LF |
886 | if (!(channel >= 1 && channel <= 14)) { |
887 | RT_TRACE(COMP_ERR, "illegal channel for Zebra " | |
888 | "8225: %d\n", channel); | |
94a79942 LF |
889 | return false; |
890 | } | |
2eed3dee | 891 | rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, |
547d0c34 LF |
892 | RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
893 | CmdID_RF_WriteReg, rZebra1_Channel, | |
894 | RF_CHANNEL_TABLE_ZEBRA[channel], 10); | |
2eed3dee | 895 | rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, |
547d0c34 | 896 | RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
94a79942 LF |
897 | CmdID_End, 0, 0, 0); |
898 | break; | |
899 | ||
900 | case RF_8256: | |
547d0c34 LF |
901 | if (!(channel >= 1 && channel <= 14)) { |
902 | RT_TRACE(COMP_ERR, "illegal channel for Zebra" | |
903 | " 8256: %d\n", channel); | |
94a79942 LF |
904 | return false; |
905 | } | |
2eed3dee | 906 | rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, |
547d0c34 LF |
907 | RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
908 | CmdID_RF_WriteReg, rZebra1_Channel, channel, | |
909 | 10); | |
2eed3dee LF |
910 | rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd, |
911 | ||
547d0c34 LF |
912 | RfDependCmdCnt++, |
913 | MAX_RFDEPENDCMD_CNT, | |
94a79942 LF |
914 | CmdID_End, 0, 0, 0); |
915 | break; | |
916 | ||
917 | case RF_8258: | |
918 | break; | |
919 | ||
920 | default: | |
547d0c34 LF |
921 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", |
922 | priv->rf_chip); | |
94a79942 LF |
923 | return false; |
924 | break; | |
925 | } | |
926 | ||
927 | ||
547d0c34 LF |
928 | do { |
929 | switch (*stage) { | |
94a79942 | 930 | case 0: |
2eed3dee | 931 | CurrentCmd = &ieee->PreCommonCmd[*step]; |
94a79942 LF |
932 | break; |
933 | case 1: | |
2eed3dee | 934 | CurrentCmd = &ieee->RfDependCmd[*step]; |
94a79942 LF |
935 | break; |
936 | case 2: | |
2eed3dee | 937 | CurrentCmd = &ieee->PostCommonCmd[*step]; |
94a79942 LF |
938 | break; |
939 | } | |
940 | ||
52a7fb09 | 941 | if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) { |
547d0c34 | 942 | if ((*stage) == 2) { |
94a79942 | 943 | return true; |
547d0c34 | 944 | } else { |
94a79942 | 945 | (*stage)++; |
547d0c34 | 946 | (*step) = 0; |
94a79942 LF |
947 | continue; |
948 | } | |
949 | } | |
950 | ||
52a7fb09 LF |
951 | if (!CurrentCmd) |
952 | continue; | |
547d0c34 | 953 | switch (CurrentCmd->CmdID) { |
94a79942 LF |
954 | case CmdID_SetTxPowerLevel: |
955 | if (priv->IC_Cut > (u8)VERSION_8190_BD) | |
547d0c34 | 956 | rtl8192_SetTxPowerLevel(dev, channel); |
94a79942 LF |
957 | break; |
958 | case CmdID_WritePortUlong: | |
547d0c34 LF |
959 | write_nic_dword(dev, CurrentCmd->Para1, |
960 | CurrentCmd->Para2); | |
94a79942 LF |
961 | break; |
962 | case CmdID_WritePortUshort: | |
547d0c34 LF |
963 | write_nic_word(dev, CurrentCmd->Para1, |
964 | (u16)CurrentCmd->Para2); | |
94a79942 LF |
965 | break; |
966 | case CmdID_WritePortUchar: | |
547d0c34 LF |
967 | write_nic_byte(dev, CurrentCmd->Para1, |
968 | (u8)CurrentCmd->Para2); | |
94a79942 LF |
969 | break; |
970 | case CmdID_RF_WriteReg: | |
547d0c34 LF |
971 | for (eRFPath = 0; eRFPath < |
972 | priv->NumTotalRFPath; eRFPath++) | |
973 | rtl8192_phy_SetRFReg(dev, | |
974 | (enum rf90_radio_path)eRFPath, | |
975 | CurrentCmd->Para1, bMask12Bits, | |
976 | CurrentCmd->Para2<<7); | |
94a79942 LF |
977 | break; |
978 | default: | |
979 | break; | |
980 | } | |
981 | ||
982 | break; | |
547d0c34 LF |
983 | } while (true); |
984 | } /*for (Number of RF paths)*/ | |
94a79942 | 985 | |
547d0c34 | 986 | (*delay) = CurrentCmd->msDelay; |
94a79942 LF |
987 | (*step)++; |
988 | return false; | |
989 | } | |
990 | ||
49aab5fd | 991 | static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) |
94a79942 LF |
992 | { |
993 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 | 994 | u32 delay = 0; |
94a79942 | 995 | |
547d0c34 LF |
996 | while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, |
997 | &priv->SwChnlStep, &delay)) { | |
998 | if (delay > 0) | |
94a79942 LF |
999 | msleep(delay); |
1000 | if (IS_NIC_DOWN(priv)) | |
547d0c34 | 1001 | break; |
94a79942 LF |
1002 | } |
1003 | } | |
1004 | void rtl8192_SwChnl_WorkItem(struct net_device *dev) | |
1005 | { | |
1006 | ||
1007 | struct r8192_priv *priv = rtllib_priv(dev); | |
1008 | ||
1009 | RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); | |
1010 | ||
547d0c34 LF |
1011 | RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, |
1012 | priv->chan, priv); | |
94a79942 LF |
1013 | |
1014 | rtl8192_phy_FinishSwChnlNow(dev , priv->chan); | |
1015 | ||
1016 | RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); | |
1017 | } | |
1018 | ||
547d0c34 | 1019 | u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) |
94a79942 LF |
1020 | { |
1021 | struct r8192_priv *priv = rtllib_priv(dev); | |
1022 | RT_TRACE(COMP_PHY, "=====>%s()\n", __func__); | |
547d0c34 LF |
1023 | if (IS_NIC_DOWN(priv)) { |
1024 | RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__); | |
94a79942 LF |
1025 | return false; |
1026 | } | |
1027 | if (priv->SwChnlInProgress) | |
1028 | return false; | |
1029 | ||
1030 | ||
547d0c34 | 1031 | switch (priv->rtllib->mode) { |
94a79942 LF |
1032 | case WIRELESS_MODE_A: |
1033 | case WIRELESS_MODE_N_5G: | |
547d0c34 | 1034 | if (channel <= 14) { |
94a79942 LF |
1035 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); |
1036 | return false; | |
1037 | } | |
1038 | break; | |
1039 | case WIRELESS_MODE_B: | |
547d0c34 | 1040 | if (channel > 14) { |
94a79942 LF |
1041 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); |
1042 | return false; | |
1043 | } | |
1044 | break; | |
1045 | case WIRELESS_MODE_G: | |
1046 | case WIRELESS_MODE_N_24G: | |
547d0c34 | 1047 | if (channel > 14) { |
94a79942 LF |
1048 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); |
1049 | return false; | |
1050 | } | |
1051 | break; | |
1052 | } | |
1053 | ||
1054 | priv->SwChnlInProgress = true; | |
1055 | if (channel == 0) | |
1056 | channel = 1; | |
1057 | ||
547d0c34 | 1058 | priv->chan = channel; |
94a79942 | 1059 | |
547d0c34 LF |
1060 | priv->SwChnlStage = 0; |
1061 | priv->SwChnlStep = 0; | |
94a79942 | 1062 | |
547d0c34 | 1063 | if (!IS_NIC_DOWN(priv)) |
94a79942 | 1064 | rtl8192_SwChnl_WorkItem(dev); |
94a79942 LF |
1065 | priv->SwChnlInProgress = false; |
1066 | return true; | |
1067 | } | |
1068 | ||
547d0c34 | 1069 | static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev) |
94a79942 LF |
1070 | { |
1071 | struct r8192_priv *priv = rtllib_priv(dev); | |
1072 | ||
547d0c34 LF |
1073 | switch (priv->CurrentChannelBW) { |
1074 | case HT_CHANNEL_WIDTH_20: | |
1075 | priv->CCKPresentAttentuation = | |
1076 | priv->CCKPresentAttentuation_20Mdefault + | |
1077 | priv->CCKPresentAttentuation_difference; | |
94a79942 | 1078 | |
547d0c34 LF |
1079 | if (priv->CCKPresentAttentuation > |
1080 | (CCKTxBBGainTableLength-1)) | |
1081 | priv->CCKPresentAttentuation = | |
1082 | CCKTxBBGainTableLength-1; | |
1083 | if (priv->CCKPresentAttentuation < 0) | |
1084 | priv->CCKPresentAttentuation = 0; | |
1085 | ||
1086 | RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent" | |
1087 | "Attentuation = %d\n", | |
1088 | priv->CCKPresentAttentuation); | |
1089 | ||
1090 | if (priv->rtllib->current_network.channel == 14 && | |
1091 | !priv->bcck_in_ch14) { | |
1092 | priv->bcck_in_ch14 = true; | |
1093 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1094 | } else if (priv->rtllib->current_network.channel != | |
1095 | 14 && priv->bcck_in_ch14) { | |
1096 | priv->bcck_in_ch14 = false; | |
1097 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1098 | } else { | |
1099 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1100 | } | |
94a79942 LF |
1101 | break; |
1102 | ||
547d0c34 LF |
1103 | case HT_CHANNEL_WIDTH_20_40: |
1104 | priv->CCKPresentAttentuation = | |
1105 | priv->CCKPresentAttentuation_40Mdefault + | |
1106 | priv->CCKPresentAttentuation_difference; | |
1107 | ||
1108 | RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent" | |
1109 | "Attentuation = %d\n", | |
1110 | priv->CCKPresentAttentuation); | |
1111 | if (priv->CCKPresentAttentuation > | |
1112 | (CCKTxBBGainTableLength - 1)) | |
94a79942 | 1113 | priv->CCKPresentAttentuation = |
547d0c34 LF |
1114 | CCKTxBBGainTableLength-1; |
1115 | if (priv->CCKPresentAttentuation < 0) | |
1116 | priv->CCKPresentAttentuation = 0; | |
1117 | ||
1118 | if (priv->rtllib->current_network.channel == 14 && | |
1119 | !priv->bcck_in_ch14) { | |
1120 | priv->bcck_in_ch14 = true; | |
1121 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1122 | } else if (priv->rtllib->current_network.channel != 14 | |
1123 | && priv->bcck_in_ch14) { | |
1124 | priv->bcck_in_ch14 = false; | |
1125 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1126 | } else { | |
1127 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1128 | } | |
94a79942 LF |
1129 | break; |
1130 | } | |
1131 | } | |
1132 | ||
94a79942 LF |
1133 | static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) |
1134 | { | |
1135 | struct r8192_priv *priv = rtllib_priv(dev); | |
1136 | ||
547d0c34 LF |
1137 | if (priv->rtllib->current_network.channel == 14 && |
1138 | !priv->bcck_in_ch14) | |
94a79942 | 1139 | priv->bcck_in_ch14 = true; |
547d0c34 LF |
1140 | else if (priv->rtllib->current_network.channel != 14 && |
1141 | priv->bcck_in_ch14) | |
94a79942 LF |
1142 | priv->bcck_in_ch14 = false; |
1143 | ||
547d0c34 LF |
1144 | switch (priv->CurrentChannelBW) { |
1145 | case HT_CHANNEL_WIDTH_20: | |
1146 | if (priv->Record_CCK_20Mindex == 0) | |
1147 | priv->Record_CCK_20Mindex = 6; | |
1148 | priv->CCK_index = priv->Record_CCK_20Mindex; | |
1149 | RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_" | |
1150 | "Switch_ThermalMeter(),CCK_index = %d\n", | |
1151 | priv->CCK_index); | |
1152 | break; | |
1153 | ||
1154 | case HT_CHANNEL_WIDTH_20_40: | |
1155 | priv->CCK_index = priv->Record_CCK_40Mindex; | |
1156 | RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_" | |
1157 | "Switch_ThermalMeter(), CCK_index = %d\n", | |
1158 | priv->CCK_index); | |
1159 | break; | |
94a79942 LF |
1160 | } |
1161 | dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); | |
1162 | } | |
94a79942 LF |
1163 | |
1164 | static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) | |
1165 | { | |
94a79942 | 1166 | struct r8192_priv *priv = rtllib_priv(dev); |
94a79942 | 1167 | |
94a79942 LF |
1168 | if (priv->IC_Cut >= IC_VersionCut_D) |
1169 | CCK_Tx_Power_Track_BW_Switch_TSSI(dev); | |
1170 | else | |
1171 | CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); | |
94a79942 LF |
1172 | } |
1173 | ||
1174 | void rtl8192_SetBWModeWorkItem(struct net_device *dev) | |
1175 | { | |
1176 | ||
1177 | struct r8192_priv *priv = rtllib_priv(dev); | |
1178 | u8 regBwOpMode; | |
1179 | ||
547d0c34 LF |
1180 | RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s " |
1181 | "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? | |
41ad3d5f | 1182 | "20MHz" : "40MHz"); |
94a79942 LF |
1183 | |
1184 | ||
547d0c34 LF |
1185 | if (priv->rf_chip == RF_PSEUDO_11N) { |
1186 | priv->SetBWModeInProgress = false; | |
94a79942 LF |
1187 | return; |
1188 | } | |
547d0c34 LF |
1189 | if (IS_NIC_DOWN(priv)) { |
1190 | RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__); | |
94a79942 LF |
1191 | return; |
1192 | } | |
1193 | regBwOpMode = read_nic_byte(dev, BW_OPMODE); | |
1194 | ||
547d0c34 LF |
1195 | switch (priv->CurrentChannelBW) { |
1196 | case HT_CHANNEL_WIDTH_20: | |
1197 | regBwOpMode |= BW_OPMODE_20MHZ; | |
1198 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); | |
1199 | break; | |
94a79942 | 1200 | |
547d0c34 LF |
1201 | case HT_CHANNEL_WIDTH_20_40: |
1202 | regBwOpMode &= ~BW_OPMODE_20MHZ; | |
1203 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); | |
1204 | break; | |
94a79942 | 1205 | |
547d0c34 LF |
1206 | default: |
1207 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown " | |
1208 | "Bandwidth: %#X\n", priv->CurrentChannelBW); | |
1209 | break; | |
94a79942 LF |
1210 | } |
1211 | ||
547d0c34 LF |
1212 | switch (priv->CurrentChannelBW) { |
1213 | case HT_CHANNEL_WIDTH_20: | |
1214 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); | |
1215 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); | |
1216 | ||
1217 | if (!priv->btxpower_tracking) { | |
1218 | write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); | |
1219 | write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); | |
1220 | write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); | |
1221 | } else { | |
1222 | CCK_Tx_Power_Track_BW_Switch(dev); | |
1223 | } | |
94a79942 | 1224 | |
547d0c34 | 1225 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); |
94a79942 | 1226 | |
547d0c34 LF |
1227 | break; |
1228 | case HT_CHANNEL_WIDTH_20_40: | |
1229 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); | |
1230 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); | |
1231 | ||
1232 | if (!priv->btxpower_tracking) { | |
1233 | write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); | |
1234 | write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); | |
1235 | write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); | |
1236 | } else { | |
1237 | CCK_Tx_Power_Track_BW_Switch(dev); | |
1238 | } | |
94a79942 | 1239 | |
547d0c34 LF |
1240 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, |
1241 | (priv->nCur40MhzPrimeSC>>1)); | |
1242 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, | |
1243 | priv->nCur40MhzPrimeSC); | |
94a79942 | 1244 | |
547d0c34 LF |
1245 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); |
1246 | break; | |
1247 | default: | |
1248 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown " | |
1249 | "Bandwidth: %#X\n", priv->CurrentChannelBW); | |
1250 | break; | |
94a79942 LF |
1251 | |
1252 | } | |
1253 | ||
547d0c34 LF |
1254 | switch (priv->rf_chip) { |
1255 | case RF_8225: | |
1256 | break; | |
94a79942 | 1257 | |
547d0c34 LF |
1258 | case RF_8256: |
1259 | PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); | |
1260 | break; | |
94a79942 | 1261 | |
547d0c34 LF |
1262 | case RF_8258: |
1263 | break; | |
94a79942 | 1264 | |
547d0c34 LF |
1265 | case RF_PSEUDO_11N: |
1266 | break; | |
94a79942 | 1267 | |
547d0c34 LF |
1268 | default: |
1269 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); | |
1270 | break; | |
94a79942 | 1271 | } |
4f6807e8 | 1272 | |
94a79942 | 1273 | atomic_dec(&(priv->rtllib->atm_swbw)); |
547d0c34 | 1274 | priv->SetBWModeInProgress = false; |
94a79942 LF |
1275 | |
1276 | RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); | |
1277 | } | |
1278 | ||
547d0c34 LF |
1279 | void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, |
1280 | enum ht_extchnl_offset Offset) | |
94a79942 LF |
1281 | { |
1282 | struct r8192_priv *priv = rtllib_priv(dev); | |
1283 | ||
1284 | ||
1285 | if (priv->SetBWModeInProgress) | |
1286 | return; | |
1287 | ||
547d0c34 LF |
1288 | atomic_inc(&(priv->rtllib->atm_swbw)); |
1289 | priv->SetBWModeInProgress = true; | |
94a79942 LF |
1290 | |
1291 | priv->CurrentChannelBW = Bandwidth; | |
1292 | ||
547d0c34 | 1293 | if (Offset == HT_EXTCHNL_OFFSET_LOWER) |
94a79942 | 1294 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; |
547d0c34 | 1295 | else if (Offset == HT_EXTCHNL_OFFSET_UPPER) |
94a79942 LF |
1296 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; |
1297 | else | |
1298 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; | |
1299 | ||
1300 | rtl8192_SetBWModeWorkItem(dev); | |
1301 | ||
1302 | } | |
1303 | ||
94a79942 LF |
1304 | void InitialGain819xPci(struct net_device *dev, u8 Operation) |
1305 | { | |
1306 | #define SCAN_RX_INITIAL_GAIN 0x17 | |
1307 | #define POWER_DETECTION_TH 0x08 | |
1308 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 LF |
1309 | u32 BitMask; |
1310 | u8 initial_gain; | |
1311 | ||
1312 | if (!IS_NIC_DOWN(priv)) { | |
1313 | switch (Operation) { | |
1314 | case IG_Backup: | |
1315 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial" | |
1316 | " gain.\n"); | |
1317 | initial_gain = SCAN_RX_INITIAL_GAIN; | |
1318 | BitMask = bMaskByte0; | |
1319 | if (dm_digtable.dig_algorithm == | |
1320 | DIG_ALGO_BY_FALSE_ALARM) | |
1321 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); | |
1322 | priv->initgain_backup.xaagccore1 = | |
1323 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, | |
1324 | BitMask); | |
1325 | priv->initgain_backup.xbagccore1 = | |
1326 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, | |
1327 | BitMask); | |
1328 | priv->initgain_backup.xcagccore1 = | |
1329 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, | |
1330 | BitMask); | |
1331 | priv->initgain_backup.xdagccore1 = | |
1332 | (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, | |
1333 | BitMask); | |
1334 | BitMask = bMaskByte2; | |
1335 | priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, | |
1336 | rCCK0_CCA, BitMask); | |
1337 | ||
1338 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is" | |
1339 | " %x\n", priv->initgain_backup.xaagccore1); | |
1340 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is" | |
1341 | " %x\n", priv->initgain_backup.xbagccore1); | |
1342 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is" | |
1343 | " %x\n", priv->initgain_backup.xcagccore1); | |
1344 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is" | |
1345 | " %x\n", priv->initgain_backup.xdagccore1); | |
1346 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is" | |
1347 | " %x\n", priv->initgain_backup.cca); | |
1348 | ||
1349 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", | |
1350 | initial_gain); | |
1351 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); | |
1352 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); | |
1353 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); | |
1354 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); | |
1355 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", | |
1356 | POWER_DETECTION_TH); | |
1357 | write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); | |
1358 | break; | |
1359 | case IG_Restore: | |
1360 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial " | |
1361 | "gain.\n"); | |
1362 | BitMask = 0x7f; | |
1363 | if (dm_digtable.dig_algorithm == | |
1364 | DIG_ALGO_BY_FALSE_ALARM) | |
1365 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); | |
1366 | ||
1367 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, | |
1368 | (u32)priv->initgain_backup.xaagccore1); | |
1369 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, | |
1370 | (u32)priv->initgain_backup.xbagccore1); | |
1371 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, | |
1372 | (u32)priv->initgain_backup.xcagccore1); | |
1373 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, | |
1374 | (u32)priv->initgain_backup.xdagccore1); | |
1375 | BitMask = bMaskByte2; | |
1376 | rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, | |
1377 | (u32)priv->initgain_backup.cca); | |
1378 | ||
1379 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50" | |
1380 | " is %x\n", priv->initgain_backup.xaagccore1); | |
1381 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58" | |
1382 | " is %x\n", priv->initgain_backup.xbagccore1); | |
1383 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60" | |
1384 | " is %x\n", priv->initgain_backup.xcagccore1); | |
1385 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68" | |
1386 | " is %x\n", priv->initgain_backup.xdagccore1); | |
1387 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a" | |
1388 | " is %x\n", priv->initgain_backup.cca); | |
1389 | ||
1390 | rtl8192_phy_setTxPower(dev, | |
1391 | priv->rtllib->current_network.channel); | |
1392 | ||
1393 | if (dm_digtable.dig_algorithm == | |
1394 | DIG_ALGO_BY_FALSE_ALARM) | |
1395 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); | |
1396 | break; | |
1397 | default: | |
1398 | RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); | |
1399 | break; | |
94a79942 LF |
1400 | } |
1401 | } | |
1402 | } | |
1403 | ||
547d0c34 | 1404 | void PHY_SetRtl8192eRfOff(struct net_device *dev) |
94a79942 LF |
1405 | { |
1406 | ||
1407 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); | |
1408 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); | |
1409 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); | |
1410 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); | |
1411 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); | |
1412 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); | |
1413 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); | |
1414 | write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07); | |
1415 | ||
1416 | } | |
94a79942 | 1417 | |
49aab5fd LF |
1418 | static bool SetRFPowerState8190(struct net_device *dev, |
1419 | enum rt_rf_power_state eRFPowerState) | |
94a79942 LF |
1420 | { |
1421 | struct r8192_priv *priv = rtllib_priv(dev); | |
547d0c34 LF |
1422 | struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) |
1423 | (&(priv->rtllib->PowerSaveControl)); | |
94a79942 LF |
1424 | bool bResult = true; |
1425 | u8 i = 0, QueueID = 0; | |
1426 | struct rtl8192_tx_ring *ring = NULL; | |
1427 | ||
4bb01423 | 1428 | if (priv->SetRFPowerStateInProgress) |
94a79942 LF |
1429 | return false; |
1430 | RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); | |
1431 | priv->SetRFPowerStateInProgress = true; | |
1432 | ||
547d0c34 LF |
1433 | switch (priv->rf_chip) { |
1434 | case RF_8256: | |
1435 | switch (eRFPowerState) { | |
1436 | case eRfOn: | |
1437 | RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n"); | |
1438 | if ((priv->rtllib->eRFPowerState == eRfOff) && | |
1439 | RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { | |
1440 | bool rtstatus = true; | |
1441 | u32 InitilizeCount = 3; | |
1442 | do { | |
1443 | InitilizeCount--; | |
1444 | priv->RegRfOff = false; | |
1445 | rtstatus = NicIFEnableNIC(dev); | |
4bb01423 | 1446 | } while (!rtstatus && (InitilizeCount > 0)); |
547d0c34 | 1447 | |
4bb01423 | 1448 | if (!rtstatus) { |
547d0c34 LF |
1449 | RT_TRACE(COMP_ERR, "%s():Initialize Ada" |
1450 | "pter fail,return\n", | |
1451 | __func__); | |
1452 | priv->SetRFPowerStateInProgress = false; | |
1453 | return false; | |
1454 | } | |
1455 | ||
1456 | RT_CLEAR_PS_LEVEL(pPSC, | |
1457 | RT_RF_OFF_LEVL_HALT_NIC); | |
1458 | } else { | |
94a79942 LF |
1459 | write_nic_byte(dev, ANAPAR, 0x37); |
1460 | mdelay(1); | |
547d0c34 LF |
1461 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, |
1462 | 0x4, 0x1); | |
94a79942 LF |
1463 | priv->bHwRfOffAction = 0; |
1464 | ||
547d0c34 LF |
1465 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, |
1466 | BIT4, 0x1); | |
1467 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, | |
1468 | 0x300, 0x3); | |
1469 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, | |
1470 | 0x18, 0x3); | |
1471 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, | |
1472 | 0x3); | |
1473 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, | |
1474 | 0x3); | |
1475 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, | |
1476 | 0x60, 0x3); | |
94a79942 | 1477 | |
547d0c34 | 1478 | } |
94a79942 | 1479 | |
547d0c34 LF |
1480 | break; |
1481 | ||
1482 | case eRfSleep: | |
1483 | if (priv->rtllib->eRFPowerState == eRfOff) | |
1484 | break; | |
94a79942 | 1485 | |
94a79942 | 1486 | |
547d0c34 LF |
1487 | for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { |
1488 | ring = &priv->tx_ring[QueueID]; | |
94a79942 | 1489 | |
547d0c34 LF |
1490 | if (skb_queue_len(&ring->queue) == 0) { |
1491 | QueueID++; | |
1492 | continue; | |
1493 | } else { | |
1494 | RT_TRACE((COMP_POWER|COMP_RF), "eRf Off" | |
1495 | "/Sleep: %d times TcbBusyQueue" | |
1496 | "[%d] !=0 before doze!\n", | |
1497 | (i+1), QueueID); | |
1498 | udelay(10); | |
1499 | i++; | |
94a79942 LF |
1500 | } |
1501 | ||
547d0c34 LF |
1502 | if (i >= MAX_DOZE_WAITING_TIMES_9x) { |
1503 | RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! " | |
1504 | "SetRFPowerState8190(): eRfOff" | |
1505 | ": %d times TcbBusyQueue[%d] " | |
1506 | "!= 0 !!!\n", | |
1507 | MAX_DOZE_WAITING_TIMES_9x, | |
1508 | QueueID); | |
1509 | break; | |
94a79942 | 1510 | } |
94a79942 | 1511 | } |
547d0c34 LF |
1512 | PHY_SetRtl8192eRfOff(dev); |
1513 | break; | |
1514 | ||
1515 | case eRfOff: | |
1516 | RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/" | |
1517 | "Sleep !\n"); | |
1518 | ||
1519 | for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { | |
1520 | ring = &priv->tx_ring[QueueID]; | |
1521 | ||
1522 | if (skb_queue_len(&ring->queue) == 0) { | |
1523 | QueueID++; | |
1524 | continue; | |
1525 | } else { | |
1526 | RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d" | |
1527 | " times TcbBusyQueue[%d] !=0 b" | |
1528 | "efore doze!\n", (i+1), | |
1529 | QueueID); | |
1530 | udelay(10); | |
1531 | i++; | |
94a79942 | 1532 | } |
94a79942 | 1533 | |
547d0c34 LF |
1534 | if (i >= MAX_DOZE_WAITING_TIMES_9x) { |
1535 | RT_TRACE(COMP_POWER, "\n\n\n SetZebra: " | |
1536 | "RFPowerState8185B(): eRfOff:" | |
1537 | " %d times TcbBusyQueue[%d] " | |
1538 | "!= 0 !!!\n", | |
1539 | MAX_DOZE_WAITING_TIMES_9x, | |
1540 | QueueID); | |
94a79942 | 1541 | break; |
547d0c34 LF |
1542 | } |
1543 | } | |
94a79942 | 1544 | |
547d0c34 LF |
1545 | if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && |
1546 | !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { | |
1547 | NicIFDisableNIC(dev); | |
1548 | RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); | |
1549 | } else if (!(pPSC->RegRfPsLevel & | |
1550 | RT_RF_OFF_LEVL_HALT_NIC)) { | |
1551 | PHY_SetRtl8192eRfOff(dev); | |
1552 | } | |
94a79942 | 1553 | |
547d0c34 | 1554 | break; |
94a79942 LF |
1555 | |
1556 | default: | |
547d0c34 | 1557 | bResult = false; |
430fb250 | 1558 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknown state" |
547d0c34 | 1559 | " to set: 0x%X!!!\n", eRFPowerState); |
94a79942 | 1560 | break; |
547d0c34 LF |
1561 | } |
1562 | ||
1563 | break; | |
1564 | ||
1565 | default: | |
1566 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); | |
1567 | break; | |
94a79942 LF |
1568 | } |
1569 | ||
1570 | if (bResult) { | |
1571 | priv->rtllib->eRFPowerState = eRFPowerState; | |
1572 | ||
d064307a LF |
1573 | switch (priv->rf_chip) { |
1574 | case RF_8256: | |
94a79942 LF |
1575 | break; |
1576 | ||
d064307a | 1577 | default: |
547d0c34 LF |
1578 | RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown " |
1579 | "RF type\n"); | |
d064307a | 1580 | break; |
94a79942 LF |
1581 | } |
1582 | } | |
1583 | ||
1584 | priv->SetRFPowerStateInProgress = false; | |
547d0c34 LF |
1585 | RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", |
1586 | bResult); | |
94a79942 LF |
1587 | return bResult; |
1588 | } | |
1589 | ||
547d0c34 LF |
1590 | bool SetRFPowerState(struct net_device *dev, |
1591 | enum rt_rf_power_state eRFPowerState) | |
94a79942 LF |
1592 | { |
1593 | struct r8192_priv *priv = rtllib_priv(dev); | |
1594 | ||
1595 | bool bResult = false; | |
1596 | ||
547d0c34 LF |
1597 | RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n", |
1598 | eRFPowerState); | |
1599 | if (eRFPowerState == priv->rtllib->eRFPowerState && | |
1600 | priv->bHwRfOffAction == 0) { | |
1601 | RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the " | |
1602 | "request for eRFPowerState(%d) is the same.\n", | |
1603 | eRFPowerState); | |
94a79942 LF |
1604 | return bResult; |
1605 | } | |
1606 | ||
1607 | bResult = SetRFPowerState8190(dev, eRFPowerState); | |
1608 | ||
547d0c34 LF |
1609 | RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", |
1610 | bResult); | |
94a79942 LF |
1611 | |
1612 | return bResult; | |
1613 | } | |
94a79942 | 1614 | |
49aab5fd | 1615 | void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation) |
94a79942 LF |
1616 | { |
1617 | struct r8192_priv *priv = rtllib_priv(dev); | |
1618 | ||
1619 | if (priv->up) { | |
1620 | switch (Operation) { | |
547d0c34 LF |
1621 | case SCAN_OPT_BACKUP: |
1622 | priv->rtllib->InitialGainHandler(dev, IG_Backup); | |
1623 | break; | |
94a79942 | 1624 | |
547d0c34 LF |
1625 | case SCAN_OPT_RESTORE: |
1626 | priv->rtllib->InitialGainHandler(dev, IG_Restore); | |
1627 | break; | |
94a79942 | 1628 | |
547d0c34 LF |
1629 | default: |
1630 | RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n"); | |
1631 | break; | |
94a79942 LF |
1632 | } |
1633 | } | |
1634 | ||
1635 | } |