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Staging: rtl8192su: remove unused files
[deliverable/linux.git] / drivers / staging / rtl8192su / r8192U_core.c
CommitLineData
5f53d8ca
JC		 1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 * Linux device driver for RTL8192U
4 *
5 * Based on the r8187 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Jerry chuang <wlanfae@realtek.com>
25 */
26
27#ifndef CONFIG_FORCE_HARD_FLOAT
28double __floatsidf (int i) { return i; }
29unsigned int __fixunsdfsi (double d) { return d; }
30double __adddf3(double a, double b) { return a+b; }
31double __addsf3(float a, float b) { return a+b; }
32double __subdf3(double a, double b) { return a-b; }
33double __extendsfdf2(float a) {return a;}
34#endif
35
36#undef LOOP_TEST
37#undef DUMP_RX
38#undef DUMP_TX
39#undef DEBUG_TX_DESC2
40#undef RX_DONT_PASS_UL
41#undef DEBUG_EPROM
42#undef DEBUG_RX_VERBOSE
43#undef DUMMY_RX
44#undef DEBUG_ZERO_RX
45#undef DEBUG_RX_SKB
46#undef DEBUG_TX_FRAG
47#undef DEBUG_RX_FRAG
48#undef DEBUG_TX_FILLDESC
49#undef DEBUG_TX
50#undef DEBUG_IRQ
51#undef DEBUG_RX
52#undef DEBUG_RXALLOC
53#undef DEBUG_REGISTERS
54#undef DEBUG_RING
55#undef DEBUG_IRQ_TASKLET
56#undef DEBUG_TX_ALLOC
57#undef DEBUG_TX_DESC
58
59#define CONFIG_RTL8192_IO_MAP
60
5f53d8ca
JC		 61#include <asm/uaccess.h>
62#include "r8192U.h"
63//#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */
64#include "r8180_93cx6.h" /* Card EEPROM */
65#include "r8192U_wx.h"
66
67#include "r8192S_rtl8225.h"
68#include "r8192S_hw.h"
69#include "r8192S_phy.h"
70#include "r8192S_phyreg.h"
71#include "r8192S_Efuse.h"
72
73#include "r819xU_cmdpkt.h"
74#include "r8192U_dm.h"
75//#include "r8192xU_phyreg.h"
76#include <linux/usb.h>
5f53d8ca 77
5f53d8ca 78#include "r8192U_pm.h"
5f53d8ca 79
2a7d71ad 80#include "ieee80211/dot11d.h"
5f53d8ca 81
5f53d8ca
JC		 82
83
5f53d8ca
JC		 84u32 rt_global_debug_component = \
85// COMP_TRACE |
86// COMP_DBG |
87// COMP_INIT |
88// COMP_RECV |
89// COMP_SEND |
90// COMP_IO |
91 COMP_POWER |
92// COMP_EPROM |
93 COMP_SWBW |
94 COMP_POWER_TRACKING |
95 COMP_TURBO |
96 COMP_QOS |
97// COMP_RATE |
98// COMP_RM |
99 COMP_DIG |
100// COMP_EFUSE |
101// COMP_CH |
102// COMP_TXAGC |
103 COMP_HIPWR |
104// COMP_HALDM |
105 COMP_SEC |
106 COMP_LED |
107// COMP_RF |
108// COMP_RXDESC |
109 COMP_FIRMWARE |
110 COMP_HT |
111 COMP_AMSDU |
112 COMP_SCAN |
113// COMP_CMD |
114 COMP_DOWN |
115 COMP_RESET |
116 COMP_ERR; //always open err flags on
5f53d8ca
JC		 117
118#define TOTAL_CAM_ENTRY 32
119#define CAM_CONTENT_COUNT 8
120
121static struct usb_device_id rtl8192_usb_id_tbl[] = {
122 /* Realtek */
123 {USB_DEVICE(0x0bda, 0x8192)},
124 {USB_DEVICE(0x0bda, 0x8709)},
125 /* Corega */
126 {USB_DEVICE(0x07aa, 0x0043)},
127 /* Belkin */
128 {USB_DEVICE(0x050d, 0x805E)},
129 /* Sitecom */
130 {USB_DEVICE(0x0df6, 0x0031)},
131 /* EnGenius */
132 {USB_DEVICE(0x1740, 0x9201)},
133 /* Dlink */
134 {USB_DEVICE(0x2001, 0x3301)},
135 /* Zinwell */
136 {USB_DEVICE(0x5a57, 0x0290)},
137 //92SU
138 {USB_DEVICE(0x0bda, 0x8172)},
139 {}
140};
141
142MODULE_LICENSE("GPL");
5f53d8ca 143MODULE_VERSION("V 1.1");
5f53d8ca
JC		 144MODULE_DEVICE_TABLE(usb, rtl8192_usb_id_tbl);
145MODULE_DESCRIPTION("Linux driver for Realtek RTL8192 USB WiFi cards");
146
147static char* ifname = "wlan%d";
148#if 0
149static int hwseqnum = 0;
150static int hwwep = 0;
151#endif
152static int hwwep = 1; //default use hw. set 0 to use software security
153static int channels = 0x3fff;
154
155
156
5f53d8ca
JC		 157module_param(ifname, charp, S_IRUGO|S_IWUSR );
158//module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
159module_param(hwwep,int, S_IRUGO|S_IWUSR);
160module_param(channels,int, S_IRUGO|S_IWUSR);
5f53d8ca
JC		 161
162MODULE_PARM_DESC(ifname," Net interface name, wlan%d=default");
163//MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
164MODULE_PARM_DESC(hwwep," Try to use hardware security support. ");
165MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
166
5f53d8ca
JC		 167static int __devinit rtl8192_usb_probe(struct usb_interface *intf,
168 const struct usb_device_id *id);
169static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf);
5f53d8ca
JC		 170
171static struct usb_driver rtl8192_usb_driver = {
5f53d8ca
JC		 172 .name = RTL819xU_MODULE_NAME, /* Driver name */
173 .id_table = rtl8192_usb_id_tbl, /* PCI_ID table */
174 .probe = rtl8192_usb_probe, /* probe fn */
175 .disconnect = rtl8192_usb_disconnect, /* remove fn */
5f53d8ca
JC		 176 .suspend = rtl8192U_suspend, /* PM suspend fn */
177 .resume = rtl8192U_resume, /* PM resume fn */
5f53d8ca 178 .reset_resume = rtl8192U_resume, /* PM reset resume fn */
5f53d8ca
JC		 179};
180
181
5f53d8ca
JC		 182static void rtl8192SU_read_eeprom_info(struct net_device *dev);
183short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
184void rtl8192SU_rx_nomal(struct sk_buff* skb);
185void rtl8192SU_rx_cmd(struct sk_buff *skb);
186bool rtl8192SU_adapter_start(struct net_device *dev);
187short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
188void rtl8192SU_link_change(struct net_device *dev);
189void InitialGain8192S(struct net_device *dev,u8 Operation);
190void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
191
192struct rtl819x_ops rtl8192su_ops = {
193 .nic_type = NIC_8192SU,
194 .rtl819x_read_eeprom_info = rtl8192SU_read_eeprom_info,
195 .rtl819x_tx = rtl8192SU_tx,
196 .rtl819x_tx_cmd = rtl8192SU_tx_cmd,
197 .rtl819x_rx_nomal = rtl8192SU_rx_nomal,
198 .rtl819x_rx_cmd = rtl8192SU_rx_cmd,
199 .rtl819x_adapter_start = rtl8192SU_adapter_start,
200 .rtl819x_link_change = rtl8192SU_link_change,
201 .rtl819x_initial_gain = InitialGain8192S,
202 .rtl819x_query_rxdesc_status = rtl8192SU_query_rxdesc_status,
203};
5f53d8ca 204
5f53d8ca
JC		 205
206typedef struct _CHANNEL_LIST
207{
208 u8 Channel[32];
209 u8 Len;
210}CHANNEL_LIST, *PCHANNEL_LIST;
211
212static CHANNEL_LIST ChannelPlan[] = {
213 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC
214 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
215 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
216 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Spain. Change to ETSI.
217 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI.
218 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, //MKK //MKK
219 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22},//MKK1
220 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Israel.
221 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // For 11a , TELEC
222 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64}, 22}, //MIC
223 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14} //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
224};
225
226static void rtl819x_set_channel_map(u8 channel_plan, struct r8192_priv* priv)
227{
228 int i, max_chan=-1, min_chan=-1;
229 struct ieee80211_device* ieee = priv->ieee80211;
230 switch (channel_plan)
231 {
232 case COUNTRY_CODE_FCC:
233 case COUNTRY_CODE_IC:
234 case COUNTRY_CODE_ETSI:
235 case COUNTRY_CODE_SPAIN:
236 case COUNTRY_CODE_FRANCE:
237 case COUNTRY_CODE_MKK:
238 case COUNTRY_CODE_MKK1:
239 case COUNTRY_CODE_ISRAEL:
240 case COUNTRY_CODE_TELEC:
241 case COUNTRY_CODE_MIC:
242 {
243 Dot11d_Init(ieee);
244 ieee->bGlobalDomain = false;
245 //acturally 8225 & 8256 rf chip only support B,G,24N mode
246 if ((priv->rf_chip == RF_8225) || (priv->rf_chip == RF_8256) || (priv->rf_chip == RF_6052))
247 {
248 min_chan = 1;
249 max_chan = 14;
250 }
251 else
252 {
253 RT_TRACE(COMP_ERR, "unknown rf chip, can't set channel map in function:%s()\n", __FUNCTION__);
254 }
255 if (ChannelPlan[channel_plan].Len != 0){
256 // Clear old channel map
257 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
258 // Set new channel map
259 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
260 {
261 if (ChannelPlan[channel_plan].Channel[i] < min_chan || ChannelPlan[channel_plan].Channel[i] > max_chan)
262 break;
263 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
264 }
265 }
266 break;
267 }
268 case COUNTRY_CODE_GLOBAL_DOMAIN:
269 {
270 GET_DOT11D_INFO(ieee)->bEnabled = 0;//this flag enabled to follow 11d country IE setting, otherwise, it shall follow global domain settings.
271 Dot11d_Reset(ieee);
272 ieee->bGlobalDomain = true;
273 break;
274 }
275 default:
276 break;
277 }
278 return;
279}
5f53d8ca
JC		 280
281#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
282
5f53d8ca
JC		 283#define rx_hal_is_cck_rate(_pDesc)\
284 ((_pDesc->RxMCS == DESC92S_RATE1M ||\
285 _pDesc->RxMCS == DESC92S_RATE2M ||\
286 _pDesc->RxMCS == DESC92S_RATE5_5M ||\
287 _pDesc->RxMCS == DESC92S_RATE11M) &&\
288 !_pDesc->RxHT)
289
290#define tx_hal_is_cck_rate(_DataRate)\
291 ( _DataRate == MGN_1M ||\
292 _DataRate == MGN_2M ||\
293 _DataRate == MGN_5_5M ||\
294 _DataRate == MGN_11M )
295
5f53d8ca
JC		 296
297
298
299void CamResetAllEntry(struct net_device *dev)
300{
301#if 1
302 u32 ulcommand = 0;
303 //2004/02/11 In static WEP, OID_ADD_KEY or OID_ADD_WEP are set before STA associate to AP.
304 // However, ResetKey is called on OID_802_11_INFRASTRUCTURE_MODE and MlmeAssociateRequest
305 // In this condition, Cam can not be reset because upper layer will not set this static key again.
306 //if(Adapter->EncAlgorithm == WEP_Encryption)
307 // return;
308//debug
309 //DbgPrint("========================================\n");
310 //DbgPrint(" Call ResetAllEntry \n");
311 //DbgPrint("========================================\n\n");
312 ulcommand |= BIT31|BIT30;
313 write_nic_dword(dev, RWCAM, ulcommand);
314#else
315 for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++)
316 CAM_mark_invalid(dev, ucIndex);
317 for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++)
318 CAM_empty_entry(dev, ucIndex);
319#endif
320
321}
322
323
324void write_cam(struct net_device *dev, u8 addr, u32 data)
325{
326 write_nic_dword(dev, WCAMI, data);
327 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) );
328}
329
330u32 read_cam(struct net_device *dev, u8 addr)
331{
332 write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff) );
333 return read_nic_dword(dev, 0xa8);
334}
335
336void write_nic_byte_E(struct net_device *dev, int indx, u8 data)
337{
338 int status;
339 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
340 struct usb_device *udev = priv->udev;
341
342 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
343 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
344 indx|0xfe00, 0, &data, 1, HZ / 2);
345
346 if (status < 0)
347 {
348 printk("write_nic_byte_E TimeOut! status:%d\n", status);
349 }
350}
351
352u8 read_nic_byte_E(struct net_device *dev, int indx)
353{
354 int status;
355 u8 data;
356 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
357 struct usb_device *udev = priv->udev;
358
359 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
360 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
361 indx|0xfe00, 0, &data, 1, HZ / 2);
362
363 if (status < 0)
364 {
365 printk("read_nic_byte_E TimeOut! status:%d\n", status);
366 }
367
368 return data;
369}
370//as 92U has extend page from 4 to 16, so modify functions below.
371void write_nic_byte(struct net_device *dev, int indx, u8 data)
372{
373 int status;
374
375 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
376 struct usb_device *udev = priv->udev;
377
378 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
379 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
5f53d8ca 380 indx, 0, &data, 1, HZ / 2);
5f53d8ca
JC		 381
382 if (status < 0)
383 {
384 printk("write_nic_byte TimeOut! status:%d\n", status);
385 }
386
387
388}
389
390
391void write_nic_word(struct net_device *dev, int indx, u16 data)
392{
393
394 int status;
395
396 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
397 struct usb_device *udev = priv->udev;
398
399 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
400 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
5f53d8ca 401 indx, 0, &data, 2, HZ / 2);
5f53d8ca
JC		 402
403 if (status < 0)
404 {
405 printk("write_nic_word TimeOut! status:%d\n", status);
406 }
407
408}
409
410
411void write_nic_dword(struct net_device *dev, int indx, u32 data)
412{
413
414 int status;
415
416 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
417 struct usb_device *udev = priv->udev;
418
419 status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
420 RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
5f53d8ca 421 indx, 0, &data, 4, HZ / 2);
5f53d8ca
JC		 422
423
424 if (status < 0)
425 {
426 printk("write_nic_dword TimeOut! status:%d\n", status);
427 }
428
429}
430
431
432
433u8 read_nic_byte(struct net_device *dev, int indx)
434{
435 u8 data;
436 int status;
437 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
438 struct usb_device *udev = priv->udev;
439
440 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
441 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
5f53d8ca 442 indx, 0, &data, 1, HZ / 2);
5f53d8ca
JC		 443
444 if (status < 0)
445 {
446 printk("read_nic_byte TimeOut! status:%d\n", status);
447 }
448
449 return data;
450}
451
452
453
454u16 read_nic_word(struct net_device *dev, int indx)
455{
456 u16 data;
457 int status;
458 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
459 struct usb_device *udev = priv->udev;
460
461 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
462 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
5f53d8ca 463 indx, 0, &data, 2, HZ / 2);
5f53d8ca
JC		 464
465 if (status < 0)
466 {
467 printk("read_nic_word TimeOut! status:%d\n", status);
468 }
469
470
471 return data;
472}
473
474u16 read_nic_word_E(struct net_device *dev, int indx)
475{
476 u16 data;
477 int status;
478 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
479 struct usb_device *udev = priv->udev;
480
481 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
482 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
483 indx|0xfe00, 0, &data, 2, HZ / 2);
484
485 if (status < 0)
486 {
487 printk("read_nic_word TimeOut! status:%d\n", status);
488 }
489
490
491 return data;
492}
493
494u32 read_nic_dword(struct net_device *dev, int indx)
495{
496 u32 data;
497 int status;
498// int result;
499
500 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
501 struct usb_device *udev = priv->udev;
502
503 status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
504 RTL8187_REQ_GET_REGS, RTL8187_REQT_READ,
5f53d8ca 505 indx, 0, &data, 4, HZ / 2);
5f53d8ca
JC		 506// if(0 != result) {
507// printk(KERN_WARNING "read size of data = %d\, date = %d\n", result, data);
508// }
509
510 if (status < 0)
511 {
512 printk("read_nic_dword TimeOut! status:%d\n", status);
513 if(status == -ENODEV) {
514 priv->usb_error = true;
515 }
516 }
517
518
519
520 return data;
521}
522
523
524//u8 read_phy_cck(struct net_device *dev, u8 adr);
525//u8 read_phy_ofdm(struct net_device *dev, u8 adr);
526/* this might still called in what was the PHY rtl8185/rtl8192 common code
527 * plans are to possibilty turn it again in one common code...
528 */
529inline void force_pci_posting(struct net_device *dev)
530{
531}
532
533
534static struct net_device_stats *rtl8192_stats(struct net_device *dev);
535void rtl8192_commit(struct net_device *dev);
536//void rtl8192_restart(struct net_device *dev);
5f53d8ca
JC		 537void rtl8192_restart(struct work_struct *work);
538//void rtl8192_rq_tx_ack(struct work_struct *work);
5f53d8ca
JC		 539
540void watch_dog_timer_callback(unsigned long data);
541
542/****************************************************************************
543 -----------------------------PROCFS STUFF-------------------------
544*****************************************************************************/
545
546static struct proc_dir_entry *rtl8192_proc = NULL;
547
548
549
550static int proc_get_stats_ap(char *page, char **start,
551 off_t offset, int count,
552 int *eof, void *data)
553{
554 struct net_device *dev = data;
555 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
556 struct ieee80211_device *ieee = priv->ieee80211;
557 struct ieee80211_network *target;
558
559 int len = 0;
560
561 list_for_each_entry(target, &ieee->network_list, list) {
562
563 len += snprintf(page + len, count - len,
564 "%s ", target->ssid);
565
566 if(target->wpa_ie_len>0 || target->rsn_ie_len>0){
567 len += snprintf(page + len, count - len,
568 "WPA\n");
569 }
570 else{
571 len += snprintf(page + len, count - len,
572 "non_WPA\n");
573 }
574
575 }
576
577 *eof = 1;
578 return len;
579}
580
5f53d8ca
JC		 581static int proc_get_registers(char *page, char **start,
582 off_t offset, int count,
583 int *eof, void *data)
584{
585 struct net_device *dev = data;
586// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
587
588 int len = 0;
589 int i,n,page0,page1,page2;
590
591 int max=0xff;
592 page0 = 0x000;
593 page1 = 0x100;
594 page2 = 0x800;
595
596 /* This dump the current register page */
597 if(!IS_BB_REG_OFFSET_92S(page0)){
598 len += snprintf(page + len, count - len,
599 "\n####################page %x##################\n ", (page0>>8));
600 for(n=0;n<=max;)
601 {
602 len += snprintf(page + len, count - len,
603 "\nD: %2x > ",n);
604 for(i=0;i<16 && n<=max;i++,n++)
605 len += snprintf(page + len, count - len,
606 "%2.2x ",read_nic_byte(dev,(page0|n)));
607 }
608 }else{
609 len += snprintf(page + len, count - len,
610 "\n####################page %x##################\n ", (page0>>8));
611 for(n=0;n<=max;)
612 {
613 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
614 for(i=0;i<4 && n<=max;n+=4,i++)
615 len += snprintf(page + len, count - len,
616 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
617 }
618 }
619 len += snprintf(page + len, count - len,"\n");
620 *eof = 1;
621 return len;
622
623}
624static int proc_get_registers_1(char *page, char **start,
625 off_t offset, int count,
626 int *eof, void *data)
627{
628 struct net_device *dev = data;
629// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
630
631 int len = 0;
632 int i,n,page0;
633
634 int max=0xff;
635 page0 = 0x100;
636
637 /* This dump the current register page */
638 len += snprintf(page + len, count - len,
639 "\n####################page %x##################\n ", (page0>>8));
640 for(n=0;n<=max;)
641 {
642 len += snprintf(page + len, count - len,
643 "\nD: %2x > ",n);
644 for(i=0;i<16 && n<=max;i++,n++)
645 len += snprintf(page + len, count - len,
646 "%2.2x ",read_nic_byte(dev,(page0|n)));
647 }
648 len += snprintf(page + len, count - len,"\n");
649 *eof = 1;
650 return len;
651
652}
653static int proc_get_registers_2(char *page, char **start,
654 off_t offset, int count,
655 int *eof, void *data)
656{
657 struct net_device *dev = data;
658// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
659
660 int len = 0;
661 int i,n,page0;
662
663 int max=0xff;
664 page0 = 0x200;
665
666 /* This dump the current register page */
667 len += snprintf(page + len, count - len,
668 "\n####################page %x##################\n ", (page0>>8));
669 for(n=0;n<=max;)
670 {
671 len += snprintf(page + len, count - len,
672 "\nD: %2x > ",n);
673 for(i=0;i<16 && n<=max;i++,n++)
674 len += snprintf(page + len, count - len,
675 "%2.2x ",read_nic_byte(dev,(page0|n)));
676 }
677 len += snprintf(page + len, count - len,"\n");
678 *eof = 1;
679 return len;
680
681}
682static int proc_get_registers_8(char *page, char **start,
683 off_t offset, int count,
684 int *eof, void *data)
685{
686 struct net_device *dev = data;
687
688 int len = 0;
689 int i,n,page0;
690
691 int max=0xff;
692 page0 = 0x800;
693
694 /* This dump the current register page */
695 len += snprintf(page + len, count - len,
696 "\n####################page %x##################\n ", (page0>>8));
697 for(n=0;n<=max;)
698 {
699 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
700 for(i=0;i<4 && n<=max;n+=4,i++)
701 len += snprintf(page + len, count - len,
702 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
703 }
704 len += snprintf(page + len, count - len,"\n");
705 *eof = 1;
706 return len;
707
708 }
709static int proc_get_registers_9(char *page, char **start,
710 off_t offset, int count,
711 int *eof, void *data)
712{
713 struct net_device *dev = data;
714// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
715
716 int len = 0;
717 int i,n,page0;
718
719 int max=0xff;
720 page0 = 0x900;
721
722 /* This dump the current register page */
723 len += snprintf(page + len, count - len,
724 "\n####################page %x##################\n ", (page0>>8));
725 for(n=0;n<=max;)
726 {
727 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
728 for(i=0;i<4 && n<=max;n+=4,i++)
729 len += snprintf(page + len, count - len,
730 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
731 }
732 len += snprintf(page + len, count - len,"\n");
733 *eof = 1;
734 return len;
735}
736static int proc_get_registers_a(char *page, char **start,
737 off_t offset, int count,
738 int *eof, void *data)
739{
740 struct net_device *dev = data;
741// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
742
743 int len = 0;
744 int i,n,page0;
745
746 int max=0xff;
747 page0 = 0xa00;
748
749 /* This dump the current register page */
750 len += snprintf(page + len, count - len,
751 "\n####################page %x##################\n ", (page0>>8));
752 for(n=0;n<=max;)
753 {
754 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
755 for(i=0;i<4 && n<=max;n+=4,i++)
756 len += snprintf(page + len, count - len,
757 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
758 }
759 len += snprintf(page + len, count - len,"\n");
760 *eof = 1;
761 return len;
762}
763static int proc_get_registers_b(char *page, char **start,
764 off_t offset, int count,
765 int *eof, void *data)
766{
767 struct net_device *dev = data;
768// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
769
770 int len = 0;
771 int i,n,page0;
772
773 int max=0xff;
774 page0 = 0xb00;
775
776 /* This dump the current register page */
777 len += snprintf(page + len, count - len,
778 "\n####################page %x##################\n ", (page0>>8));
779 for(n=0;n<=max;)
780 {
781 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
782 for(i=0;i<4 && n<=max;n+=4,i++)
783 len += snprintf(page + len, count - len,
784 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
785 }
786 len += snprintf(page + len, count - len,"\n");
787 *eof = 1;
788 return len;
789 }
790static int proc_get_registers_c(char *page, char **start,
791 off_t offset, int count,
792 int *eof, void *data)
793{
794 struct net_device *dev = data;
795// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
796
797 int len = 0;
798 int i,n,page0;
799
800 int max=0xff;
801 page0 = 0xc00;
802
803 /* This dump the current register page */
804 len += snprintf(page + len, count - len,
805 "\n####################page %x##################\n ", (page0>>8));
806 for(n=0;n<=max;)
807 {
808 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
809 for(i=0;i<4 && n<=max;n+=4,i++)
810 len += snprintf(page + len, count - len,
811 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
812 }
813 len += snprintf(page + len, count - len,"\n");
814 *eof = 1;
815 return len;
816}
817static int proc_get_registers_d(char *page, char **start,
818 off_t offset, int count,
819 int *eof, void *data)
820{
821 struct net_device *dev = data;
822// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
823
824 int len = 0;
825 int i,n,page0;
826
827 int max=0xff;
828 page0 = 0xd00;
829
830 /* This dump the current register page */
831 len += snprintf(page + len, count - len,
832 "\n####################page %x##################\n ", (page0>>8));
833 for(n=0;n<=max;)
834 {
835 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
836 for(i=0;i<4 && n<=max;n+=4,i++)
837 len += snprintf(page + len, count - len,
838 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
839 }
840 len += snprintf(page + len, count - len,"\n");
841 *eof = 1;
842 return len;
843}
844static int proc_get_registers_e(char *page, char **start,
845 off_t offset, int count,
846 int *eof, void *data)
847{
848 struct net_device *dev = data;
849// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
850
851 int len = 0;
852 int i,n,page0;
853
854 int max=0xff;
855 page0 = 0xe00;
856
857 /* This dump the current register page */
858 len += snprintf(page + len, count - len,
859 "\n####################page %x##################\n ", (page0>>8));
860 for(n=0;n<=max;)
861 {
862 len += snprintf(page + len, count - len, "\nD: %2x > ",n);
863 for(i=0;i<4 && n<=max;n+=4,i++)
864 len += snprintf(page + len, count - len,
865 "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord));
866 }
867 len += snprintf(page + len, count - len,"\n");
868 *eof = 1;
869 return len;
870}
5f53d8ca
JC		 871
872#if 0
873static int proc_get_cck_reg(char *page, char **start,
874 off_t offset, int count,
875 int *eof, void *data)
876{
877 struct net_device *dev = data;
878// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
879
880 int len = 0;
881 int i,n;
882
883 int max = 0x5F;
884
885 /* This dump the current register page */
886 for(n=0;n<=max;)
887 {
888 //printk( "\nD: %2x> ", n);
889 len += snprintf(page + len, count - len,
890 "\nD: %2x > ",n);
891
892 for(i=0;i<16 && n<=max;i++,n++)
893 len += snprintf(page + len, count - len,
894 "%2x ",read_phy_cck(dev,n));
895
896 // printk("%2x ",read_nic_byte(dev,n));
897 }
898 len += snprintf(page + len, count - len,"\n");
899
900
901 *eof = 1;
902 return len;
903}
904
905#endif
906
907#if 0
908static int proc_get_ofdm_reg(char *page, char **start,
909 off_t offset, int count,
910 int *eof, void *data)
911{
912 struct net_device *dev = data;
913// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
914
915 int len = 0;
916 int i,n;
917
918 //int max=0xff;
919 int max = 0x40;
920
921 /* This dump the current register page */
922 for(n=0;n<=max;)
923 {
924 //printk( "\nD: %2x> ", n);
925 len += snprintf(page + len, count - len,
926 "\nD: %2x > ",n);
927
928 for(i=0;i<16 && n<=max;i++,n++)
929 len += snprintf(page + len, count - len,
930 "%2x ",read_phy_ofdm(dev,n));
931
932 // printk("%2x ",read_nic_byte(dev,n));
933 }
934 len += snprintf(page + len, count - len,"\n");
935
936
937
938 *eof = 1;
939 return len;
940}
941
942#endif
943
944#if 0
945static int proc_get_stats_hw(char *page, char **start,
946 off_t offset, int count,
947 int *eof, void *data)
948{
949 struct net_device *dev = data;
950 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
951
952 int len = 0;
953
954 len += snprintf(page + len, count - len,
955 "NIC int: %lu\n"
956 "Total int: %lu\n",
957 priv->stats.ints,
958 priv->stats.shints);
959
960 *eof = 1;
961 return len;
962}
963#endif
964
965static int proc_get_stats_tx(char *page, char **start,
966 off_t offset, int count,
967 int *eof, void *data)
968{
969 struct net_device *dev = data;
970 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
971
972 int len = 0;
973
974 len += snprintf(page + len, count - len,
975 "TX VI priority ok int: %lu\n"
976 "TX VI priority error int: %lu\n"
977 "TX VO priority ok int: %lu\n"
978 "TX VO priority error int: %lu\n"
979 "TX BE priority ok int: %lu\n"
980 "TX BE priority error int: %lu\n"
981 "TX BK priority ok int: %lu\n"
982 "TX BK priority error int: %lu\n"
983 "TX MANAGE priority ok int: %lu\n"
984 "TX MANAGE priority error int: %lu\n"
985 "TX BEACON priority ok int: %lu\n"
986 "TX BEACON priority error int: %lu\n"
987// "TX high priority ok int: %lu\n"
988// "TX high priority failed error int: %lu\n"
989 "TX queue resume: %lu\n"
990 "TX queue stopped?: %d\n"
991 "TX fifo overflow: %lu\n"
992// "TX beacon: %lu\n"
993 "TX VI queue: %d\n"
994 "TX VO queue: %d\n"
995 "TX BE queue: %d\n"
996 "TX BK queue: %d\n"
997// "TX HW queue: %d\n"
998 "TX VI dropped: %lu\n"
999 "TX VO dropped: %lu\n"
1000 "TX BE dropped: %lu\n"
1001 "TX BK dropped: %lu\n"
1002 "TX total data packets %lu\n",
1003// "TX beacon aborted: %lu\n",
1004 priv->stats.txviokint,
1005 priv->stats.txvierr,
1006 priv->stats.txvookint,
1007 priv->stats.txvoerr,
1008 priv->stats.txbeokint,
1009 priv->stats.txbeerr,
1010 priv->stats.txbkokint,
1011 priv->stats.txbkerr,
1012 priv->stats.txmanageokint,
1013 priv->stats.txmanageerr,
1014 priv->stats.txbeaconokint,
1015 priv->stats.txbeaconerr,
1016// priv->stats.txhpokint,
1017// priv->stats.txhperr,
1018 priv->stats.txresumed,
1019 netif_queue_stopped(dev),
1020 priv->stats.txoverflow,
1021// priv->stats.txbeacon,
1022 atomic_read(&(priv->tx_pending[VI_PRIORITY])),
1023 atomic_read(&(priv->tx_pending[VO_PRIORITY])),
1024 atomic_read(&(priv->tx_pending[BE_PRIORITY])),
1025 atomic_read(&(priv->tx_pending[BK_PRIORITY])),
1026// read_nic_byte(dev, TXFIFOCOUNT),
1027 priv->stats.txvidrop,
1028 priv->stats.txvodrop,
1029 priv->stats.txbedrop,
1030 priv->stats.txbkdrop,
1031 priv->stats.txdatapkt
1032// priv->stats.txbeaconerr
1033 );
1034
1035 *eof = 1;
1036 return len;
1037}
1038
1039
1040
1041static int proc_get_stats_rx(char *page, char **start,
1042 off_t offset, int count,
1043 int *eof, void *data)
1044{
1045 struct net_device *dev = data;
1046 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1047
1048 int len = 0;
1049
1050 len += snprintf(page + len, count - len,
1051 "RX packets: %lu\n"
1052 "RX urb status error: %lu\n"
1053 "RX invalid urb error: %lu\n",
1054 priv->stats.rxoktotal,
1055 priv->stats.rxstaterr,
1056 priv->stats.rxurberr);
1057
1058 *eof = 1;
1059 return len;
1060}
5f53d8ca 1061
5f53d8ca
JC		 1062void rtl8192_proc_module_init(void)
1063{
1064 RT_TRACE(COMP_INIT, "Initializing proc filesystem");
5f53d8ca 1065 rtl8192_proc=create_proc_entry(RTL819xU_MODULE_NAME, S_IFDIR, init_net.proc_net);
5f53d8ca
JC		 1066}
1067
1068
1069void rtl8192_proc_module_remove(void)
1070{
5f53d8ca 1071 remove_proc_entry(RTL819xU_MODULE_NAME, init_net.proc_net);
5f53d8ca
JC		 1072}
1073
1074
1075void rtl8192_proc_remove_one(struct net_device *dev)
1076{
1077 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1078
1079
1080 if (priv->dir_dev) {
1081 // remove_proc_entry("stats-hw", priv->dir_dev);
1082 remove_proc_entry("stats-tx", priv->dir_dev);
1083 remove_proc_entry("stats-rx", priv->dir_dev);
1084 // remove_proc_entry("stats-ieee", priv->dir_dev);
1085 remove_proc_entry("stats-ap", priv->dir_dev);
1086 remove_proc_entry("registers", priv->dir_dev);
1087 remove_proc_entry("registers-1", priv->dir_dev);
1088 remove_proc_entry("registers-2", priv->dir_dev);
1089 remove_proc_entry("registers-8", priv->dir_dev);
1090 remove_proc_entry("registers-9", priv->dir_dev);
1091 remove_proc_entry("registers-a", priv->dir_dev);
1092 remove_proc_entry("registers-b", priv->dir_dev);
1093 remove_proc_entry("registers-c", priv->dir_dev);
1094 remove_proc_entry("registers-d", priv->dir_dev);
1095 remove_proc_entry("registers-e", priv->dir_dev);
1096 // remove_proc_entry("cck-registers",priv->dir_dev);
1097 // remove_proc_entry("ofdm-registers",priv->dir_dev);
1098 //remove_proc_entry(dev->name, rtl8192_proc);
1099 remove_proc_entry("wlan0", rtl8192_proc);
1100 priv->dir_dev = NULL;
1101 }
1102}
1103
1104
1105void rtl8192_proc_init_one(struct net_device *dev)
1106{
1107 struct proc_dir_entry *e;
1108 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1109 priv->dir_dev = create_proc_entry(dev->name,
1110 S_IFDIR | S_IRUGO | S_IXUGO,
1111 rtl8192_proc);
1112 if (!priv->dir_dev) {
1113 RT_TRACE(COMP_ERR, "Unable to initialize /proc/net/rtl8192/%s\n",
1114 dev->name);
1115 return;
1116 }
1117 #if 0
1118 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
1119 priv->dir_dev, proc_get_stats_hw, dev);
1120
1121 if (!e) {
1122 DMESGE("Unable to initialize "
1123 "/proc/net/rtl8192/%s/stats-hw\n",
1124 dev->name);
1125 }
1126 #endif
1127 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
1128 priv->dir_dev, proc_get_stats_rx, dev);
1129
1130 if (!e) {
1131 RT_TRACE(COMP_ERR,"Unable to initialize "
1132 "/proc/net/rtl8192/%s/stats-rx\n",
1133 dev->name);
1134 }
1135
1136
1137 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
1138 priv->dir_dev, proc_get_stats_tx, dev);
1139
1140 if (!e) {
1141 RT_TRACE(COMP_ERR, "Unable to initialize "
1142 "/proc/net/rtl8192/%s/stats-tx\n",
1143 dev->name);
1144 }
1145 #if 0
1146 e = create_proc_read_entry("stats-ieee", S_IFREG | S_IRUGO,
1147 priv->dir_dev, proc_get_stats_ieee, dev);
1148
1149 if (!e) {
1150 DMESGE("Unable to initialize "
1151 "/proc/net/rtl8192/%s/stats-ieee\n",
1152 dev->name);
1153 }
1154
1155 #endif
1156
1157 e = create_proc_read_entry("stats-ap", S_IFREG | S_IRUGO,
1158 priv->dir_dev, proc_get_stats_ap, dev);
1159
1160 if (!e) {
1161 RT_TRACE(COMP_ERR, "Unable to initialize "
1162 "/proc/net/rtl8192/%s/stats-ap\n",
1163 dev->name);
1164 }
1165
1166 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
1167 priv->dir_dev, proc_get_registers, dev);
1168 if (!e) {
1169 RT_TRACE(COMP_ERR, "Unable to initialize "
1170 "/proc/net/rtl8192/%s/registers\n",
1171 dev->name);
1172 }
5f53d8ca
JC		 1173 e = create_proc_read_entry("registers-1", S_IFREG | S_IRUGO,
1174 priv->dir_dev, proc_get_registers_1, dev);
1175 if (!e) {
1176 RT_TRACE(COMP_ERR, "Unable to initialize "
1177 "/proc/net/rtl8192/%s/registers-1\n",
1178 dev->name);
1179 }
1180 e = create_proc_read_entry("registers-2", S_IFREG | S_IRUGO,
1181 priv->dir_dev, proc_get_registers_2, dev);
1182 if (!e) {
1183 RT_TRACE(COMP_ERR, "Unable to initialize "
1184 "/proc/net/rtl8192/%s/registers-2\n",
1185 dev->name);
1186 }
1187 e = create_proc_read_entry("registers-8", S_IFREG | S_IRUGO,
1188 priv->dir_dev, proc_get_registers_8, dev);
1189 if (!e) {
1190 RT_TRACE(COMP_ERR, "Unable to initialize "
1191 "/proc/net/rtl8192/%s/registers-8\n",
1192 dev->name);
1193 }
1194 e = create_proc_read_entry("registers-9", S_IFREG | S_IRUGO,
1195 priv->dir_dev, proc_get_registers_9, dev);
1196 if (!e) {
1197 RT_TRACE(COMP_ERR, "Unable to initialize "
1198 "/proc/net/rtl8192/%s/registers-9\n",
1199 dev->name);
1200 }
1201 e = create_proc_read_entry("registers-a", S_IFREG | S_IRUGO,
1202 priv->dir_dev, proc_get_registers_a, dev);
1203 if (!e) {
1204 RT_TRACE(COMP_ERR, "Unable to initialize "
1205 "/proc/net/rtl8192/%s/registers-a\n",
1206 dev->name);
1207 }
1208 e = create_proc_read_entry("registers-b", S_IFREG | S_IRUGO,
1209 priv->dir_dev, proc_get_registers_b, dev);
1210 if (!e) {
1211 RT_TRACE(COMP_ERR, "Unable to initialize "
1212 "/proc/net/rtl8192/%s/registers-b\n",
1213 dev->name);
1214 }
1215 e = create_proc_read_entry("registers-c", S_IFREG | S_IRUGO,
1216 priv->dir_dev, proc_get_registers_c, dev);
1217 if (!e) {
1218 RT_TRACE(COMP_ERR, "Unable to initialize "
1219 "/proc/net/rtl8192/%s/registers-c\n",
1220 dev->name);
1221 }
1222 e = create_proc_read_entry("registers-d", S_IFREG | S_IRUGO,
1223 priv->dir_dev, proc_get_registers_d, dev);
1224 if (!e) {
1225 RT_TRACE(COMP_ERR, "Unable to initialize "
1226 "/proc/net/rtl8192/%s/registers-d\n",
1227 dev->name);
1228 }
1229 e = create_proc_read_entry("registers-e", S_IFREG | S_IRUGO,
1230 priv->dir_dev, proc_get_registers_e, dev);
1231 if (!e) {
1232 RT_TRACE(COMP_ERR, "Unable to initialize "
1233 "/proc/net/rtl8192/%s/registers-e\n",
1234 dev->name);
1235 }
5f53d8ca
JC		 1236#if 0
1237 e = create_proc_read_entry("cck-registers", S_IFREG | S_IRUGO,
1238 priv->dir_dev, proc_get_cck_reg, dev);
1239 if (!e) {
1240 RT_TRACE(COMP_ERR, "Unable to initialize "
1241 "/proc/net/rtl8192/%s/cck-registers\n",
1242 dev->name);
1243 }
1244
1245 e = create_proc_read_entry("ofdm-registers", S_IFREG | S_IRUGO,
1246 priv->dir_dev, proc_get_ofdm_reg, dev);
1247 if (!e) {
1248 RT_TRACE(COMP_ERR, "Unable to initialize "
1249 "/proc/net/rtl8192/%s/ofdm-registers\n",
1250 dev->name);
1251 }
1252#endif
1253}
1254/****************************************************************************
1255 -----------------------------MISC STUFF-------------------------
1256*****************************************************************************/
1257
1258/* this is only for debugging */
1259void print_buffer(u32 *buffer, int len)
1260{
1261 int i;
1262 u8 *buf =(u8*)buffer;
1263
1264 printk("ASCII BUFFER DUMP (len: %x):\n",len);
1265
1266 for(i=0;i<len;i++)
1267 printk("%c",buf[i]);
1268
1269 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
1270
1271 for(i=0;i<len;i++)
1272 printk("%x",buf[i]);
1273
1274 printk("\n");
1275}
1276
1277//short check_nic_enough_desc(struct net_device *dev, priority_t priority)
1278short check_nic_enough_desc(struct net_device *dev,int queue_index)
1279{
1280 struct r8192_priv *priv = ieee80211_priv(dev);
1281 int used = atomic_read(&priv->tx_pending[queue_index]);
1282
1283 return (used < MAX_TX_URB);
1284}
1285
1286void tx_timeout(struct net_device *dev)
1287{
1288 struct r8192_priv *priv = ieee80211_priv(dev);
1289 //rtl8192_commit(dev);
1290
5f53d8ca 1291 schedule_work(&priv->reset_wq);
5f53d8ca
JC		 1292 //DMESG("TXTIMEOUT");
1293}
1294
1295
1296/* this is only for debug */
1297void dump_eprom(struct net_device *dev)
1298{
1299 int i;
1300 for(i=0; i<63; i++)
1301 RT_TRACE(COMP_EPROM, "EEPROM addr %x : %x", i, eprom_read(dev,i));
1302}
1303
1304/* this is only for debug */
1305void rtl8192_dump_reg(struct net_device *dev)
1306{
1307 int i;
1308 int n;
1309 int max=0x1ff;
1310
1311 RT_TRACE(COMP_PHY, "Dumping NIC register map");
1312
1313 for(n=0;n<=max;)
1314 {
1315 printk( "\nD: %2x> ", n);
1316 for(i=0;i<16 && n<=max;i++,n++)
1317 printk("%2x ",read_nic_byte(dev,n));
1318 }
1319 printk("\n");
1320}
1321
1322/****************************************************************************
1323 ------------------------------HW STUFF---------------------------
1324*****************************************************************************/
1325
1326#if 0
1327void rtl8192_irq_enable(struct net_device *dev)
1328{
1329 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1330 //priv->irq_enabled = 1;
1331/*
1332 write_nic_word(dev,INTA_MASK,INTA_RXOK | INTA_RXDESCERR | INTA_RXOVERFLOW |\
1333 INTA_TXOVERFLOW | INTA_HIPRIORITYDESCERR | INTA_HIPRIORITYDESCOK |\
1334 INTA_NORMPRIORITYDESCERR | INTA_NORMPRIORITYDESCOK |\
1335 INTA_LOWPRIORITYDESCERR | INTA_LOWPRIORITYDESCOK | INTA_TIMEOUT);
1336*/
1337 write_nic_word(dev,INTA_MASK, priv->irq_mask);
1338}
1339
1340
1341void rtl8192_irq_disable(struct net_device *dev)
1342{
1343// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1344
1345 write_nic_word(dev,INTA_MASK,0);
1346 force_pci_posting(dev);
1347// priv->irq_enabled = 0;
1348}
1349#endif
1350
1351void rtl8192_set_mode(struct net_device *dev,int mode)
1352{
1353 u8 ecmd;
1354 ecmd=read_nic_byte(dev, EPROM_CMD);
1355 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
1356 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
1357 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
1358 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
1359 write_nic_byte(dev, EPROM_CMD, ecmd);
1360}
1361
1362
1363void rtl8192_update_msr(struct net_device *dev)
1364{
1365 struct r8192_priv *priv = ieee80211_priv(dev);
1366 u8 msr;
1367
1368 msr = read_nic_byte(dev, MSR);
1369 msr &= ~ MSR_LINK_MASK;
1370
1371 /* do not change in link_state != WLAN_LINK_ASSOCIATED.
1372 * msr must be updated if the state is ASSOCIATING.
1373 * this is intentional and make sense for ad-hoc and
1374 * master (see the create BSS/IBSS func)
1375 */
1376 if (priv->ieee80211->state == IEEE80211_LINKED){
1377
1378 if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
1379 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
1380 else if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1381 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
1382 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
1383 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
1384
1385 }else
1386 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
1387
1388 write_nic_byte(dev, MSR, msr);
1389}
1390
1391void rtl8192_set_chan(struct net_device *dev,short ch)
1392{
1393 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1394// u32 tx;
1395 RT_TRACE(COMP_CH, "=====>%s()====ch:%d\n", __FUNCTION__, ch);
1396 //printk("=====>%s()====ch:%d\n", __FUNCTION__, ch);
1397 priv->chan=ch;
1398 #if 0
1399 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC ||
1400 priv->ieee80211->iw_mode == IW_MODE_MASTER){
1401
1402 priv->ieee80211->link_state = WLAN_LINK_ASSOCIATED;
1403 priv->ieee80211->master_chan = ch;
1404 rtl8192_update_beacon_ch(dev);
1405 }
1406 #endif
1407
1408 /* this hack should avoid frame TX during channel setting*/
1409
1410
1411// tx = read_nic_dword(dev,TX_CONF);
1412// tx &= ~TX_LOOPBACK_MASK;
1413
1414#ifndef LOOP_TEST
1415// write_nic_dword(dev,TX_CONF, tx |( TX_LOOPBACK_MAC<<TX_LOOPBACK_SHIFT));
1416
1417 //need to implement rf set channel here WB
1418
1419 if (priv->rf_set_chan)
1420 priv->rf_set_chan(dev,priv->chan);
1421 mdelay(10);
1422// write_nic_dword(dev,TX_CONF,tx | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT));
1423#endif
1424}
1425
5f53d8ca 1426static void rtl8192_rx_isr(struct urb *urb);
5f53d8ca
JC		 1427
1428u32 get_rxpacket_shiftbytes_819xusb(struct ieee80211_rx_stats *pstats)
1429{
1430
5f53d8ca
JC		 1431 return (sizeof(rx_desc_819x_usb) + pstats->RxDrvInfoSize
1432 + pstats->RxBufShift);
1433
1434}
1435static int rtl8192_rx_initiate(struct net_device*dev)
1436{
1437 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1438 struct urb *entry;
1439 struct sk_buff *skb;
1440 struct rtl8192_rx_info *info;
1441
1442 /* nomal packet rx procedure */
1443 while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB) {
1444 skb = __dev_alloc_skb(RX_URB_SIZE, GFP_KERNEL);
1445 if (!skb)
1446 break;
5f53d8ca 1447 entry = usb_alloc_urb(0, GFP_KERNEL);
5f53d8ca
JC		 1448 if (!entry) {
1449 kfree_skb(skb);
1450 break;
1451 }
1452// printk("nomal packet IN request!\n");
1453 usb_fill_bulk_urb(entry, priv->udev,
1454 usb_rcvbulkpipe(priv->udev, 3), skb->tail,
1455 RX_URB_SIZE, rtl8192_rx_isr, skb);
1456 info = (struct rtl8192_rx_info *) skb->cb;
1457 info->urb = entry;
1458 info->dev = dev;
1459 info->out_pipe = 3; //denote rx normal packet queue
1460 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 1461 usb_submit_urb(entry, GFP_KERNEL);
5f53d8ca
JC		 1462 }
1463
1464 /* command packet rx procedure */
1465 while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB + 3) {
1466// printk("command packet IN request!\n");
1467 skb = __dev_alloc_skb(RX_URB_SIZE ,GFP_KERNEL);
1468 if (!skb)
1469 break;
5f53d8ca 1470 entry = usb_alloc_urb(0, GFP_KERNEL);
5f53d8ca
JC		 1471 if (!entry) {
1472 kfree_skb(skb);
1473 break;
1474 }
1475 usb_fill_bulk_urb(entry, priv->udev,
1476 usb_rcvbulkpipe(priv->udev, 9), skb->tail,
1477 RX_URB_SIZE, rtl8192_rx_isr, skb);
1478 info = (struct rtl8192_rx_info *) skb->cb;
1479 info->urb = entry;
1480 info->dev = dev;
1481 info->out_pipe = 9; //denote rx cmd packet queue
1482 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 1483 usb_submit_urb(entry, GFP_KERNEL);
5f53d8ca
JC		 1484 }
1485
1486 return 0;
1487}
1488
1489void rtl8192_set_rxconf(struct net_device *dev)
1490{
1491 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1492 u32 rxconf;
1493
1494 rxconf=read_nic_dword(dev,RCR);
1495 rxconf = rxconf &~ MAC_FILTER_MASK;
1496 rxconf = rxconf | RCR_AMF;
1497 rxconf = rxconf | RCR_ADF;
1498 rxconf = rxconf | RCR_AB;
1499 rxconf = rxconf | RCR_AM;
1500 //rxconf = rxconf | RCR_ACF;
1501
1502 if (dev->flags & IFF_PROMISC) {DMESG ("NIC in promisc mode");}
1503
1504 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1505 dev->flags & IFF_PROMISC){
1506 rxconf = rxconf | RCR_AAP;
1507 } /*else if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
1508 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
1509 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
1510 }*/else{
1511 rxconf = rxconf | RCR_APM;
1512 rxconf = rxconf | RCR_CBSSID;
1513 }
1514
1515
1516 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1517 rxconf = rxconf | RCR_AICV;
1518 rxconf = rxconf | RCR_APWRMGT;
1519 }
1520
1521 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1522 rxconf = rxconf | RCR_ACRC32;
1523
1524
1525 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
1526 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
1527 rxconf = rxconf &~ MAX_RX_DMA_MASK;
1528 rxconf = rxconf | ((u32)7<<RCR_MXDMA_OFFSET);
1529
1530// rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
1531 rxconf = rxconf | RCR_ONLYERLPKT;
1532
1533// rxconf = rxconf &~ RCR_CS_MASK;
1534// rxconf = rxconf | (1<<RCR_CS_SHIFT);
1535
1536 write_nic_dword(dev, RCR, rxconf);
1537
1538 #ifdef DEBUG_RX
1539 DMESG("rxconf: %x %x",rxconf ,read_nic_dword(dev,RCR));
1540 #endif
1541}
1542//wait to be removed
1543void rtl8192_rx_enable(struct net_device *dev)
1544{
1545 //u8 cmd;
1546
1547 //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1548
1549 rtl8192_rx_initiate(dev);
1550
1551// rtl8192_set_rxconf(dev);
1552#if 0
1553 if(NIC_8187 == priv->card_8187) {
1554 cmd=read_nic_byte(dev,CMD);
1555 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
1556 }
1557 else {
1558 //write_nic_dword(dev, RX_CONF, priv->ReceiveConfig);
1559 }
1560#endif
1561}
1562
1563
1564void rtl8192_tx_enable(struct net_device *dev)
1565{
1566#if 0
1567 u8 cmd;
1568 u8 byte;
1569 u32 txconf;
1570 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1571 //test loopback
1572 // priv->TransmitConfig |= (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT);
1573 if(NIC_8187B == priv->card_8187){
1574 write_nic_dword(dev, TX_CONF, priv->TransmitConfig);
1575 byte = read_nic_byte(dev, MSR);
1576 byte |= MSR_LINK_ENEDCA;
1577 write_nic_byte(dev, MSR, byte);
1578 } else {
1579 byte = read_nic_byte(dev,CW_CONF);
1580 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
1581 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
1582 write_nic_byte(dev, CW_CONF, byte);
1583
1584 byte = read_nic_byte(dev, TX_AGC_CTL);
1585 byte &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
1586 byte &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
1587 byte &= ~(1<<TX_AGC_CTL_FEEDBACK_ANT);
1588 write_nic_byte(dev, TX_AGC_CTL, byte);
1589
1590 txconf= read_nic_dword(dev,TX_CONF);
1591
1592
1593 txconf = txconf &~ TX_LOOPBACK_MASK;
1594
1595#ifndef LOOP_TEST
1596 txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT);
1597#else
1598 txconf = txconf | (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT);
1599#endif
1600 txconf = txconf &~ TCR_SRL_MASK;
1601 txconf = txconf &~ TCR_LRL_MASK;
1602
1603 txconf = txconf | (priv->retry_data<<TX_LRLRETRY_SHIFT); // long
1604 txconf = txconf | (priv->retry_rts<<TX_SRLRETRY_SHIFT); // short
1605
1606 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
1607
1608 txconf = txconf &~ TCR_MXDMA_MASK;
1609 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
1610
1611 txconf = txconf | TCR_DISReqQsize;
1612 txconf = txconf | TCR_DISCW;
1613 txconf = txconf &~ TCR_SWPLCPLEN;
1614
1615 txconf=txconf | (1<<TX_NOICV_SHIFT);
1616
1617 write_nic_dword(dev,TX_CONF,txconf);
1618
1619#ifdef DEBUG_TX
1620 DMESG("txconf: %x %x",txconf,read_nic_dword(dev,TX_CONF));
1621#endif
1622
1623 cmd=read_nic_byte(dev,CMD);
1624 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
1625 }
1626#endif
1627}
1628
1629#if 0
1630void rtl8192_beacon_tx_enable(struct net_device *dev)
1631{
1632 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1633 priv->dma_poll_mask &=~(1<<TX_DMA_STOP_BEACON_SHIFT);
1634 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1635 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1636 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1637}
1638
1639
1640void rtl8192_
1641_disable(struct net_device *dev)
1642{
1643 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1644 priv->dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT);
1645 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1646 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1647 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1648}
1649
1650#endif
1651
1652
1653void rtl8192_rtx_disable(struct net_device *dev)
1654{
1655 u8 cmd;
1656 struct r8192_priv *priv = ieee80211_priv(dev);
1657 struct sk_buff *skb;
1658 struct rtl8192_rx_info *info;
1659
1660 cmd=read_nic_byte(dev,CMDR);
1661 write_nic_byte(dev, CMDR, cmd &~ \
1662 (CR_TE|CR_RE));
1663 force_pci_posting(dev);
1664 mdelay(10);
1665
1666 while ((skb = __skb_dequeue(&priv->rx_queue))) {
1667 info = (struct rtl8192_rx_info *) skb->cb;
1668 if (!info->urb)
1669 continue;
1670
1671 usb_kill_urb(info->urb);
1672 kfree_skb(skb);
1673 }
1674
1675 if (skb_queue_len(&priv->skb_queue)) {
1676 printk(KERN_WARNING "skb_queue not empty\n");
1677 }
1678
1679 skb_queue_purge(&priv->skb_queue);
1680 return;
1681}
1682
1683
1684int alloc_tx_beacon_desc_ring(struct net_device *dev, int count)
1685{
1686 #if 0
1687 int i;
1688 u32 *tmp;
1689 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1690
1691 priv->txbeaconring = (u32*)pci_alloc_consistent(priv->pdev,
1692 sizeof(u32)*8*count,
1693 &priv->txbeaconringdma);
1694 if (!priv->txbeaconring) return -1;
1695 for (tmp=priv->txbeaconring,i=0;i<count;i++){
1696 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1697 /*
1698 *(tmp+2) = (u32)dma_tmp;
1699 *(tmp+3) = bufsize;
1700 */
1701 if(i+1<count)
1702 *(tmp+4) = (u32)priv->txbeaconringdma+((i+1)*8*4);
1703 else
1704 *(tmp+4) = (u32)priv->txbeaconringdma;
1705
1706 tmp=tmp+8;
1707 }
1708 #endif
1709 return 0;
1710}
1711
1712#if 0
1713void rtl8192_reset(struct net_device *dev)
1714{
1715
1716 //struct r8192_priv *priv = ieee80211_priv(dev);
1717 //u8 cr;
1718
1719
1720 /* make sure the analog power is on before
1721 * reset, otherwise reset may fail
1722 */
1723#if 0
1724 if(NIC_8187 == priv->card_8187) {
1725 rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1726 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1727 rtl8192_irq_disable(dev);
1728 mdelay(200);
1729 write_nic_byte_E(dev,0x18,0x10);
1730 write_nic_byte_E(dev,0x18,0x11);
1731 write_nic_byte_E(dev,0x18,0x00);
1732 mdelay(200);
1733 }
1734#endif
1735 printk("=====>reset?\n");
1736#if 0
1737 cr=read_nic_byte(dev,CMD);
1738 cr = cr & 2;
1739 cr = cr | (1<<CMD_RST_SHIFT);
1740 write_nic_byte(dev,CMD,cr);
1741
1742 force_pci_posting(dev);
1743
1744 mdelay(200);
1745
1746 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
1747 RT_TRACE(COMP_ERR, "Card reset timeout!\n");
1748 else
1749 RT_TRACE(COMP_DOWN, "Card successfully reset\n");
1750#endif
1751#if 0
1752 if(NIC_8187 == priv->card_8187) {
1753
1754 printk("This is RTL8187 Reset procedure\n");
1755 rtl8192_set_mode(dev,EPROM_CMD_LOAD);
1756 force_pci_posting(dev);
1757 mdelay(200);
1758
1759 /* after the eeprom load cycle, make sure we have
1760 * correct anaparams
1761 */
1762 rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1763 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1764 }
1765 else
1766#endif
1767 printk("This is RTL8187B Reset procedure\n");
1768
1769}
1770#endif
1771inline u16 ieeerate2rtlrate(int rate)
1772{
1773 switch(rate){
1774 case 10:
1775 return 0;
1776 case 20:
1777 return 1;
1778 case 55:
1779 return 2;
1780 case 110:
1781 return 3;
1782 case 60:
1783 return 4;
1784 case 90:
1785 return 5;
1786 case 120:
1787 return 6;
1788 case 180:
1789 return 7;
1790 case 240:
1791 return 8;
1792 case 360:
1793 return 9;
1794 case 480:
1795 return 10;
1796 case 540:
1797 return 11;
1798 default:
1799 return 3;
1800
1801 }
1802}
1803static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540};
1804inline u16 rtl8192_rate2rate(short rate)
1805{
1806 if (rate >11) return 0;
1807 return rtl_rate[rate];
1808}
1809
5f53d8ca 1810static void rtl8192_rx_isr(struct urb *urb)
5f53d8ca
JC		 1811{
1812 struct sk_buff *skb = (struct sk_buff *) urb->context;
1813 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
1814 struct net_device *dev = info->dev;
1815 struct r8192_priv *priv = ieee80211_priv(dev);
1816 int out_pipe = info->out_pipe;
1817 int err;
1818 if(!priv->up)
1819 return;
1820 if (unlikely(urb->status)) {
1821 info->urb = NULL;
1822 priv->stats.rxstaterr++;
1823 priv->ieee80211->stats.rx_errors++;
1824 usb_free_urb(urb);
1825 // printk("%s():rx status err\n",__FUNCTION__);
1826 return;
1827 }
1ec9e48d 1828
5f53d8ca 1829 skb_unlink(skb, &priv->rx_queue);
5f53d8ca
JC		 1830 skb_put(skb, urb->actual_length);
1831
1832 skb_queue_tail(&priv->skb_queue, skb);
1833 tasklet_schedule(&priv->irq_rx_tasklet);
1834
1835 skb = dev_alloc_skb(RX_URB_SIZE);
1836 if (unlikely(!skb)) {
1837 usb_free_urb(urb);
1838 printk("%s():can,t alloc skb\n",__FUNCTION__);
1839 /* TODO check rx queue length and refill *somewhere* */
1840 return;
1841 }
1842
1843 usb_fill_bulk_urb(urb, priv->udev,
1844 usb_rcvbulkpipe(priv->udev, out_pipe), skb->tail,
1845 RX_URB_SIZE, rtl8192_rx_isr, skb);
1846
1847 info = (struct rtl8192_rx_info *) skb->cb;
1848 info->urb = urb;
1849 info->dev = dev;
1850 info->out_pipe = out_pipe;
1851
1852 urb->transfer_buffer = skb->tail;
1853 urb->context = skb;
1854 skb_queue_tail(&priv->rx_queue, skb);
5f53d8ca 1855 err = usb_submit_urb(urb, GFP_ATOMIC);
5f53d8ca
JC		 1856 if(err && err != EPERM)
1857 printk("can not submit rxurb, err is %x,URB status is %x\n",err,urb->status);
1858}
1859
1860u32
1861rtl819xusb_rx_command_packet(
1862 struct net_device *dev,
1863 struct ieee80211_rx_stats *pstats
1864 )
1865{
1866 u32 status;
1867
1868 //RT_TRACE(COMP_RECV, DBG_TRACE, ("---> RxCommandPacketHandle819xUsb()\n"));
1869
1870 status = cmpk_message_handle_rx(dev, pstats);
1871 if (status)
1872 {
1873 DMESG("rxcommandpackethandle819xusb: It is a command packet\n");
1874 }
1875 else
1876 {
1877 //RT_TRACE(COMP_RECV, DBG_TRACE, ("RxCommandPacketHandle819xUsb: It is not a command packet\n"));
1878 }
1879
1880 //RT_TRACE(COMP_RECV, DBG_TRACE, ("<--- RxCommandPacketHandle819xUsb()\n"));
1881 return status;
1882}
1883
1884#if 0
1885void rtl8192_tx_queues_stop(struct net_device *dev)
1886{
1887 //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1888 u8 dma_poll_mask = (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
1889 dma_poll_mask |= (1<<TX_DMA_STOP_HIPRIORITY_SHIFT);
1890 dma_poll_mask |= (1<<TX_DMA_STOP_NORMPRIORITY_SHIFT);
1891 dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT);
1892
1893 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1894 write_nic_byte(dev,TX_DMA_POLLING,dma_poll_mask);
1895 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1896}
1897#endif
1898
1899void rtl8192_data_hard_stop(struct net_device *dev)
1900{
1901 //FIXME !!
1902 #if 0
1903 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1904 priv->dma_poll_mask |= (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
1905 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1906 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1907 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1908 #endif
1909}
1910
1911
1912void rtl8192_data_hard_resume(struct net_device *dev)
1913{
1914 // FIXME !!
1915 #if 0
1916 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1917 priv->dma_poll_mask &= ~(1<<TX_DMA_STOP_LOWPRIORITY_SHIFT);
1918 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
1919 write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask);
1920 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
1921 #endif
1922}
1923
1924/* this function TX data frames when the ieee80211 stack requires this.
1925 * It checks also if we need to stop the ieee tx queue, eventually do it
1926 */
1927void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int rate)
1928{
1929 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1930 int ret;
1931 unsigned long flags;
1932 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
1933 u8 queue_index = tcb_desc->queue_index;
1934
1935 /* shall not be referred by command packet */
1936 assert(queue_index != TXCMD_QUEUE);
1937
1938 spin_lock_irqsave(&priv->tx_lock,flags);
1939
1940 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
1941// tcb_desc->RATRIndex = 7;
1942// tcb_desc->bTxDisableRateFallBack = 1;
1943// tcb_desc->bTxUseDriverAssingedRate = 1;
1944 tcb_desc->bTxEnableFwCalcDur = 1;
1945 skb_push(skb, priv->ieee80211->tx_headroom);
1946 ret = priv->ops->rtl819x_tx(dev, skb);
1947
1948 //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom);
1949 //priv->ieee80211->stats.tx_packets++;
1950
1951 spin_unlock_irqrestore(&priv->tx_lock,flags);
1952
1953// return ret;
1954 return;
1955}
1956
1957/* This is a rough attempt to TX a frame
1958 * This is called by the ieee 80211 stack to TX management frames.
1959 * If the ring is full packet are dropped (for data frame the queue
1960 * is stopped before this can happen).
1961 */
1962int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
1963{
1964 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
1965 int ret;
1966 unsigned long flags;
1967 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
1968 u8 queue_index = tcb_desc->queue_index;
1969
1970
1971 spin_lock_irqsave(&priv->tx_lock,flags);
1972
1973 memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
1974 if(queue_index == TXCMD_QUEUE) {
1975 skb_push(skb, USB_HWDESC_HEADER_LEN);
1976 priv->ops->rtl819x_tx_cmd(dev, skb);
1977 ret = 1;
1978 spin_unlock_irqrestore(&priv->tx_lock,flags);
1979 return ret;
1980 } else {
1981 skb_push(skb, priv->ieee80211->tx_headroom);
1982 ret = priv->ops->rtl819x_tx(dev, skb);
1983 }
1984
1985 spin_unlock_irqrestore(&priv->tx_lock,flags);
1986
1987 return ret;
1988}
1989
1990
1991void rtl8192_try_wake_queue(struct net_device *dev, int pri);
1992
5f53d8ca 1993
5f53d8ca 1994static void rtl8192_tx_isr(struct urb *tx_urb)
5f53d8ca
JC		 1995{
1996 struct sk_buff *skb = (struct sk_buff*)tx_urb->context;
1997 struct net_device *dev = NULL;
1998 struct r8192_priv *priv = NULL;
1999 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2000 u8 queue_index = tcb_desc->queue_index;
2001// bool bToSend0Byte;
2002// u16 BufLen = skb->len;
2003
2004 memcpy(&dev,(struct net_device*)(skb->cb),sizeof(struct net_device*));
2005 priv = ieee80211_priv(dev);
2006
2007 if(tcb_desc->queue_index != TXCMD_QUEUE) {
2008 if(tx_urb->status == 0) {
2009 // dev->trans_start = jiffies;
2010 // As act as station mode, destion shall be unicast address.
2011 //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom);
2012 //priv->ieee80211->stats.tx_packets++;
2013 priv->stats.txoktotal++;
2014 priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++;
2015 priv->stats.txbytesunicast += (skb->len - priv->ieee80211->tx_headroom);
2016 } else {
2017 priv->ieee80211->stats.tx_errors++;
2018 //priv->stats.txmanageerr++;
2019 /* TODO */
2020 }
2021 }
2022
2023 /* free skb and tx_urb */
2024 if(skb != NULL) {
2025 dev_kfree_skb_any(skb);
2026 usb_free_urb(tx_urb);
2027 atomic_dec(&priv->tx_pending[queue_index]);
2028 }
2029
2030#if 0 //we need to send zero byte packet just after 512 byte(64 byte)packet is transmitted, or we will halt. It will greatly reduced available page in FW, and ruin our throughput. WB 2008.08.27
2031 if(BufLen > 0 && ((BufLen % 512 == 0)||(BufLen % 64 == 0))) {
2032 bToSend0Byte = true;
2033 }
2034
2035 bToSend0Byte = false;
2036 //
2037 // Note that, we at most handle 1 MPDU to send here, either
2038 // fragment or MPDU in wait queue.
2039 //
2040 if(!bToSend0Byte)
2041#endif
2042 {
2043 //
2044 // Handle HW Beacon:
2045 // We had transfer our beacon frame to host controler at this moment.
2046 //
2047#if 0
2048 if(tcb_desc->tx_queue == BEACON_QUEUE)
2049 {
2050 priv->bSendingBeacon = FALSE;
2051 }
2052#endif
2053 //
2054 // Caution:
2055 // Handling the wait queue of command packets.
2056 // For Tx command packets, we must not do TCB fragment because it is not handled right now.
2057 // We must cut the packets to match the size of TX_CMD_PKT before we send it.
2058 //
2059 if (queue_index == MGNT_QUEUE){
2060 if (priv->ieee80211->ack_tx_to_ieee){
2061 if (rtl8192_is_tx_queue_empty(dev)){
2062 priv->ieee80211->ack_tx_to_ieee = 0;
2063 ieee80211_ps_tx_ack(priv->ieee80211, 1);
2064 }
2065 }
2066 }
2067 /* Handle MPDU in wait queue. */
2068 if(queue_index != BEACON_QUEUE) {
2069 /* Don't send data frame during scanning.*/
2070 if((skb_queue_len(&priv->ieee80211->skb_waitQ[queue_index]) != 0)&&\
2071 (!(priv->ieee80211->queue_stop))) {
2072 if(NULL != (skb = skb_dequeue(&(priv->ieee80211->skb_waitQ[queue_index]))))
2073 priv->ieee80211->softmac_hard_start_xmit(skb, dev);
2074
2075 return; //modified by david to avoid further processing AMSDU
2076 }
5f53d8ca
JC		 2077 }
2078 }
2079
2080#if 0
2081 else
2082 {
2083 RT_TRACE( COMP_SEND,"HalUsbOutComplete(%d): bToSend0Byte.\n", PipeIndex);
2084
2085 //
2086 // In this case, we don't return skb now.
2087 // It will be returned when the 0-byte request completed.
2088 //
2089
2090 //
2091 // Bulk out an 0-byte padding transfer.
2092 //
2093 HalUsbOut0Byte(pAdapter, PipeIndex, skb);
2094 }
2095
2096#endif
2097}
2098
2099void rtl8192_beacon_stop(struct net_device *dev)
2100{
2101 u8 msr, msrm, msr2;
2102 struct r8192_priv *priv = ieee80211_priv(dev);
2103
2104 msr = read_nic_byte(dev, MSR);
2105 msrm = msr & MSR_LINK_MASK;
2106 msr2 = msr & ~MSR_LINK_MASK;
2107
2108 if(NIC_8192U == priv->card_8192) {
2109 usb_kill_urb(priv->rx_urb[MAX_RX_URB]);
2110 }
2111 if ((msrm == (MSR_LINK_ADHOC<<MSR_LINK_SHIFT) ||
2112 (msrm == (MSR_LINK_MASTER<<MSR_LINK_SHIFT)))){
2113 write_nic_byte(dev, MSR, msr2 | MSR_LINK_NONE);
2114 write_nic_byte(dev, MSR, msr);
2115 }
2116}
2117
2118void rtl8192_config_rate(struct net_device* dev, u16* rate_config)
2119{
2120 struct r8192_priv *priv = ieee80211_priv(dev);
2121 struct ieee80211_network *net;
2122 u8 i=0, basic_rate = 0;
2123 net = & priv->ieee80211->current_network;
2124
2125 for (i=0; i<net->rates_len; i++)
2126 {
2127 basic_rate = net->rates[i]&0x7f;
2128 switch(basic_rate)
2129 {
2130 case MGN_1M: *rate_config |= RRSR_1M; break;
2131 case MGN_2M: *rate_config |= RRSR_2M; break;
2132 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
2133 case MGN_11M: *rate_config |= RRSR_11M; break;
2134 case MGN_6M: *rate_config |= RRSR_6M; break;
2135 case MGN_9M: *rate_config |= RRSR_9M; break;
2136 case MGN_12M: *rate_config |= RRSR_12M; break;
2137 case MGN_18M: *rate_config |= RRSR_18M; break;
2138 case MGN_24M: *rate_config |= RRSR_24M; break;
2139 case MGN_36M: *rate_config |= RRSR_36M; break;
2140 case MGN_48M: *rate_config |= RRSR_48M; break;
2141 case MGN_54M: *rate_config |= RRSR_54M; break;
2142 }
2143 }
2144 for (i=0; i<net->rates_ex_len; i++)
2145 {
2146 basic_rate = net->rates_ex[i]&0x7f;
2147 switch(basic_rate)
2148 {
2149 case MGN_1M: *rate_config |= RRSR_1M; break;
2150 case MGN_2M: *rate_config |= RRSR_2M; break;
2151 case MGN_5_5M: *rate_config |= RRSR_5_5M; break;
2152 case MGN_11M: *rate_config |= RRSR_11M; break;
2153 case MGN_6M: *rate_config |= RRSR_6M; break;
2154 case MGN_9M: *rate_config |= RRSR_9M; break;
2155 case MGN_12M: *rate_config |= RRSR_12M; break;
2156 case MGN_18M: *rate_config |= RRSR_18M; break;
2157 case MGN_24M: *rate_config |= RRSR_24M; break;
2158 case MGN_36M: *rate_config |= RRSR_36M; break;
2159 case MGN_48M: *rate_config |= RRSR_48M; break;
2160 case MGN_54M: *rate_config |= RRSR_54M; break;
2161 }
2162 }
2163}
2164
2165
2166#define SHORT_SLOT_TIME 9
2167#define NON_SHORT_SLOT_TIME 20
2168
2169void rtl8192_update_cap(struct net_device* dev, u16 cap)
2170{
2171 //u32 tmp = 0;
2172 struct r8192_priv *priv = ieee80211_priv(dev);
2173 struct ieee80211_network *net = &priv->ieee80211->current_network;
2174 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
2175
2176 //LZM MOD 090303 HW_VAR_ACK_PREAMBLE
5f53d8ca
JC		 2177 if(0)
2178 {
2179 u8 tmp = 0;
2180 tmp = ((priv->nCur40MhzPrimeSC) << 5);
2181 if (priv->short_preamble)
2182 tmp |= 0x80;
2183 write_nic_byte(dev, RRSR+2, tmp);
2184 }
5f53d8ca
JC		 2185
2186 if (net->mode & (IEEE_G|IEEE_N_24G))
2187 {
2188 u8 slot_time = 0;
2189 if ((cap & WLAN_CAPABILITY_SHORT_SLOT)&&(!priv->ieee80211->pHTInfo->bCurrentRT2RTLongSlotTime))
2190 {//short slot time
2191 slot_time = SHORT_SLOT_TIME;
2192 }
2193 else //long slot time
2194 slot_time = NON_SHORT_SLOT_TIME;
2195 priv->slot_time = slot_time;
2196 write_nic_byte(dev, SLOT_TIME, slot_time);
2197 }
2198
2199}
2200void rtl8192_net_update(struct net_device *dev)
2201{
2202
2203 struct r8192_priv *priv = ieee80211_priv(dev);
2204 struct ieee80211_network *net;
2205 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
2206 u16 rate_config = 0;
2207 net = & priv->ieee80211->current_network;
2208
2209 rtl8192_config_rate(dev, &rate_config);
2210 priv->basic_rate = rate_config &= 0x15f;
2211
2212 write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]);
2213 write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]);
2214 //for(i=0;i<ETH_ALEN;i++)
2215 // write_nic_byte(dev,BSSID+i,net->bssid[i]);
2216
2217 rtl8192_update_msr(dev);
2218// rtl8192_update_cap(dev, net->capability);
2219 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
2220 {
2221 write_nic_word(dev, ATIMWND, 2);
2222 write_nic_word(dev, BCN_DMATIME, 1023);
2223 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
2224// write_nic_word(dev, BcnIntTime, 100);
2225 write_nic_word(dev, BCN_DRV_EARLY_INT, 1);
2226 write_nic_byte(dev, BCN_ERR_THRESH, 100);
2227 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
2228 // TODO: BcnIFS may required to be changed on ASIC
2229 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
2230
2231 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
2232 }
2233
2234
2235
2236}
2237
2238//temporary hw beacon is not used any more.
2239//open it when necessary
2240#if 1
2241void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate)
2242{
2243
2244#if 0
2245 struct r8192_priv *priv = ieee80211_priv(dev);
2246 struct sk_buff *skb;
2247 int i = 0;
2248 //u8 cr;
2249
2250 rtl8192_net_update(dev);
2251
2252 skb = ieee80211_get_beacon(priv->ieee80211);
2253 if(!skb){
2254 DMESG("not enought memory for allocating beacon");
2255 return;
2256 }
2257
2258
2259 write_nic_byte(dev, BQREQ, read_nic_byte(dev, BQREQ) | (1<<7));
2260
2261 i=0;
2262 //while(!read_nic_byte(dev,BQREQ & (1<<7)))
2263 while( (read_nic_byte(dev, BQREQ) & (1<<7)) == 0 )
2264 {
2265 msleep_interruptible_rtl(HZ/2);
2266 if(i++ > 10){
2267 DMESGW("get stuck to wait HW beacon to be ready");
2268 return ;
2269 }
2270 }
2271 skb->cb[0] = NORM_PRIORITY;
2272 skb->cb[1] = 0; //morefragment = 0
2273 skb->cb[2] = ieeerate2rtlrate(tx_rate);
2274
2275 rtl8192_tx(dev,skb);
2276
2277#endif
2278}
2279#endif
2280inline u8 rtl8192_IsWirelessBMode(u16 rate)
2281{
2282 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
2283 return 1;
2284 else return 0;
2285}
2286
2287u16 N_DBPSOfRate(u16 DataRate);
2288
2289u16 ComputeTxTime(
2290 u16 FrameLength,
2291 u16 DataRate,
2292 u8 bManagementFrame,
2293 u8 bShortPreamble
2294)
2295{
2296 u16 FrameTime;
2297 u16 N_DBPS;
2298 u16 Ceiling;
2299
2300 if( rtl8192_IsWirelessBMode(DataRate) )
2301 {
2302 if( bManagementFrame || !bShortPreamble || DataRate == 10 )
2303 { // long preamble
2304 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
2305 }
2306 else
2307 { // Short preamble
2308 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
2309 }
2310 if( ( FrameLength*8 % (DataRate/10) ) != 0 ) //Get the Ceilling
2311 FrameTime ++;
2312 } else { //802.11g DSSS-OFDM PLCP length field calculation.
2313 N_DBPS = N_DBPSOfRate(DataRate);
2314 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
2315 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
2316 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
2317 }
2318 return FrameTime;
2319}
2320
2321u16 N_DBPSOfRate(u16 DataRate)
2322{
2323 u16 N_DBPS = 24;
2324
2325 switch(DataRate)
2326 {
2327 case 60:
2328 N_DBPS = 24;
2329 break;
2330
2331 case 90:
2332 N_DBPS = 36;
2333 break;
2334
2335 case 120:
2336 N_DBPS = 48;
2337 break;
2338
2339 case 180:
2340 N_DBPS = 72;
2341 break;
2342
2343 case 240:
2344 N_DBPS = 96;
2345 break;
2346
2347 case 360:
2348 N_DBPS = 144;
2349 break;
2350
2351 case 480:
2352 N_DBPS = 192;
2353 break;
2354
2355 case 540:
2356 N_DBPS = 216;
2357 break;
2358
2359 default:
2360 break;
2361 }
2362
2363 return N_DBPS;
2364}
2365
2366void rtl819xU_cmd_isr(struct urb *tx_cmd_urb, struct pt_regs *regs)
2367{
2368#if 0
2369 struct net_device *dev = (struct net_device*)tx_cmd_urb->context;
2370 struct r8192_priv *priv = ieee80211_priv(dev);
2371 int last_init_packet = 0;
2372 u8 *ptr_cmd_buf;
2373 u16 cmd_buf_len;
2374
2375 if(tx_cmd_urb->status != 0) {
2376 priv->pFirmware.firmware_seg_index = 0; //only begin transter, should it can be set to 1
2377 }
2378
2379 /* Free the urb and the corresponding buf for common Tx cmd packet, or
2380 * last segment of each firmware img.
2381 */
2382 if((priv->pFirmware.firmware_seg_index == 0) ||(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum)) {
2383 priv->pFirmware.firmware_seg_index = 0;//only begin transter, should it can be set to 1
2384 } else {
2385 /* prepare for last transfer */
2386 /* update some infomation for */
2387 /* last segment of the firmware img need indicate to device */
2388 priv->pFirmware.firmware_seg_index++;
2389 if(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum) {
2390 last_init_packet = 1;
2391 }
2392
2393 cmd_buf_len = priv->pFirmware.firmware_seg_container[priv->pFirmware.firmware_seg_index-1].seg_size;
2394 ptr_cmd_buf = priv->pFfirmware.firmware_seg_container[priv->pFfirmware.firmware_seg_index-1].seg_ptr;
2395 rtl819xU_tx_cmd(dev, ptr_cmd_buf, cmd_buf_len, last_init_packet, DESC_PACKET_TYPE_INIT);
2396 }
2397
2398 kfree(tx_cmd_urb->transfer_buffer);
2399#endif
2400 usb_free_urb(tx_cmd_urb);
2401}
2402
2403unsigned int txqueue2outpipe(struct r8192_priv* priv,unsigned int tx_queue) {
2404
2405 if(tx_queue >= 9)
2406 {
2407 RT_TRACE(COMP_ERR,"%s():Unknown queue ID!!!\n",__FUNCTION__);
2408 return 0x04;
2409 }
2410 return priv->txqueue_to_outpipemap[tx_queue];
2411}
2412
5f53d8ca
JC		 2413short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb)
2414{
2415 struct r8192_priv *priv = ieee80211_priv(dev);
2416 int status;
2417 struct urb *tx_urb;
2418 unsigned int idx_pipe;
2419 tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data;
2420 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2421 u8 queue_index = tcb_desc->queue_index;
2422 u32 PktSize = 0;
2423
2424 //printk("\n %s::::::::::::::::::::::queue_index = %d\n",__FUNCTION__, queue_index);
2425 atomic_inc(&priv->tx_pending[queue_index]);
2426
5f53d8ca 2427 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 2428 if(!tx_urb){
2429 dev_kfree_skb(skb);
2430 return -ENOMEM;
2431 }
2432
2433 memset(pdesc, 0, USB_HWDESC_HEADER_LEN);
2434
2435 /* Tx descriptor ought to be set according to the skb->cb */
2436 pdesc->LINIP = tcb_desc->bLastIniPkt;
2437 PktSize = (u16)(skb->len - USB_HWDESC_HEADER_LEN);
2438 pdesc->PktSize = PktSize;
2439 //printk("PKTSize = %d %x\n",pdesc->PktSize,pdesc->PktSize);
2440 //----------------------------------------------------------------------------
2441 // Fill up USB_OUT_CONTEXT.
2442 //----------------------------------------------------------------------------
2443 // Get index to out pipe from specified QueueID.
2444 idx_pipe = txqueue2outpipe(priv,queue_index);
2445 //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,queue_index,priv->RtOutPipes[idx_pipe]);
2446
2447#ifdef JOHN_DUMP_TXDESC
2448 int i;
2449 printk("Len = %d\n", skb->len);
2450 for (i = 0; i < 8; i++)
2451 printk("%2.2x ", *((u8*)skb->data+i));
2452 printk("\n");
2453#endif
2454
2455 usb_fill_bulk_urb(tx_urb,
2456 priv->udev,
2457 usb_sndbulkpipe(priv->udev,priv->RtOutPipes[idx_pipe]),
2458 skb->data,
2459 skb->len,
2460 rtl8192_tx_isr,
2461 skb);
2462
5f53d8ca 2463 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 2464 if (!status){
2465 return 0;
2466 }else{
2467 printk("Error TX CMD URB, error %d",
2468 status);
2469 return -1;
2470 }
2471}
5f53d8ca
JC		 2472
2473/*
2474 * Mapping Software/Hardware descriptor queue id to "Queue Select Field"
2475 * in TxFwInfo data structure
2476 * 2006.10.30 by Emily
2477 *
2478 * \param QUEUEID Software Queue
2479*/
2480u8 MapHwQueueToFirmwareQueue(u8 QueueID)
2481{
2482 u8 QueueSelect = 0x0; //defualt set to
2483
2484 switch(QueueID) {
2485 case BE_QUEUE:
2486 QueueSelect = QSLT_BE; //or QSelect = pTcb->priority;
2487 break;
2488
2489 case BK_QUEUE:
2490 QueueSelect = QSLT_BK; //or QSelect = pTcb->priority;
2491 break;
2492
2493 case VO_QUEUE:
2494 QueueSelect = QSLT_VO; //or QSelect = pTcb->priority;
2495 break;
2496
2497 case VI_QUEUE:
2498 QueueSelect = QSLT_VI; //or QSelect = pTcb->priority;
2499 break;
2500 case MGNT_QUEUE:
2501 QueueSelect = QSLT_MGNT;
2502 break;
2503
2504 case BEACON_QUEUE:
2505 QueueSelect = QSLT_BEACON;
2506 break;
2507
2508 // TODO: 2006.10.30 mark other queue selection until we verify it is OK
2509 // TODO: Remove Assertions
2510//#if (RTL819X_FPGA_VER & RTL819X_FPGA_GUANGAN_070502)
2511 case TXCMD_QUEUE:
2512 QueueSelect = QSLT_CMD;
2513 break;
2514//#endif
2515 case HIGH_QUEUE:
2516 QueueSelect = QSLT_HIGH;
2517 break;
2518
2519 default:
2520 RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection: %d \n", QueueID);
2521 break;
2522 }
2523 return QueueSelect;
2524}
2525
5f53d8ca
JC		 2526u8 MRateToHwRate8190Pci(u8 rate)
2527{
2528 u8 ret = DESC92S_RATE1M;
2529
2530 switch(rate)
2531 {
2532 // CCK and OFDM non-HT rates
2533 case MGN_1M: ret = DESC92S_RATE1M; break;
2534 case MGN_2M: ret = DESC92S_RATE2M; break;
2535 case MGN_5_5M: ret = DESC92S_RATE5_5M; break;
2536 case MGN_11M: ret = DESC92S_RATE11M; break;
2537 case MGN_6M: ret = DESC92S_RATE6M; break;
2538 case MGN_9M: ret = DESC92S_RATE9M; break;
2539 case MGN_12M: ret = DESC92S_RATE12M; break;
2540 case MGN_18M: ret = DESC92S_RATE18M; break;
2541 case MGN_24M: ret = DESC92S_RATE24M; break;
2542 case MGN_36M: ret = DESC92S_RATE36M; break;
2543 case MGN_48M: ret = DESC92S_RATE48M; break;
2544 case MGN_54M: ret = DESC92S_RATE54M; break;
2545
2546 // HT rates since here
2547 case MGN_MCS0: ret = DESC92S_RATEMCS0; break;
2548 case MGN_MCS1: ret = DESC92S_RATEMCS1; break;
2549 case MGN_MCS2: ret = DESC92S_RATEMCS2; break;
2550 case MGN_MCS3: ret = DESC92S_RATEMCS3; break;
2551 case MGN_MCS4: ret = DESC92S_RATEMCS4; break;
2552 case MGN_MCS5: ret = DESC92S_RATEMCS5; break;
2553 case MGN_MCS6: ret = DESC92S_RATEMCS6; break;
2554 case MGN_MCS7: ret = DESC92S_RATEMCS7; break;
2555 case MGN_MCS8: ret = DESC92S_RATEMCS8; break;
2556 case MGN_MCS9: ret = DESC92S_RATEMCS9; break;
2557 case MGN_MCS10: ret = DESC92S_RATEMCS10; break;
2558 case MGN_MCS11: ret = DESC92S_RATEMCS11; break;
2559 case MGN_MCS12: ret = DESC92S_RATEMCS12; break;
2560 case MGN_MCS13: ret = DESC92S_RATEMCS13; break;
2561 case MGN_MCS14: ret = DESC92S_RATEMCS14; break;
2562 case MGN_MCS15: ret = DESC92S_RATEMCS15; break;
2563
2564 // Set the highest SG rate
2565 case MGN_MCS0_SG:
2566 case MGN_MCS1_SG:
2567 case MGN_MCS2_SG:
2568 case MGN_MCS3_SG:
2569 case MGN_MCS4_SG:
2570 case MGN_MCS5_SG:
2571 case MGN_MCS6_SG:
2572 case MGN_MCS7_SG:
2573 case MGN_MCS8_SG:
2574 case MGN_MCS9_SG:
2575 case MGN_MCS10_SG:
2576 case MGN_MCS11_SG:
2577 case MGN_MCS12_SG:
2578 case MGN_MCS13_SG:
2579 case MGN_MCS14_SG:
2580 case MGN_MCS15_SG:
2581 {
2582 ret = DESC92S_RATEMCS15_SG;
2583 break;
2584 }
2585
2586 default: break;
2587 }
2588 return ret;
2589}
5f53d8ca
JC		 2590
2591u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc)
2592{
2593 u8 tmp_Short;
2594
2595 tmp_Short = (TxHT==1)?((tcb_desc->bUseShortGI)?1:0):((tcb_desc->bUseShortPreamble)?1:0);
2596
2597 if(TxHT==1 && TxRate != DESC90_RATEMCS15)
2598 tmp_Short = 0;
2599
2600 return tmp_Short;
2601}
2602
5f53d8ca 2603static void tx_zero_isr(struct urb *tx_urb)
5f53d8ca
JC		 2604{
2605 return;
2606}
2607
2608
5f53d8ca
JC		 2609/*
2610 * The tx procedure is just as following, skb->cb will contain all the following
2611 *information: * priority, morefrag, rate, &dev.
2612 * */
2613 // <Note> Buffer format for 8192S Usb bulk out:
2614//
2615// --------------------------------------------------
2616// | 8192S Usb Tx Desc | 802_11_MAC_header | data |
2617// --------------------------------------------------
2618// | 32 bytes | 24 bytes |0-2318 bytes|
2619// --------------------------------------------------
2620// |<------------ BufferLen ------------------------->|
2621
2622short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb)
2623{
2624 struct r8192_priv *priv = ieee80211_priv(dev);
2625 cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
2626 tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data;
2627 //tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);//92su del
2628 struct usb_device *udev = priv->udev;
2629 int pend;
2630 int status;
2631 struct urb *tx_urb = NULL, *tx_urb_zero = NULL;
2632 //int urb_len;
2633 unsigned int idx_pipe;
2634 u16 MPDUOverhead = 0;
2635 //RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc));
2636
2637#if 0
2638 /* Added by Annie for filling Len_Adjust field. 2005-12-14. */
2639 RT_ENC_ALG EncAlg = NO_Encryption;
2640#endif
2641
2642
2643 pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]);
2644 /* we are locked here so the two atomic_read and inc are executed
2645 * without interleaves * !!! For debug purpose */
2646 if( pend > MAX_TX_URB){
2647 switch (tcb_desc->queue_index) {
2648 case VO_PRIORITY:
2649 priv->stats.txvodrop++;
2650 break;
2651 case VI_PRIORITY:
2652 priv->stats.txvidrop++;
2653 break;
2654 case BE_PRIORITY:
2655 priv->stats.txbedrop++;
2656 break;
2657 default://BK_PRIORITY
2658 priv->stats.txbkdrop++;
2659 break;
2660 }
2661 printk("To discard skb packet!\n");
2662 dev_kfree_skb_any(skb);
2663 return -1;
2664 }
2665
5f53d8ca 2666 tx_urb = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 2667 if(!tx_urb){
2668 dev_kfree_skb_any(skb);
2669 return -ENOMEM;
2670 }
2671
2672 memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
2673
2674
5f53d8ca 2675 tx_desc->NonQos = (IsQoSDataFrame(skb->data)==TRUE)? 0:1;
5f53d8ca
JC		 2676
2677 /* Fill Tx descriptor */
2678 //memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb));
2679
2680 // This part can just fill to the first descriptor of the frame.
2681 /* DWORD 0 */
2682 tx_desc->TxHT = (tcb_desc->data_rate&0x80)?1:0;
2683
5f53d8ca
JC		 2684
2685 tx_desc->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate);
2686 //tx_desc->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur;
2687 tx_desc->TxShort = QueryIsShort(tx_desc->TxHT, tx_desc->TxRate, tcb_desc);
2688
2689
2690 // Aggregation related
2691 if(tcb_desc->bAMPDUEnable) {//AMPDU enabled
2692 tx_desc->AllowAggregation = 1;
2693 /* DWORD 1 */
2694 //tx_fwinfo->RxMF = tcb_desc->ampdu_factor;
2695 //tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity
2696 } else {
2697 tx_desc->AllowAggregation = 0;
2698 /* DWORD 1 */
2699 //tx_fwinfo->RxMF = 0;
2700 //tx_fwinfo->RxAMD = 0;
2701 }
2702
2703 //
2704 // <Roger_Notes> For AMPDU case, we must insert SSN into TX_DESC,
2705 // FW according as this SSN to do necessary packet retry.
2706 // 2008.06.06.
2707 //
2708 {
2709 u8 *pSeq;
2710 u16 Temp;
2711 //pSeq = (u8 *)(VirtualAddress+USB_HWDESC_HEADER_LEN + FRAME_OFFSET_SEQUENCE);
2712 pSeq = (u8 *)(skb->data+USB_HWDESC_HEADER_LEN + 22);
2713 Temp = pSeq[0];
2714 Temp <<= 12;
2715 Temp |= (*(u16 *)pSeq)>>4;
2716 tx_desc->Seq = Temp;
2717 }
2718
2719 /* Protection mode related */
2720 tx_desc->RTSEn = (tcb_desc->bRTSEnable)?1:0;
2721 tx_desc->CTS2Self = (tcb_desc->bCTSEnable)?1:0;
2722 tx_desc->RTSSTBC = (tcb_desc->bRTSSTBC)?1:0;
2723 tx_desc->RTSHT = (tcb_desc->rts_rate&0x80)?1:0;
2724 tx_desc->RTSRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate);
2725 tx_desc->RTSSubcarrier = (tx_desc->RTSHT==0)?(tcb_desc->RTSSC):0;
2726 tx_desc->RTSBW = (tx_desc->RTSHT==1)?((tcb_desc->bRTSBW)?1:0):0;
2727 tx_desc->RTSShort = (tx_desc->RTSHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\
2728 (tcb_desc->bRTSUseShortGI?1:0);
2729 //LZM 090219
2730 tx_desc->DisRTSFB = 0;
2731 tx_desc->RTSRateFBLmt = 0xf;
2732
2733 // <Roger_EXP> 2008.09.22. We disable RTS rate fallback temporarily.
2734 //tx_desc->DisRTSFB = 0x01;
2735
2736 /* Set Bandwidth and sub-channel settings. */
2737 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2738 {
2739 if(tcb_desc->bPacketBW) {
2740 tx_desc->TxBandwidth = 1;
2741 tx_desc->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode
2742 } else {
2743 tx_desc->TxBandwidth = 0;
2744 tx_desc->TxSubCarrier = priv->nCur40MhzPrimeSC;
2745 }
2746 } else {
2747 tx_desc->TxBandwidth = 0;
2748 tx_desc->TxSubCarrier = 0;
2749 }
2750
5f53d8ca
JC		 2751
2752 //memset(tx_desc, 0, sizeof(tx_desc_819x_usb));
2753 /* DWORD 0 */
2754 tx_desc->LINIP = 0;
2755 //tx_desc->CmdInit = 1; //92su del
2756 tx_desc->Offset = USB_HWDESC_HEADER_LEN;
2757
5f53d8ca
JC		 2758 {
2759 tx_desc->PktSize = (skb->len - USB_HWDESC_HEADER_LEN) & 0xffff;
2760 }
2761
2762 /*DWORD 1*/
2763 //tx_desc->SecCAMID= 0;//92su del
2764 tx_desc->RaBRSRID= tcb_desc->RATRIndex;
2765//#ifdef RTL8192S_PREPARE_FOR_NORMAL_RELEASE
2766#if 0//LZM 090219
2767 tx_desc->RaBRSRID= 1;
2768#endif
2769
2770#if 0
2771 /* Fill security related */
2772 if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag)
2773 {
2774 EncAlg = SecGetEncryptionOverhead(
2775 Adapter,
2776 &EncryptionMPDUHeadOverhead,
2777 &EncryptionMPDUTailOverhead,
2778 NULL,
2779 NULL,
2780 FALSE,
2781 FALSE);
2782 //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code
2783 //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead;
2784 MPDUOverhead = EncryptionMPDUTailOverhead;
2785 tx_desc->NoEnc = 0;
2786 RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg));
2787 //CamDumpAll(Adapter);
2788 }
2789 else
2790#endif
2791 {
2792 MPDUOverhead = 0;
2793 //tx_desc->NoEnc = 1;//92su del
2794 }
2795#if 0
2796 switch(EncAlg){
2797 case NO_Encryption:
2798 tx_desc->SecType = 0x0;
2799 break;
2800 case WEP40_Encryption:
2801 case WEP104_Encryption:
2802 tx_desc->SecType = 0x1;
2803 break;
2804 case TKIP_Encryption:
2805 tx_desc->SecType = 0x2;
2806 break;
2807 case AESCCMP_Encryption:
2808 tx_desc->SecType = 0x3;
2809 break;
2810 default:
2811 tx_desc->SecType = 0x0;
2812 break;
2813 }
2814#else
2815 tx_desc->SecType = 0x0;
2816#endif
2817 if (tcb_desc->bHwSec)
2818 {
2819 switch (priv->ieee80211->pairwise_key_type)
2820 {
2821 case KEY_TYPE_WEP40:
2822 case KEY_TYPE_WEP104:
2823 tx_desc->SecType = 0x1;
2824 //tx_desc->NoEnc = 0;//92su del
2825 break;
2826 case KEY_TYPE_TKIP:
2827 tx_desc->SecType = 0x2;
2828 //tx_desc->NoEnc = 0;//92su del
2829 break;
2830 case KEY_TYPE_CCMP:
2831 tx_desc->SecType = 0x3;
2832 //tx_desc->NoEnc = 0;//92su del
2833 break;
2834 case KEY_TYPE_NA:
2835 tx_desc->SecType = 0x0;
2836 //tx_desc->NoEnc = 1;//92su del
2837 break;
2838 default:
2839 tx_desc->SecType = 0x0;
2840 //tx_desc->NoEnc = 1;//92su del
2841 break;
2842 }
2843 }
2844
2845 //tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);//92su del
2846
2847
2848 tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate;
2849 tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack;
2850 tx_desc->DataRateFBLmt = 0x1F;// Alwasy enable all rate fallback range
2851
2852 tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index);
2853
2854
2855 /* Fill fields that are required to be initialized in all of the descriptors */
2856 //DWORD 0
2857#if 0
2858 tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0;
2859 tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0;
2860#else
2861 tx_desc->FirstSeg = 1;
2862 tx_desc->LastSeg = 1;
2863#endif
2864 tx_desc->OWN = 1;
2865
5f53d8ca
JC		 2866 {
2867 //DWORD 2
2868 //tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN);
2869 tx_desc->TxBufferSize = (u32)(skb->len);//92su mod FIXLZM
2870 }
2871
2872#if 0
2873 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(1)TxFillDescriptor8192SUsb(): DataRate(%#x)\n", pTcb->DataRate));
2874 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(2)TxFillDescriptor8192SUsb(): bTxUseDriverAssingedRate(%#x)\n", pTcb->bTxUseDriverAssingedRate));
2875 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(3)TxFillDescriptor8192SUsb(): bAMPDUEnable(%d)\n", pTcb->bAMPDUEnable));
2876 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(4)TxFillDescriptor8192SUsb(): bRTSEnable(%d)\n", pTcb->bRTSEnable));
2877 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(5)TxFillDescriptor8192SUsb(): RTSRate(%#x)\n", pTcb->RTSRate));
2878 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(6)TxFillDescriptor8192SUsb(): bCTSEnable(%d)\n", pTcb->bCTSEnable));
2879 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(7)TxFillDescriptor8192SUsb(): bUseShortGI(%d)\n", pTcb->bUseShortGI));
2880 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(8)TxFillDescriptor8192SUsb(): bPacketBW(%d)\n", pTcb->bPacketBW));
2881 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(9)TxFillDescriptor8192SUsb(): CurrentChannelBW(%d)\n", pHalData->CurrentChannelBW));
2882 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(10)TxFillDescriptor8192SUsb(): bTxDisableRateFallBack(%d)\n", pTcb->bTxDisableRateFallBack));
2883 RT_TRACE(COMP_FPGA, DBG_LOUD, ("(11)TxFillDescriptor8192SUsb(): RATRIndex(%d)\n", pTcb->RATRIndex));
2884#endif
2885
2886 /* Get index to out pipe from specified QueueID */
2887 idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index);
2888 //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,tcb_desc->queue_index,priv->RtOutPipes[idx_pipe]);
2889
2890 //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb));
2891 //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb));
2892
2893 /* To submit bulk urb */
2894 usb_fill_bulk_urb(tx_urb,
2895 udev,
2896 usb_sndbulkpipe(udev,priv->RtOutPipes[idx_pipe]),
2897 skb->data,
2898 skb->len, rtl8192_tx_isr, skb);
2899
5f53d8ca 2900 status = usb_submit_urb(tx_urb, GFP_ATOMIC);
5f53d8ca
JC		 2901 if (!status){
2902//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27
2903 bool bSend0Byte = false;
2904 u8 zero = 0;
2905 if(udev->speed == USB_SPEED_HIGH)
2906 {
2907 if (skb->len > 0 && skb->len % 512 == 0)
2908 bSend0Byte = true;
2909 }
2910 else
2911 {
2912 if (skb->len > 0 && skb->len % 64 == 0)
2913 bSend0Byte = true;
2914 }
2915 if (bSend0Byte)
2916 {
2917#if 1
5f53d8ca 2918 tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC);
5f53d8ca
JC		 2919 if(!tx_urb_zero){
2920 RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n");
2921 return -ENOMEM;
2922 }
2923 usb_fill_bulk_urb(tx_urb_zero,udev,
2924 usb_sndbulkpipe(udev,idx_pipe), &zero,
2925 0, tx_zero_isr, dev);
5f53d8ca 2926 status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC);
5f53d8ca
JC		 2927 if (status){
2928 RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status);
2929 return -1;
2930 }
2931#endif
2932 }
2933 dev->trans_start = jiffies;
2934 atomic_inc(&priv->tx_pending[tcb_desc->queue_index]);
2935 return 0;
2936 }else{
2937 RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
2938 status);
2939 return -1;
2940 }
2941}
5f53d8ca 2942
5f53d8ca 2943#if 0
0f29f587
BZ		 2944void rtl8192_set_rate(struct net_device *dev)
2945{
2946 int i;
2947 u16 word;
2948 int basic_rate,min_rr_rate,max_rr_rate;
5f53d8ca 2949
0f29f587 2950// struct r8192_priv *priv = ieee80211_priv(dev);
5f53d8ca 2951
0f29f587
BZ		 2952 //if (ieee80211_is_54g(priv->ieee80211->current_network) &&
2953// priv->ieee80211->state == IEEE80211_LINKED){
2954 basic_rate = ieeerate2rtlrate(240);
2955 min_rr_rate = ieeerate2rtlrate(60);
2956 max_rr_rate = ieeerate2rtlrate(240);
5f53d8ca 2957
0f29f587
BZ		 2958//
2959// }else{
2960// basic_rate = ieeerate2rtlrate(20);
2961// min_rr_rate = ieeerate2rtlrate(10);
2962// max_rr_rate = ieeerate2rtlrate(110);
2963// }
5f53d8ca 2964
0f29f587
BZ		 2965 write_nic_byte(dev, RESP_RATE,
2966 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
5f53d8ca 2967
0f29f587
BZ		 2968 //word = read_nic_word(dev, BRSR);
2969 word = read_nic_word(dev, BRSR_8187);
2970 word &= ~BRSR_MBR_8185;
5f53d8ca 2971
5f53d8ca 2972
0f29f587
BZ		 2973 for(i=0;i<=basic_rate;i++)
2974 word |= (1<<i);
2975
2976 //write_nic_word(dev, BRSR, word);
2977 write_nic_word(dev, BRSR_8187, word);
2978 //DMESG("RR:%x BRSR: %x", read_nic_byte(dev,RESP_RATE), read_nic_word(dev,BRSR));
2979}
5f53d8ca 2980#endif
5f53d8ca 2981
5f53d8ca 2982
5f53d8ca
JC		 2983void rtl8192SU_net_update(struct net_device *dev)
2984{
2985
2986 struct r8192_priv *priv = ieee80211_priv(dev);
2987 struct ieee80211_device* ieee = priv->ieee80211;
2988 struct ieee80211_network *net = &priv->ieee80211->current_network;
2989 //u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
2990 u16 rate_config = 0;
2991 u32 regTmp = 0;
2992 u8 rateIndex = 0;
2993 u8 retrylimit = 0x30;
2994 u16 cap = net->capability;
2995
2996 priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE;
2997
2998//HW_VAR_BASIC_RATE
2999 //update Basic rate: RR, BRSR
3000 rtl8192_config_rate(dev, &rate_config); //HalSetBrateCfg
3001
5f53d8ca 3002 priv->basic_rate = rate_config = rate_config & 0x15f;
5f53d8ca
JC		 3003
3004 // Set RRSR rate table.
3005 write_nic_byte(dev, RRSR, rate_config&0xff);
3006 write_nic_byte(dev, RRSR+1, (rate_config>>8)&0xff);
3007
3008 // Set RTS initial rate
3009 while(rate_config > 0x1)
3010 {
3011 rate_config = (rate_config>> 1);
3012 rateIndex++;
3013 }
3014 write_nic_byte(dev, INIRTSMCS_SEL, rateIndex);
3015//HW_VAR_BASIC_RATE
3016
3017 //set ack preample
3018 regTmp = (priv->nCur40MhzPrimeSC) << 5;
3019 if (priv->short_preamble)
3020 regTmp |= 0x80;
3021 write_nic_byte(dev, RRSR+2, regTmp);
3022
3023 write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]);
3024 write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]);
3025
3026 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
3027 //2008.10.24 added by tynli for beacon changed.
3028 PHY_SetBeaconHwReg( dev, net->beacon_interval);
3029
3030 rtl8192_update_cap(dev, cap);
3031
3032 if (ieee->iw_mode == IW_MODE_ADHOC){
3033 retrylimit = 7;
3034 //we should enable ibss interrupt here, but disable it temporarily
3035 if (0){
3036 priv->irq_mask |= (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
3037 //rtl8192_irq_disable(dev);
3038 //rtl8192_irq_enable(dev);
3039 }
3040 }
3041 else{
3042 if (0){
3043 priv->irq_mask &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
3044 //rtl8192_irq_disable(dev);
3045 //rtl8192_irq_enable(dev);
3046 }
3047 }
3048
3049 priv->ShortRetryLimit = priv->LongRetryLimit = retrylimit;
3050
3051 write_nic_word(dev, RETRY_LIMIT,
3052 retrylimit << RETRY_LIMIT_SHORT_SHIFT | \
3053 retrylimit << RETRY_LIMIT_LONG_SHIFT);
3054}
3055
3056void rtl8192SU_update_ratr_table(struct net_device* dev)
3057{
3058 struct r8192_priv* priv = ieee80211_priv(dev);
3059 struct ieee80211_device* ieee = priv->ieee80211;
3060 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
3061 //struct ieee80211_network *net = &ieee->current_network;
3062 u32 ratr_value = 0;
3063
3064 u8 rate_index = 0;
3065 int WirelessMode = ieee->mode;
3066 u8 MimoPs = ieee->pHTInfo->PeerMimoPs;
3067
3068 u8 bNMode = 0;
3069
3070 rtl8192_config_rate(dev, (u16*)(&ratr_value));
3071 ratr_value |= (*(u16*)(pMcsRate)) << 12;
3072
3073 //switch (ieee->mode)
3074 switch (WirelessMode)
3075 {
3076 case IEEE_A:
3077 ratr_value &= 0x00000FF0;
3078 break;
3079 case IEEE_B:
3080 ratr_value &= 0x0000000D;
3081 break;
3082 case IEEE_G:
3083 ratr_value &= 0x00000FF5;
3084 break;
3085 case IEEE_N_24G:
3086 case IEEE_N_5G:
3087 {
3088 bNMode = 1;
3089
3090 if (MimoPs == 0) //MIMO_PS_STATIC
3091 {
3092 ratr_value &= 0x0007F005;
3093 }
3094 else
3095 { // MCS rate only => for 11N mode.
3096 u32 ratr_mask;
3097
3098 // 1T2R or 1T1R, Spatial Stream 2 should be disabled
3099 if ( priv->rf_type == RF_1T2R ||
3100 priv->rf_type == RF_1T1R ||
3101 (ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_2SS) )
3102 ratr_mask = 0x000ff005;
3103 else
3104 ratr_mask = 0x0f0ff005;
3105
3106 if((ieee->pHTInfo->bCurTxBW40MHz) &&
3107 !(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_40_MHZ))
3108 ratr_mask |= 0x00000010; // Set 6MBps
3109
3110 // Select rates for rate adaptive mechanism.
3111 ratr_value &= ratr_mask;
3112 }
3113 }
3114 break;
3115 default:
3116 if(0)
3117 {
3118 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
3119 {
3120 ratr_value &= 0x000ff0f5;
3121 }
3122 else
3123 {
3124 ratr_value &= 0x0f0ff0f5;
3125 }
3126 }
3127 //printk("====>%s(), mode is not correct:%x\n", __FUNCTION__, ieee->mode);
3128 break;
3129 }
3130
5f53d8ca 3131 ratr_value &= 0x0FFFFFFF;
5f53d8ca
JC		 3132
3133 // Get MAX MCS available.
3134 if ( (bNMode && ((ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI)==0)) &&
3135 ((ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI40MHz) ||
3136 (!ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI20MHz)))
3137 {
3138 u8 shortGI_rate = 0;
3139 u32 tmp_ratr_value = 0;
3140 ratr_value |= 0x10000000;//???
3141 tmp_ratr_value = (ratr_value>>12);
3142 for(shortGI_rate=15; shortGI_rate>0; shortGI_rate--)
3143 {
3144 if((1<<shortGI_rate) & tmp_ratr_value)
3145 break;
3146 }
3147 shortGI_rate = (shortGI_rate<<12)|(shortGI_rate<<8)|(shortGI_rate<<4)|(shortGI_rate);
3148 write_nic_byte(dev, SG_RATE, shortGI_rate);
3149 //printk("==>SG_RATE:%x\n", read_nic_byte(dev, SG_RATE));
3150 }
3151 write_nic_dword(dev, ARFR0+rate_index*4, ratr_value);
3152 printk("=============>ARFR0+rate_index*4:%#x\n", ratr_value);
3153
3154 //2 UFWP
3155 if (ratr_value & 0xfffff000){
3156 //printk("===>set to N mode\n");
3157 HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_N);
3158 }
3159 else {
3160 //printk("===>set to B/G mode\n");
3161 HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_BG);
3162 }
3163}
3164
3165void rtl8192SU_link_change(struct net_device *dev)
3166{
3167 struct r8192_priv *priv = ieee80211_priv(dev);
3168 struct ieee80211_device* ieee = priv->ieee80211;
3169 //unsigned long flags;
3170 u32 reg = 0;
3171
3172 printk("=====>%s 1\n", __func__);
3173 reg = read_nic_dword(dev, RCR);
3174
3175 if (ieee->state == IEEE80211_LINKED)
3176 {
3177
3178 rtl8192SU_net_update(dev);
3179 rtl8192SU_update_ratr_table(dev);
3180 ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_ENABLE);
3181 priv->ReceiveConfig = reg |= RCR_CBSSID;
3182
3183 }else{
3184 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
3185
3186 }
3187
3188 write_nic_dword(dev, RCR, reg);
3189 rtl8192_update_msr(dev);
3190
3191 printk("<=====%s 2\n", __func__);
3192}
5f53d8ca
JC		 3193
3194static struct ieee80211_qos_parameters def_qos_parameters = {
3195 {3,3,3,3},/* cw_min */
3196 {7,7,7,7},/* cw_max */
3197 {2,2,2,2},/* aifs */
3198 {0,0,0,0},/* flags */
3199 {0,0,0,0} /* tx_op_limit */
3200};
3201
3202
5f53d8ca
JC		 3203void rtl8192_update_beacon(struct work_struct * work)
3204{
3205 struct r8192_priv *priv = container_of(work, struct r8192_priv, update_beacon_wq.work);
3206 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 3207 struct ieee80211_device* ieee = priv->ieee80211;
3208 struct ieee80211_network* net = &ieee->current_network;
3209
3210 if (ieee->pHTInfo->bCurrentHTSupport)
3211 HTUpdateSelfAndPeerSetting(ieee, net);
3212 ieee->pHTInfo->bCurrentRT2RTLongSlotTime = net->bssht.bdRT2RTLongSlotTime;
3213 // Joseph test for turbo mode with AP
3214 ieee->pHTInfo->RT2RT_HT_Mode = net->bssht.RT2RT_HT_Mode;
3215 rtl8192_update_cap(dev, net->capability);
3216}
3217/*
3218* background support to run QoS activate functionality
3219*/
3220int WDCAPARA_ADD[] = {EDCAPARA_BE,EDCAPARA_BK,EDCAPARA_VI,EDCAPARA_VO};
1ec9e48d 3221
5f53d8ca
JC		 3222void rtl8192_qos_activate(struct work_struct * work)
3223{
3224 struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate);
3225 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 3226 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
3227 u8 mode = priv->ieee80211->current_network.mode;
3228 //u32 size = sizeof(struct ieee80211_qos_parameters);
3229 u8 u1bAIFS;
3230 u32 u4bAcParam;
3231 int i;
3232
3233 if (priv == NULL)
3234 return;
3235
5f53d8ca 3236 mutex_lock(&priv->mutex);
1ec9e48d 3237
5f53d8ca
JC		 3238 if(priv->ieee80211->state != IEEE80211_LINKED)
3239 goto success;
3240 RT_TRACE(COMP_QOS,"qos active process with associate response received\n");
3241 /* It better set slot time at first */
3242 /* For we just support b/g mode at present, let the slot time at 9/20 selection */
3243 /* update the ac parameter to related registers */
3244 for(i = 0; i < QOS_QUEUE_NUM; i++) {
3245 //Mode G/A: slotTimeTimer = 9; Mode B: 20
3246 u1bAIFS = qos_parameters->aifs[i] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
3247 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[i]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
3248 (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)|
3249 (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)|
3250 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
3251
3252 write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
3253 //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4322);
3254 }
3255
3256success:
5f53d8ca 3257 mutex_unlock(&priv->mutex);
5f53d8ca
JC		 3258}
3259
3260static int rtl8192_qos_handle_probe_response(struct r8192_priv *priv,
3261 int active_network,
3262 struct ieee80211_network *network)
3263{
3264 int ret = 0;
3265 u32 size = sizeof(struct ieee80211_qos_parameters);
3266
3267 if(priv->ieee80211->state !=IEEE80211_LINKED)
3268 return ret;
3269
3270 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
3271 return ret;
3272
3273 if (network->flags & NETWORK_HAS_QOS_MASK) {
3274 if (active_network &&
3275 (network->flags & NETWORK_HAS_QOS_PARAMETERS))
3276 network->qos_data.active = network->qos_data.supported;
3277
3278 if ((network->qos_data.active == 1) && (active_network == 1) &&
3279 (network->flags & NETWORK_HAS_QOS_PARAMETERS) &&
3280 (network->qos_data.old_param_count !=
3281 network->qos_data.param_count)) {
3282 network->qos_data.old_param_count =
3283 network->qos_data.param_count;
5f53d8ca 3284 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 3285 RT_TRACE (COMP_QOS, "QoS parameters change call "
3286 "qos_activate\n");
3287 }
3288 } else {
3289 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
3290 &def_qos_parameters, size);
3291
3292 if ((network->qos_data.active == 1) && (active_network == 1)) {
5f53d8ca 3293 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 3294 RT_TRACE(COMP_QOS, "QoS was disabled call qos_activate \n");
3295 }
3296 network->qos_data.active = 0;
3297 network->qos_data.supported = 0;
3298 }
3299
3300 return 0;
3301}
3302
3303/* handle manage frame frame beacon and probe response */
3304static int rtl8192_handle_beacon(struct net_device * dev,
3305 struct ieee80211_beacon * beacon,
3306 struct ieee80211_network * network)
3307{
3308 struct r8192_priv *priv = ieee80211_priv(dev);
3309
3310 rtl8192_qos_handle_probe_response(priv,1,network);
5f53d8ca 3311 queue_delayed_work(priv->priv_wq, &priv->update_beacon_wq, 0);
5f53d8ca 3312
5f53d8ca
JC		 3313 return 0;
3314
3315}
3316
3317/*
3318* handling the beaconing responses. if we get different QoS setting
3319* off the network from the associated setting, adjust the QoS
3320* setting
3321*/
3322static int rtl8192_qos_association_resp(struct r8192_priv *priv,
3323 struct ieee80211_network *network)
3324{
3325 int ret = 0;
3326 unsigned long flags;
3327 u32 size = sizeof(struct ieee80211_qos_parameters);
3328 int set_qos_param = 0;
3329
3330 if ((priv == NULL) || (network == NULL))
3331 return ret;
3332
3333 if(priv->ieee80211->state !=IEEE80211_LINKED)
3334 return ret;
3335
3336 if ((priv->ieee80211->iw_mode != IW_MODE_INFRA))
3337 return ret;
3338
3339 spin_lock_irqsave(&priv->ieee80211->lock, flags);
3340 if(network->flags & NETWORK_HAS_QOS_PARAMETERS) {
3341 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
3342 &network->qos_data.parameters,\
3343 sizeof(struct ieee80211_qos_parameters));
3344 priv->ieee80211->current_network.qos_data.active = 1;
3345#if 0
3346 if((priv->ieee80211->current_network.qos_data.param_count != \
3347 network->qos_data.param_count))
3348#endif
3349 {
3350 set_qos_param = 1;
3351 /* update qos parameter for current network */
3352 priv->ieee80211->current_network.qos_data.old_param_count = \
3353 priv->ieee80211->current_network.qos_data.param_count;
3354 priv->ieee80211->current_network.qos_data.param_count = \
3355 network->qos_data.param_count;
3356 }
3357 } else {
3358 memcpy(&priv->ieee80211->current_network.qos_data.parameters,\
3359 &def_qos_parameters, size);
3360 priv->ieee80211->current_network.qos_data.active = 0;
3361 priv->ieee80211->current_network.qos_data.supported = 0;
3362 set_qos_param = 1;
3363 }
3364
3365 spin_unlock_irqrestore(&priv->ieee80211->lock, flags);
3366
3367 RT_TRACE(COMP_QOS, "%s: network->flags = %d,%d\n",__FUNCTION__,network->flags ,priv->ieee80211->current_network.qos_data.active);
3368 if (set_qos_param == 1)
5f53d8ca 3369 queue_work(priv->priv_wq, &priv->qos_activate);
5f53d8ca
JC		 3370
3371 return ret;
3372}
3373
3374
3375static int rtl8192_handle_assoc_response(struct net_device *dev,
3376 struct ieee80211_assoc_response_frame *resp,
3377 struct ieee80211_network *network)
3378{
3379 struct r8192_priv *priv = ieee80211_priv(dev);
3380 rtl8192_qos_association_resp(priv, network);
3381 return 0;
3382}
3383
3384
3385void rtl8192_update_ratr_table(struct net_device* dev)
3386 // POCTET_STRING posLegacyRate,
3387 // u8* pMcsRate)
3388 // PRT_WLAN_STA pEntry)
3389{
3390 struct r8192_priv* priv = ieee80211_priv(dev);
3391 struct ieee80211_device* ieee = priv->ieee80211;
3392 u8* pMcsRate = ieee->dot11HTOperationalRateSet;
3393 //struct ieee80211_network *net = &ieee->current_network;
3394 u32 ratr_value = 0;
3395 u8 rate_index = 0;
3396 rtl8192_config_rate(dev, (u16*)(&ratr_value));
3397 ratr_value |= (*(u16*)(pMcsRate)) << 12;
3398// switch (net->mode)
3399 switch (ieee->mode)
3400 {
3401 case IEEE_A:
3402 ratr_value &= 0x00000FF0;
3403 break;
3404 case IEEE_B:
3405 ratr_value &= 0x0000000F;
3406 break;
3407 case IEEE_G:
3408 ratr_value &= 0x00000FF7;
3409 break;
3410 case IEEE_N_24G:
3411 case IEEE_N_5G:
3412 if (ieee->pHTInfo->PeerMimoPs == 0) //MIMO_PS_STATIC
3413 ratr_value &= 0x0007F007;
3414 else{
3415 if (priv->rf_type == RF_1T2R)
3416 ratr_value &= 0x000FF007;
3417 else
3418 ratr_value &= 0x0F81F007;
3419 }
3420 break;
3421 default:
3422 break;
3423 }
3424 ratr_value &= 0x0FFFFFFF;
3425 if(ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI40MHz){
3426 ratr_value |= 0x80000000;
3427 }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){
3428 ratr_value |= 0x80000000;
3429 }
3430 write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
3431 write_nic_byte(dev, UFWP, 1);
3432}
3433
3434static u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04};
3435static u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04};
3436bool GetNmodeSupportBySecCfg8192(struct net_device*dev)
3437{
3438#if 1
3439 struct r8192_priv* priv = ieee80211_priv(dev);
3440 struct ieee80211_device* ieee = priv->ieee80211;
3441 struct ieee80211_network * network = &ieee->current_network;
3442 int wpa_ie_len= ieee->wpa_ie_len;
3443 struct ieee80211_crypt_data* crypt;
3444 int encrypt;
5f53d8ca 3445 return TRUE;
5f53d8ca
JC		 3446
3447 crypt = ieee->crypt[ieee->tx_keyidx];
3448 //we use connecting AP's capability instead of only security config on our driver to distinguish whether it should use N mode or G mode
3449 encrypt = (network->capability & WLAN_CAPABILITY_PRIVACY) || (ieee->host_encrypt && crypt && crypt->ops && (0 == strcmp(crypt->ops->name,"WEP")));
3450
3451 /* simply judge */
3452 if(encrypt && (wpa_ie_len == 0)) {
3453 /* wep encryption, no N mode setting */
3454 return false;
3455// } else if((wpa_ie_len != 0)&&(memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) {
3456 } else if((wpa_ie_len != 0)) {
3457 /* parse pairwise key type */
3458 //if((pairwisekey = WEP40)||(pairwisekey = WEP104)||(pairwisekey = TKIP))
3459 if (((ieee->wpa_ie[0] == 0xdd) && (!memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) || ((ieee->wpa_ie[0] == 0x30) && (!memcmp(&ieee->wpa_ie[10],ccmp_rsn_ie, 4))))
3460 return true;
3461 else
3462 return false;
3463 } else {
3464 return true;
3465 }
3466
3467#if 0
3468 //In here we discuss with SD4 David. He think we still can send TKIP in broadcast group key in MCS rate.
3469 //We can't force in G mode if Pairwie key is AES and group key is TKIP
3470 if((pSecInfo->GroupEncAlgorithm == WEP104_Encryption) || (pSecInfo->GroupEncAlgorithm == WEP40_Encryption) ||
3471 (pSecInfo->PairwiseEncAlgorithm == WEP104_Encryption) ||
3472 (pSecInfo->PairwiseEncAlgorithm == WEP40_Encryption) || (pSecInfo->PairwiseEncAlgorithm == TKIP_Encryption))
3473 {
3474 return false;
3475 }
3476 else
3477 return true;
3478#endif
3479 return true;
3480#endif
3481}
3482
3483bool GetHalfNmodeSupportByAPs819xUsb(struct net_device* dev)
3484{
3485 bool Reval;
3486 struct r8192_priv* priv = ieee80211_priv(dev);
3487 struct ieee80211_device* ieee = priv->ieee80211;
3488
3489// Added by Roger, 2008.08.29.
5f53d8ca 3490 return false;
5f53d8ca
JC		 3491
3492 if(ieee->bHalfWirelessN24GMode == true)
3493 Reval = true;
3494 else
3495 Reval = false;
3496
3497 return Reval;
3498}
3499
3500void rtl8192_refresh_supportrate(struct r8192_priv* priv)
3501{
3502 struct ieee80211_device* ieee = priv->ieee80211;
3503 //we donot consider set support rate for ABG mode, only HT MCS rate is set here.
3504 if (ieee->mode == WIRELESS_MODE_N_24G || ieee->mode == WIRELESS_MODE_N_5G)
3505 {
3506 memcpy(ieee->Regdot11HTOperationalRateSet, ieee->RegHTSuppRateSet, 16);
3507 //RT_DEBUG_DATA(COMP_INIT, ieee->RegHTSuppRateSet, 16);
3508 //RT_DEBUG_DATA(COMP_INIT, ieee->Regdot11HTOperationalRateSet, 16);
3509 }
3510 else
3511 memset(ieee->Regdot11HTOperationalRateSet, 0, 16);
3512 return;
3513}
3514
3515u8 rtl8192_getSupportedWireleeMode(struct net_device*dev)
3516{
3517 struct r8192_priv *priv = ieee80211_priv(dev);
3518 u8 ret = 0;
3519 switch(priv->rf_chip)
3520 {
3521 case RF_8225:
3522 case RF_8256:
3523 case RF_PSEUDO_11N:
3524 case RF_6052:
3525 ret = (WIRELESS_MODE_N_24G|WIRELESS_MODE_G|WIRELESS_MODE_B);
3526 break;
3527 case RF_8258:
3528 ret = (WIRELESS_MODE_A|WIRELESS_MODE_N_5G);
3529 break;
3530 default:
3531 ret = WIRELESS_MODE_B;
3532 break;
3533 }
3534 return ret;
3535}
3536void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode)
3537{
3538 struct r8192_priv *priv = ieee80211_priv(dev);
3539 u8 bSupportMode = rtl8192_getSupportedWireleeMode(dev);
3540
3541#if 1
3542 if ((wireless_mode == WIRELESS_MODE_AUTO) || ((wireless_mode&bSupportMode)==0))
3543 {
3544 if(bSupportMode & WIRELESS_MODE_N_24G)
3545 {
3546 wireless_mode = WIRELESS_MODE_N_24G;
3547 }
3548 else if(bSupportMode & WIRELESS_MODE_N_5G)
3549 {
3550 wireless_mode = WIRELESS_MODE_N_5G;
3551 }
3552 else if((bSupportMode & WIRELESS_MODE_A))
3553 {
3554 wireless_mode = WIRELESS_MODE_A;
3555 }
3556 else if((bSupportMode & WIRELESS_MODE_G))
3557 {
3558 wireless_mode = WIRELESS_MODE_G;
3559 }
3560 else if((bSupportMode & WIRELESS_MODE_B))
3561 {
3562 wireless_mode = WIRELESS_MODE_B;
3563 }
3564 else{
3565 RT_TRACE(COMP_ERR, "%s(), No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n", __FUNCTION__,bSupportMode);
3566 wireless_mode = WIRELESS_MODE_B;
3567 }
3568 }
3569#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA
3570 ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting );
3571#endif
5f53d8ca
JC		 3572 //LZM 090306 usb crash here, mark it temp
3573 //write_nic_word(dev, SIFS_OFDM, 0x0e0e);
5f53d8ca
JC		 3574 priv->ieee80211->mode = wireless_mode;
3575
3576 if ((wireless_mode == WIRELESS_MODE_N_24G) || (wireless_mode == WIRELESS_MODE_N_5G))
3577 priv->ieee80211->pHTInfo->bEnableHT = 1;
3578 else
3579 priv->ieee80211->pHTInfo->bEnableHT = 0;
3580 RT_TRACE(COMP_INIT, "Current Wireless Mode is %x\n", wireless_mode);
3581 rtl8192_refresh_supportrate(priv);
3582#endif
3583
3584}
3585
3586
3587short rtl8192_is_tx_queue_empty(struct net_device *dev)
3588{
3589 int i=0;
3590 struct r8192_priv *priv = ieee80211_priv(dev);
3591 //struct ieee80211_device* ieee = priv->ieee80211;
3592 for (i=0; i<=MGNT_QUEUE; i++)
3593 {
3594 if ((i== TXCMD_QUEUE) || (i == HCCA_QUEUE) )
3595 continue;
3596 if (atomic_read(&priv->tx_pending[i]))
3597 {
3598 printk("===>tx queue is not empty:%d, %d\n", i, atomic_read(&priv->tx_pending[i]));
3599 return 0;
3600 }
3601 }
3602 return 1;
3603}
3604#if 0
3605void rtl8192_rq_tx_ack(struct net_device *dev)
3606{
3607 struct r8192_priv *priv = ieee80211_priv(dev);
3608 priv->ieee80211->ack_tx_to_ieee = 1;
3609}
3610#endif
3611void rtl8192_hw_sleep_down(struct net_device *dev)
3612{
3613 RT_TRACE(COMP_POWER, "%s()============>come to sleep down\n", __FUNCTION__);
3614#ifdef TODO
3615// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
3616#endif
3617}
1ec9e48d 3618
5f53d8ca
JC		 3619void rtl8192_hw_sleep_wq (struct work_struct *work)
3620{
3621// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
3622// struct ieee80211_device * ieee = (struct ieee80211_device*)
3623// container_of(work, struct ieee80211_device, watch_dog_wq);
3624 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3625 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
3626 struct net_device *dev = ieee->dev;
1ec9e48d 3627
5f53d8ca
JC		 3628 //printk("=========>%s()\n", __FUNCTION__);
3629 rtl8192_hw_sleep_down(dev);
3630}
3631// printk("dev is %d\n",dev);
3632// printk("&*&(^*(&(&=========>%s()\n", __FUNCTION__);
3633void rtl8192_hw_wakeup(struct net_device* dev)
3634{
3635// u32 flags = 0;
3636
3637// spin_lock_irqsave(&priv->ps_lock,flags);
3638 RT_TRACE(COMP_POWER, "%s()============>come to wake up\n", __FUNCTION__);
3639#ifdef TODO
3640// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
3641#endif
3642 //FIXME: will we send package stored while nic is sleep?
3643// spin_unlock_irqrestore(&priv->ps_lock,flags);
3644}
1ec9e48d 3645
5f53d8ca
JC		 3646void rtl8192_hw_wakeup_wq (struct work_struct *work)
3647{
3648// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq);
3649// struct ieee80211_device * ieee = (struct ieee80211_device*)
3650// container_of(work, struct ieee80211_device, watch_dog_wq);
3651 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3652 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
3653 struct net_device *dev = ieee->dev;
5f53d8ca 3654
1ec9e48d 3655 rtl8192_hw_wakeup(dev);
5f53d8ca
JC		 3656}
3657
3658#define MIN_SLEEP_TIME 50
3659#define MAX_SLEEP_TIME 10000
3660void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl)
3661{
3662
3663 struct r8192_priv *priv = ieee80211_priv(dev);
3664
3665 u32 rb = jiffies;
3666 unsigned long flags;
3667
3668 spin_lock_irqsave(&priv->ps_lock,flags);
3669
3670 /* Writing HW register with 0 equals to disable
3671 * the timer, that is not really what we want
3672 */
3673 tl -= MSECS(4+16+7);
3674
3675 //if(tl == 0) tl = 1;
3676
3677 /* FIXME HACK FIXME HACK */
3678// force_pci_posting(dev);
3679 //mdelay(1);
3680
3681// rb = read_nic_dword(dev, TSFTR);
3682
3683 /* If the interval in witch we are requested to sleep is too
3684 * short then give up and remain awake
3685 */
3686 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
3687 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
3688 spin_unlock_irqrestore(&priv->ps_lock,flags);
3689 printk("too short to sleep\n");
3690 return;
3691 }
3692
3693// write_nic_dword(dev, TimerInt, tl);
3694// rb = read_nic_dword(dev, TSFTR);
3695 {
3696 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
3697 // if (tl<rb)
3698
5f53d8ca 3699 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
5f53d8ca
JC		 3700 }
3701 /* if we suspect the TimerInt is gone beyond tl
3702 * while setting it, then give up
3703 */
3704#if 1
3705 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
3706 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
3707 printk("========>too long to sleep:%x, %x, %lx\n", tl, rb, MSECS(MAX_SLEEP_TIME));
3708 spin_unlock_irqrestore(&priv->ps_lock,flags);
3709 return;
3710 }
3711#endif
3712// if(priv->rf_sleep)
3713// priv->rf_sleep(dev);
3714
3715 //printk("<=========%s()\n", __FUNCTION__);
5f53d8ca 3716 queue_delayed_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq,0);
1ec9e48d 3717
5f53d8ca
JC		 3718 spin_unlock_irqrestore(&priv->ps_lock,flags);
3719}
3720//init priv variables here. only non_zero value should be initialized here.
3721static void rtl8192_init_priv_variable(struct net_device* dev)
3722{
3723 struct r8192_priv *priv = ieee80211_priv(dev);
3724 u8 i;
3725 priv->card_8192 = NIC_8192U;
3726 priv->chan = 1; //set to channel 1
3727 priv->ieee80211->mode = WIRELESS_MODE_AUTO; //SET AUTO
3728 priv->ieee80211->iw_mode = IW_MODE_INFRA;
3729 priv->ieee80211->ieee_up=0;
3730 priv->retry_rts = DEFAULT_RETRY_RTS;
3731 priv->retry_data = DEFAULT_RETRY_DATA;
3732 priv->ieee80211->rts = DEFAULT_RTS_THRESHOLD;
3733 priv->ieee80211->rate = 110; //11 mbps
3734 priv->ieee80211->short_slot = 1;
3735 priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0;
3736 priv->CckPwEnl = 6;
3737 //for silent reset
3738 priv->IrpPendingCount = 1;
3739 priv->ResetProgress = RESET_TYPE_NORESET;
3740 priv->bForcedSilentReset = 0;
3741 priv->bDisableNormalResetCheck = false;
3742 priv->force_reset = false;
3743
3744 priv->ieee80211->FwRWRF = 0; //we don't use FW read/write RF until stable firmware is available.
3745 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
3746 priv->ieee80211->iw_mode = IW_MODE_INFRA;
3747 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
3748 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
3749 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE |
3750 IEEE_SOFTMAC_BEACONS;//added by amy 080604 //| //IEEE_SOFTMAC_SINGLE_QUEUE;
3751
3752 priv->ieee80211->active_scan = 1;
3753 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION | IEEE80211_OFDM_MODULATION;
3754 priv->ieee80211->host_encrypt = 1;
3755 priv->ieee80211->host_decrypt = 1;
3756 priv->ieee80211->start_send_beacons = NULL;//rtl819xusb_beacon_tx;//-by amy 080604
3757 priv->ieee80211->stop_send_beacons = NULL;//rtl8192_beacon_stop;//-by amy 080604
3758 priv->ieee80211->softmac_hard_start_xmit = rtl8192_hard_start_xmit;
3759 priv->ieee80211->set_chan = rtl8192_set_chan;
3760 priv->ieee80211->link_change = priv->ops->rtl819x_link_change;
3761 priv->ieee80211->softmac_data_hard_start_xmit = rtl8192_hard_data_xmit;
3762 priv->ieee80211->data_hard_stop = rtl8192_data_hard_stop;
3763 priv->ieee80211->data_hard_resume = rtl8192_data_hard_resume;
3764 priv->ieee80211->init_wmmparam_flag = 0;
3765 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
3766 priv->ieee80211->check_nic_enough_desc = check_nic_enough_desc;
3767 priv->ieee80211->tx_headroom = TX_PACKET_SHIFT_BYTES;
3768 priv->ieee80211->qos_support = 1;
3769
3770 //added by WB
3771// priv->ieee80211->SwChnlByTimerHandler = rtl8192_phy_SwChnl;
3772 priv->ieee80211->SetBWModeHandler = rtl8192_SetBWMode;
3773 priv->ieee80211->handle_assoc_response = rtl8192_handle_assoc_response;
3774 priv->ieee80211->handle_beacon = rtl8192_handle_beacon;
3775 //for LPS
3776 priv->ieee80211->sta_wake_up = rtl8192_hw_wakeup;
3777// priv->ieee80211->ps_request_tx_ack = rtl8192_rq_tx_ack;
3778 priv->ieee80211->enter_sleep_state = rtl8192_hw_to_sleep;
3779 priv->ieee80211->ps_is_queue_empty = rtl8192_is_tx_queue_empty;
3780 //added by david
3781 priv->ieee80211->GetNmodeSupportBySecCfg = GetNmodeSupportBySecCfg8192;
3782 priv->ieee80211->GetHalfNmodeSupportByAPsHandler = GetHalfNmodeSupportByAPs819xUsb;
3783 priv->ieee80211->SetWirelessMode = rtl8192_SetWirelessMode;
3784 //added by amy
3785 priv->ieee80211->InitialGainHandler = priv->ops->rtl819x_initial_gain;
3786 priv->card_type = USB;
3787
5f53d8ca
JC		 3788//1 RTL8192SU/
3789 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
3790 priv->ieee80211->SetFwCmdHandler = HalSetFwCmd8192S;
3791 priv->bRFSiOrPi = 0;//o=si,1=pi;
3792 //lzm add
3793 priv->bInHctTest = false;
3794
3795 priv->MidHighPwrTHR_L1 = 0x3B;
3796 priv->MidHighPwrTHR_L2 = 0x40;
3797
3798 if(priv->bInHctTest)
3799 {
3800 priv->ShortRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC;
3801 priv->LongRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC;
3802 }
3803 else
3804 {
3805 priv->ShortRetryLimit = HAL_RETRY_LIMIT_INFRA;
3806 priv->LongRetryLimit = HAL_RETRY_LIMIT_INFRA;
3807 }
3808
3809 priv->SetFwCmdInProgress = false; //is set FW CMD in Progress? 92S only
3810 priv->CurrentFwCmdIO = 0;
3811
3812 priv->MinSpaceCfg = 0;
3813
3814 priv->EarlyRxThreshold = 7;
3815 priv->enable_gpio0 = 0;
3816 priv->TransmitConfig =
3817 ((u32)TCR_MXDMA_2048<<TCR_MXDMA_OFFSET) | // Max DMA Burst Size per Tx DMA Burst, 7: reservied.
3818 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | // Short retry limit
3819 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit
3820 (false ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
3821 if(priv->bInHctTest)
3822 priv->ReceiveConfig = //priv->CSMethod |
3823 RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
3824 RCR_ACF |RCR_APPFCS| //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
3825 RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
3826 RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
3827 RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status
3828 ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
3829 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
3830 (priv->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0);
3831 else
3832 priv->ReceiveConfig = //priv->CSMethod |
3833 RCR_AMF | RCR_ADF | RCR_AB |
3834 RCR_AM | RCR_APM |RCR_AAP |RCR_ADD3|RCR_APP_ICV|
3835 RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status
3836 RCR_APP_MIC | RCR_APPFCS;
3837
3838 // <Roger_EXP> 2008.06.16.
3839 priv->IntrMask = (u16)(IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK | \
3840 IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | \
3841 IMR_BDOK | IMR_RXCMDOK | /*IMR_TIMEOUT0 |*/ IMR_RDU | IMR_RXFOVW | \
3842 IMR_TXFOVW | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
3843
3844//1 End
3845
5f53d8ca
JC		 3846
3847 priv->AcmControl = 0;
3848 priv->pFirmware = (rt_firmware*)vmalloc(sizeof(rt_firmware));
3849 if (priv->pFirmware)
3850 memset(priv->pFirmware, 0, sizeof(rt_firmware));
3851
3852 /* rx related queue */
3853 skb_queue_head_init(&priv->rx_queue);
3854 skb_queue_head_init(&priv->skb_queue);
3855
3856 /* Tx related queue */
3857 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
3858 skb_queue_head_init(&priv->ieee80211->skb_waitQ [i]);
3859 }
3860 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
3861 skb_queue_head_init(&priv->ieee80211->skb_aggQ [i]);
3862 }
3863 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
3864 skb_queue_head_init(&priv->ieee80211->skb_drv_aggQ [i]);
3865 }
3866 priv->rf_set_chan = rtl8192_phy_SwChnl;
3867}
3868
3869//init lock here
3870static void rtl8192_init_priv_lock(struct r8192_priv* priv)
3871{
3872 spin_lock_init(&priv->tx_lock);
3873 spin_lock_init(&priv->irq_lock);//added by thomas
3874 //spin_lock_init(&priv->rf_lock);//use rf_sem, or will crash in some OS.
3875 sema_init(&priv->wx_sem,1);
3876 sema_init(&priv->rf_sem,1);
3877 spin_lock_init(&priv->ps_lock);
5f53d8ca 3878 mutex_init(&priv->mutex);
5f53d8ca
JC		 3879}
3880
5f53d8ca 3881extern void rtl819x_watchdog_wqcallback(struct work_struct *work);
5f53d8ca
JC		 3882
3883void rtl8192_irq_rx_tasklet(struct r8192_priv *priv);
3884//init tasklet and wait_queue here. only 2.6 above kernel is considered
3885#define DRV_NAME "wlan0"
3886static void rtl8192_init_priv_task(struct net_device* dev)
3887{
3888 struct r8192_priv *priv = ieee80211_priv(dev);
3889
5f53d8ca
JC		 3890#ifdef PF_SYNCTHREAD
3891 priv->priv_wq = create_workqueue(DRV_NAME,0);
3892#else
3893 priv->priv_wq = create_workqueue(DRV_NAME);
3894#endif
5f53d8ca 3895
5f53d8ca
JC		 3896 INIT_WORK(&priv->reset_wq, rtl8192_restart);
3897
3898 //INIT_DELAYED_WORK(&priv->watch_dog_wq, hal_dm_watchdog);
3899 INIT_DELAYED_WORK(&priv->watch_dog_wq, rtl819x_watchdog_wqcallback);
3900 INIT_DELAYED_WORK(&priv->txpower_tracking_wq, dm_txpower_trackingcallback);
3901// INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
3902 INIT_DELAYED_WORK(&priv->rfpath_check_wq, dm_rf_pathcheck_workitemcallback);
3903 INIT_DELAYED_WORK(&priv->update_beacon_wq, rtl8192_update_beacon);
3904 INIT_DELAYED_WORK(&priv->initialgain_operate_wq, InitialGainOperateWorkItemCallBack);
3905 //INIT_WORK(&priv->SwChnlWorkItem, rtl8192_SwChnl_WorkItem);
3906 //INIT_WORK(&priv->SetBWModeWorkItem, rtl8192_SetBWModeWorkItem);
3907 INIT_WORK(&priv->qos_activate, rtl8192_qos_activate);
3908 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq);
3909 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq);
3910
5f53d8ca
JC		 3911 tasklet_init(&priv->irq_rx_tasklet,
3912 (void(*)(unsigned long))rtl8192_irq_rx_tasklet,
3913 (unsigned long)priv);
3914}
3915
3916static void rtl8192_get_eeprom_size(struct net_device* dev)
3917{
3918 u16 curCR = 0;
3919 struct r8192_priv *priv = ieee80211_priv(dev);
3920 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
3921 curCR = read_nic_word_E(dev,EPROM_CMD);
3922 RT_TRACE(COMP_EPROM, "read from Reg EPROM_CMD(%x):%x\n", EPROM_CMD, curCR);
3923 //whether need I consider BIT5?
3924 priv->epromtype = (curCR & Cmd9346CR_9356SEL) ? EPROM_93c56 : EPROM_93c46;
3925 RT_TRACE(COMP_EPROM, "<===========%s(), epromtype:%d\n", __FUNCTION__, priv->epromtype);
3926}
3927
3928//used to swap endian. as ntohl & htonl are not neccessary to swap endian, so use this instead.
3929static inline u16 endian_swap(u16* data)
3930{
3931 u16 tmp = *data;
3932 *data = (tmp >> 8) | (tmp << 8);
3933 return *data;
3934}
3935
5f53d8ca
JC		 3936u8 rtl8192SU_UsbOptionToEndPointNumber(u8 UsbOption)
3937{
3938 u8 nEndPoint = 0;
3939 switch(UsbOption)
3940 {
3941 case 0:
3942 nEndPoint = 6;
3943 break;
3944 case 1:
3945 nEndPoint = 11;
3946 break;
3947 case 2:
3948 nEndPoint = 4;
3949 break;
3950 default:
3951 RT_TRACE(COMP_INIT, "UsbOptionToEndPointNumber(): Invalid UsbOption(%#x)\n", UsbOption);
3952 break;
3953 }
3954 return nEndPoint;
3955}
3956
3957u8 rtl8192SU_BoardTypeToRFtype(struct net_device* dev, u8 Boardtype)
3958{
3959 u8 RFtype = RF_1T2R;
3960
3961 switch(Boardtype)
3962 {
3963 case 0:
3964 RFtype = RF_1T1R;
3965 break;
3966 case 1:
3967 RFtype = RF_1T2R;
3968 break;
3969 case 2:
3970 RFtype = RF_2T2R;
3971 break;
3972 case 3:
3973 RFtype = RF_2T2R_GREEN;
3974 break;
3975 default:
3976 break;
3977 }
3978
3979 return RFtype;
3980}
3981
3982//
3983// Description:
3984// Config HW adapter information into initial value.
3985//
3986// Assumption:
3987// 1. After Auto load fail(i.e, check CR9346 fail)
3988//
3989// Created by Roger, 2008.10.21.
3990//
3991void
3992rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev)
3993{
3994 struct r8192_priv *priv = ieee80211_priv(dev);
3995 //u16 i,usValue;
3996 //u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
3997 u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117
3998 int i;
3999
4000 RT_TRACE(COMP_INIT, "====> ConfigAdapterInfo8192SForAutoLoadFail\n");
4001
4002 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
4003 //PlatformStallExecution(10000);
4004 mdelay(10);
4005 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
4006
4007 //RT_ASSERT(priv->AutoloadFailFlag==TRUE, ("ReadAdapterInfo8192SEEPROM(): AutoloadFailFlag !=TRUE\n"));
4008
4009 // Initialize IC Version && Channel Plan
4010 priv->eeprom_vid = 0;
4011 priv->eeprom_pid = 0;
4012 priv->card_8192_version = 0;
4013 priv->eeprom_ChannelPlan = 0;
4014 priv->eeprom_CustomerID = 0;
4015 priv->eeprom_SubCustomerID = 0;
4016 priv->bIgnoreDiffRateTxPowerOffset = false;
4017
4018 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
4019 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
4020 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
4021 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
4022 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
4023 RT_TRACE(COMP_INIT, "IgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset);
4024
4025
4026
4027 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
4028 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
4029
4030 for(i=0; i<5; i++)
4031 priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM;
4032
4033 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("EFUSE USB PHY Param: \n"), priv->EEPROMUsbPhyParam, 5);
4034
4035 {
4036 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
4037 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
4038 u8 i;
4039
4040 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
4041
4042 for(i = 0; i < 6; i++)
4043 dev->dev_addr[i] = sMacAddr[i];
4044 }
4045 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
4046 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
4047 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
4048
4049 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
4050 dev->dev_addr[0], dev->dev_addr[1],
4051 dev->dev_addr[2], dev->dev_addr[3],
4052 dev->dev_addr[4], dev->dev_addr[5]);
4053
4054 priv->EEPROMBoardType = EEPROM_Default_BoardType;
4055 priv->rf_type = RF_1T2R; //RF_2T2R
4056 priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff;
4057 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
4058 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
4059 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
4060 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
4061 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
4062 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
4063
4064
5f53d8ca
JC		 4065
4066 for (rf_path = 0; rf_path < 2; rf_path++)
4067 {
4068 for (i = 0; i < 3; i++)
4069 {
4070 // Read CCK RF A & B Tx power
4071 priv->RfCckChnlAreaTxPwr[rf_path][i] =
4072 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] =
4073 priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] =
4074 (u8)(EEPROM_Default_TxPower & 0xff);
4075 }
4076 }
4077
4078 for (i = 0; i < 3; i++)
4079 {
4080 //RT_TRACE((COMP_EFUSE), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
4081 //priv->RfCckChnlAreaTxPwr[rf_path][i]);
4082 //RT_TRACE((COMP_EFUSE), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
4083 //priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]);
4084 //RT_TRACE((COMP_EFUSE), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
4085 //priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]);
4086 }
4087
4088 // Assign dedicated channel tx power
4089 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
4090 {
4091 if (i < 3) // Cjanel 1-3
4092 index = 0;
4093 else if (i < 9) // Channel 4-9
4094 index = 1;
4095 else // Channel 10-14
4096 index = 2;
4097
4098 // Record A & B CCK /OFDM - 1T/2T Channel area tx power
4099 priv->RfTxPwrLevelCck[rf_path][i] =
4100 priv->RfCckChnlAreaTxPwr[rf_path][index];
4101 priv->RfTxPwrLevelOfdm1T[rf_path][i] =
4102 priv->RfOfdmChnlAreaTxPwr1T[rf_path][index];
4103 priv->RfTxPwrLevelOfdm2T[rf_path][i] =
4104 priv->RfOfdmChnlAreaTxPwr2T[rf_path][index];
4105 }
4106
4107 for(i=0; i<14; i++)
4108 {
4109 //RT_TRACE((COMP_EFUSE), "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n",
4110 //rf_path, i, priv->RfTxPwrLevelCck[0][i],
4111 //priv->RfTxPwrLevelOfdm1T[0][i] ,
4112 //priv->RfTxPwrLevelOfdm2T[0][i] );
4113 }
5f53d8ca
JC		 4114
4115 //
4116 // Update remained HAL variables.
4117 //
4118 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
4119 priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;//new
4120 priv->TxPowerDiff = priv->EEPROMTxPowerDiff;
4121 //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit0~3
4122 //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit4~7
4123 priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit12~15
4124 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
4125 priv->LedStrategy = SW_LED_MODE0;
4126
4127 init_rate_adaptive(dev);
4128
4129 RT_TRACE(COMP_INIT, "<==== ConfigAdapterInfo8192SForAutoLoadFail\n");
4130
4131}
4132
4133#if 0
4134static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev)
4135{
4136 u16 EEPROMId = 0;
4137 u8 bLoad_From_EEPOM = false;
4138 struct r8192_priv *priv = ieee80211_priv(dev);
4139 u16 tmpValue = 0;
4140 u8 tmpBuffer[30];
4141 int i;
4142
4143 RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__);
4144
4145
4146 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
4147 udelay(10000);
4148 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
4149
4150
4151 EEPROMId = eprom_read(dev, 0); //first read EEPROM ID out;
4152 RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", EEPROMId);
4153
4154 if (EEPROMId != RTL8190_EEPROM_ID)
4155 {
4156 priv->AutoloadFailFlag = true;
4157 RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", EEPROMId, RTL8190_EEPROM_ID);
4158 }
4159 else
4160 {
4161 priv->AutoloadFailFlag = false;
4162 bLoad_From_EEPOM = true;
4163 }
4164
4165 if (bLoad_From_EEPOM)
4166 {
4167 tmpValue = eprom_read(dev, (EEPROM_VID>>1));
4168 priv->eeprom_vid = endian_swap(&tmpValue);
4169 priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1));
4170
4171 // Version ID, Channel plan
4172 tmpValue = eprom_read(dev, (EEPROM_Version>>1));
4173 //pHalData->card_8192_version = (VERSION_8192S)((usValue&0x00ff));
4174 priv->eeprom_ChannelPlan =(tmpValue&0xff00)>>8;
4175 priv->bTXPowerDataReadFromEEPORM = true;
4176
4177 // Customer ID, 0x00 and 0xff are reserved for Realtek.
4178 tmpValue = eprom_read(dev, (u16)(EEPROM_CustomID>>1)) ;
4179 priv->eeprom_CustomerID = (u8)( tmpValue & 0xff);
4180 priv->eeprom_SubCustomerID = (u8)((tmpValue & 0xff00)>>8);
4181 }
4182 else
4183 {
4184 priv->eeprom_vid = 0;
4185 priv->eeprom_pid = 0;
4186 //priv->card_8192_version = VERSION_8192SU_A;
4187 priv->eeprom_ChannelPlan = 0;
4188 priv->eeprom_CustomerID = 0;
4189 priv->eeprom_SubCustomerID = 0;
4190 }
4191 RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan);
4192 //set channelplan from eeprom
4193 priv->ChannelPlan = priv->eeprom_ChannelPlan;// FIXLZM
4194
4195 RT_TRACE(COMP_INIT, "EEPROMId = 0x%4x\n", EEPROMId);
4196 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
4197 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
4198 //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID));
4199 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
4200 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
4201 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
4202
4203 // Read USB optional function.
4204 if(bLoad_From_EEPOM)
4205 {
4206 tmpValue = eprom_read(dev, (EEPROM_USB_OPTIONAL>>1));
4207 priv->EEPROMUsbOption = (u8)(tmpValue&0xff);
4208 }
4209 else
4210 {
4211 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
4212 }
4213
4214 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
4215
4216
4217 if (bLoad_From_EEPOM)
4218 {
4219 int i;
4220 for (i=0; i<6; i+=2)
4221 {
4222 u16 tmp = 0;
4223 tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1));
4224 *(u16*)(&dev->dev_addr[i]) = tmp;
4225 }
4226 }
4227 else
4228 {
4229 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
4230 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
4231 u8 i;
4232
4233 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
4234
4235 for(i = 0; i < 6; i++)
4236 dev->dev_addr[i] = sMacAddr[i];
4237
4238 //memcpy(dev->dev_addr, sMacAddr, 6);
4239 //should I set IDR0 here?
4240 }
4241 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
4242 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
4243 RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr));
4244
4245 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R
5f53d8ca
JC		 4246 priv->rf_chip = RF_6052;
4247 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
4248 //priv->card_8192_version = VERSION_8192SU_A; //Over write for temporally experiment. 2008.10.16. By Roger.
5f53d8ca
JC		 4249
4250 {
4251#if 0
4252 if(bLoad_From_EEPOM)
4253 {
4254 tempval = (ReadEEprom(Adapter, (EEPROM_RFInd_PowerDiff>>1))) & 0xff;
4255 if (tempval&0x80) //RF-indication, bit[7]
4256 pHalData->RF_Type = RF_1T2R;
4257 else
4258 pHalData->RF_Type = RF_2T4R;
4259 }
4260#endif
4261
4262 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff;
4263 RT_TRACE(COMP_INIT, "TxPowerDiff = %#x\n", priv->EEPROMTxPowerDiff);
4264
4265
4266 //
4267 // Read antenna tx power offset of B/C/D to A from EEPROM
4268 // and read ThermalMeter from EEPROM
4269 //
4270 if(bLoad_From_EEPOM)
4271 {
4272 tmpValue = eprom_read(dev, (EEPROM_PwDiff>>1));
4273 priv->EEPROMPwDiff = tmpValue&0x00ff;
4274 priv->EEPROMThermalMeter = (tmpValue&0xff00)>>8;
4275 }
4276 else
4277 {
4278 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
4279 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
4280 }
4281 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff);
4282 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
4283
4284 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
4285
4286
4287 // Read CrystalCap from EEPROM
4288 if(bLoad_From_EEPOM)
4289 {
4290 priv->EEPROMCrystalCap =(u8) (((eprom_read(dev, (EEPROM_CrystalCap>>1)))&0xf000)>>12);
4291 }
4292 else
4293 {
4294 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
4295 }
4296 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
4297
4298
4299 //if(pHalData->EEPROM_Def_Ver == 0) // old eeprom definition
4300 {
4301
4302 //
4303 // Get Tx Power Base.//===>
4304 //
4305 if(bLoad_From_EEPOM)
4306 {
4307 priv->EEPROMTxPwrBase =(u8) ((eprom_read(dev, (EEPROM_TxPowerBase>>1)))&0xff);
4308 }
4309 else
4310 {
4311 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
4312 }
4313
4314 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
4315
4316 //
4317 // Get CustomerID(Boad Type)
4318 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
4319 // Others: Reserved. Default is 0x2: RTL8192SU.
4320 //
4321 if(bLoad_From_EEPOM)
4322 {
4323 tmpValue = eprom_read(dev, (u16) (EEPROM_BoardType>>1));
4324 priv->EEPROMBoardType = (u8)(tmpValue&0xff);
4325 }
4326 else
4327 {
4328 priv->EEPROMBoardType = EEPROM_Default_BoardType;
4329 }
4330
4331 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
4332
5f53d8ca
JC		 4333 // Please add code in the section!!!!
4334 // And merge tx power difference section.
5f53d8ca
JC		 4335
4336 //
4337 // Get TSSI value for each path.
4338 //
4339 if(bLoad_From_EEPOM)
4340 {
4341 tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_A)>>1));
4342 priv->EEPROMTSSI_A = (u8)((tmpValue&0xff00)>>8);
4343 }
4344 else
4345 { // Default setting for Empty EEPROM
4346 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
4347 }
4348
4349 if(bLoad_From_EEPOM)
4350 {
4351 tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_B)>>1));
4352 priv->EEPROMTSSI_B = (u8)(tmpValue&0xff);
4353 priv->EEPROMTxPwrTkMode = (u8)((tmpValue&0xff00)>>8);
4354 }
4355 else
4356 { // Default setting for Empty EEPROM
4357 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
4358 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
4359 }
4360
4361 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
4362 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
4363
5f53d8ca 4364
5f53d8ca
JC		 4365 }
4366
5f53d8ca 4367
5f53d8ca
JC		 4368 priv->TxPowerDiff = priv->EEPROMPwDiff;
4369 // Antenna B gain offset to antenna A, bit0~3
4370 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
4371 // Antenna C gain offset to antenna A, bit4~7
4372 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
4373 // CrystalCap, bit12~15
4374 priv->CrystalCap = priv->EEPROMCrystalCap;
4375 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
4376 // 92U does not enable TX power tracking.
4377 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
4378 }
4379
4380 priv->LedStrategy = SW_LED_MODE0;
4381
4382 if(priv->rf_type == RF_1T2R)
4383 {
4384 RT_TRACE(COMP_EPROM, "\n1T2R config\n");
4385 }
4386 else
4387 {
4388 RT_TRACE(COMP_EPROM, "\n2T4R config\n");
4389 }
4390
4391 // 2008/01/16 MH We can only know RF type in the function. So we have to init
4392 // DIG RATR table again.
4393 init_rate_adaptive(dev);
4394 //we need init DIG RATR table here again.
4395
4396 RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__);
4397 return;
4398}
4399
4400//
4401// Description:
4402// 1. Read HW adapter information by E-Fuse.
4403// 2. Refered from SD1 Richard.
4404//
4405// Assumption:
4406// 1. Boot from E-Fuse and CR9346 regiser has verified.
4407// 2. PASSIVE_LEVEL (USB interface)
4408//
4409// Created by Roger, 2008.10.21.
4410//
4411void
4412rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev)
4413{
4414 struct r8192_priv *priv = ieee80211_priv(dev);
4415 u16 i,usValue;
4416 u16 EEPROMId;
4417 u8 readbyte;
4418 u8 OFDMTxPwr[14];
4419 u8 CCKTxPwr[14];
4420 u8 HT2T_TxPwr[6];
4421 u8 UsbPhyParam[5];
4422 u8 hwinfo[HWSET_MAX_SIZE_92S];
4423
4424
4425 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SEFuse\n");
4426
4427 //
4428 // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming
4429 // from suspend mode.
4430 // 2008.10.21.
4431 //
4432 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
4433 //PlatformStallExecution(10000);
4434 mdelay(10);
4435 write_nic_byte(dev, SYS_FUNC_EN+1, 0x40);
4436 write_nic_byte(dev, SYS_FUNC_EN+1, 0x50);
4437
4438 readbyte = read_nic_byte(dev, EFUSE_TEST+3);
4439 write_nic_byte(dev, EFUSE_TEST+3, (readbyte | 0x80));
4440 write_nic_byte(dev, EFUSE_TEST+3, 0x72);
4441 write_nic_byte(dev, EFUSE_CLK, 0x03);
4442
4443 //
4444 // Dump EFUSe at init time for later use
4445 //
4446 // Read EFUSE real map to shadow!!
4447 EFUSE_ShadowMapUpdate(dev);
4448
4449 memcpy(hwinfo, (void*)&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
4450 //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("MAP \n"), hwinfo, HWSET_MAX_SIZE_92S);
4451
4452 //
4453 // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still
4454 // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue).
4455 // 2008.10.21.
4456 //
4457 ReadEFuse(dev, 0, 2, (unsigned char*) &EEPROMId);
4458
4459 if( EEPROMId != RTL8190_EEPROM_ID )
4460 {
4461 RT_TRACE(COMP_INIT, "EEPROM ID(%#x) is invalid!!\n", EEPROMId);
4462 priv->AutoloadFailFlag=true;
4463 }
4464 else
4465 {
4466 priv->AutoloadFailFlag=false;
4467 }
4468
4469 // Read IC Version && Channel Plan
4470 if(!priv->AutoloadFailFlag)
4471 {
4472
4473 // VID, PID
4474 ReadEFuse(dev, EEPROM_VID, 2, (unsigned char*) &priv->eeprom_vid);
4475 ReadEFuse(dev, EEPROM_PID, 2, (unsigned char*) &priv->eeprom_pid);
4476
4477 // Version ID, Channel plan
4478 ReadEFuse(dev, EEPROM_Version, 2, (unsigned char*) &usValue);
4479 //pHalData->VersionID = (VERSION_8192S)(usValue&0x00ff);
4480 priv->eeprom_ChannelPlan = (usValue&0xff00>>8);
4481 priv->bTXPowerDataReadFromEEPORM = true;
4482
4483 // Customer ID, 0x00 and 0xff are reserved for Realtek.
4484 ReadEFuse(dev, EEPROM_CustomID, 2, (unsigned char*) &usValue);
4485 priv->eeprom_CustomerID = (u8)( usValue & 0xff);
4486 priv->eeprom_SubCustomerID = (u8)((usValue & 0xff00)>>8);
4487 }
4488 else
4489 {
4490 priv->eeprom_vid = 0;
4491 priv->eeprom_pid = 0;
4492 priv->eeprom_ChannelPlan = 0;
4493 priv->eeprom_CustomerID = 0;
4494 priv->eeprom_SubCustomerID = 0;
4495 }
4496
4497 RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId);
4498 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
4499 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
4500 //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID));
4501 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
4502 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
4503 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
4504
4505
4506 // Read USB optional function.
4507 if(!priv->AutoloadFailFlag)
4508 {
4509 ReadEFuse(dev, EEPROM_USB_OPTIONAL, 1, (unsigned char*) &priv->EEPROMUsbOption);
4510 }
4511 else
4512 {
4513 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
4514 }
4515
4516 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
4517
4518
4519 // Read USB PHY parameters.
4520 if(!priv->AutoloadFailFlag)
4521 {
4522 ReadEFuse(dev, EEPROM_USB_PHY_PARA1, 5, (unsigned char*)UsbPhyParam);
4523 for(i=0; i<5; i++)
4524 {
4525 priv->EEPROMUsbPhyParam[i] = UsbPhyParam[i];
4526 RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]);
4527 }
4528 }
4529 else
4530 {
4531 for(i=0; i<5; i++)
4532 {
4533 priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM;
4534 RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]);
4535 }
4536 }
4537
4538
4539 //Read Permanent MAC address
4540 if(!priv->AutoloadFailFlag)
4541 {
4542 u8 macaddr[6] = {0x00, 0xe1, 0x86, 0x4c, 0x92, 0x00};
4543
4544 ReadEFuse(dev, EEPROM_NODE_ADDRESS_BYTE_0, 6, (unsigned char*)macaddr);
4545 for(i=0; i<6; i++)
4546 dev->dev_addr[i] = macaddr[i];
4547 }
4548 else
4549 {//Auto load fail
4550
4551 //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15.
4552 static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
4553 u8 i;
4554
4555 //if(!Adapter->bInHctTest)
4556 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
4557
4558 for(i = 0; i < 6; i++)
4559 dev->dev_addr[i] = sMacAddr[i];
4560 }
4561
4562 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
4563 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
4564 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
4565
4566 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
4567 dev->dev_addr[0], dev->dev_addr[1],
4568 dev->dev_addr[2], dev->dev_addr[3],
4569 dev->dev_addr[4], dev->dev_addr[5]);
4570
4571 // 2007/11/15 MH For RTL8192USB we assign as 1T2R now.
4572 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; // default : 1T2R
4573
5f53d8ca
JC		 4574 priv->rf_chip = RF_6052;
4575 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
5f53d8ca
JC		 4576
4577 {
4578 //
4579 // Read antenna tx power offset of B/C/D to A from EEPROM
4580 // and read ThermalMeter from EEPROM
4581 //
4582 if(!priv->AutoloadFailFlag)
4583 {
4584 ReadEFuse(dev, EEPROM_PwDiff, 2, (unsigned char*) &usValue);
4585 priv->EEPROMPwDiff = usValue&0x00ff;
4586 priv->EEPROMThermalMeter = (usValue&0xff00)>>8;
4587 }
4588 else
4589 {
4590 priv->EEPROMPwDiff = EEPROM_Default_PwDiff;
4591 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
4592 }
4593
4594 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff);
4595 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
4596
4597 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
4598
4599 //
4600 // Read Tx Power gain offset of legacy OFDM to HT rate.
4601 // Read CrystalCap from EEPROM
4602 //
4603 if(!priv->AutoloadFailFlag)
4604 {
4605 ReadEFuse(dev, EEPROM_CrystalCap, 1, (unsigned char*) &usValue);
4606 priv->EEPROMCrystalCap = (u8)((usValue&0xf0)>>4);
4607 }
4608 else
4609 {
4610 priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
4611 }
4612
4613 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
4614
4615 priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff;
4616 RT_TRACE(COMP_INIT, "TxPowerDiff = %d\n", priv->EEPROMTxPowerDiff);
4617
4618
4619 //
4620 // Get Tx Power Base.
4621 //
4622 if(!priv->AutoloadFailFlag)
4623 {
4624 ReadEFuse(dev, EEPROM_TxPowerBase, 1, (unsigned char*) &priv->EEPROMTxPwrBase );
4625 }
4626 else
4627 {
4628 priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
4629 }
4630
4631 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
4632
4633 //
4634 // Get CustomerID(Boad Type)
4635 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
4636 // Others: Reserved. Default is 0x2: RTL8192SU.
4637 //
4638 if(!priv->AutoloadFailFlag)
4639 {
4640 ReadEFuse(dev, EEPROM_BoardType, 1, (unsigned char*) &priv->EEPROMBoardType );
4641 }
4642 else
4643 {
4644 priv->EEPROMBoardType = EEPROM_Default_BoardType;
4645 }
4646
4647 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
4648
4649 //if(pHalData->EEPROM_Def_Ver == 0)
4650 {
5f53d8ca
JC		 4651 // Please add code in the section!!!!
4652 // And merge tx power difference section.
5f53d8ca
JC		 4653
4654 //
4655 // Get TSSI value for each path.
4656 //
4657 if(!priv->AutoloadFailFlag)
4658 {
4659 ReadEFuse(dev, EEPROM_TSSI_A, 2, (unsigned char*)&usValue);
4660 priv->EEPROMTSSI_A = (u8)(usValue&0xff);
4661 priv->EEPROMTSSI_B = (u8)((usValue&0xff00)>>8);
4662 }
4663 else
4664 { // Default setting for Empty EEPROM
4665 priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
4666 priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
4667 }
4668
4669 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n",
4670 priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
4671
4672 //
4673 // Get Tx Power tracking mode.
4674 //
4675 if(!priv->AutoloadFailFlag)
4676 {
4677 ReadEFuse(dev, EEPROM_TxPwTkMode, 1, (unsigned char*)&priv->EEPROMTxPwrTkMode);
4678 }
4679 else
4680 { // Default setting for Empty EEPROM
4681 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
4682 }
4683
4684 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
4685
4686
4687 // TODO: The following HT 2T Path A and B Power Index should be updated.!! Added by Roger, 2008.20.23.
4688
4689 //
4690 // Get HT 2T Path A and B Power Index.
4691 //
4692 if(!priv->AutoloadFailFlag)
4693 {
4694 ReadEFuse(dev, EEPROM_HT2T_CH1_A, 6, (unsigned char*)HT2T_TxPwr);
4695 for(i=0; i<6; i++)
4696 {
4697 priv->EEPROMHT2T_TxPwr[i] = HT2T_TxPwr[i];
4698 }
4699 }
4700 else
4701 { // Default setting for Empty EEPROM
4702 for(i=0; i<6; i++)
4703 {
4704 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
4705 }
4706 }
4707
4708 for(i=0; i<6; i++)
4709 {
4710 RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n",
4711 i, priv->EEPROMHT2T_TxPwr[i]);
4712 }
4713 }
4714
5f53d8ca 4715
5f53d8ca
JC		 4716 priv->TxPowerDiff = priv->EEPROMPwDiff;
4717 // Antenna B gain offset to antenna A, bit0~3
4718 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
4719 // Antenna C gain offset to antenna A, bit4~7
4720 priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);
4721 // CrystalCap, bit12~15
4722 priv->CrystalCap = priv->EEPROMCrystalCap;
4723 // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
4724 // 92U does not enable TX power tracking.
4725 priv->ThermalMeter[0] = priv->EEPROMThermalMeter;
4726 }
4727
4728 priv->LedStrategy = SW_LED_MODE0;
4729
4730 init_rate_adaptive(dev);
4731
4732 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SEFuse\n");
4733
4734}
4735#endif
4736
4737//
4738// Description:
4739// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
4740//
4741// Assumption:
4742// 1. CR9346 regiser has verified.
4743// 2. PASSIVE_LEVEL (USB interface)
4744//
4745// Created by Roger, 2008.10.21.
4746//
4747void
4748rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev)
4749{
4750 struct r8192_priv *priv = ieee80211_priv(dev);
4751 u16 i,usValue;
4752 u8 tmpU1b, tempval;
4753 u16 EEPROMId;
4754 u8 hwinfo[HWSET_MAX_SIZE_92S];
4755 u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117
4756
4757
4758 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n");
4759
4760 //
4761 // <Roger_Note> The following operation are prevent Efuse leakage by turn on 2.5V.
4762 // 2008.11.25.
4763 //
4764 tmpU1b = read_nic_byte(dev, EFUSE_TEST+3);
4765 write_nic_byte(dev, EFUSE_TEST+3, tmpU1b|0x80);
4766 //PlatformStallExecution(1000);
4767 mdelay(10);
4768 write_nic_byte(dev, EFUSE_TEST+3, (tmpU1b&(~BIT7)));
4769
4770 // Retrieve Chip version.
4771 priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF);
4772 RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version);
4773
4774 switch(priv->card_8192_version)
4775 {
4776 case 0:
4777 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_ACUT.\n");
4778 break;
4779 case 1:
4780 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_BCUT.\n");
4781 break;
4782 case 2:
4783 RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_CCUT.\n");
4784 break;
4785 default:
4786 RT_TRACE(COMP_INIT, "Unknown Chip Version!!\n");
4787 priv->card_8192_version = VERSION_8192S_BCUT;
4788 break;
4789 }
4790
4791 //if (IS_BOOT_FROM_EEPROM(Adapter))
4792 if(priv->EepromOrEfuse)
4793 { // Read frin EEPROM
4794 write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
4795 //PlatformStallExecution(10000);
4796 mdelay(10);
4797 write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep
4798 // Read all Content from EEPROM or EFUSE.
4799 for(i = 0; i < HWSET_MAX_SIZE_92S; i += 2)
4800 {
4801 usValue = eprom_read(dev, (u16) (i>>1));
4802 *((u16*)(&hwinfo[i])) = usValue;
4803 }
4804 }
4805 else if (!(priv->EepromOrEfuse))
4806 { // Read from EFUSE
4807
4808 //
4809 // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming
4810 // from suspend mode.
4811 // 2008.10.21.
4812 //
4813 //PlatformEFIOWrite1Byte(Adapter, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader
4814 //PlatformStallExecution(10000);
4815 //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x40);
4816 //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x50);
4817
4818 //tmpU1b = PlatformEFIORead1Byte(Adapter, EFUSE_TEST+3);
4819 //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, (tmpU1b | 0x80));
4820 //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, 0x72);
4821 //PlatformEFIOWrite1Byte(Adapter, EFUSE_CLK, 0x03);
4822
4823 // Read EFUSE real map to shadow.
4824 EFUSE_ShadowMapUpdate(dev);
4825 memcpy(hwinfo, &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
4826 }
4827 else
4828 {
4829 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SUsb(): Invalid boot type!!\n");
4830 }
4831
4832 //YJ,test,090106
4833 //dump_buf(hwinfo,HWSET_MAX_SIZE_92S);
4834 //
4835 // <Roger_Notes> The following are EFUSE/EEPROM independent operations!!
4836 //
4837 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("MAP: \n"), hwinfo, HWSET_MAX_SIZE_92S);
4838
4839 //
4840 // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still
4841 // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue).
4842 // 2008.10.21.
4843 //
4844 EEPROMId = *((u16 *)&hwinfo[0]);
4845
4846 if( EEPROMId != RTL8190_EEPROM_ID )
4847 {
4848 RT_TRACE(COMP_INIT, "ID(%#x) is invalid!!\n", EEPROMId);
4849 priv->bTXPowerDataReadFromEEPORM = FALSE;
4850 priv->AutoloadFailFlag=TRUE;
4851 }
4852 else
4853 {
4854 priv->AutoloadFailFlag=FALSE;
5f53d8ca 4855 priv->bTXPowerDataReadFromEEPORM = TRUE;
5f53d8ca
JC		 4856 }
4857 // Read IC Version && Channel Plan
4858 if(!priv->AutoloadFailFlag)
4859 {
4860 // VID, PID
4861 priv->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
4862 priv->eeprom_pid = *(u16 *)&hwinfo[EEPROM_PID];
4863 priv->bIgnoreDiffRateTxPowerOffset = false; //cosa for test
4864
4865
4866 // EEPROM Version ID, Channel plan
4867 priv->EEPROMVersion = *(u8 *)&hwinfo[EEPROM_Version];
4868 priv->eeprom_ChannelPlan = *(u8 *)&hwinfo[EEPROM_ChannelPlan];
4869
4870 // Customer ID, 0x00 and 0xff are reserved for Realtek.
4871 priv->eeprom_CustomerID = *(u8 *)&hwinfo[EEPROM_CustomID];
4872 priv->eeprom_SubCustomerID = *(u8 *)&hwinfo[EEPROM_SubCustomID];
4873 }
4874 else
4875 {
4876 //priv->eeprom_vid = 0;
4877 //priv->eeprom_pid = 0;
4878 //priv->EEPROMVersion = 0;
4879 //priv->eeprom_ChannelPlan = 0;
4880 //priv->eeprom_CustomerID = 0;
4881 //priv->eeprom_SubCustomerID = 0;
4882
4883 rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev);
4884 return;
4885 }
4886
4887
4888 RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId);
4889 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
4890 RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid);
4891 RT_TRACE(COMP_INIT, "EEPROM Version ID: 0x%2x\n", priv->EEPROMVersion);
4892 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID);
4893 RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID);
4894 RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan);
4895 RT_TRACE(COMP_INIT, "bIgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset);
4896
4897
4898 // Read USB optional function.
4899 if(!priv->AutoloadFailFlag)
4900 {
4901 priv->EEPROMUsbOption = *(u8 *)&hwinfo[EEPROM_USB_OPTIONAL];
4902 }
4903 else
4904 {
4905 priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC;
4906 }
4907
4908
4909 priv->EEPROMUsbEndPointNumber = rtl8192SU_UsbOptionToEndPointNumber((priv->EEPROMUsbOption&EEPROM_EP_NUMBER)>>3);
4910
4911 RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption);
4912 RT_TRACE(COMP_INIT, "EndPoint Number = %#x\n", priv->EEPROMUsbEndPointNumber);
4913
4914#ifdef TO_DO_LIST
4915 //
4916 // Decide CustomerID according to VID/DID or EEPROM
4917 //
4918 switch(pHalData->EEPROMCustomerID)
4919 {
4920 case EEPROM_CID_ALPHA:
4921 pMgntInfo->CustomerID = RT_CID_819x_ALPHA;
4922 break;
4923
4924 case EEPROM_CID_CAMEO:
4925 pMgntInfo->CustomerID = RT_CID_819x_CAMEO;
4926 break;
4927
4928 case EEPROM_CID_SITECOM:
4929 pMgntInfo->CustomerID = RT_CID_819x_Sitecom;
4930 RT_TRACE(COMP_INIT, DBG_LOUD, ("CustomerID = 0x%4x\n", pMgntInfo->CustomerID));
4931
4932 break;
4933
4934 case EEPROM_CID_WHQL:
4935 Adapter->bInHctTest = TRUE;
4936
4937 pMgntInfo->bSupportTurboMode = FALSE;
4938 pMgntInfo->bAutoTurboBy8186 = FALSE;
4939
4940 pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
4941 pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
4942 pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
4943 pMgntInfo->keepAliveLevel = 0;
4944 break;
4945
4946 default:
4947 pMgntInfo->CustomerID = RT_CID_DEFAULT;
4948 break;
4949
4950 }
4951
4952 //
4953 // Led mode
4954 //
4955 switch(pMgntInfo->CustomerID)
4956 {
4957 case RT_CID_DEFAULT:
4958 case RT_CID_819x_ALPHA:
4959 pHalData->LedStrategy = SW_LED_MODE1;
4960 pHalData->bRegUseLed = TRUE;
4961 pHalData->SwLed1.bLedOn = TRUE;
4962 break;
4963 case RT_CID_819x_CAMEO:
4964 pHalData->LedStrategy = SW_LED_MODE1;
4965 pHalData->bRegUseLed = TRUE;
4966 break;
4967
4968 case RT_CID_819x_Sitecom:
4969 pHalData->LedStrategy = SW_LED_MODE2;
4970 pHalData->bRegUseLed = TRUE;
4971 break;
4972
4973 default:
4974 pHalData->LedStrategy = SW_LED_MODE0;
4975 break;
4976 }
4977#endif
4978
4979 // Read USB PHY parameters.
4980 for(i=0; i<5; i++)
4981 priv->EEPROMUsbPhyParam[i] = *(u8 *)&hwinfo[EEPROM_USB_PHY_PARA1+i];
4982
4983 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("USB PHY Param: \n"), pHalData->EEPROMUsbPhyParam, 5);
4984
4985
4986 //Read Permanent MAC address
4987 for(i=0; i<6; i++)
4988 dev->dev_addr[i] = *(u8 *)&hwinfo[EEPROM_NODE_ADDRESS_BYTE_0+i];
4989
4990 //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
4991 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
4992 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
4993
4994 RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
4995 dev->dev_addr[0], dev->dev_addr[1],
4996 dev->dev_addr[2], dev->dev_addr[3],
4997 dev->dev_addr[4], dev->dev_addr[5]);
4998
4999 //
5000 // Get CustomerID(Boad Type)
5001 // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU.
5002 // Others: Reserved. Default is 0x2: RTL8192SU.
5003 //
5004 //if(!priv->AutoloadFailFlag)
5005 //{
5006 priv->EEPROMBoardType = *(u8 *)&hwinfo[EEPROM_BoardType];
5007 priv->rf_type = rtl8192SU_BoardTypeToRFtype(dev, priv->EEPROMBoardType);
5008 //}
5009 //else
5010 //{
5011 // priv->EEPROMBoardType = EEPROM_Default_BoardType;
5012 // priv->rf_type = RF_1T2R;
5013 //}
5014
5f53d8ca 5015 priv->rf_chip = RF_6052;
5f53d8ca
JC		 5016
5017 priv->rf_chip = RF_6052;//lzm test
5018 RT_TRACE(COMP_INIT, "BoardType = 0x%2x\n", priv->EEPROMBoardType);
5019 RT_TRACE(COMP_INIT, "RF_Type = 0x%2x\n", priv->rf_type);
5020
5021 //
5022 // Read antenna tx power offset of B/C/D to A from EEPROM
5023 // and read ThermalMeter from EEPROM
5024 //
5025 //if(!priv->AutoloadFailFlag)
5026 {
5027 priv->EEPROMTxPowerDiff = *(u8 *)&hwinfo[EEPROM_PwDiff];
5028 priv->EEPROMThermalMeter = *(u8 *)&hwinfo[EEPROM_ThermalMeter];
5029 }
5030 //else
5031 //{
5032 // priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff;
5033 // priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
5034 //}
5035
5036 RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMTxPowerDiff);
5037 RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter);
5038
5039 //
5040 // Read Tx Power gain offset of legacy OFDM to HT rate.
5041 // Read CrystalCap from EEPROM
5042 //
5043 //if(!priv->AutoloadFailFlag)
5044 {
5045 priv->EEPROMCrystalCap = *(u8 *)&hwinfo[EEPROM_CrystalCap];
5046 }
5047 //else
5048 //{
5049 // priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap;
5050 //}
5051
5052 RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap);
5053
5054 //
5055 // Get Tx Power Base.
5056 //
5057 //if(!priv->AutoloadFailFlag)
5058 {
5059 priv->EEPROMTxPwrBase = *(u8 *)&hwinfo[EEPROM_TxPowerBase];
5060 }
5061 //else
5062 //{
5063 // priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase;
5064 //}
5065
5066 RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase);
5067
5068
5069 //
5070 // Get TSSI value for each path.
5071 //
5072 //if(!priv->AutoloadFailFlag)
5073 {
5074 priv->EEPROMTSSI_A = *(u8 *)&hwinfo[EEPROM_TSSI_A];
5075 priv->EEPROMTSSI_B = *(u8 *)&hwinfo[EEPROM_TSSI_B];
5076 }
5077 //else
5078 //{ // Default setting for Empty EEPROM
5079 // priv->EEPROMTSSI_A = EEPROM_Default_TSSI;
5080 // priv->EEPROMTSSI_B = EEPROM_Default_TSSI;
5081 //}
5082
5083 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
5084
5085 //
5086 // Get Tx Power tracking mode.
5087 //
5088 //if(!priv->AutoloadFailFlag)
5089 {
5090 priv->EEPROMTxPwrTkMode = *(u8 *)&hwinfo[EEPROM_TxPwTkMode];
5091 }
5092
5093 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
5094
5095
5f53d8ca
JC		 5096 {
5097 //
5098 // Buffer TxPwIdx(i.e., from offset 0x55~0x66, total 18Bytes)
5099 // Update CCK, OFDM (1T/2T)Tx Power Index from above buffer.
5100 //
5101
5102 //
5103 // Get Tx Power Level by Channel
5104 //
5105 //if(!priv->AutoloadFailFlag)
5106 {
5107 // Read Tx power of Channel 1 ~ 14 from EFUSE.
5108 // 92S suupport RF A & B
5109 for (rf_path = 0; rf_path < 2; rf_path++)
5110 {
5111 for (i = 0; i < 3; i++)
5112 {
5113 // Read CCK RF A & B Tx power
5114 priv->RfCckChnlAreaTxPwr[rf_path][i] =
5115 hwinfo[EEPROM_TxPwIndex+rf_path*3+i];
5116
5117 // Read OFDM RF A & B Tx power for 1T
5118 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] =
5119 hwinfo[EEPROM_TxPwIndex+6+rf_path*3+i];
5120
5121 // Read OFDM RF A & B Tx power for 2T
5122 priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] =
5123 hwinfo[EEPROM_TxPwIndex+12+rf_path*3+i];
5124 }
5125 }
5126
5127 }
5128//
5129 // Update Tx Power HAL variables.
5130//
5131 for (rf_path = 0; rf_path < 2; rf_path++)
5132 {
5133 for (i = 0; i < 3; i++)
5134 {
5135 RT_TRACE((COMP_INIT), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5136 priv->RfCckChnlAreaTxPwr[rf_path][i]);
5137 RT_TRACE((COMP_INIT), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i,
5138 priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]);
5139 RT_TRACE((COMP_INIT), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]);
5140 }
5141
5142 // Assign dedicated channel tx power
5143 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
5144 {
5145 if (i < 3) // Cjanel 1-3
5146 index = 0;
5147 else if (i < 9) // Channel 4-9
5148 index = 1;
5149 else // Channel 10-14
5150 index = 2;
5151
5152 // Record A & B CCK /OFDM - 1T/2T Channel area tx power
5153 priv->RfTxPwrLevelCck[rf_path][i] =
5154 priv->RfCckChnlAreaTxPwr[rf_path][index];
5155 priv->RfTxPwrLevelOfdm1T[rf_path][i] =
5156 priv->RfOfdmChnlAreaTxPwr1T[rf_path][index];
5157 priv->RfTxPwrLevelOfdm2T[rf_path][i] =
5158 priv->RfOfdmChnlAreaTxPwr2T[rf_path][index];
5159 if (rf_path == 0)
5160 {
5161 priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ;
5162 priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i];
5163 }
5164 }
5165
5166 for(i=0; i<14; i++)
5167 {
5168 RT_TRACE((COMP_INIT),
5169 "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n",
5170 rf_path, i, priv->RfTxPwrLevelCck[rf_path][i],
5171 priv->RfTxPwrLevelOfdm1T[rf_path][i] ,
5172 priv->RfTxPwrLevelOfdm2T[rf_path][i] );
5173 }
5174 }
5175 }
5176
5177 //
5178 // 2009/02/09 Cosa add for new EEPROM format
5179 //
5180 for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level.
5181 {
5182 // Read tx power difference between HT OFDM 20/40 MHZ
5183 if (i < 3) // Cjanel 1-3
5184 index = 0;
5185 else if (i < 9) // Channel 4-9
5186 index = 1;
5187 else // Channel 10-14
5188 index = 2;
5189
5190 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF+index])&0xff;
5191 priv->TxPwrHt20Diff[RF90_PATH_A][i] = (tempval&0xF);
5192 priv->TxPwrHt20Diff[RF90_PATH_B][i] = ((tempval>>4)&0xF);
5193
5194 // Read OFDM<->HT tx power diff
5195 if (i < 3) // Cjanel 1-3
5196 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF])&0xff;
5197 else if (i < 9) // Channel 4-9
5198 tempval = (*(u8 *)&hwinfo[EEPROM_PwDiff])&0xff;
5199 else // Channel 10-14
5200 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+1])&0xff;
5201
5202 //cosa tempval = (*(u1Byte *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+index])&0xff;
5203 priv->TxPwrLegacyHtDiff[RF90_PATH_A][i] = (tempval&0xF);
5204 priv->TxPwrLegacyHtDiff[RF90_PATH_B][i] = ((tempval>>4)&0xF);
5205
5206 //
5207 // Read Band Edge tx power offset and check if user enable the ability
5208 //
5209 // HT 40 band edge channel
5210 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE])&0xff;
5211 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
5212 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
5213 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+1])&0xff;
5214 priv->TxPwrbandEdgeHt40[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
5215 priv->TxPwrbandEdgeHt40[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
5216 // HT 20 band edge channel
5217 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+2])&0xff;
5218 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
5219 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
5220 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+3])&0xff;
5221 priv->TxPwrbandEdgeHt20[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
5222 priv->TxPwrbandEdgeHt20[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
5223 // OFDM band edge channel
5224 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+4])&0xff;
5225 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel
5226 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel
5227 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+5])&0xff;
5228 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel
5229 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel
5230
5231 priv->TxPwrbandEdgeFlag = (*(u8 *)&hwinfo[TX_PWR_BAND_EDGE_CHK]);
5232 }
5233
5234 for(i=0; i<14; i++)
5235 RT_TRACE(COMP_INIT, "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_A][i]);
5236 for(i=0; i<14; i++)
5237 RT_TRACE(COMP_INIT, "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_A][i]);
5238 for(i=0; i<14; i++)
5239 RT_TRACE(COMP_INIT, "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_B][i]);
5240 for(i=0; i<14; i++)
5241 RT_TRACE(COMP_INIT, "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_B][i]);
5242 RT_TRACE(COMP_INIT, "RF-A HT40 band-edge low/high power diff = 0x%x/0x%x\n",
5243 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0],
5244 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]);
5245 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT40 band-edge low/high power diff = 0x%x/0x%x\n",
5246 priv->TxPwrbandEdgeHt40[RF90_PATH_B][0],
5247 priv->TxPwrbandEdgeHt40[RF90_PATH_B][1]);
5248
5249 RT_TRACE((COMP_INIT&COMP_DBG), "RF-A HT20 band-edge low/high power diff = 0x%x/0x%x\n",
5250 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0],
5251 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1]);
5252 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT20 band-edge low/high power diff = 0x%x/0x%x\n",
5253 priv->TxPwrbandEdgeHt20[RF90_PATH_B][0],
5254 priv->TxPwrbandEdgeHt20[RF90_PATH_B][1]);
5255
5256 RT_TRACE((COMP_INIT&COMP_DBG), "RF-A OFDM band-edge low/high power diff = 0x%x/0x%x\n",
5257 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0],
5258 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]);
5259 RT_TRACE((COMP_INIT&COMP_DBG), "RF-B OFDM band-edge low/high power diff = 0x%x/0x%x\n",
5260 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0],
5261 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1]);
5262 RT_TRACE((COMP_INIT&COMP_DBG), "Band-edge enable flag = %d\n", priv->TxPwrbandEdgeFlag);
5f53d8ca
JC		 5263
5264 //
5265 // Update remained HAL variables.
5266 //
5267 priv->TSSI_13dBm = priv->EEPROMThermalMeter *100;
5268 priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;
5269 priv->TxPowerDiff = priv->EEPROMTxPowerDiff;
5270 //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit[3:0]
5271 //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit[7:4]
5272 priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit[15:12]
5273 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter&0x1f);// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2
5274 priv->LedStrategy = SW_LED_MODE0;
5275
5276 init_rate_adaptive(dev);
5277
5278 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n");
5279
5280 //return RT_STATUS_SUCCESS;
5281}
5282
5283
5284//
5285// Description:
5286// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
5287//
5288// Assumption:
5289// 1. CR9346 regiser has verified.
5290// 2. PASSIVE_LEVEL (USB interface)
5291//
5292// Created by Roger, 2008.10.21.
5293//
5294static void rtl8192SU_read_eeprom_info(struct net_device *dev)
5295{
5296 struct r8192_priv *priv = ieee80211_priv(dev);
5297 u8 tmpU1b;
5298
5299 RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n");
5300
5301 // Retrieve Chip version.
5302 priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF);
5303 RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version);
5304
5305 tmpU1b = read_nic_byte(dev, EPROM_CMD);//CR9346
5306
5307 // To check system boot selection.
5308 if (tmpU1b & CmdEERPOMSEL)
5309 {
5310 RT_TRACE(COMP_INIT, "Boot from EEPROM\n");
5311 priv->EepromOrEfuse = TRUE;
5312 }
5313 else
5314 {
5315 RT_TRACE(COMP_INIT, "Boot from EFUSE\n");
5316 priv->EepromOrEfuse = FALSE;
5317 }
5318
5319 // To check autoload success or not.
5320 if (tmpU1b & CmdEEPROM_En)
5321 {
5322 RT_TRACE(COMP_INIT, "Autoload OK!!\n");
5323 priv->AutoloadFailFlag=FALSE;
5324 rtl8192SU_ReadAdapterInfo8192SUsb(dev);//eeprom or e-fuse
5325 }
5326 else
5327 { // Auto load fail.
5328 RT_TRACE(COMP_INIT, "AutoLoad Fail reported from CR9346!!\n");
5329 priv->AutoloadFailFlag=TRUE;
5330 rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev);
5331
5332 //if (IS_BOOT_FROM_EFUSE(Adapter))
5333 if(!priv->EepromOrEfuse)
5334 {
5335 RT_TRACE(COMP_INIT, "Update shadow map for EFuse future use!!\n");
5336 EFUSE_ShadowMapUpdate(dev);
5337 }
5338 }
5339#ifdef TO_DO_LIST
5340 if((priv->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK))
5341 {
5342 pMgntInfo->ChannelPlan = HalMapChannelPlan8192S(Adapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK))));
5343 pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan.
5344 }
5345 else
5346 {
5347 pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan;
5348 }
5349
5350 switch(pMgntInfo->ChannelPlan)
5351 {
5352 case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN:
5353 {
5354 PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo);
5355
5356 pDot11dInfo->bEnabled = TRUE;
5357 }
5358 RT_TRACE(COMP_INIT, DBG_LOUD, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n"));
5359 break;
5360 }
5361
5362 RT_TRACE(COMP_INIT, DBG_LOUD, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan));
5363 RT_TRACE(COMP_INIT, DBG_LOUD, ("ChannelPlan = %d\n" , pMgntInfo->ChannelPlan));
5364
5365 RT_TRACE(COMP_INIT, DBG_LOUD, ("<==== ReadAdapterInfo8192S\n"));
5366#endif
5367
5368 RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n");
5369
5370 //return RT_STATUS_SUCCESS;
5371}
0f29f587
BZ		 5372
5373short rtl8192_get_channel_map(struct net_device * dev)
5f53d8ca 5374{
5f53d8ca 5375 struct r8192_priv *priv = ieee80211_priv(dev);
0f29f587
BZ		 5376 if(priv->ChannelPlan > COUNTRY_CODE_GLOBAL_DOMAIN){
5377 printk("rtl8180_init:Error channel plan! Set to default.\n");
5378 priv->ChannelPlan= 0;
5f53d8ca 5379 }
0f29f587 5380 RT_TRACE(COMP_INIT, "Channel plan is %d\n",priv->ChannelPlan);
5f53d8ca 5381
0f29f587
BZ		 5382 rtl819x_set_channel_map(priv->ChannelPlan, priv);
5383 return 0;
5384}
5f53d8ca
JC		 5385
5386short rtl8192_init(struct net_device *dev)
5387{
5388
5389 struct r8192_priv *priv = ieee80211_priv(dev);
5390
5f53d8ca
JC		 5391 rtl8192_init_priv_variable(dev);
5392 rtl8192_init_priv_lock(priv);
5393 rtl8192_init_priv_task(dev);
5394 rtl8192_get_eeprom_size(dev);
5395 priv->ops->rtl819x_read_eeprom_info(dev);
5396 rtl8192_get_channel_map(dev);
5397 init_hal_dm(dev);
5398 init_timer(&priv->watch_dog_timer);
5399 priv->watch_dog_timer.data = (unsigned long)dev;
5400 priv->watch_dog_timer.function = watch_dog_timer_callback;
5401
5402 //rtl8192_adapter_start(dev);
5403#ifdef DEBUG_EPROM
5404 dump_eprom(dev);
5405#endif
5406 return 0;
5407}
5408
5409/******************************************************************************
5410 *function: This function actually only set RRSR, RATR and BW_OPMODE registers
5411 * not to do all the hw config as its name says
5412 * input: net_device dev
5413 * output: none
5414 * return: none
5415 * notice: This part need to modified according to the rate set we filtered
5416 * ****************************************************************************/
5417void rtl8192_hwconfig(struct net_device* dev)
5418{
5419 u32 regRATR = 0, regRRSR = 0;
5420 u8 regBwOpMode = 0, regTmp = 0;
5421 struct r8192_priv *priv = ieee80211_priv(dev);
5422
5423// Set RRSR, RATR, and BW_OPMODE registers
5424 //
5425 switch(priv->ieee80211->mode)
5426 {
5427 case WIRELESS_MODE_B:
5428 regBwOpMode = BW_OPMODE_20MHZ;
5429 regRATR = RATE_ALL_CCK;
5430 regRRSR = RATE_ALL_CCK;
5431 break;
5432 case WIRELESS_MODE_A:
5433 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
5434 regRATR = RATE_ALL_OFDM_AG;
5435 regRRSR = RATE_ALL_OFDM_AG;
5436 break;
5437 case WIRELESS_MODE_G:
5438 regBwOpMode = BW_OPMODE_20MHZ;
5439 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5440 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5441 break;
5442 case WIRELESS_MODE_AUTO:
5443#ifdef TO_DO_LIST
5444 if (Adapter->bInHctTest)
5445 {
5446 regBwOpMode = BW_OPMODE_20MHZ;
5447 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5448 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5449 }
5450 else
5451#endif
5452 {
5453 regBwOpMode = BW_OPMODE_20MHZ;
5454 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
5455 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5456 }
5457 break;
5458 case WIRELESS_MODE_N_24G:
5459 // It support CCK rate by default.
5460 // CCK rate will be filtered out only when associated AP does not support it.
5461 regBwOpMode = BW_OPMODE_20MHZ;
5462 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
5463 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5464 break;
5465 case WIRELESS_MODE_N_5G:
5466 regBwOpMode = BW_OPMODE_5G;
5467 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
5468 regRRSR = RATE_ALL_OFDM_AG;
5469 break;
5470 }
5471
5472 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
5473 {
5474 u32 ratr_value = 0;
5475 ratr_value = regRATR;
5476 if (priv->rf_type == RF_1T2R)
5477 {
5478 ratr_value &= ~(RATE_ALL_OFDM_2SS);
5479 }
5480 write_nic_dword(dev, RATR0, ratr_value);
5481 write_nic_byte(dev, UFWP, 1);
5482 }
5483 regTmp = read_nic_byte(dev, 0x313);
5484 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
5485 write_nic_dword(dev, RRSR, regRRSR);
5486
5487 //
5488 // Set Retry Limit here
5489 //
5490 write_nic_word(dev, RETRY_LIMIT,
5491 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | \
5492 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
5493 // Set Contention Window here
5494
5495 // Set Tx AGC
5496
5497 // Set Tx Antenna including Feedback control
5498
5499 // Set Auto Rate fallback control
5500
5501
5502}
5503
5f53d8ca
JC		 5504
5505//
5506// Description:
5507// Initial HW relted registers.
5508//
5509// Assumption:
5510// Config RTL8192S USB MAC, we should config MAC before download FW.
5511//
5512// 2008.09.03, Added by Roger.
5513//
5514static void rtl8192SU_MacConfigBeforeFwDownloadASIC(struct net_device *dev)
5515{
5516 u8 tmpU1b;// i;
5517// u16 tmpU2b;
5518// u32 tmpU4b;
5519 u8 PollingCnt = 20;
5520
5521 RT_TRACE(COMP_INIT, "--->MacConfigBeforeFwDownloadASIC()\n");
5522
5523 //2MAC Initialization for power on sequence, Revised by Roger. 2008.09.03.
5524
5525 //
5526 //<Roger_Notes> Set control path switch to HW control and reset Digital Core, CPU Core and
5527 // MAC I/O to solve FW download fail when system from resume sate.
5528 // 2008.11.04.
5529 //
5530 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
5531 if(tmpU1b & 0x80)
5532 {
5533 tmpU1b &= 0x3f;
5534 write_nic_byte(dev, SYS_CLKR+1, tmpU1b);
5535 }
5536 // Clear FW RPWM for FW control LPS. by tynli. 2009.02.23
5537 write_nic_byte(dev, RPWM, 0x0);
5538
5539 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
5540 tmpU1b &= 0x73;
5541 write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b);
5542 udelay(1000);
5543
5544 //Revised POS, suggested by SD1 Alex, 2008.09.27.
5545 write_nic_byte(dev, SPS0_CTRL+1, 0x53);
5546 write_nic_byte(dev, SPS0_CTRL, 0x57);
5547
5548 //Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias
5549 tmpU1b = read_nic_byte(dev, AFE_MISC);
5550 write_nic_byte(dev, AFE_MISC, (tmpU1b|AFE_BGEN|AFE_MBEN));
5551
5552 //Enable PLL Power (LDOA15V)
5553 tmpU1b = read_nic_byte(dev, LDOA15_CTRL);
5554 write_nic_byte(dev, LDOA15_CTRL, (tmpU1b|LDA15_EN));
5555
5556 //Enable LDOV12D block
5557 tmpU1b = read_nic_byte(dev, LDOV12D_CTRL);
5558 write_nic_byte(dev, LDOV12D_CTRL, (tmpU1b|LDV12_EN));
5559
5560 //mpU1b = read_nic_byte(Adapter, SPS1_CTRL);
5561 //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_LDEN));
5562
5563 //PlatformSleepUs(2000);
5564
5565 //Enable Switch Regulator Block
5566 //tmpU1b = read_nic_byte(Adapter, SPS1_CTRL);
5567 //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_SWEN));
5568
5569 //write_nic_dword(Adapter, SPS1_CTRL, 0x00a7b267);
5570
5571 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1);
5572 write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b|0x08));
5573
5574 //Engineer Packet CP test Enable
5575 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
5576 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x20));
5577
5578 //Support 64k IMEM, suggested by SD1 Alex.
5579 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1);
5580 write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b& 0x68));
5581
5582 //Enable AFE clock
5583 tmpU1b = read_nic_byte(dev, AFE_XTAL_CTRL+1);
5584 write_nic_byte(dev, AFE_XTAL_CTRL+1, (tmpU1b& 0xfb));
5585
5586 //Enable AFE PLL Macro Block
5587 tmpU1b = read_nic_byte(dev, AFE_PLL_CTRL);
5588 write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|0x11));
5589
5590 //Attatch AFE PLL to MACTOP/BB/PCIe Digital
5591 tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL);
5592 write_nic_byte(dev, SYS_ISO_CTRL, (tmpU1b&0xEE));
5593
5594 // Switch to 40M clock
5595 write_nic_byte(dev, SYS_CLKR, 0x00);
5596
5597 //SSC Disable
5598 tmpU1b = read_nic_byte(dev, SYS_CLKR);
5599 //write_nic_byte(dev, SYS_CLKR, (tmpU1b&0x5f));
5600 write_nic_byte(dev, SYS_CLKR, (tmpU1b|0xa0));
5601
5602 //Enable MAC clock
5603 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
5604 write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x18));
5605
5606 //Revised POS, suggested by SD1 Alex, 2008.09.27.
5607 write_nic_byte(dev, PMC_FSM, 0x02);
5608
5609 //Enable Core digital and enable IOREG R/W
5610 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
5611 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x08));
5612
5613 //Enable REG_EN
5614 tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1);
5615 write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x80));
5616
5617 //Switch the control path to FW
5618 tmpU1b = read_nic_byte(dev, SYS_CLKR+1);
5619 write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x80)& 0xBF);
5620
5621 write_nic_byte(dev, CMDR, 0xFC);
5622 write_nic_byte(dev, CMDR+1, 0x37);
5623
5624 //Fix the RX FIFO issue(usb error), 970410
5625 tmpU1b = read_nic_byte_E(dev, 0x5c);
5626 write_nic_byte_E(dev, 0x5c, (tmpU1b|BIT7));
5627
5628 //For power save, used this in the bit file after 970621
5629 tmpU1b = read_nic_byte(dev, SYS_CLKR);
5630 write_nic_byte(dev, SYS_CLKR, tmpU1b&(~SYS_CPU_CLKSEL));
5631
5632 // Revised for 8051 ROM code wrong operation. Added by Roger. 2008.10.16.
5633 write_nic_byte_E(dev, 0x1c, 0x80);
5634
5635 //
5636 // <Roger_EXP> To make sure that TxDMA can ready to download FW.
5637 // We should reset TxDMA if IMEM RPT was not ready.
5638 // Suggested by SD1 Alex. 2008.10.23.
5639 //
5640 do
5641 {
5642 tmpU1b = read_nic_byte(dev, TCR);
5643 if((tmpU1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
5644 break;
5645 //PlatformStallExecution(5);
5646 udelay(5);
5647 }while(PollingCnt--); // Delay 1ms
5648
5649 if(PollingCnt <= 0 )
5650 {
5651 RT_TRACE(COMP_INIT, "MacConfigBeforeFwDownloadASIC(): Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", tmpU1b);
5652 tmpU1b = read_nic_byte(dev, CMDR);
5653 write_nic_byte(dev, CMDR, tmpU1b&(~TXDMA_EN));
5654 udelay(2);
5655 write_nic_byte(dev, CMDR, tmpU1b|TXDMA_EN);// Reset TxDMA
5656 }
5657
5658
5659 RT_TRACE(COMP_INIT, "<---MacConfigBeforeFwDownloadASIC()\n");
5660}
5f53d8ca
JC		 5661
5662
5f53d8ca
JC		 5663#if 0
5664static void rtl8192SU_SetHwRegAmpduMinSpace(struct net_device *dev, u8 MinSpaceCfg)
5665{
5666 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
5667 struct ieee80211_device* ieee = priv->ieee80211;
5668 u8 MinSpacingToSet;
5669 u8 SecMinSpace;
5670
5f53d8ca
JC		 5671 MinSpacingToSet = MinSpaceCfg;
5672 if(MinSpacingToSet <= 7)
5673 {
5674 switch(ieee->pairwise_key_type)
5675 {
5676 case KEY_TYPE_NA: SecMinSpace = 0; break;
5677 case KEY_TYPE_CCMP:
5678 case KEY_TYPE_WEP40:
5679 case KEY_TYPE_WEP104:
5680 case KEY_TYPE_TKIP: SecMinSpace = 6; break;
5681 default: SecMinSpace = 7; break;
5682 }
5683
5684 if(MinSpacingToSet < SecMinSpace)
5685 MinSpacingToSet = SecMinSpace;
5686 priv->MinSpaceCfg = ((priv->MinSpaceCfg&0xf8) |MinSpacingToSet);
5687 RT_TRACE(COMP_SEC, "Set AMPDU_MIN_SPACE: %x\n", priv->MinSpaceCfg);
5688 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);
5689 }
5690
5f53d8ca
JC		 5691}
5692#endif
5693
5694//
5695// Description:
5696// Initial HW relted registers.
5697//
5698// Assumption:
5699// 1. This function is only invoked at driver intialization once.
5700// 2. PASSIVE LEVEL.
5701//
5702// 2008.06.10, Added by Roger.
5703//
5704static void rtl8192SU_MacConfigAfterFwDownload(struct net_device *dev)
5705{
5706 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
5707 //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
5708 //u8 tmpU1b, RxPageCfg, i;
5709 u16 tmpU2b;
5710 u8 tmpU1b;//, i;
5711
5712
5713 RT_TRACE(COMP_INIT, "--->MacConfigAfterFwDownload()\n");
5714
5715 // Enable Tx/Rx
5716 tmpU2b = (BBRSTn|BB_GLB_RSTn|SCHEDULE_EN|MACRXEN|MACTXEN|DDMA_EN|
5717 FW2HW_EN|RXDMA_EN|TXDMA_EN|HCI_RXDMA_EN|HCI_TXDMA_EN); //3
5718 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_COMMAND, &tmpU1b );
5719 write_nic_word(dev, CMDR, tmpU2b); //LZM REGISTER COM 090305
5720
5721 // Loopback mode or not
5722 priv->LoopbackMode = RTL8192SU_NO_LOOPBACK; // Set no loopback as default.
5723 if(priv->LoopbackMode == RTL8192SU_NO_LOOPBACK)
5724 tmpU1b = LBK_NORMAL;
5725 else if (priv->LoopbackMode == RTL8192SU_MAC_LOOPBACK )
5726 tmpU1b = LBK_MAC_DLB;
5727 else
5728 RT_TRACE(COMP_INIT, "Serious error: wrong loopback mode setting\n");
5729
5730 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_LBK_MODE, &tmpU1b);
5731 write_nic_byte(dev, LBKMD_SEL, tmpU1b);
5732
5733 // Set RCR
5734 write_nic_dword(dev, RCR, priv->ReceiveConfig);
5735 RT_TRACE(COMP_INIT, "MacConfigAfterFwDownload(): Current RCR settings(%#x)\n", priv->ReceiveConfig);
5736
5737
5738 // Set RQPN
5739 //
5740 // <Roger_Notes> 2008.08.18.
5741 // 6 endpoints:
5742 // (1) Page number on CMDQ is 0x03.
5743 // (2) Page number on BCNQ, HQ and MGTQ is 0.
5744 // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07.
5745 // (4) Page number on PUBQ is 0xdd
5746 //
5747 // 11 endpoints:
5748 // (1) Page number on CMDQ is 0x00.
5749 // (2) Page number on BCNQ is 0x02, HQ and MGTQ are 0x03.
5750 // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07.
5751 // (4) Page number on PUBQ is 0xd8
5752 //
5753 //write_nic_dword(Adapter, 0xa0, 0x07070707); //BKQ, BEQ, VIQ and VOQ
5754 //write_nic_byte(dev, 0xa4, 0x00); // HCCAQ
5755#if 0 //LZM 090219
5756#ifdef USE_SIX_USB_ENDPOINT
5757 //write_nic_dword(Adapter, 0xa5, 0x00000003); //CMDQ, MGTQ, HQ and BCNQ
5758 //write_nic_byte(dev, 0xa9, 0xdd); // PUBQ
5759 tmpU1b = read_nic_byte(dev, 0xab); // RQPN
5760 write_nic_byte(dev, 0xab, tmpU1b|BIT7|BIT6);// reduce to 6 endpoints.
5761#else
5762 write_nic_dword(dev, 0xa5, 0x02030300); //CMDQ, MGTQ, HQ and BCNQ
5763 write_nic_byte(dev, 0xa9, 0xd8); // PUBQ
5764 tmpU1b = read_nic_byte(dev, 0xab); // RQPN
5765 write_nic_byte(dev, 0xab, (tmpU1b&(~BIT6))|BIT7); // Disable reduced endpoint.
5766#endif
5767#endif
5768
5f53d8ca
JC		 5769
5770 // Fix the RX FIFO issue(USB error), Rivesed by Roger, 2008-06-14
5771 tmpU1b = read_nic_byte_E(dev, 0x5C);
5772 write_nic_byte_E(dev, 0x5C, tmpU1b|BIT7);
5773
5f53d8ca
JC		 5774#if 0 //LZM 090219
5775 //
5776 // Suggested by SD1 Alex, 2008-06-14.
5777 //
5778 write_nic_byte(dev, TXOP_STALL_CTRL, 0x80);//NAV
5779
5780
5781 //
5782 // Set Data Auto Rate Fallback Retry Count register.
5783 //
5784 write_nic_dword(dev, DARFRC, 0x04010000);
5785 write_nic_dword(dev, DARFRC+4, 0x09070605);
5786 write_nic_dword(dev, RARFRC, 0x04010000);
5787 write_nic_dword(dev, RARFRC+4, 0x09070605);
5788
5789 // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
5790 for (i = 0; i < 8; i++)
5f53d8ca 5791 write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
5f53d8ca
JC		 5792
5793 //
5794 // Set driver info, we only accept PHY status now.
5795 //
5796 //write_nic_byte(dev, RXDRVINFO_SZ, 4);
5797
5798 //
5799 // Aggregation length limit. Revised by Roger. 2008.09.22.
5800 //
5801 write_nic_dword(dev, AGGLEN_LMT_L, 0x66666666); // Long GI
5802 write_nic_byte(dev, AGGLEN_LMT_H, 0x06); // Set AMPDU length to 12Kbytes for ShortGI case.
5803
5804 //
5805 // For Min Spacing configuration.
5806 //
5807 //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AMPDU_MIN_SPACE, (u8*)(&Adapter->MgntInfo.MinSpaceCfg));
5808 rtl8192SU_SetHwRegAmpduMinSpace(dev,priv->MinSpaceCfg);
5809#endif
5810
5811 // For EFUSE init configuration.
5812 //if (IS_BOOT_FROM_EFUSE(Adapter)) // We may R/W EFUSE in EFUSE mode
5813 if (priv->bBootFromEfuse)
5814 {
5815 u8 tempval;
5816
5817 tempval = read_nic_byte(dev, SYS_ISO_CTRL+1);
5818 tempval &= 0xFE;
5819 write_nic_byte(dev, SYS_ISO_CTRL+1, tempval);
5820
5821 // Enable LDO 2.5V for write action
5822 //tempval = read_nic_byte(Adapter, EFUSE_TEST+3);
5823 //write_nic_byte(Adapter, EFUSE_TEST+3, (tempval | 0x80));
5824
5825 // Change Efuse Clock for write action
5826 //write_nic_byte(Adapter, EFUSE_CLK, 0x03);
5827
5828 // Change Program timing
5829 write_nic_byte(dev, EFUSE_CTRL+3, 0x72);
5830 //printk("!!!!!!!!!!!!!!!!!!!!!%s: write 0x33 with 0x72\n",__FUNCTION__);
5831 RT_TRACE(COMP_INIT, "EFUSE CONFIG OK\n");
5832 }
5833
5834
5835 RT_TRACE(COMP_INIT, "<---MacConfigAfterFwDownload()\n");
5836}
5837
5838void rtl8192SU_HwConfigureRTL8192SUsb(struct net_device *dev)
5839{
5840
5841 struct r8192_priv *priv = ieee80211_priv(dev);
5842 u8 regBwOpMode = 0;
5843 u32 regRATR = 0, regRRSR = 0;
5844 u8 regTmp = 0;
5845 u32 i = 0;
5846
5847 //1 This part need to modified according to the rate set we filtered!!
5848 //
5849 // Set RRSR, RATR, and BW_OPMODE registers
5850 //
5851 switch(priv->ieee80211->mode)
5852 {
5853 case WIRELESS_MODE_B:
5854 regBwOpMode = BW_OPMODE_20MHZ;
5855 regRATR = RATE_ALL_CCK;
5856 regRRSR = RATE_ALL_CCK;
5857 break;
5858 case WIRELESS_MODE_A:
5859 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
5860 regRATR = RATE_ALL_OFDM_AG;
5861 regRRSR = RATE_ALL_OFDM_AG;
5862 break;
5863 case WIRELESS_MODE_G:
5864 regBwOpMode = BW_OPMODE_20MHZ;
5865 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5866 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5867 break;
5868 case WIRELESS_MODE_AUTO:
5869 if (priv->bInHctTest)
5870 {
5871 regBwOpMode = BW_OPMODE_20MHZ;
5872 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5873 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5874 }
5875 else
5876 {
5877 regBwOpMode = BW_OPMODE_20MHZ;
5878 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
5879 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5880 }
5881 break;
5882 case WIRELESS_MODE_N_24G:
5883 // It support CCK rate by default.
5884 // CCK rate will be filtered out only when associated AP does not support it.
5885 regBwOpMode = BW_OPMODE_20MHZ;
5886 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
5887 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
5888 break;
5889 case WIRELESS_MODE_N_5G:
5890 regBwOpMode = BW_OPMODE_5G;
5891 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
5892 regRRSR = RATE_ALL_OFDM_AG;
5893 break;
5894 }
5895
5896 //
5897 // <Roger_Notes> We disable CCK response rate until FIB CCK rate IC's back.
5898 // 2008.09.23.
5899 //
5900 regTmp = read_nic_byte(dev, INIRTSMCS_SEL);
5f53d8ca 5901 regRRSR = ((regRRSR & 0x000fffff)<<8) | regTmp;
5f53d8ca
JC		 5902
5903 //
5904 // Update SIFS timing.
5905 //
5906 //priv->SifsTime = 0x0e0e0a0a;
5907 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SIFS, (pu1Byte)&pHalData->SifsTime);
5908 { u8 val[4] = {0x0e, 0x0e, 0x0a, 0x0a};
5909 // SIFS for CCK Data ACK
5910 write_nic_byte(dev, SIFS_CCK, val[0]);
5911 // SIFS for CCK consecutive tx like CTS data!
5912 write_nic_byte(dev, SIFS_CCK+1, val[1]);
5913
5914 // SIFS for OFDM Data ACK
5915 write_nic_byte(dev, SIFS_OFDM, val[2]);
5916 // SIFS for OFDM consecutive tx like CTS data!
5917 write_nic_byte(dev, SIFS_OFDM+1, val[3]);
5918 }
5919
5920 write_nic_dword(dev, INIRTSMCS_SEL, regRRSR);
5921 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
5922
5923 //
5924 // Suggested by SD1 Alex, 2008-06-14.
5925 //
5926 //PlatformEFIOWrite1Byte(Adapter, TXOP_STALL_CTRL, 0x80);//NAV to protect all TXOP.
5927
5928 //
5929 // Set Data Auto Rate Fallback Retry Count register.
5930 //
5931 write_nic_dword(dev, DARFRC, 0x02010000);
5932 write_nic_dword(dev, DARFRC+4, 0x06050403);
5933 write_nic_dword(dev, RARFRC, 0x02010000);
5934 write_nic_dword(dev, RARFRC+4, 0x06050403);
5935
5936 // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22.
5937 for (i = 0; i < 8; i++)
5f53d8ca 5938 write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0);
5f53d8ca
JC		 5939
5940 //
5941 // Aggregation length limit. Revised by Roger. 2008.09.22.
5942 //
5943 write_nic_byte(dev, AGGLEN_LMT_H, 0x0f); // Set AMPDU length to 12Kbytes for ShortGI case.
5944 write_nic_dword(dev, AGGLEN_LMT_L, 0xddd77442); // Long GI
5945 write_nic_dword(dev, AGGLEN_LMT_L+4, 0xfffdd772);
5946
5947 // Set NAV protection length
5948 write_nic_word(dev, NAV_PROT_LEN, 0x0080);
5949
5950 // Set TXOP stall control for several queue/HI/BCN/MGT/
5951 write_nic_byte(dev, TXOP_STALL_CTRL, 0x00); // NAV Protect next packet.
5952
5953 // Set MSDU lifetime.
5954 write_nic_byte(dev, MLT, 0x8f);
5955
5956 // Set CCK/OFDM SIFS
5957 write_nic_word(dev, SIFS_CCK, 0x0a0a); // CCK SIFS shall always be 10us.
5958 write_nic_word(dev, SIFS_OFDM, 0x0e0e);
5959
5960 write_nic_byte(dev, ACK_TIMEOUT, 0x40);
5961
5962 // CF-END Threshold
5963 write_nic_byte(dev, CFEND_TH, 0xFF);
5964
5965 //
5966 // For Min Spacing configuration.
5967 //
5968 switch(priv->rf_type)
5969 {
5970 case RF_1T2R:
5971 case RF_1T1R:
5972 RT_TRACE(COMP_INIT, "Initializeadapter: RF_Type%s\n", (priv->rf_type==RF_1T1R? "(1T1R)":"(1T2R)"));
5973 priv->MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
5974 break;
5975 case RF_2T2R:
5976 case RF_2T2R_GREEN:
5977 RT_TRACE(COMP_INIT, "Initializeadapter:RF_Type(2T2R)\n");
5978 priv->MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
5979 break;
5980 }
5981 write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);
5982
5983 //LZM 090219
5984 //
5985 // For Min Spacing configuration.
5986 //
5987 //priv->MinSpaceCfg = 0x00;
5988 //rtl8192SU_SetHwRegAmpduMinSpace(dev, priv->MinSpaceCfg);
5989}
5990
5f53d8ca 5991
5f53d8ca
JC		 5992// Description: Initial HW relted registers.
5993//
5994// Assumption: This function is only invoked at driver intialization once.
5995//
5996// 2008.06.10, Added by Roger.
5997bool rtl8192SU_adapter_start(struct net_device *dev)
5998{
5999 struct r8192_priv *priv = ieee80211_priv(dev);
6000 //u32 dwRegRead = 0;
6001 //bool init_status = true;
6002 //u32 ulRegRead;
6003 bool rtStatus = true;
6004 //u8 PipeIndex;
6005 //u8 eRFPath, tmpU1b;
6006 u8 fw_download_times = 1;
6007
6008
6009 RT_TRACE(COMP_INIT, "--->InitializeAdapter8192SUsb()\n");
6010
6011 //pHalData->bGPIOChangeRF = FALSE;
6012
6013
6014 //
6015 // <Roger_Notes> 2008.06.15.
6016 //
6017 // Initialization Steps on RTL8192SU:
6018 // a. MAC initialization prior to sending down firmware code.
6019 // b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM).
6020 // c. MAC configuration after firmware has been download successfully.
6021 // d. Initialize BB related configurations.
6022 // e. Initialize RF related configurations.
6023 // f. Start to BulkIn transfer.
6024 //
6025
6026 //
6027 //a. MAC initialization prior to send down firmware code.
6028 //
6029start:
6030 rtl8192SU_MacConfigBeforeFwDownloadASIC(dev);
6031
6032 //
6033 //b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM).
6034 //
6035 rtStatus = FirmwareDownload92S(dev);
6036 if(rtStatus != true)
6037 {
6038 if(fw_download_times == 1){
6039 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed once, Download again!!\n");
6040 fw_download_times = fw_download_times + 1;
6041 goto start;
6042 }else{
6043 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed twice, end!!\n");
6044 goto end;
6045 }
6046 }
6047 //
6048 //c. MAC configuration after firmware has been download successfully.
6049 //
6050 rtl8192SU_MacConfigAfterFwDownload(dev);
6051
5f53d8ca
JC		 6052 //priv->bLbusEnable = TRUE;
6053 //if(priv->RegRfOff == TRUE)
6054 // priv->eRFPowerState = eRfOff;
6055
6056 // Save target channel
6057 // <Roger_Notes> Current Channel will be updated again later.
6058 //priv->CurrentChannel = Channel;
6059 rtStatus = PHY_MACConfig8192S(dev);//===>ok
6060 if(rtStatus != true)
6061 {
6062 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure MAC!!\n");
6063 goto end;
6064 }
6065 if (1){
6066 int i;
6067 for (i=0; i<4; i++)
6068 write_nic_dword(dev,WDCAPARA_ADD[i], 0x5e4322);
6069 write_nic_byte(dev,AcmHwCtrl, 0x01);
6070 }
6071
6072
6073 //
6074 //d. Initialize BB related configurations.
6075 //
6076
6077 rtStatus = PHY_BBConfig8192S(dev);//===>ok
6078 if(rtStatus != true)
6079 {
6080 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure BB!!\n");
6081 goto end;
6082 }
6083
6084 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);//===>ok
6085
6086 //
6087 // e. Initialize RF related configurations.
6088 //
6089 // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W.
6090 priv->Rf_Mode = RF_OP_By_SW_3wire;
6091
6092 // For RF test only from Scott's suggestion
6093 //write_nic_byte(dev, 0x27, 0xDB);
6094 //write_nic_byte(dev, 0x1B, 0x07);
6095
6096
6097 write_nic_byte(dev, AFE_XTAL_CTRL+1, 0xDB);
6098
6099 // <Roger_Notes> The following IOs are configured for each RF modules.
6100 // Enable RF module and reset RF and SDM module. 2008.11.17.
6101 if(priv->card_8192_version == VERSION_8192S_ACUT)
6102 write_nic_byte(dev, SPS1_CTRL+3, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB)); // Fix A-Cut bug.
6103 else
6104 write_nic_byte(dev, RF_CTRL, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB));
6105
6106 rtStatus = PHY_RFConfig8192S(dev);//===>ok
6107 if(rtStatus != true)
6108 {
6109 RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure RF!!\n");
6110 goto end;
6111 }
6112
6113
6114 // Set CCK and OFDM Block "ON"
6115 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
6116 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
6117
6118 //
6119 // Turn off Radio B while RF type is 1T1R by SD3 Wilsion's request.
6120 // Revised by Roger, 2008.12.18.
6121 //
6122 if(priv->rf_type == RF_1T1R)
6123 {
6124 // This is needed for PHY_REG after 20081219
6125 rtl8192_setBBreg(dev, rFPGA0_RFMOD, 0xff000000, 0x03);
6126 // This is needed for PHY_REG before 20081219
6127 //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x11);
6128 }
6129
5f53d8ca
JC		 6130
6131 //LZM 090219
6132 // Set CCK and OFDM Block "ON"
6133 //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
6134 //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
6135
6136
6137 //3//Get hardware version, do it in read eeprom?
6138 //GetHardwareVersion819xUsb(Adapter);
6139
6140 //3//
6141 //3 //Set Hardware
6142 //3//
6143 rtl8192SU_HwConfigureRTL8192SUsb(dev);//==>ok
6144
6145 //
6146 // <Roger_Notes> We set MAC address here if autoload was failed before,
6147 // otherwise IDR0 will NOT contain any value.
6148 //
6149 write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]);
6150 write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]);
6151 if(!priv->bInHctTest)
6152 {
6153 if(priv->ResetProgress == RESET_TYPE_NORESET)
6154 {
6155 //RT_TRACE(COMP_MLME, DBG_LOUD, ("Initializeadapter8192SUsb():RegWirelessMode(%#x) \n", Adapter->RegWirelessMode));
6156 //Adapter->HalFunc.SetWirelessModeHandler(Adapter, Adapter->RegWirelessMode);
6157 rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);//===>ok
6158 }
6159 }
6160 else
6161 {
6162 priv->ieee80211->mode = WIRELESS_MODE_G;
6163 rtl8192_SetWirelessMode(dev, WIRELESS_MODE_G);
6164 }
6165
6166 //Security related.
6167 //-----------------------------------------------------------------------------
6168 // Set up security related. 070106, by rcnjko:
6169 // 1. Clear all H/W keys.
6170 // 2. Enable H/W encryption/decryption.
6171 //-----------------------------------------------------------------------------
6172 //CamResetAllEntry(Adapter);
6173 //Adapter->HalFunc.EnableHWSecCfgHandler(Adapter);
6174
6175 //SecClearAllKeys(Adapter);
6176 CamResetAllEntry(dev);
6177 //SecInit(Adapter);
6178 {
6179 u8 SECR_value = 0x0;
6180 SECR_value |= SCR_TxEncEnable;
6181 SECR_value |= SCR_RxDecEnable;
6182 SECR_value |= SCR_NoSKMC;
6183 write_nic_byte(dev, SECR, SECR_value);
6184 }
6185
6186#if 0
6187
6188 if(pHalData->VersionID == VERSION_8192SU_A)
6189 {
6190 // cosa add for tx power level initialization.
6191 GetTxPowerOriginalOffset(Adapter);
6192 SetTxPowerLevel819xUsb(Adapter, Channel);
6193 }
6194#endif
6195
6196
6197#ifdef TO_DO_LIST
6198
6199 //PHY_UpdateInitialGain(dev);
6200
6201 if(priv->RegRfOff == true)
6202 { // User disable RF via registry.
6203 u8 eRFPath = 0;
6204
6205 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RegRfOff ----------\n");
6206 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW);
6207 // Those action will be discard in MgntActSet_RF_State because off the same state
6208 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
6209 rtl8192_setBBreg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
6210 }
6211 else if(priv->RfOffReason > RF_CHANGE_BY_PS)
6212 { // H/W or S/W RF OFF before sleep.
6213 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RfOffReason(%d) ----------\n", priv->RfOffReason);
6214 MgntActSet_RF_State(dev, eRfOff, priv->RfOffReason);
6215 }
6216 else
6217 {
6218 priv->eRFPowerState = eRfOn;
6219 priv->RfOffReason = 0;
6220 RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): RF is on ----------\n");
6221 }
6222
6223#endif
6224
6225
6226//
6227// f. Start to BulkIn transfer.
6228//
6229#ifdef TO_DO_LIST
6230
6231#ifndef UNDER_VISTA
6232 {
6233 u8 i;
6234 PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
6235
6236 for(PipeIndex=0; PipeIndex < MAX_RX_QUEUE; PipeIndex++)
6237 {
6238 if (PipeIndex == 0)
6239 {
6240 for(i=0; i<32; i++)
6241 HalUsbInMpdu(Adapter, PipeIndex);
6242 }
6243 else
6244 {
6245 //HalUsbInMpdu(Adapter, PipeIndex);
6246 //HalUsbInMpdu(Adapter, PipeIndex);
6247 //HalUsbInMpdu(Adapter, PipeIndex);
6248 }
6249 }
6250 PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
6251 }
6252#else
6253 // Joseph add to 819X code base for Vista USB platform.
6254 // This part may need to be add to Hal819xU code base. too.
6255 PlatformUsbEnableInPipes(Adapter);
6256#endif
6257
6258 RT_TRACE(COMP_INIT, "HighestOperaRate = %x\n", Adapter->MgntInfo.HighestOperaRate);
6259
6260 PlatformStartWorkItem( &(pHalData->RtUsbCheckForHangWorkItem) );
6261
6262 //
6263 // <Roger_EXP> The following configurations are for ASIC verification temporally.
6264 // 2008.07.10.
6265 //
6266
6267#endif
6268
6269 //
6270 // Read EEPROM TX power index and PHY_REG_PG.txt to capture correct
6271 // TX power index for different rate set.
6272 //
6273 //if(priv->card_8192_version >= VERSION_8192S_ACUT)
6274 {
6275 // Get original hw reg values
6276 PHY_GetHWRegOriginalValue(dev);
6277
6278 // Write correct tx power index//FIXLZM
6279 PHY_SetTxPowerLevel8192S(dev, priv->chan);
6280 }
6281
6282 {
6283 u8 tmpU1b = 0;
6284 // EEPROM R/W workaround
6285 tmpU1b = read_nic_byte(dev, MAC_PINMUX_CFG);
6286 write_nic_byte(dev, MAC_PINMUX_CFG, tmpU1b&(~GPIOMUX_EN));
6287 }
6288
6289//
6290//<Roger_Notes> 2008.08.19.
6291// We return status here for temporal FPGA verification, 2008.08.19.
6292
6293#ifdef RTL8192SU_FW_IQK
6294 write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
6295 ChkFwCmdIoDone(dev);
6296#endif
6297
6298 //
6299 // <Roger_Notes> We enable high power mechanism after NIC initialized.
6300 // 2008.11.27.
6301 //
6302 write_nic_dword(dev, WFM5, FW_RA_RESET);
6303 ChkFwCmdIoDone(dev);
6304 write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
6305 ChkFwCmdIoDone(dev);
6306 write_nic_dword(dev, WFM5, FW_RA_REFRESH);
6307 ChkFwCmdIoDone(dev);
6308 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
6309
6310// <Roger_Notes> We return status here for temporal FPGA verification. 2008.05.12.
6311//
5f53d8ca
JC		 6312
6313// The following IO was for FPGA verification purpose. Added by Roger, 2008.09.11.
6314#if 0
6315 // 2008/08/19 MH From SD1 Jong, we must write some register for true PHY/MAC FPGA.
6316 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x30);
6317 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x30);
6318
6319 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
6320
6321 //write_nic_dword(Adapter, RCR, 0x817FF02F);
6322
6323 write_nic_dword(Adapter, rTxAGC_Mcs15_Mcs12, 0x06060606);
6324#endif
6325end:
6326return rtStatus;
6327}
6328
5f53d8ca
JC		 6329/* this configures registers for beacon tx and enables it via
6330 * rtl8192_beacon_tx_enable(). rtl8192_beacon_tx_disable() might
6331 * be used to stop beacon transmission
6332 */
6333#if 0
6334void rtl8192_start_tx_beacon(struct net_device *dev)
6335{
6336 int i;
6337 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
6338 u16 word;
6339 DMESG("Enabling beacon TX");
6340 //write_nic_byte(dev, TX_CONF,0xe6);// TX_CONF
6341 //rtl8192_init_beacon(dev);
6342 //set_nic_txring(dev);
6343// rtl8192_prepare_beacon(dev);
6344 rtl8192_irq_disable(dev);
6345// rtl8192_beacon_tx_enable(dev);
6346 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
6347 //write_nic_byte(dev,0x9d,0x20); //DMA Poll
6348 //write_nic_word(dev,0x7a,0);
6349 //write_nic_word(dev,0x7a,0x8000);
6350
6351
6352 word = read_nic_word(dev, BcnItv);
6353 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
6354 write_nic_word(dev, BcnItv, word);
6355
6356 write_nic_word(dev, AtimWnd,
6357 read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd);
6358
6359 word = read_nic_word(dev, BCN_INTR_ITV);
6360 word &= ~BCN_INTR_ITV_MASK;
6361
6362 //word |= priv->ieee80211->beacon_interval *
6363 // ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
6364 // FIXME:FIXME check if correct ^^ worked with 0x3e8;
6365
6366 write_nic_word(dev, BCN_INTR_ITV, word);
6367
6368 //write_nic_word(dev,0x2e,0xe002);
6369 //write_nic_dword(dev,0x30,0xb8c7832e);
6370 for(i=0; i<ETH_ALEN; i++)
6371 write_nic_byte(dev, BSSID+i, priv->ieee80211->beacon_cell_ssid[i]);
6372
6373// rtl8192_update_msr(dev);
6374
6375
6376 //write_nic_byte(dev,CONFIG4,3); /* !!!!!!!!!! */
6377
6378 rtl8192_set_mode(dev, EPROM_CMD_NORMAL);
6379
6380 rtl8192_irq_enable(dev);
6381
6382 /* VV !!!!!!!!!! VV*/
6383 /*
6384 rtl8192_set_mode(dev,EPROM_CMD_CONFIG);
6385 write_nic_byte(dev,0x9d,0x00);
6386 rtl8192_set_mode(dev,EPROM_CMD_NORMAL);
6387*/
6388}
6389#endif
6390/***************************************************************************
6391 -------------------------------NET STUFF---------------------------
6392***************************************************************************/
6393
6394static struct net_device_stats *rtl8192_stats(struct net_device *dev)
6395{
6396 struct r8192_priv *priv = ieee80211_priv(dev);
6397
6398 return &priv->ieee80211->stats;
6399}
6400
6401bool
6402HalTxCheckStuck819xUsb(
6403 struct net_device *dev
6404 )
6405{
6406 struct r8192_priv *priv = ieee80211_priv(dev);
6407 u16 RegTxCounter = read_nic_word(dev, 0x128);
6408 bool bStuck = FALSE;
6409 RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter);
6410 if(priv->TxCounter==RegTxCounter)
6411 bStuck = TRUE;
6412
6413 priv->TxCounter = RegTxCounter;
6414
6415 return bStuck;
6416}
6417
6418/*
6419* <Assumption: RT_TX_SPINLOCK is acquired.>
6420* First added: 2006.11.19 by emily
6421*/
6422RESET_TYPE
6423TxCheckStuck(struct net_device *dev)
6424{
6425 struct r8192_priv *priv = ieee80211_priv(dev);
6426 u8 QueueID;
6427// PRT_TCB pTcb;
6428// u8 ResetThreshold;
6429 bool bCheckFwTxCnt = false;
6430 //unsigned long flags;
6431
6432 //
6433 // Decide Stuch threshold according to current power save mode
6434 //
6435
6436// RT_TRACE(COMP_RESET, " ==> TxCheckStuck()\n");
6437// PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
6438// spin_lock_irqsave(&priv->ieee80211->lock,flags);
6439 for (QueueID = 0; QueueID<=BEACON_QUEUE;QueueID ++)
6440 {
6441 if(QueueID == TXCMD_QUEUE)
6442 continue;
6443#if 1
5f53d8ca 6444 if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0))
5f53d8ca
JC		 6445 continue;
6446#endif
6447
6448 bCheckFwTxCnt = true;
6449 }
6450// PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
6451// spin_unlock_irqrestore(&priv->ieee80211->lock,flags);
6452// RT_TRACE(COMP_RESET,"bCheckFwTxCnt is %d\n",bCheckFwTxCnt);
6453#if 1
6454 if(bCheckFwTxCnt)
6455 {
6456 if(HalTxCheckStuck819xUsb(dev))
6457 {
6458 RT_TRACE(COMP_RESET, "TxCheckStuck(): Fw indicates no Tx condition! \n");
6459 return RESET_TYPE_SILENT;
6460 }
6461 }
6462#endif
6463 return RESET_TYPE_NORESET;
6464}
6465
6466bool
6467HalRxCheckStuck819xUsb(struct net_device *dev)
6468{
6469 u16 RegRxCounter = read_nic_word(dev, 0x130);
6470 struct r8192_priv *priv = ieee80211_priv(dev);
6471 bool bStuck = FALSE;
6472//#ifdef RTL8192SU
6473
6474//#else
6475 static u8 rx_chk_cnt = 0;
6476 RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter);
6477 // If rssi is small, we should check rx for long time because of bad rx.
6478 // or maybe it will continuous silent reset every 2 seconds.
6479 rx_chk_cnt++;
6480 if(priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5))
6481 {
6482 rx_chk_cnt = 0; //high rssi, check rx stuck right now.
6483 }
6484 else if(priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High+5) &&
6485 ((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_40M) ||
6486 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_20M)) )
6487 {
6488 if(rx_chk_cnt < 2)
6489 {
6490 return bStuck;
6491 }
6492 else
6493 {
6494 rx_chk_cnt = 0;
6495 }
6496 }
6497 else if(((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_40M) ||
6498 (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_20M)) &&
6499 priv->undecorated_smoothed_pwdb >= VeryLowRSSI)
6500 {
6501 if(rx_chk_cnt < 4)
6502 {
6503 //DbgPrint("RSSI < %d && RSSI >= %d, no check this time \n", RateAdaptiveTH_Low, VeryLowRSSI);
6504 return bStuck;
6505 }
6506 else
6507 {
6508 rx_chk_cnt = 0;
6509 //DbgPrint("RSSI < %d && RSSI >= %d, check this time \n", RateAdaptiveTH_Low, VeryLowRSSI);
6510 }
6511 }
6512 else
6513 {
6514 if(rx_chk_cnt < 8)
6515 {
6516 //DbgPrint("RSSI <= %d, no check this time \n", VeryLowRSSI);
6517 return bStuck;
6518 }
6519 else
6520 {
6521 rx_chk_cnt = 0;
6522 //DbgPrint("RSSI <= %d, check this time \n", VeryLowRSSI);
6523 }
6524 }
6525//#endif
6526
6527 if(priv->RxCounter==RegRxCounter)
6528 bStuck = TRUE;
6529
6530 priv->RxCounter = RegRxCounter;
6531
6532 return bStuck;
6533}
6534
6535RESET_TYPE
6536RxCheckStuck(struct net_device *dev)
6537{
6538 struct r8192_priv *priv = ieee80211_priv(dev);
6539 //int i;
6540 bool bRxCheck = FALSE;
6541
6542// RT_TRACE(COMP_RESET," ==> RxCheckStuck()\n");
6543 //PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
6544
6545 if(priv->IrpPendingCount > 1)
6546 bRxCheck = TRUE;
6547 //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
6548
6549// RT_TRACE(COMP_RESET,"bRxCheck is %d \n",bRxCheck);
6550 if(bRxCheck)
6551 {
6552 if(HalRxCheckStuck819xUsb(dev))
6553 {
6554 RT_TRACE(COMP_RESET, "RxStuck Condition\n");
6555 return RESET_TYPE_SILENT;
6556 }
6557 }
6558 return RESET_TYPE_NORESET;
6559}
6560
6561
6562/**
6563* This function is called by Checkforhang to check whether we should ask OS to reset driver
6564*
6565* \param pAdapter The adapter context for this miniport
6566*
6567* Note:NIC with USB interface sholud not call this function because we cannot scan descriptor
6568* to judge whether there is tx stuck.
6569* Note: This function may be required to be rewrite for Vista OS.
6570* <<<Assumption: Tx spinlock has been acquired >>>
6571*
6572* 8185 and 8185b does not implement this function. This is added by Emily at 2006.11.24
6573*/
6574RESET_TYPE
6575rtl819x_ifcheck_resetornot(struct net_device *dev)
6576{
6577 struct r8192_priv *priv = ieee80211_priv(dev);
6578 RESET_TYPE TxResetType = RESET_TYPE_NORESET;
6579 RESET_TYPE RxResetType = RESET_TYPE_NORESET;
6580 RT_RF_POWER_STATE rfState;
6581
5f53d8ca 6582 return RESET_TYPE_NORESET;
5f53d8ca
JC		 6583
6584 rfState = priv->ieee80211->eRFPowerState;
6585
6586 TxResetType = TxCheckStuck(dev);
6587#if 1
6588 if( rfState != eRfOff ||
6589 /*ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FW_DOWNLOAD_FAILURE)) &&*/
6590 (priv->ieee80211->iw_mode != IW_MODE_ADHOC))
6591 {
6592 // If driver is in the status of firmware download failure , driver skips RF initialization and RF is
6593 // in turned off state. Driver should check whether Rx stuck and do silent reset. And
6594 // if driver is in firmware download failure status, driver should initialize RF in the following
6595 // silent reset procedure Emily, 2008.01.21
6596
6597 // Driver should not check RX stuck in IBSS mode because it is required to
6598 // set Check BSSID in order to send beacon, however, if check BSSID is
6599 // set, STA cannot hear any packet a all. Emily, 2008.04.12
6600 RxResetType = RxCheckStuck(dev);
6601 }
6602#endif
6603 if(TxResetType==RESET_TYPE_NORMAL || RxResetType==RESET_TYPE_NORMAL)
6604 return RESET_TYPE_NORMAL;
6605 else if(TxResetType==RESET_TYPE_SILENT || RxResetType==RESET_TYPE_SILENT){
6606 RT_TRACE(COMP_RESET,"%s():silent reset\n",__FUNCTION__);
6607 return RESET_TYPE_SILENT;
6608 }
6609 else
6610 return RESET_TYPE_NORESET;
6611
6612}
6613
6614void rtl8192_cancel_deferred_work(struct r8192_priv* priv);
6615int _rtl8192_up(struct net_device *dev);
6616int rtl8192_close(struct net_device *dev);
6617
6618
6619
6620void
6621CamRestoreAllEntry( struct net_device *dev)
6622{
6623 u8 EntryId = 0;
6624 struct r8192_priv *priv = ieee80211_priv(dev);
6625 u8* MacAddr = priv->ieee80211->current_network.bssid;
6626
6627 static u8 CAM_CONST_ADDR[4][6] = {
6628 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
6629 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
6630 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
6631 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}};
6632 static u8 CAM_CONST_BROAD[] =
6633 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
6634
6635 RT_TRACE(COMP_SEC, "CamRestoreAllEntry: \n");
6636
6637
6638 if ((priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP40)||
6639 (priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP104))
6640 {
6641
6642 for(EntryId=0; EntryId<4; EntryId++)
6643 {
6644 {
6645 MacAddr = CAM_CONST_ADDR[EntryId];
6646 setKey(dev,
6647 EntryId ,
6648 EntryId,
6649 priv->ieee80211->pairwise_key_type,
6650 MacAddr,
6651 0,
6652 NULL);
6653 }
6654 }
6655
6656 }
6657 else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_TKIP)
6658 {
6659
6660 {
6661 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
6662 setKey(dev,
6663 4,
6664 0,
6665 priv->ieee80211->pairwise_key_type,
6666 (u8*)dev->dev_addr,
6667 0,
6668 NULL);
6669 else
6670 setKey(dev,
6671 4,
6672 0,
6673 priv->ieee80211->pairwise_key_type,
6674 MacAddr,
6675 0,
6676 NULL);
6677 }
6678 }
6679 else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP)
6680 {
6681
6682 {
6683 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
6684 setKey(dev,
6685 4,
6686 0,
6687 priv->ieee80211->pairwise_key_type,
6688 (u8*)dev->dev_addr,
6689 0,
6690 NULL);
6691 else
6692 setKey(dev,
6693 4,
6694 0,
6695 priv->ieee80211->pairwise_key_type,
6696 MacAddr,
6697 0,
6698 NULL);
6699 }
6700 }
6701
6702
6703
6704 if(priv->ieee80211->group_key_type == KEY_TYPE_TKIP)
6705 {
6706 MacAddr = CAM_CONST_BROAD;
6707 for(EntryId=1 ; EntryId<4 ; EntryId++)
6708 {
6709 {
6710 setKey(dev,
6711 EntryId,
6712 EntryId,
6713 priv->ieee80211->group_key_type,
6714 MacAddr,
6715 0,
6716 NULL);
6717 }
6718 }
6719 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
6720 setKey(dev,
6721 0,
6722 0,
6723 priv->ieee80211->group_key_type,
6724 CAM_CONST_ADDR[0],
6725 0,
6726 NULL);
6727 }
6728 else if(priv->ieee80211->group_key_type == KEY_TYPE_CCMP)
6729 {
6730 MacAddr = CAM_CONST_BROAD;
6731 for(EntryId=1; EntryId<4 ; EntryId++)
6732 {
6733 {
6734 setKey(dev,
6735 EntryId ,
6736 EntryId,
6737 priv->ieee80211->group_key_type,
6738 MacAddr,
6739 0,
6740 NULL);
6741 }
6742 }
6743
6744 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
6745 setKey(dev,
6746 0 ,
6747 0,
6748 priv->ieee80211->group_key_type,
6749 CAM_CONST_ADDR[0],
6750 0,
6751 NULL);
6752 }
6753}
6754//////////////////////////////////////////////////////////////
6755// This function is used to fix Tx/Rx stop bug temporarily.
6756// This function will do "system reset" to NIC when Tx or Rx is stuck.
6757// The method checking Tx/Rx stuck of this function is supported by FW,
6758// which reports Tx and Rx counter to register 0x128 and 0x130.
6759//////////////////////////////////////////////////////////////
6760void
6761rtl819x_ifsilentreset(struct net_device *dev)
6762{
6763 //OCTET_STRING asocpdu;
6764 struct r8192_priv *priv = ieee80211_priv(dev);
6765 u8 reset_times = 0;
6766 int reset_status = 0;
6767 struct ieee80211_device *ieee = priv->ieee80211;
6768
6769
6770 // 2007.07.20. If we need to check CCK stop, please uncomment this line.
6771 //bStuck = Adapter->HalFunc.CheckHWStopHandler(Adapter);
6772
6773 if(priv->ResetProgress==RESET_TYPE_NORESET)
6774 {
6775RESET_START:
6776
6777 RT_TRACE(COMP_RESET,"=========>Reset progress!! \n");
6778
6779 // Set the variable for reset.
6780 priv->ResetProgress = RESET_TYPE_SILENT;
6781// rtl8192_close(dev);
6782#if 1
6783 down(&priv->wx_sem);
6784 if(priv->up == 0)
6785 {
6786 RT_TRACE(COMP_ERR,"%s():the driver is not up! return\n",__FUNCTION__);
6787 up(&priv->wx_sem);
6788 return ;
6789 }
6790 priv->up = 0;
6791 RT_TRACE(COMP_RESET,"%s():======>start to down the driver\n",__FUNCTION__);
6792// if(!netif_queue_stopped(dev))
6793// netif_stop_queue(dev);
6794
6795 rtl8192_rtx_disable(dev);
6796 rtl8192_cancel_deferred_work(priv);
6797 deinit_hal_dm(dev);
6798 del_timer_sync(&priv->watch_dog_timer);
6799
6800 ieee->sync_scan_hurryup = 1;
6801 if(ieee->state == IEEE80211_LINKED)
6802 {
6803 down(&ieee->wx_sem);
6804 printk("ieee->state is IEEE80211_LINKED\n");
6805 ieee80211_stop_send_beacons(priv->ieee80211);
6806 del_timer_sync(&ieee->associate_timer);
5f53d8ca 6807 cancel_delayed_work(&ieee->associate_retry_wq);
5f53d8ca
JC		 6808 ieee80211_stop_scan(ieee);
6809 netif_carrier_off(dev);
6810 up(&ieee->wx_sem);
6811 }
6812 else{
6813 printk("ieee->state is NOT LINKED\n");
6814 ieee80211_softmac_stop_protocol(priv->ieee80211); }
6815 up(&priv->wx_sem);
6816 RT_TRACE(COMP_RESET,"%s():<==========down process is finished\n",__FUNCTION__);
6817 //rtl8192_irq_disable(dev);
6818 RT_TRACE(COMP_RESET,"%s():===========>start to up the driver\n",__FUNCTION__);
6819 reset_status = _rtl8192_up(dev);
6820
6821 RT_TRACE(COMP_RESET,"%s():<===========up process is finished\n",__FUNCTION__);
6822 if(reset_status == -EAGAIN)
6823 {
6824 if(reset_times < 3)
6825 {
6826 reset_times++;
6827 goto RESET_START;
6828 }
6829 else
6830 {
6831 RT_TRACE(COMP_ERR," ERR!!! %s(): Reset Failed!!\n", __FUNCTION__);
6832 }
6833 }
6834#endif
6835 ieee->is_silent_reset = 1;
6836#if 1
6837 EnableHWSecurityConfig8192(dev);
6838#if 1
6839 if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA)
6840 {
6841 ieee->set_chan(ieee->dev, ieee->current_network.channel);
6842
6843#if 1
5f53d8ca 6844 queue_work(ieee->wq, &ieee->associate_complete_wq);
5f53d8ca
JC		 6845#endif
6846
6847 }
6848 else if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_ADHOC)
6849 {
6850 ieee->set_chan(ieee->dev, ieee->current_network.channel);
6851 ieee->link_change(ieee->dev);
6852
6853 // notify_wx_assoc_event(ieee);
6854
6855 ieee80211_start_send_beacons(ieee);
6856
6857 if (ieee->data_hard_resume)
6858 ieee->data_hard_resume(ieee->dev);
6859 netif_carrier_on(ieee->dev);
6860 }
6861#endif
6862
6863 CamRestoreAllEntry(dev);
6864
6865 priv->ResetProgress = RESET_TYPE_NORESET;
6866 priv->reset_count++;
6867
6868 priv->bForcedSilentReset =false;
6869 priv->bResetInProgress = false;
6870
6871 // For test --> force write UFWP.
6872 write_nic_byte(dev, UFWP, 1);
6873 RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count);
6874#endif
6875 }
6876}
6877
6878void CAM_read_entry(
6879 struct net_device *dev,
6880 u32 iIndex
6881)
6882{
6883 u32 target_command=0;
6884 u32 target_content=0;
6885 u8 entry_i=0;
6886 u32 ulStatus;
6887 s32 i=100;
6888// printk("=======>start read CAM\n");
6889 for(entry_i=0;entry_i<CAM_CONTENT_COUNT;entry_i++)
6890 {
6891 // polling bit, and No Write enable, and address
6892 target_command= entry_i+CAM_CONTENT_COUNT*iIndex;
6893 target_command= target_command | BIT31;
6894
6895 //Check polling bit is clear
6896// mdelay(1);
6897#if 1
6898 while((i--)>=0)
6899 {
6900 ulStatus = read_nic_dword(dev, RWCAM);
6901 if(ulStatus & BIT31){
6902 continue;
6903 }
6904 else{
6905 break;
6906 }
6907 }
6908#endif
6909 write_nic_dword(dev, RWCAM, target_command);
6910 RT_TRACE(COMP_SEC,"CAM_read_entry(): WRITE A0: %x \n",target_command);
6911 // printk("CAM_read_entry(): WRITE A0: %lx \n",target_command);
6912 target_content = read_nic_dword(dev, RCAMO);
6913 RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A8: %x \n",target_content);
6914 // printk("CAM_read_entry(): WRITE A8: %lx \n",target_content);
6915 }
6916 printk("\n");
6917}
6918
6919void rtl819x_update_rxcounts(
6920 struct r8192_priv *priv,
6921 u32* TotalRxBcnNum,
6922 u32* TotalRxDataNum
6923)
6924{
6925 u16 SlotIndex;
6926 u8 i;
6927
6928 *TotalRxBcnNum = 0;
6929 *TotalRxDataNum = 0;
6930
6931 SlotIndex = (priv->ieee80211->LinkDetectInfo.SlotIndex++)%(priv->ieee80211->LinkDetectInfo.SlotNum);
6932 priv->ieee80211->LinkDetectInfo.RxBcnNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod;
6933 priv->ieee80211->LinkDetectInfo.RxDataNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod;
6934 for( i=0; i<priv->ieee80211->LinkDetectInfo.SlotNum; i++ ){
6935 *TotalRxBcnNum += priv->ieee80211->LinkDetectInfo.RxBcnNum[i];
6936 *TotalRxDataNum += priv->ieee80211->LinkDetectInfo.RxDataNum[i];
6937 }
6938}
6939
5f53d8ca
JC		 6940extern void rtl819x_watchdog_wqcallback(struct work_struct *work)
6941{
6942 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
6943 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,watch_dog_wq);
6944 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 6945 struct ieee80211_device* ieee = priv->ieee80211;
6946 RESET_TYPE ResetType = RESET_TYPE_NORESET;
6947 static u8 check_reset_cnt=0;
6948 bool bBusyTraffic = false;
6949
6950 if(!priv->up)
6951 return;
6952 hal_dm_watchdog(dev);
6953
6954 {//to get busy traffic condition
6955 if(ieee->state == IEEE80211_LINKED)
6956 {
6957 //windows mod 666 to 100.
6958 //if( ieee->LinkDetectInfo.NumRxOkInPeriod> 666 ||
6959 // ieee->LinkDetectInfo.NumTxOkInPeriod> 666 ) {
6960 if( ieee->LinkDetectInfo.NumRxOkInPeriod> 100 ||
6961 ieee->LinkDetectInfo.NumTxOkInPeriod> 100 ) {
6962 bBusyTraffic = true;
6963 }
6964 ieee->LinkDetectInfo.NumRxOkInPeriod = 0;
6965 ieee->LinkDetectInfo.NumTxOkInPeriod = 0;
6966 ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
6967 }
6968 }
6969 //added by amy for AP roaming
6970 {
6971 if(priv->ieee80211->state == IEEE80211_LINKED && priv->ieee80211->iw_mode == IW_MODE_INFRA)
6972 {
6973 u32 TotalRxBcnNum = 0;
6974 u32 TotalRxDataNum = 0;
6975
6976 rtl819x_update_rxcounts(priv, &TotalRxBcnNum, &TotalRxDataNum);
6977 if((TotalRxBcnNum+TotalRxDataNum) == 0)
6978 {
6979 #ifdef TODO
6980 if(rfState == eRfOff)
6981 RT_TRACE(COMP_ERR,"========>%s()\n",__FUNCTION__);
6982 #endif
6983 printk("===>%s(): AP is power off,connect another one\n",__FUNCTION__);
6984 // Dot11d_Reset(dev);
6985 priv->ieee80211->state = IEEE80211_ASSOCIATING;
6986 notify_wx_assoc_event(priv->ieee80211);
6987 RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid);
6988 ieee->is_roaming = true;
6989 priv->ieee80211->link_change(dev);
5f53d8ca 6990 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
5f53d8ca
JC		 6991 }
6992 }
6993 priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod=0;
6994 priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod=0;
6995 }
6996// CAM_read_entry(dev,4);
6997 //check if reset the driver
6998 if(check_reset_cnt++ >= 3 && !ieee->is_roaming)
6999 {
7000 ResetType = rtl819x_ifcheck_resetornot(dev);
7001 check_reset_cnt = 3;
7002 //DbgPrint("Start to check silent reset\n");
7003 }
7004 // RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType);
7005#if 1
7006 if( (priv->force_reset) || (priv->ResetProgress==RESET_TYPE_NORESET &&
7007 (priv->bForcedSilentReset ||
7008 (!priv->bDisableNormalResetCheck && ResetType==RESET_TYPE_SILENT)))) // This is control by OID set in Pomelo
7009 {
7010 RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType);
7011 rtl819x_ifsilentreset(dev);
7012 }
7013#endif
7014 priv->force_reset = false;
7015 priv->bForcedSilentReset = false;
7016 priv->bResetInProgress = false;
7017 RT_TRACE(COMP_TRACE, " <==RtUsbCheckForHangWorkItemCallback()\n");
7018
7019}
7020
7021void watch_dog_timer_callback(unsigned long data)
7022{
7023 struct r8192_priv *priv = ieee80211_priv((struct net_device *) data);
7024 //printk("===============>watch_dog timer\n");
5f53d8ca 7025 queue_delayed_work(priv->priv_wq,&priv->watch_dog_wq, 0);
5f53d8ca
JC		 7026 mod_timer(&priv->watch_dog_timer, jiffies + MSECS(IEEE80211_WATCH_DOG_TIME));
7027#if 0
7028 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
7029 add_timer(&priv->watch_dog_timer);
7030#endif
7031}
7032int _rtl8192_up(struct net_device *dev)
7033{
7034 struct r8192_priv *priv = ieee80211_priv(dev);
7035 //int i;
7036 int init_status = 0;
7037 priv->up=1;
7038 priv->ieee80211->ieee_up=1;
7039 RT_TRACE(COMP_INIT, "Bringing up iface");
7040 init_status = priv->ops->rtl819x_adapter_start(dev);
7041 if(!init_status)
7042 {
7043 RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n", __FUNCTION__);
7044 priv->up=priv->ieee80211->ieee_up = 0;
7045 return -EAGAIN;
7046 }
7047 RT_TRACE(COMP_INIT, "start adapter finished\n");
7048 rtl8192_rx_enable(dev);
7049// rtl8192_tx_enable(dev);
7050 if(priv->ieee80211->state != IEEE80211_LINKED)
7051 ieee80211_softmac_start_protocol(priv->ieee80211);
7052 ieee80211_reset_queue(priv->ieee80211);
7053 watch_dog_timer_callback((unsigned long) dev);
7054 if(!netif_queue_stopped(dev))
7055 netif_start_queue(dev);
7056 else
7057 netif_wake_queue(dev);
7058
7059 /*
7060 * Make sure that drop_unencrypted is initialized as "0"
7061 * No packets will be sent in non-security mode if we had set drop_unencrypted.
7062 * ex, After kill wpa_supplicant process, make the driver up again.
7063 * drop_unencrypted remains as "1", which is set by wpa_supplicant. 2008/12/04.john
7064 */
7065 priv->ieee80211->drop_unencrypted = 0;
7066
7067 return 0;
7068}
7069
7070
7071int rtl8192_open(struct net_device *dev)
7072{
7073 struct r8192_priv *priv = ieee80211_priv(dev);
7074 int ret;
7075 down(&priv->wx_sem);
7076 ret = rtl8192_up(dev);
7077 up(&priv->wx_sem);
7078 return ret;
7079
7080}
7081
7082
7083int rtl8192_up(struct net_device *dev)
7084{
7085 struct r8192_priv *priv = ieee80211_priv(dev);
7086
7087 if (priv->up == 1) return -1;
7088
7089 return _rtl8192_up(dev);
7090}
7091
7092
7093int rtl8192_close(struct net_device *dev)
7094{
7095 struct r8192_priv *priv = ieee80211_priv(dev);
7096 int ret;
7097
7098 down(&priv->wx_sem);
7099
7100 ret = rtl8192_down(dev);
7101
7102 up(&priv->wx_sem);
7103
7104 return ret;
7105
7106}
7107
7108int rtl8192_down(struct net_device *dev)
7109{
7110 struct r8192_priv *priv = ieee80211_priv(dev);
7111 int i;
7112
7113 if (priv->up == 0) return -1;
7114
7115 priv->up=0;
7116 priv->ieee80211->ieee_up = 0;
7117 RT_TRACE(COMP_DOWN, "==========>%s()\n", __FUNCTION__);
7118/* FIXME */
7119 if (!netif_queue_stopped(dev))
7120 netif_stop_queue(dev);
7121
7122 rtl8192_rtx_disable(dev);
7123 //rtl8192_irq_disable(dev);
7124
7125 /* Tx related queue release */
7126 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
7127 skb_queue_purge(&priv->ieee80211->skb_waitQ [i]);
7128 }
7129 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
7130 skb_queue_purge(&priv->ieee80211->skb_aggQ [i]);
7131 }
7132
7133 for(i = 0; i < MAX_QUEUE_SIZE; i++) {
7134 skb_queue_purge(&priv->ieee80211->skb_drv_aggQ [i]);
7135 }
7136
7137 //as cancel_delayed_work will del work->timer, so if work is not definedas struct delayed_work, it will corrupt
7138// flush_scheduled_work();
7139 rtl8192_cancel_deferred_work(priv);
7140 deinit_hal_dm(dev);
7141 del_timer_sync(&priv->watch_dog_timer);
7142
7143
7144 ieee80211_softmac_stop_protocol(priv->ieee80211);
7145 memset(&priv->ieee80211->current_network, 0 , offsetof(struct ieee80211_network, list));
7146 RT_TRACE(COMP_DOWN, "<==========%s()\n", __FUNCTION__);
7147
7148 return 0;
7149}
7150
7151
7152void rtl8192_commit(struct net_device *dev)
7153{
7154 struct r8192_priv *priv = ieee80211_priv(dev);
7155 int reset_status = 0;
7156 //u8 reset_times = 0;
7157 if (priv->up == 0) return ;
7158 priv->up = 0;
7159
7160 rtl8192_cancel_deferred_work(priv);
7161 del_timer_sync(&priv->watch_dog_timer);
7162 //cancel_delayed_work(&priv->SwChnlWorkItem);
7163
7164 ieee80211_softmac_stop_protocol(priv->ieee80211);
7165
7166 //rtl8192_irq_disable(dev);
7167 rtl8192_rtx_disable(dev);
7168 reset_status = _rtl8192_up(dev);
7169
7170}
7171
7172/*
7173void rtl8192_restart(struct net_device *dev)
7174{
7175 struct r8192_priv *priv = ieee80211_priv(dev);
7176*/
5f53d8ca
JC		 7177void rtl8192_restart(struct work_struct *work)
7178{
7179 struct r8192_priv *priv = container_of(work, struct r8192_priv, reset_wq);
7180 struct net_device *dev = priv->ieee80211->dev;
5f53d8ca
JC		 7181
7182 down(&priv->wx_sem);
7183
7184 rtl8192_commit(dev);
7185
7186 up(&priv->wx_sem);
7187}
7188
7189static void r8192_set_multicast(struct net_device *dev)
7190{
7191 struct r8192_priv *priv = ieee80211_priv(dev);
7192 short promisc;
7193
7194 //down(&priv->wx_sem);
7195
7196 /* FIXME FIXME */
7197
7198 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
7199
7200 if (promisc != priv->promisc)
7201 // rtl8192_commit(dev);
7202
7203 priv->promisc = promisc;
7204
7205 //schedule_work(&priv->reset_wq);
7206 //up(&priv->wx_sem);
7207}
7208
7209
7210int r8192_set_mac_adr(struct net_device *dev, void *mac)
7211{
7212 struct r8192_priv *priv = ieee80211_priv(dev);
7213 struct sockaddr *addr = mac;
7214
7215 down(&priv->wx_sem);
7216
7217 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
7218
5f53d8ca 7219 schedule_work(&priv->reset_wq);
1ec9e48d 7220
5f53d8ca
JC		 7221 up(&priv->wx_sem);
7222
7223 return 0;
7224}
7225
7226/* based on ipw2200 driver */
7227int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
7228{
7229 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
7230 struct iwreq *wrq = (struct iwreq *)rq;
7231 int ret=-1;
7232 struct ieee80211_device *ieee = priv->ieee80211;
7233 u32 key[4];
7234 u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
7235 u8 zero_addr[6] = {0};
7236 struct iw_point *p = &wrq->u.data;
7237 struct ieee_param *ipw = NULL;//(struct ieee_param *)wrq->u.data.pointer;
7238
7239 down(&priv->wx_sem);
7240
7241
7242 if (p->length < sizeof(struct ieee_param) || !p->pointer){
7243 ret = -EINVAL;
7244 goto out;
7245 }
7246
7247 ipw = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL);
7248 if (ipw == NULL){
7249 ret = -ENOMEM;
7250 goto out;
7251 }
7252 if (copy_from_user(ipw, p->pointer, p->length)) {
7253 kfree(ipw);
7254 ret = -EFAULT;
7255 goto out;
7256 }
7257
7258 switch (cmd) {
7259 case RTL_IOCTL_WPA_SUPPLICANT:
7260 //parse here for HW security
7261 if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION)
7262 {
7263 if (ipw->u.crypt.set_tx)
7264 {
7265 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
7266 ieee->pairwise_key_type = KEY_TYPE_CCMP;
7267 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
7268 ieee->pairwise_key_type = KEY_TYPE_TKIP;
7269 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0)
7270 {
7271 if (ipw->u.crypt.key_len == 13)
7272 ieee->pairwise_key_type = KEY_TYPE_WEP104;
7273 else if (ipw->u.crypt.key_len == 5)
7274 ieee->pairwise_key_type = KEY_TYPE_WEP40;
7275 }
7276 else
7277 ieee->pairwise_key_type = KEY_TYPE_NA;
7278
7279 if (ieee->pairwise_key_type)
7280 {
7281 // FIXME:these two lines below just to fix ipw interface bug, that is, it will never set mode down to driver. So treat it as ADHOC mode, if no association procedure. WB. 2009.02.04
7282 if (memcmp(ieee->ap_mac_addr, zero_addr, 6) == 0)
7283 ieee->iw_mode = IW_MODE_ADHOC;
7284 memcpy((u8*)key, ipw->u.crypt.key, 16);
7285 EnableHWSecurityConfig8192(dev);
7286 //we fill both index entry and 4th entry for pairwise key as in IPW interface, adhoc will only get here, so we need index entry for its default key serching!
7287 //added by WB.
7288 setKey(dev, 4, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
7289 if (ieee->iw_mode == IW_MODE_ADHOC)
7290 setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
7291 }
7292 }
7293 else //if (ipw->u.crypt.idx) //group key use idx > 0
7294 {
7295 memcpy((u8*)key, ipw->u.crypt.key, 16);
7296 if (strcmp(ipw->u.crypt.alg, "CCMP") == 0)
7297 ieee->group_key_type= KEY_TYPE_CCMP;
7298 else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0)
7299 ieee->group_key_type = KEY_TYPE_TKIP;
7300 else if (strcmp(ipw->u.crypt.alg, "WEP") == 0)
7301 {
7302 if (ipw->u.crypt.key_len == 13)
7303 ieee->group_key_type = KEY_TYPE_WEP104;
7304 else if (ipw->u.crypt.key_len == 5)
7305 ieee->group_key_type = KEY_TYPE_WEP40;
7306 }
7307 else
7308 ieee->group_key_type = KEY_TYPE_NA;
7309
7310 if (ieee->group_key_type)
7311 {
7312 setKey( dev,
7313 ipw->u.crypt.idx,
7314 ipw->u.crypt.idx, //KeyIndex
7315 ieee->group_key_type, //KeyType
7316 broadcast_addr, //MacAddr
7317 0, //DefaultKey
7318 key); //KeyContent
7319 }
7320 }
7321 }
7322#ifdef JOHN_HWSEC_DEBUG
7323 //john's test 0711
7324 printk("@@ wrq->u pointer = ");
7325 for(i=0;i<wrq->u.data.length;i++){
7326 if(i%10==0) printk("\n");
7327 printk( "%8x|", ((u32*)wrq->u.data.pointer)[i] );
7328 }
7329 printk("\n");
7330#endif /*JOHN_HWSEC_DEBUG*/
7331 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
7332 break;
7333
7334 default:
7335 ret = -EOPNOTSUPP;
7336 break;
7337 }
7338 kfree(ipw);
7339 ipw = NULL;
7340out:
7341 up(&priv->wx_sem);
7342 return ret;
7343}
7344
5f53d8ca
JC		 7345u8 rtl8192SU_HwRateToMRate(bool bIsHT, u8 rate,bool bFirstAMPDU)
7346{
7347
7348 u8 ret_rate = 0x02;
7349
7350 if( bFirstAMPDU )
7351 {
7352 if(!bIsHT)
7353 {
7354 switch(rate)
7355 {
7356
7357 case DESC92S_RATE1M: ret_rate = MGN_1M; break;
7358 case DESC92S_RATE2M: ret_rate = MGN_2M; break;
7359 case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break;
7360 case DESC92S_RATE11M: ret_rate = MGN_11M; break;
7361 case DESC92S_RATE6M: ret_rate = MGN_6M; break;
7362 case DESC92S_RATE9M: ret_rate = MGN_9M; break;
7363 case DESC92S_RATE12M: ret_rate = MGN_12M; break;
7364 case DESC92S_RATE18M: ret_rate = MGN_18M; break;
7365 case DESC92S_RATE24M: ret_rate = MGN_24M; break;
7366 case DESC92S_RATE36M: ret_rate = MGN_36M; break;
7367 case DESC92S_RATE48M: ret_rate = MGN_48M; break;
7368 case DESC92S_RATE54M: ret_rate = MGN_54M; break;
7369
7370 default:
7371 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
7372 break;
7373 }
7374 }
7375 else
7376 {
7377 switch(rate)
7378 {
7379
7380 case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break;
7381 case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break;
7382 case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break;
7383 case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break;
7384 case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break;
7385 case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break;
7386 case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break;
7387 case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break;
7388 case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break;
7389 case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break;
7390 case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break;
7391 case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break;
7392 case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break;
7393 case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break;
7394 case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break;
7395 case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break;
7396 case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break;
7397
7398 default:
7399 RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT );
7400 break;
7401 }
7402
7403 }
7404 }
7405 else
7406 {
7407 switch(rate)
7408 {
7409
7410 case DESC92S_RATE1M: ret_rate = MGN_1M; break;
7411 case DESC92S_RATE2M: ret_rate = MGN_2M; break;
7412 case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break;
7413 case DESC92S_RATE11M: ret_rate = MGN_11M; break;
7414 case DESC92S_RATE6M: ret_rate = MGN_6M; break;
7415 case DESC92S_RATE9M: ret_rate = MGN_9M; break;
7416 case DESC92S_RATE12M: ret_rate = MGN_12M; break;
7417 case DESC92S_RATE18M: ret_rate = MGN_18M; break;
7418 case DESC92S_RATE24M: ret_rate = MGN_24M; break;
7419 case DESC92S_RATE36M: ret_rate = MGN_36M; break;
7420 case DESC92S_RATE48M: ret_rate = MGN_48M; break;
7421 case DESC92S_RATE54M: ret_rate = MGN_54M; break;
7422 case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break;
7423 case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break;
7424 case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break;
7425 case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break;
7426 case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break;
7427 case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break;
7428 case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break;
7429 case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break;
7430 case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break;
7431 case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break;
7432 case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break;
7433 case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break;
7434 case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break;
7435 case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break;
7436 case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break;
7437 case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break;
7438 case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break;
7439
7440 default:
7441 RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT );
7442 break;
7443 }
7444 }
7445 return ret_rate;
7446}
5f53d8ca
JC		 7447
7448u8 HwRateToMRate90(bool bIsHT, u8 rate)
7449{
7450 u8 ret_rate = 0xff;
7451
7452 if(!bIsHT) {
7453 switch(rate) {
7454 case DESC90_RATE1M: ret_rate = MGN_1M; break;
7455 case DESC90_RATE2M: ret_rate = MGN_2M; break;
7456 case DESC90_RATE5_5M: ret_rate = MGN_5_5M; break;
7457 case DESC90_RATE11M: ret_rate = MGN_11M; break;
7458 case DESC90_RATE6M: ret_rate = MGN_6M; break;
7459 case DESC90_RATE9M: ret_rate = MGN_9M; break;
7460 case DESC90_RATE12M: ret_rate = MGN_12M; break;
7461 case DESC90_RATE18M: ret_rate = MGN_18M; break;
7462 case DESC90_RATE24M: ret_rate = MGN_24M; break;
7463 case DESC90_RATE36M: ret_rate = MGN_36M; break;
7464 case DESC90_RATE48M: ret_rate = MGN_48M; break;
7465 case DESC90_RATE54M: ret_rate = MGN_54M; break;
7466
7467 default:
7468 ret_rate = 0xff;
7469 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
7470 break;
7471 }
7472
7473 } else {
7474 switch(rate) {
7475 case DESC90_RATEMCS0: ret_rate = MGN_MCS0; break;
7476 case DESC90_RATEMCS1: ret_rate = MGN_MCS1; break;
7477 case DESC90_RATEMCS2: ret_rate = MGN_MCS2; break;
7478 case DESC90_RATEMCS3: ret_rate = MGN_MCS3; break;
7479 case DESC90_RATEMCS4: ret_rate = MGN_MCS4; break;
7480 case DESC90_RATEMCS5: ret_rate = MGN_MCS5; break;
7481 case DESC90_RATEMCS6: ret_rate = MGN_MCS6; break;
7482 case DESC90_RATEMCS7: ret_rate = MGN_MCS7; break;
7483 case DESC90_RATEMCS8: ret_rate = MGN_MCS8; break;
7484 case DESC90_RATEMCS9: ret_rate = MGN_MCS9; break;
7485 case DESC90_RATEMCS10: ret_rate = MGN_MCS10; break;
7486 case DESC90_RATEMCS11: ret_rate = MGN_MCS11; break;
7487 case DESC90_RATEMCS12: ret_rate = MGN_MCS12; break;
7488 case DESC90_RATEMCS13: ret_rate = MGN_MCS13; break;
7489 case DESC90_RATEMCS14: ret_rate = MGN_MCS14; break;
7490 case DESC90_RATEMCS15: ret_rate = MGN_MCS15; break;
7491 case DESC90_RATEMCS32: ret_rate = (0x80|0x20); break;
7492
7493 default:
7494 ret_rate = 0xff;
7495 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT);
7496 break;
7497 }
7498 }
7499
7500 return ret_rate;
7501}
7502
7503/**
7504 * Function: UpdateRxPktTimeStamp
7505 * Overview: Recored down the TSF time stamp when receiving a packet
7506 *
7507 * Input:
7508 * PADAPTER Adapter
7509 * PRT_RFD pRfd,
7510 *
7511 * Output:
7512 * PRT_RFD pRfd
7513 * (pRfd->Status.TimeStampHigh is updated)
7514 * (pRfd->Status.TimeStampLow is updated)
7515 * Return:
7516 * None
7517 */
7518void UpdateRxPktTimeStamp8190 (struct net_device *dev, struct ieee80211_rx_stats *stats)
7519{
7520 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
7521
7522 if(stats->bIsAMPDU && !stats->bFirstMPDU) {
7523 stats->mac_time[0] = priv->LastRxDescTSFLow;
7524 stats->mac_time[1] = priv->LastRxDescTSFHigh;
7525 } else {
7526 priv->LastRxDescTSFLow = stats->mac_time[0];
7527 priv->LastRxDescTSFHigh = stats->mac_time[1];
7528 }
7529}
7530
7531//by amy 080606
7532
7533long rtl819x_translate_todbm(u8 signal_strength_index )// 0-100 index.
7534{
7535 long signal_power; // in dBm.
7536
7537 // Translate to dBm (x=0.5y-95).
7538 signal_power = (long)((signal_strength_index + 1) >> 1);
7539 signal_power -= 95;
7540
7541 return signal_power;
7542}
7543
7544
7545/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to
7546 be a local static. Otherwise, it may increase when we return from S3/S4. The
7547 value will be kept in memory or disk. We must delcare the value in adapter
7548 and it will be reinitialized when return from S3/S4. */
7549void rtl8192_process_phyinfo(struct r8192_priv * priv,u8* buffer, struct ieee80211_rx_stats * pprevious_stats, struct ieee80211_rx_stats * pcurrent_stats)
7550{
7551 bool bcheck = false;
7552 u8 rfpath;
7553 u32 nspatial_stream, tmp_val;
7554 //u8 i;
7555 static u32 slide_rssi_index=0, slide_rssi_statistics=0;
7556 static u32 slide_evm_index=0, slide_evm_statistics=0;
7557 static u32 last_rssi=0, last_evm=0;
7558
7559 static u32 slide_beacon_adc_pwdb_index=0, slide_beacon_adc_pwdb_statistics=0;
7560 static u32 last_beacon_adc_pwdb=0;
7561
7562 struct ieee80211_hdr_3addr *hdr;
7563 u16 sc ;
7564 unsigned int frag,seq;
7565 hdr = (struct ieee80211_hdr_3addr *)buffer;
7566 sc = le16_to_cpu(hdr->seq_ctl);
7567 frag = WLAN_GET_SEQ_FRAG(sc);
7568 seq = WLAN_GET_SEQ_SEQ(sc);
7569 //cosa add 04292008 to record the sequence number
7570 pcurrent_stats->Seq_Num = seq;
7571 //
7572 // Check whether we should take the previous packet into accounting
7573 //
7574 if(!pprevious_stats->bIsAMPDU)
7575 {
7576 // if previous packet is not aggregated packet
7577 bcheck = true;
7578 }else
7579 {
7580 #if 0
7581 // if previous packet is aggregated packet, and current packet
7582 // (1) is not AMPDU
7583 // (2) is the first packet of one AMPDU
7584 // that means the previous packet is the last one aggregated packet
7585 if( !pcurrent_stats->bIsAMPDU || pcurrent_stats->bFirstMPDU)
7586 bcheck = true;
7587 #endif
7588 }
7589
7590
7591 if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX)
7592 {
7593 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
7594 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
7595 priv->stats.slide_rssi_total -= last_rssi;
7596 }
7597 priv->stats.slide_rssi_total += pprevious_stats->SignalStrength;
7598
7599 priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength;
7600 if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
7601 slide_rssi_index = 0;
7602
7603 // <1> Showed on UI for user, in dbm
7604 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
7605 priv->stats.signal_strength = rtl819x_translate_todbm((u8)tmp_val);
7606 pcurrent_stats->rssi = priv->stats.signal_strength;
7607 //
7608 // If the previous packet does not match the criteria, neglect it
7609 //
7610 if(!pprevious_stats->bPacketMatchBSSID)
7611 {
7612 if(!pprevious_stats->bToSelfBA)
7613 return;
7614 }
7615
7616 if(!bcheck)
7617 return;
7618
7619
7620 //rtl8190_process_cck_rxpathsel(priv,pprevious_stats);//only rtl8190 supported
7621
7622 //
7623 // Check RSSI
7624 //
7625 priv->stats.num_process_phyinfo++;
7626
7627 /* record the general signal strength to the sliding window. */
7628
7629
7630 // <2> Showed on UI for engineering
7631 // hardware does not provide rssi information for each rf path in CCK
7632 if(!pprevious_stats->bIsCCK && (pprevious_stats->bPacketToSelf || pprevious_stats->bToSelfBA))
7633 {
7634 for (rfpath = RF90_PATH_A; rfpath < priv->NumTotalRFPath; rfpath++)
7635 {
7636 if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, rfpath))
7637 continue;
7638
7639 //Fixed by Jacken 2008-03-20
7640 if(priv->stats.rx_rssi_percentage[rfpath] == 0)
7641 {
7642 priv->stats.rx_rssi_percentage[rfpath] = pprevious_stats->RxMIMOSignalStrength[rfpath];
7643 //DbgPrint("MIMO RSSI initialize \n");
7644 }
7645 if(pprevious_stats->RxMIMOSignalStrength[rfpath] > priv->stats.rx_rssi_percentage[rfpath])
7646 {
7647 priv->stats.rx_rssi_percentage[rfpath] =
7648 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
7649 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
7650 priv->stats.rx_rssi_percentage[rfpath] = priv->stats.rx_rssi_percentage[rfpath] + 1;
7651 }
7652 else
7653 {
7654 priv->stats.rx_rssi_percentage[rfpath] =
7655 ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) +
7656 (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor);
7657 }
7658 RT_TRACE(COMP_DBG,"priv->stats.rx_rssi_percentage[rfPath] = %d \n" ,priv->stats.rx_rssi_percentage[rfpath] );
7659 }
7660 }
7661
7662
7663 //
7664 // Check PWDB.
7665 //
7666 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
7667 pprevious_stats->bIsCCK? "CCK": "OFDM",
7668 pprevious_stats->RxPWDBAll);
7669
7670 if(pprevious_stats->bPacketBeacon)
7671 {
7672/* record the beacon pwdb to the sliding window. */
7673 if(slide_beacon_adc_pwdb_statistics++ >= PHY_Beacon_RSSI_SLID_WIN_MAX)
7674 {
7675 slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX;
7676 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index];
7677 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
7678 //DbgPrint("slide_beacon_adc_pwdb_index = %d, last_beacon_adc_pwdb = %d, Adapter->RxStats.Slide_Beacon_Total = %d\n",
7679 // slide_beacon_adc_pwdb_index, last_beacon_adc_pwdb, Adapter->RxStats.Slide_Beacon_Total);
7680 }
7681 priv->stats.Slide_Beacon_Total += pprevious_stats->RxPWDBAll;
7682 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = pprevious_stats->RxPWDBAll;
7683 //DbgPrint("slide_beacon_adc_pwdb_index = %d, pPreviousRfd->Status.RxPWDBAll = %d\n", slide_beacon_adc_pwdb_index, pPreviousRfd->Status.RxPWDBAll);
7684 slide_beacon_adc_pwdb_index++;
7685 if(slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
7686 slide_beacon_adc_pwdb_index = 0;
7687 pprevious_stats->RxPWDBAll = priv->stats.Slide_Beacon_Total/slide_beacon_adc_pwdb_statistics;
7688 if(pprevious_stats->RxPWDBAll >= 3)
7689 pprevious_stats->RxPWDBAll -= 3;
7690 }
7691
7692 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
7693 pprevious_stats->bIsCCK? "CCK": "OFDM",
7694 pprevious_stats->RxPWDBAll);
7695
7696
7697 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
7698 {
7699 if(priv->undecorated_smoothed_pwdb < 0) // initialize
7700 {
7701 priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll;
7702 //DbgPrint("First pwdb initialize \n");
7703 }
7704#if 1
7705 if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb)
7706 {
7707 priv->undecorated_smoothed_pwdb =
7708 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
7709 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
7710 priv->undecorated_smoothed_pwdb = priv->undecorated_smoothed_pwdb + 1;
7711 }
7712 else
7713 {
7714 priv->undecorated_smoothed_pwdb =
7715 ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
7716 (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
7717 }
7718#else
7719 //Fixed by Jacken 2008-03-20
7720 if(pPreviousRfd->Status.RxPWDBAll > (u32)pHalData->UndecoratedSmoothedPWDB)
7721 {
7722 pHalData->UndecoratedSmoothedPWDB =
7723 ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
7724 pHalData->UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB + 1;
7725 }
7726 else
7727 {
7728 pHalData->UndecoratedSmoothedPWDB =
7729 ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
7730 }
7731#endif
7732
7733 }
7734
7735 //
7736 // Check EVM
7737 //
7738 /* record the general EVM to the sliding window. */
7739 if(pprevious_stats->SignalQuality == 0)
7740 {
7741 }
7742 else
7743 {
7744 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA){
7745 if(slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX){
7746 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
7747 last_evm = priv->stats.slide_evm[slide_evm_index];
7748 priv->stats.slide_evm_total -= last_evm;
7749 }
7750
7751 priv->stats.slide_evm_total += pprevious_stats->SignalQuality;
7752
7753 priv->stats.slide_evm[slide_evm_index++] = pprevious_stats->SignalQuality;
7754 if(slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
7755 slide_evm_index = 0;
7756
7757 // <1> Showed on UI for user, in percentage.
7758 tmp_val = priv->stats.slide_evm_total/slide_evm_statistics;
7759 priv->stats.signal_quality = tmp_val;
7760 //cosa add 10/11/2007, Showed on UI for user in Windows Vista, for Link quality.
7761 priv->stats.last_signal_strength_inpercent = tmp_val;
7762 }
7763
7764 // <2> Showed on UI for engineering
7765 if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA)
7766 {
7767 for(nspatial_stream = 0; nspatial_stream<2 ; nspatial_stream++) // 2 spatial stream
7768 {
7769 if(pprevious_stats->RxMIMOSignalQuality[nspatial_stream] != -1)
7770 {
7771 if(priv->stats.rx_evm_percentage[nspatial_stream] == 0) // initialize
7772 {
7773 priv->stats.rx_evm_percentage[nspatial_stream] = pprevious_stats->RxMIMOSignalQuality[nspatial_stream];
7774 }
7775 priv->stats.rx_evm_percentage[nspatial_stream] =
7776 ( (priv->stats.rx_evm_percentage[nspatial_stream]* (Rx_Smooth_Factor-1)) +
7777 (pprevious_stats->RxMIMOSignalQuality[nspatial_stream]* 1)) / (Rx_Smooth_Factor);
7778 }
7779 }
7780 }
7781 }
7782
7783
7784}
7785
7786/*-----------------------------------------------------------------------------
7787 * Function: rtl819x_query_rxpwrpercentage()
7788 *
7789 * Overview:
7790 *
7791 * Input: char antpower
7792 *
7793 * Output: NONE
7794 *
7795 * Return: 0-100 percentage
7796 *
7797 * Revised History:
7798 * When Who Remark
7799 * 05/26/2008 amy Create Version 0 porting from windows code.
7800 *
7801 *---------------------------------------------------------------------------*/
7802static u8 rtl819x_query_rxpwrpercentage(
7803 char antpower
7804 )
7805{
7806 if ((antpower <= -100) || (antpower >= 20))
7807 {
7808 return 0;
7809 }
7810 else if (antpower >= 0)
7811 {
7812 return 100;
7813 }
7814 else
7815 {
7816 return (100+antpower);
7817 }
7818
7819} /* QueryRxPwrPercentage */
7820
7821static u8
7822rtl819x_evm_dbtopercentage(
7823 char value
7824 )
7825{
7826 char ret_val;
7827
7828 ret_val = value;
7829
7830 if(ret_val >= 0)
7831 ret_val = 0;
7832 if(ret_val <= -33)
7833 ret_val = -33;
7834 ret_val = 0 - ret_val;
7835 ret_val*=3;
7836 if(ret_val == 99)
7837 ret_val = 100;
7838 return(ret_val);
7839}
7840//
7841// Description:
7842// We want good-looking for signal strength/quality
7843// 2007/7/19 01:09, by cosa.
7844//
7845long
7846rtl819x_signal_scale_mapping(
7847 long currsig
7848 )
7849{
7850 long retsig;
7851
7852 // Step 1. Scale mapping.
7853 if(currsig >= 61 && currsig <= 100)
7854 {
7855 retsig = 90 + ((currsig - 60) / 4);
7856 }
7857 else if(currsig >= 41 && currsig <= 60)
7858 {
7859 retsig = 78 + ((currsig - 40) / 2);
7860 }
7861 else if(currsig >= 31 && currsig <= 40)
7862 {
7863 retsig = 66 + (currsig - 30);
7864 }
7865 else if(currsig >= 21 && currsig <= 30)
7866 {
7867 retsig = 54 + (currsig - 20);
7868 }
7869 else if(currsig >= 5 && currsig <= 20)
7870 {
7871 retsig = 42 + (((currsig - 5) * 2) / 3);
7872 }
7873 else if(currsig == 4)
7874 {
7875 retsig = 36;
7876 }
7877 else if(currsig == 3)
7878 {
7879 retsig = 27;
7880 }
7881 else if(currsig == 2)
7882 {
7883 retsig = 18;
7884 }
7885 else if(currsig == 1)
7886 {
7887 retsig = 9;
7888 }
7889 else
7890 {
7891 retsig = currsig;
7892 }
7893
7894 return retsig;
7895}
7896
5f53d8ca
JC		 7897/*-----------------------------------------------------------------------------
7898 * Function: QueryRxPhyStatus8192S()
7899 *
7900 * Overview:
7901 *
7902 * Input: NONE
7903 *
7904 * Output: NONE
7905 *
7906 * Return: NONE
7907 *
7908 * Revised History:
7909 * When Who Remark
7910 * 06/01/2007 MHC Create Version 0.
7911 * 06/05/2007 MHC Accordign to HW's new data sheet, we add CCK and OFDM
7912 * descriptor definition.
7913 * 07/04/2007 MHC According to Jerry and Bryant's document. We read
7914 * ir_isolation and ext_lna for RF's init value and use
7915 * to compensate RSSI after receiving packets.
7916 * 09/10/2008 MHC Modify name and PHY status field for 92SE.
7917 * 09/19/2008 MHC Add CCK/OFDM SS/SQ for 92S series.
7918 *
7919 *---------------------------------------------------------------------------*/
7920static void rtl8192SU_query_rxphystatus(
7921 struct r8192_priv * priv,
7922 struct ieee80211_rx_stats * pstats,
7923 rx_desc_819x_usb *pDesc,
7924 rx_drvinfo_819x_usb * pdrvinfo,
7925 struct ieee80211_rx_stats * precord_stats,
7926 bool bpacket_match_bssid,
7927 bool bpacket_toself,
7928 bool bPacketBeacon,
7929 bool bToSelfBA
7930 )
7931{
7932 //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status);
7933 //PHY_STS_CCK_8192S_T *pCck_buf;
7934 phy_sts_cck_819xusb_t * pcck_buf;
7935 phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc;
7936 //u8 *prxpkt;
7937 //u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
7938 u8 i, max_spatial_stream, rxsc_sgien_exflg;
7939 char rx_pwr[4], rx_pwr_all=0;
7940 //long rx_avg_pwr = 0;
7941 //char rx_snrX, rx_evmX;
7942 u8 evm, pwdb_all;
7943 u32 RSSI, total_rssi=0;//, total_evm=0;
7944// long signal_strength_index = 0;
7945 u8 is_cck_rate=0;
7946 u8 rf_rx_num = 0;
7947
7948
7949
7950 priv->stats.numqry_phystatus++;
7951
7952 is_cck_rate = rx_hal_is_cck_rate(pDesc);
7953
7954 // Record it for next packet processing
7955 memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats));
7956 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid;
7957 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
7958 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo);
7959 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
7960 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
7961
5f53d8ca
JC		 7962
7963 pstats->RxMIMOSignalQuality[0] = -1;
7964 pstats->RxMIMOSignalQuality[1] = -1;
7965 precord_stats->RxMIMOSignalQuality[0] = -1;
7966 precord_stats->RxMIMOSignalQuality[1] = -1;
7967
7968 if(is_cck_rate)
7969 {
7970 u8 report;//, tmp_pwdb;
7971 //char cck_adc_pwdb[4];
7972
7973 // CCK Driver info Structure is not the same as OFDM packet.
7974 pcck_buf = (phy_sts_cck_819xusb_t *)pdrvinfo;
7975
7976 //
7977 // (1)Hardware does not provide RSSI for CCK
7978 //
7979
7980 //
7981 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
7982 //
7983
7984 priv->stats.numqry_phystatusCCK++;
7985
7986 if(!priv->bCckHighPower)
7987 {
7988 report = pcck_buf->cck_agc_rpt & 0xc0;
7989 report = report>>6;
7990 switch(report)
7991 {
7992 //Fixed by Jacken from Bryant 2008-03-20
7993 //Original value is -38 , -26 , -14 , -2
7994 //Fixed value is -35 , -23 , -11 , 6
7995 case 0x3:
7996 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e);
7997 break;
7998 case 0x2:
7999 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e);
8000 break;
8001 case 0x1:
8002 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e);
8003 break;
8004 case 0x0:
8005 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);//6->8
8006 break;
8007 }
8008 }
8009 else
8010 {
8011 report = pdrvinfo->cfosho[0] & 0x60;
8012 report = report>>5;
8013 switch(report)
8014 {
8015 case 0x3:
8016 rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
8017 break;
8018 case 0x2:
8019 rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1);
8020 break;
8021 case 0x1:
8022 rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;
8023 break;
8024 case 0x0:
8025 rx_pwr_all = -8 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;//6->-8
8026 break;
8027 }
8028 }
8029
8030 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);//check it
8031 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
8032 //pstats->RecvSignalPower = pwdb_all;
8033 pstats->RecvSignalPower = rx_pwr_all;
8034
8035 //
8036 // (3) Get Signal Quality (EVM)
8037 //
8038 //if(bpacket_match_bssid)
8039 {
8040 u8 sq;
8041
8042 if(pstats->RxPWDBAll > 40)
8043 {
8044 sq = 100;
8045 }else
8046 {
8047 sq = pcck_buf->sq_rpt;
8048
8049 if(pcck_buf->sq_rpt > 64)
8050 sq = 0;
8051 else if (pcck_buf->sq_rpt < 20)
8052 sq = 100;
8053 else
8054 sq = ((64-sq) * 100) / 44;
8055 }
8056 pstats->SignalQuality = precord_stats->SignalQuality = sq;
8057 pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq;
8058 pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1;
8059 }
8060 }
8061 else
8062 {
8063 priv->stats.numqry_phystatusHT++;
8064
8065 // 2008/09/19 MH For 92S debug, RX RF path always enable!!
8066 priv->brfpath_rxenable[0] = priv->brfpath_rxenable[1] = TRUE;
8067
8068 //
8069 // (1)Get RSSI for HT rate
8070 //
8071 //for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++)
8072 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
8073 {
8074 // 2008/01/30 MH we will judge RF RX path now.
8075 if (priv->brfpath_rxenable[i])
8076 rf_rx_num++;
8077 //else
8078 // continue;
8079
8080 //if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i))
8081 // continue;
8082
8083 //Fixed by Jacken from Bryant 2008-03-20
8084 //Original value is 106
8085 //rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
8086 rx_pwr[i] = ((pdrvinfo->gain_trsw[i]&0x3F)*2) - 110;
8087
8088 /* Translate DBM to percentage. */
8089 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); //check ok
8090 total_rssi += RSSI;
8091 RT_TRACE(COMP_RF, "RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI);
8092
8093 //Get Rx snr value in DB
8094 //tmp_rxsnr = pofdm_buf->rxsnr_X[i];
8095 //rx_snrX = (char)(tmp_rxsnr);
8096 //rx_snrX /= 2;
8097 //priv->stats.rxSNRdB[i] = (long)rx_snrX;
8098 priv->stats.rxSNRdB[i] = (long)(pdrvinfo->rxsnr[i]/2);
8099
8100 /* Translate DBM to percentage. */
8101 //RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
8102 //total_rssi += RSSI;
8103
8104 /* Record Signal Strength for next packet */
8105 //if(bpacket_match_bssid)
8106 {
8107 pstats->RxMIMOSignalStrength[i] =(u8) RSSI;
8108 precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI;
8109 }
8110 }
8111
8112
8113 //
8114 // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
8115 //
8116 //Fixed by Jacken from Bryant 2008-03-20
8117 //Original value is 106
8118 //rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106;
8119 rx_pwr_all = (((pdrvinfo->pwdb_all ) >> 1 )& 0x7f) -106;
8120 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
8121
8122 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
8123 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
8124 pstats->RecvSignalPower = rx_pwr_all;
8125
8126 //
8127 // (3)EVM of HT rate
8128 //
8129 //if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 &&
8130 // pdrvinfo->RxRate<=DESC90_RATEMCS15)
8131 if(pDesc->RxHT && pDesc->RxMCS>=DESC92S_RATEMCS8 &&
8132 pDesc->RxMCS<=DESC92S_RATEMCS15)
8133 max_spatial_stream = 2; //both spatial stream make sense
8134 else
8135 max_spatial_stream = 1; //only spatial stream 1 makes sense
8136
8137 for(i=0; i<max_spatial_stream; i++)
8138 {
8139 //tmp_rxevm = pofdm_buf->rxevm_X[i];
8140 //rx_evmX = (char)(tmp_rxevm);
8141
8142 // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
8143 // fill most significant bit to "zero" when doing shifting operation which may change a negative
8144 // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
8145 //rx_evmX /= 2; //dbm
8146
8147 //evm = rtl819x_evm_dbtopercentage(rx_evmX);
8148 evm = rtl819x_evm_dbtopercentage( (pdrvinfo->rxevm[i] /*/ 2*/)); //dbm
8149 RT_TRACE(COMP_RF, "RXRATE=%x RXEVM=%x EVM=%s%d\n", pDesc->RxMCS, pdrvinfo->rxevm[i], "%", evm);
8150#if 0
8151 EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100//=====>from here
8152#endif
8153
8154 //if(bpacket_match_bssid)
8155 {
8156 if(i==0) // Fill value in RFD, Get the first spatial stream only
8157 pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff);
8158 pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff);
8159 }
8160 }
8161
8162
8163 /* record rx statistics for debug */
8164 //rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
8165 prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg;
8166 //if(pdrvinfo->BW) //40M channel
8167 if(pDesc->BW) //40M channel
8168 priv->stats.received_bwtype[1+pdrvinfo->rxsc]++;
8169 else //20M channel
8170 priv->stats.received_bwtype[0]++;
8171 }
8172
8173 //UI BSS List signal strength(in percentage), make it good looking, from 0~100.
8174 //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
8175 if(is_cck_rate)
8176 {
8177 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;//check ok
8178
8179 }
8180 else
8181 {
8182 //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX);
8183 // We can judge RX path number now.
8184 if (rf_rx_num != 0)
8185 pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num)));
8186 }
8187}/* QueryRxPhyStatus8192S */
0f29f587
BZ		 8188
8189void
8190rtl8192_record_rxdesc_forlateruse(
8191 struct ieee80211_rx_stats * psrc_stats,
8192 struct ieee80211_rx_stats * ptarget_stats
8193)
8194{
8195 ptarget_stats->bIsAMPDU = psrc_stats->bIsAMPDU;
8196 ptarget_stats->bFirstMPDU = psrc_stats->bFirstMPDU;
8197 ptarget_stats->Seq_Num = psrc_stats->Seq_Num;
8198}
8199
8200static void rtl8192SU_query_rxphystatus(
5f53d8ca
JC		 8201 struct r8192_priv * priv,
8202 struct ieee80211_rx_stats * pstats,
0f29f587 8203 rx_desc_819x_usb *pDesc,
5f53d8ca
JC		 8204 rx_drvinfo_819x_usb * pdrvinfo,
8205 struct ieee80211_rx_stats * precord_stats,
8206 bool bpacket_match_bssid,
8207 bool bpacket_toself,
8208 bool bPacketBeacon,
8209 bool bToSelfBA
0f29f587
BZ		 8210 );
8211void rtl8192SU_TranslateRxSignalStuff(struct sk_buff *skb,
8212 struct ieee80211_rx_stats * pstats,
8213 rx_desc_819x_usb *pDesc,
8214 rx_drvinfo_819x_usb *pdrvinfo)
5f53d8ca 8215{
0f29f587
BZ		 8216 // TODO: We must only check packet for current MAC address. Not finish
8217 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
8218 struct net_device *dev=info->dev;
8219 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8220 bool bpacket_match_bssid, bpacket_toself;
8221 bool bPacketBeacon=FALSE, bToSelfBA=FALSE;
8222 static struct ieee80211_rx_stats previous_stats;
8223 struct ieee80211_hdr_3addr *hdr;//by amy
8224 u16 fc,type;
5f53d8ca 8225
0f29f587 8226 // Get Signal Quality for only RX data queue (but not command queue)
5f53d8ca 8227
0f29f587
BZ		 8228 u8* tmp_buf;
8229 //u16 tmp_buf_len = 0;
8230 u8 *praddr;
5f53d8ca 8231
0f29f587
BZ		 8232 /* Get MAC frame start address. */
8233 tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats);
5f53d8ca 8234
0f29f587
BZ		 8235 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
8236 fc = le16_to_cpu(hdr->frame_ctl);
8237 type = WLAN_FC_GET_TYPE(fc);
8238 praddr = hdr->addr1;
5f53d8ca 8239
0f29f587
BZ		 8240 /* Check if the received packet is acceptabe. */
8241 bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) &&
8242 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
8243 && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
8244 bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr));
5f53d8ca
JC		 8245
8246#if 1//cosa
8247 if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
8248 {
8249 bPacketBeacon = true;
8250 //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
8251 }
8252 if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK)
8253 {
8254 if((eqMacAddr(praddr,dev->dev_addr)))
8255 bToSelfBA = true;
8256 //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf);
8257 }
8258
8259#endif
8260
8261
8262 if(bpacket_match_bssid)
8263 {
8264 priv->stats.numpacket_matchbssid++;
8265 }
8266 if(bpacket_toself){
8267 priv->stats.numpacket_toself++;
8268 }
8269 //
8270 // Process PHY information for previous packet (RSSI/PWDB/EVM)
8271 //
8272 // Because phy information is contained in the last packet of AMPDU only, so driver
8273 // should process phy information of previous packet
8274 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
8275 rtl8192SU_query_rxphystatus(priv, pstats, pDesc, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA);
8276 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
8277
8278}
5f53d8ca
JC		 8279
8280/**
8281* Function: UpdateReceivedRateHistogramStatistics
8282* Overview: Recored down the received data rate
8283*
8284* Input:
8285* struct net_device *dev
8286* struct ieee80211_rx_stats *stats
8287*
8288* Output:
8289*
8290* (priv->stats.ReceivedRateHistogram[] is updated)
8291* Return:
8292* None
8293*/
8294void
8295UpdateReceivedRateHistogramStatistics8190(
8296 struct net_device *dev,
8297 struct ieee80211_rx_stats *stats
8298 )
8299{
8300 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8301 u32 rcvType=1; //0: Total, 1:OK, 2:CRC, 3:ICV
8302 u32 rateIndex;
8303 u32 preamble_guardinterval; //1: short preamble/GI, 0: long preamble/GI
8304
8305
8306 if(stats->bCRC)
8307 rcvType = 2;
8308 else if(stats->bICV)
8309 rcvType = 3;
8310
8311 if(stats->bShortPreamble)
8312 preamble_guardinterval = 1;// short
8313 else
8314 preamble_guardinterval = 0;// long
8315
8316 switch(stats->rate)
8317 {
8318 //
8319 // CCK rate
8320 //
8321 case MGN_1M: rateIndex = 0; break;
8322 case MGN_2M: rateIndex = 1; break;
8323 case MGN_5_5M: rateIndex = 2; break;
8324 case MGN_11M: rateIndex = 3; break;
8325 //
8326 // Legacy OFDM rate
8327 //
8328 case MGN_6M: rateIndex = 4; break;
8329 case MGN_9M: rateIndex = 5; break;
8330 case MGN_12M: rateIndex = 6; break;
8331 case MGN_18M: rateIndex = 7; break;
8332 case MGN_24M: rateIndex = 8; break;
8333 case MGN_36M: rateIndex = 9; break;
8334 case MGN_48M: rateIndex = 10; break;
8335 case MGN_54M: rateIndex = 11; break;
8336 //
8337 // 11n High throughput rate
8338 //
8339 case MGN_MCS0: rateIndex = 12; break;
8340 case MGN_MCS1: rateIndex = 13; break;
8341 case MGN_MCS2: rateIndex = 14; break;
8342 case MGN_MCS3: rateIndex = 15; break;
8343 case MGN_MCS4: rateIndex = 16; break;
8344 case MGN_MCS5: rateIndex = 17; break;
8345 case MGN_MCS6: rateIndex = 18; break;
8346 case MGN_MCS7: rateIndex = 19; break;
8347 case MGN_MCS8: rateIndex = 20; break;
8348 case MGN_MCS9: rateIndex = 21; break;
8349 case MGN_MCS10: rateIndex = 22; break;
8350 case MGN_MCS11: rateIndex = 23; break;
8351 case MGN_MCS12: rateIndex = 24; break;
8352 case MGN_MCS13: rateIndex = 25; break;
8353 case MGN_MCS14: rateIndex = 26; break;
8354 case MGN_MCS15: rateIndex = 27; break;
8355 default: rateIndex = 28; break;
8356 }
8357 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
8358 priv->stats.received_rate_histogram[0][rateIndex]++; //total
8359 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
8360}
8361
5f53d8ca
JC		 8362void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe)
8363{
8364 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
8365 struct net_device *dev=info->dev;
8366 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8367 //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
8368 rx_drvinfo_819x_usb *driver_info = NULL;
8369
8370 //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status;
8371 //PHAL_DATA_8192SUSB pHalData = GET_HAL_DATA(Adapter);
8372 //pu1Byte pDesc = (pu1Byte)pDescIn;
8373 //PRX_DRIVER_INFO_8192S pDrvInfo;
8374
5f53d8ca
JC		 8375 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
8376
8377 if(0)
8378 {
8379 int m = 0;
8380 printk("========================");
8381 for(m=0; m<skb->len; m++){
8382 if((m%32) == 0)
8383 printk("\n");
8384 printk("%2x ",((u8*)skb->data)[m]);
8385 }
8386 printk("\n========================\n");
8387
8388 }
8389
8390
8391 //
8392 //Get Rx Descriptor Raw Information
8393 //
8394 stats->Length = desc->Length ;
8395 stats->RxDrvInfoSize = desc->RxDrvInfoSize*RX_DRV_INFO_SIZE_UNIT;
8396 stats->RxBufShift = (desc->Shift)&0x03;
8397 stats->bICV = desc->ICV;
8398 stats->bCRC = desc->CRC32;
8399 stats->bHwError = stats->bCRC|stats->bICV;
8400 stats->Decrypted = !desc->SWDec;//RTL8190 set this bit to indicate that Hw does not decrypt packet
8401 stats->bIsAMPDU = (desc->AMSDU==1);
8402 stats->bFirstMPDU = (desc->PAGGR==1) && (desc->FAGGR==1);
8403 stats->bShortPreamble = desc->SPLCP;
8404 stats->RxIs40MHzPacket = (desc->BW==1);
8405 stats->TimeStampLow = desc->TSFL;
8406
8407 if((desc->FAGGR==1) || (desc->PAGGR==1))
8408 {// Rx A-MPDU
8409 RT_TRACE(COMP_RXDESC, "FirstAGGR = %d, PartAggr = %d\n", desc->FAGGR, desc->PAGGR);
8410 }
8411//YJ,test,090310
8412if(stats->bHwError)
8413{
8414 if(stats->bICV)
8415 printk("%s: Receive ICV error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__);
8416 if(stats->bCRC)
8417 printk("%s: Receive CRC error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__);
8418}
8419
8420 if(IS_UNDER_11N_AES_MODE(priv->ieee80211))
8421 {
8422 // Always received ICV error packets in AES mode.
8423 // This fixed HW later MIC write bug.
8424 if(stats->bICV && !stats->bCRC)
8425 {
8426 stats->bICV = FALSE;
8427 stats->bHwError = FALSE;
8428 }
8429 }
8430
8431 // Transform HwRate to MRate
8432 if(!stats->bHwError)
8433 //stats->DataRate = HwRateToMRate(
8434 // (BOOLEAN)GET_RX_DESC_RXHT(pDesc),
8435 // (u1Byte)GET_RX_DESC_RXMCS(pDesc),
8436 // (BOOLEAN)GET_RX_DESC_PAGGR(pDesc));
8437 stats->rate = rtl8192SU_HwRateToMRate(desc->RxHT, desc->RxMCS, desc->PAGGR);
8438 else
8439 stats->rate = MGN_1M;
8440
8441 //
8442 // Collect Rx rate/AMPDU/TSFL
8443 //
8444 //UpdateRxdRateHistogramStatistics8192S(Adapter, pRfd);
8445 //UpdateRxAMPDUHistogramStatistics8192S(Adapter, pRfd);
8446 //UpdateRxPktTimeStamp8192S(Adapter, pRfd);
8447 UpdateReceivedRateHistogramStatistics8190(dev, stats);
8448 //UpdateRxAMPDUHistogramStatistics8192S(dev, stats); //FIXLZM
8449 UpdateRxPktTimeStamp8190(dev, stats);
8450
8451 //
8452 // Get PHY Status and RSVD parts.
8453 // <Roger_Notes> It only appears on last aggregated packet.
8454 //
8455 if (desc->PHYStatus)
8456 {
8457 //driver_info = (rx_drvinfo_819x_usb *)(skb->data + RX_DESC_SIZE + stats->RxBufShift);
8458 driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \
8459 stats->RxBufShift);
8460 if(0)
8461 {
8462 int m = 0;
8463 printk("========================\n");
8464 printk("RX_DESC_SIZE:%d, RxBufShift:%d, RxDrvInfoSize:%d\n",
8465 RX_DESC_SIZE, stats->RxBufShift, stats->RxDrvInfoSize);
8466 for(m=0; m<32; m++){
8467 printk("%2x ",((u8*)driver_info)[m]);
8468 }
8469 printk("\n========================\n");
8470
8471 }
8472
8473 }
8474
8475 //YJ,add,090107
8476 skb_pull(skb, sizeof(rx_desc_819x_usb));
8477 //YJ,add,090107,end
8478
8479 //
8480 // Get Total offset of MPDU Frame Body
8481 //
8482 if((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
8483 {
8484 stats->bShift = 1;
8485 //YJ,add,090107
8486 skb_pull(skb, stats->RxBufShift + stats->RxDrvInfoSize);
8487 //YJ,add,090107,end
8488 }
8489
8490 //
8491 // Get PHY Status and RSVD parts.
8492 // <Roger_Notes> It only appears on last aggregated packet.
8493 //
8494 if (desc->PHYStatus)
8495 {
8496 rtl8192SU_TranslateRxSignalStuff(skb, stats, desc, driver_info);
8497 }
8498}
5f53d8ca 8499
5f53d8ca
JC		 8500#if 0
8501/*-----------------------------------------------------------------------------
8502 * Function: UpdateRxAMPDUHistogramStatistics8192S
8503 *
8504 * Overview: Recored down the received A-MPDU aggregation size and pkt number
8505 *
8506 * Input: Adapter
8507 *
8508 * Output: Adapter
8509 * (Adapter->RxStats.RxAMPDUSizeHistogram[] is updated)
8510 * (Adapter->RxStats.RxAMPDUNumHistogram[] is updated)
8511 *
8512 * Return: NONE
8513 *
8514 * Revised History:
8515 * When Who Remark
8516 * 09/18/2008 MHC Create Version 0.
8517 *
8518 *---------------------------------------------------------------------------*/
8519static void
8520UpdateRxAMPDUHistogramStatistics8192S(
8521 struct net_device *dev,
8522 struct ieee80211_rx_stats *stats
8523 )
8524{
8525 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
8526 u8 size_index;
8527 u8 num_index;
8528 u16 update_size = 0;
8529 u8 update_num = 0;
8530
8531 if(stats->bIsAMPDU)
8532 {
8533 if(stats->bFirstMPDU)
8534 {
8535 if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0)
8536 {
8537 update_size = stats->nRxAMPDU_Size;
8538 update_num = stats->nRxAMPDU_AggrNum;
8539 }
8540 stats->nRxAMPDU_Size = stats->Length;
8541 stats->nRxAMPDU_AggrNum = 1;
8542 }
8543 else
8544 {
8545 stats->nRxAMPDU_Size += stats->Length;
8546 stats->nRxAMPDU_AggrNum++;
8547 }
8548 }
8549 else
8550 {
8551 if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0)
8552 {
8553 update_size = stats->nRxAMPDU_Size;
8554 update_num = stats->nRxAMPDU_AggrNum;
8555 }
8556 stats->nRxAMPDU_Size = 0;
8557 stats->nRxAMPDU_AggrNum = 0;
8558 }
8559
8560 if(update_size!=0 && update_num!= 0)
8561 {
8562 if(update_size < 4096)
8563 size_index = 0;
8564 else if(update_size < 8192)
8565 size_index = 1;
8566 else if(update_size < 16384)
8567 size_index = 2;
8568 else if(update_size < 32768)
8569 size_index = 3;
8570 else if(update_size < 65536)
8571 size_index = 4;
8572 else
8573 {
8574 RT_TRACE(COMP_RXDESC,
8575 ("UpdateRxAMPDUHistogramStatistics8192S(): A-MPDU too large\n");
8576 }
8577
8578 Adapter->RxStats.RxAMPDUSizeHistogram[size_index]++;
8579
8580 if(update_num < 5)
8581 num_index = 0;
8582 else if(update_num < 10)
8583 num_index = 1;
8584 else if(update_num < 20)
8585 num_index = 2;
8586 else if(update_num < 40)
8587 num_index = 3;
8588 else
8589 num_index = 4;
8590
8591 Adapter->RxStats.RxAMPDUNumHistogram[num_index]++;
8592 }
8593} // UpdateRxAMPDUHistogramStatistics8192S
8594#endif
8595
5f53d8ca
JC		 8596
8597
5f53d8ca
JC		 8598//
8599// Description:
8600// The strarting address of wireless lan header will shift 1 or 2 or 3 or "more" bytes for the following reason :
8601// (1) QoS control : shift 2 bytes
8602// (2) Mesh Network : shift 1 or 3 bytes
8603// (3) RxDriverInfo occupies the front parts of Rx Packets buffer(shift units is in 8Bytes)
8604//
8605// It is because Lextra CPU used by 8186 or 865x series assert exception if the statrting address
8606// of IP header is not double word alignment.
8607// This features is supported in 818xb and 8190 only, but not 818x.
8608//
8609// parameter: PRT_RFD, Pointer of Reeceive frame descriptor which is initialized according to
8610// Rx Descriptor
8611// return value: unsigned int, number of total shifted bytes
8612//
8613// Notes: 2008/06/28, created by Roger
8614//
8615u32 GetRxPacketShiftBytes8192SU(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe)
8616{
8617 //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status;
8618
8619 return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize + Status->RxBufShift);
8620}
8621
8622void rtl8192SU_rx_nomal(struct sk_buff* skb)
8623{
8624 rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
8625 struct net_device *dev=info->dev;
8626 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8627 struct ieee80211_rx_stats stats = {
8628 .signal = 0,
8629 .noise = -98,
8630 .rate = 0,
8631 // .mac_time = jiffies,
8632 .freq = IEEE80211_24GHZ_BAND,
8633 };
8634 u32 rx_pkt_len = 0;
8635 struct ieee80211_hdr_1addr *ieee80211_hdr = NULL;
8636 bool unicast_packet = false;
8637
5f53d8ca
JC		 8638 //printk("**********skb->len = %d\n", skb->len);
8639 /* 20 is for ps-poll */
8640 if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) {
8641
8642 /* first packet should not contain Rx aggregation header */
8643 rtl8192SU_query_rxdesc_status(skb, &stats, false);
8644 /* TODO */
8645
8646 /* hardware related info */
5f53d8ca
JC		 8647 priv->stats.rxoktotal++; //YJ,test,090108
8648
8649 /* Process the MPDU recevied */
8650 skb_trim(skb, skb->len - 4/*sCrcLng*/);//FIXLZM
8651
8652 rx_pkt_len = skb->len;
8653 ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data;
8654 unicast_packet = false;
8655 if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) {
8656 //TODO
8657 }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){
8658 //TODO
8659 }else {
8660 /* unicast packet */
8661 unicast_packet = true;
8662 }
8663
8664 if(!ieee80211_rx(priv->ieee80211,skb, &stats)) {
8665 dev_kfree_skb_any(skb);
8666 } else {
8667 // priv->stats.rxoktotal++; //YJ,test,090108
8668 if(unicast_packet) {
8669 priv->stats.rxbytesunicast += rx_pkt_len;
8670 }
8671 }
8672
8673 //up is firs pkt, follow is next and next
5f53d8ca
JC		 8674 }
8675 else
8676 {
8677 priv->stats.rxurberr++;
8678 printk("actual_length:%d\n", skb->len);
8679 dev_kfree_skb_any(skb);
8680 }
8681
8682}
5f53d8ca
JC		 8683
8684void
8685rtl819xusb_process_received_packet(
8686 struct net_device *dev,
8687 struct ieee80211_rx_stats *pstats
8688 )
8689{
8690// bool bfreerfd=false, bqueued=false;
8691 u8* frame;
8692 u16 frame_len=0;
8693 struct r8192_priv *priv = ieee80211_priv(dev);
8694// u8 index = 0;
8695// u8 TID = 0;
8696 //u16 seqnum = 0;
8697 //PRX_TS_RECORD pts = NULL;
8698
8699 // Get shifted bytes of Starting address of 802.11 header. 2006.09.28, by Emily
8700 //porting by amy 080508
8701 pstats->virtual_address += get_rxpacket_shiftbytes_819xusb(pstats);
8702 frame = pstats->virtual_address;
8703 frame_len = pstats->packetlength;
8704#ifdef TODO // by amy about HCT
8705 if(!Adapter->bInHctTest)
8706 CountRxErrStatistics(Adapter, pRfd);
8707#endif
8708 {
8709 #ifdef ENABLE_PS //by amy for adding ps function in future
8710 RT_RF_POWER_STATE rtState;
8711 // When RF is off, we should not count the packet for hw/sw synchronize
8712 // reason, ie. there may be a duration while sw switch is changed and hw
8713 // switch is being changed. 2006.12.04, by shien chang.
8714 Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (u8* )(&rtState));
8715 if (rtState == eRfOff)
8716 {
8717 return;
8718 }
8719 #endif
8720 priv->stats.rxframgment++;
8721
8722 }
8723#ifdef TODO
8724 RmMonitorSignalStrength(Adapter, pRfd);
8725#endif
8726 /* 2007/01/16 MH Add RX command packet handle here. */
8727 /* 2007/03/01 MH We have to release RFD and return if rx pkt is cmd pkt. */
8728 if (rtl819xusb_rx_command_packet(dev, pstats))
8729 {
8730 return;
8731 }
8732
8733#ifdef SW_CRC_CHECK
8734 SwCrcCheck();
8735#endif
8736
8737
8738}
8739
8740void query_rx_cmdpkt_desc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats)
8741{
8742// rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
8743// struct net_device *dev=info->dev;
8744// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
8745 rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data;
8746// rx_drvinfo_819x_usb *driver_info;
8747
8748 //
8749 //Get Rx Descriptor Information
8750 //
8751 stats->virtual_address = (u8*)skb->data;
8752 stats->Length = desc->Length;
8753 stats->RxDrvInfoSize = 0;
8754 stats->RxBufShift = 0;
8755 stats->packetlength = stats->Length-scrclng;
8756 stats->fraglength = stats->packetlength;
8757 stats->fragoffset = 0;
8758 stats->ntotalfrag = 1;
8759}
8760
5f53d8ca
JC		 8761void rtl8192SU_rx_cmd(struct sk_buff *skb)
8762{
8763 struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb;
8764 struct net_device *dev = info->dev;
8765
8766 /* TODO */
8767 struct ieee80211_rx_stats stats = {
8768 .signal = 0,
8769 .noise = -98,
8770 .rate = 0,
8771 // .mac_time = jiffies,
8772 .freq = IEEE80211_24GHZ_BAND,
8773 };
8774
8775 //
8776 // Check buffer length to determine if this is a valid MPDU.
8777 //
8778 if( (skb->len >= sizeof(rx_desc_819x_usb)) && (skb->len <= RX_URB_SIZE) )//&&
8779 //(pHalData->SwChnlInProgress == FALSE))
8780 {
8781 //
8782 // Collection information in Rx descriptor.
8783 //
8784#if 0
8785 pRxDesc = pContext->Buffer;
8786
8787 pRfd->Buffer.VirtualAddress = pContext->Buffer; // 061109, rcnjko, for multi-platform consideration..
8788
8789 pRtRfdStatus->Length = (u2Byte)GET_RX_DESC_PKT_LEN(pRxDesc);
8790 pRtRfdStatus->RxDrvInfoSize = 0;
8791 pRtRfdStatus->RxBufShift = 0;
8792
8793 pRfd->PacketLength = pRfd->Status.Length - sCrcLng;
8794 pRfd->FragLength = pRfd->PacketLength;
8795 pRfd->FragOffset = 0;
8796 pRfd->nTotalFrag = 1;
8797 pRfd->queue_id = PipeIndex;
8798#endif
8799 query_rx_cmdpkt_desc_status(skb,&stats);
8800 // this is to be done by amy 080508 prfd->queue_id = 1;
8801
8802 //
8803 // Process the MPDU recevied.
8804 //
8805 rtl819xusb_process_received_packet(dev,&stats);
8806
8807 dev_kfree_skb_any(skb);
8808 }
8809 else
8810 {
8811 //RTInsertTailListWithCnt(&pAdapter->RfdIdleQueue, &pRfd->List, &pAdapter->NumIdleRfd);
8812 //RT_ASSERT(pAdapter->NumIdleRfd <= pAdapter->NumRfd, ("HalUsbInCommandComplete8192SUsb(): Adapter->NumIdleRfd(%d)\n", pAdapter->NumIdleRfd));
8813 //RT_TRACE(COMP_RECV, DBG_LOUD, ("HalUsbInCommandComplete8192SUsb(): NOT enough Resources!! BufLenUsed(%d), NumIdleRfd(%d)\n",
8814 //pContext->BufLenUsed, pAdapter->NumIdleRfd));
8815 }
8816
8817 //
8818 // Reuse USB_IN_CONTEXT since we had finished processing the
8819 // buffer in USB_IN_CONTEXT.
8820 //
8821 //HalUsbReturnInContext(pAdapter, pContext);
8822
8823 //
8824 // Issue another bulk IN transfer.
8825 //
8826 //HalUsbInMpdu(pAdapter, PipeIndex);
8827
8828 RT_TRACE(COMP_RECV, "<--- HalUsbInCommandComplete8192SUsb()\n");
8829
8830}
5f53d8ca
JC		 8831
8832void rtl8192_irq_rx_tasklet(struct r8192_priv *priv)
8833{
8834 struct sk_buff *skb;
8835 struct rtl8192_rx_info *info;
8836
8837 while (NULL != (skb = skb_dequeue(&priv->skb_queue))) {
8838 info = (struct rtl8192_rx_info *)skb->cb;
8839 switch (info->out_pipe) {
8840 /* Nomal packet pipe */
8841 case 3:
8842 //RT_TRACE(COMP_RECV, "normal in-pipe index(%d)\n",info->out_pipe);
8843 priv->IrpPendingCount--;
8844 priv->ops->rtl819x_rx_nomal(skb);
8845 break;
8846
8847 /* Command packet pipe */
8848 case 9:
8849 RT_TRACE(COMP_RECV, "command in-pipe index(%d)\n",\
8850 info->out_pipe);
8851 priv->ops->rtl819x_rx_cmd(skb);
8852 break;
8853
8854 default: /* should never get here! */
8855 RT_TRACE(COMP_ERR, "Unknown in-pipe index(%d)\n",\
8856 info->out_pipe);
8857 dev_kfree_skb(skb);
8858 break;
8859
8860 }
8861 }
8862}
8863
8864
8865
8866/****************************************************************************
8867 ---------------------------- USB_STUFF---------------------------
8868*****************************************************************************/
5f53d8ca
JC		 8869//LZM Merge from windows HalUsbSetQueuePipeMapping8192SUsb 090319
8870static void HalUsbSetQueuePipeMapping8192SUsb(struct usb_interface *intf, struct net_device *dev)
8871{
8872 struct r8192_priv *priv = ieee80211_priv(dev);
8873 struct usb_host_interface *iface_desc;
8874 struct usb_endpoint_descriptor *endpoint;
8875 u8 i = 0;
8876
8877 priv->ep_in_num = 0;
8878 priv->ep_out_num = 0;
8879 memset(priv->RtOutPipes,0,16);
8880 memset(priv->RtInPipes,0,16);
8881
5f53d8ca
JC		 8882 iface_desc = intf->cur_altsetting;
8883 priv->ep_num = iface_desc->desc.bNumEndpoints;
8884
8885 for (i = 0; i < priv->ep_num; ++i) {
8886 endpoint = &iface_desc->endpoint[i].desc;
5f53d8ca
JC		 8887 if (usb_endpoint_is_bulk_in(endpoint)) {
8888 priv->RtInPipes[priv->ep_in_num] = usb_endpoint_num(endpoint);
8889 priv->ep_in_num ++;
8890 //printk("in_endpoint_idx = %d\n", usb_endpoint_num(endpoint));
8891 } else if (usb_endpoint_is_bulk_out(endpoint)) {
8892 priv->RtOutPipes[priv->ep_out_num] = usb_endpoint_num(endpoint);
8893 priv->ep_out_num ++;
8894 //printk("out_endpoint_idx = %d\n", usb_endpoint_num(endpoint));
8895 }
5f53d8ca
JC		 8896 }
8897 {
8898 memset(priv->txqueue_to_outpipemap,0,9);
8899 if (priv->ep_num == 6) {
8900 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
8901 u8 queuetopipe[] = {3, 2, 1, 0, 4, 4, 4, 4, 4};
8902
8903 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
8904 } else if (priv->ep_num == 4) {
8905 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
8906 u8 queuetopipe[] = {1, 1, 0, 0, 2, 2, 2, 2, 2};
8907
8908 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
8909 } else if (priv->ep_num > 9) {
8910 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
8911 u8 queuetopipe[] = {3, 2, 1, 0, 4, 8, 7, 6, 5};
8912
8913 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
8914 } else {//use sigle pipe
8915 // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON
8916 u8 queuetopipe[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
8917 memcpy(priv->txqueue_to_outpipemap,queuetopipe,9);
8918 }
8919 }
8920 printk("==>ep_num:%d, in_ep_num:%d, out_ep_num:%d\n", priv->ep_num, priv->ep_in_num, priv->ep_out_num);
8921
8922 printk("==>RtInPipes:");
8923 for(i=0; i < priv->ep_in_num; i++)
8924 printk("%d ", priv->RtInPipes[i]);
8925 printk("\n");
8926
8927 printk("==>RtOutPipes:");
8928 for(i=0; i < priv->ep_out_num; i++)
8929 printk("%d ", priv->RtOutPipes[i]);
8930 printk("\n");
8931
8932 printk("==>txqueue_to_outpipemap for BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON:\n");
8933 for(i=0; i < 9; i++)
8934 printk("%d ", priv->txqueue_to_outpipemap[i]);
8935 printk("\n");
5f53d8ca
JC		 8936
8937 return;
8938}
5f53d8ca 8939
77b92881
BZ		 8940static const struct net_device_ops rtl8192_netdev_ops = {
8941 .ndo_open = rtl8192_open,
8942 .ndo_stop = rtl8192_close,
8943 .ndo_get_stats = rtl8192_stats,
8944 .ndo_tx_timeout = tx_timeout,
8945 .ndo_do_ioctl = rtl8192_ioctl,
8946 .ndo_set_multicast_list = r8192_set_multicast,
8947 .ndo_set_mac_address = r8192_set_mac_adr,
8948 .ndo_validate_addr = eth_validate_addr,
8949 .ndo_change_mtu = eth_change_mtu,
ce9c010c 8950 .ndo_start_xmit = rtl8192_ieee80211_xmit,
77b92881
BZ		 8951};
8952
5f53d8ca
JC		 8953static int __devinit rtl8192_usb_probe(struct usb_interface *intf,
8954 const struct usb_device_id *id)
5f53d8ca
JC		 8955{
8956// unsigned long ioaddr = 0;
8957 struct net_device *dev = NULL;
8958 struct r8192_priv *priv= NULL;
5f53d8ca 8959 struct usb_device *udev = interface_to_usbdev(intf);
1ec9e48d 8960
5f53d8ca
JC		 8961 RT_TRACE(COMP_INIT, "Oops: i'm coming\n");
8962
8963 dev = alloc_ieee80211(sizeof(struct r8192_priv));
8964
5f53d8ca
JC		 8965 usb_set_intfdata(intf, dev);
8966 SET_NETDEV_DEV(dev, &intf->dev);
5f53d8ca 8967 priv = ieee80211_priv(dev);
5f53d8ca 8968 priv->ieee80211 = netdev_priv(dev);
5f53d8ca
JC		 8969 priv->udev=udev;
8970
5f53d8ca 8971 HalUsbSetQueuePipeMapping8192SUsb(intf, dev);
5f53d8ca 8972
5f53d8ca
JC		 8973 //printk("===============>NIC 8192SU\n");
8974 priv->ops = &rtl8192su_ops;
5f53d8ca 8975
77b92881 8976 dev->netdev_ops = &rtl8192_netdev_ops;
5f53d8ca
JC		 8977
8978 //DMESG("Oops: i'm coming\n");
5f53d8ca 8979 dev->wireless_handlers = (struct iw_handler_def *) &r8192_wx_handlers_def;
3bd709f2 8980
5f53d8ca
JC		 8981 dev->type=ARPHRD_ETHER;
8982
8983 dev->watchdog_timeo = HZ*3; //modified by john, 0805
8984
8985 if (dev_alloc_name(dev, ifname) < 0){
8986 RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying wlan%%d...\n");
8987 ifname = "wlan%d";
8988 dev_alloc_name(dev, ifname);
8989 }
8990
8991 RT_TRACE(COMP_INIT, "Driver probe completed1\n");
8992#if 1
8993 if(rtl8192_init(dev)!=0){
8994 RT_TRACE(COMP_ERR, "Initialization failed");
8995 goto fail;
8996 }
8997#endif
8998 netif_carrier_off(dev);
8999 netif_stop_queue(dev);
9000
9001 register_netdev(dev);
9002 RT_TRACE(COMP_INIT, "dev name=======> %s\n",dev->name);
9003 rtl8192_proc_init_one(dev);
9004
9005
9006 RT_TRACE(COMP_INIT, "Driver probe completed\n");
5f53d8ca 9007 return 0;
5f53d8ca
JC		 9008fail:
9009 free_ieee80211(dev);
9010
9011 RT_TRACE(COMP_ERR, "wlan driver load failed\n");
5f53d8ca 9012 return -ENODEV;
5f53d8ca
JC		 9013}
9014
9015//detach all the work and timer structure declared or inititialize in r8192U_init function.
9016void rtl8192_cancel_deferred_work(struct r8192_priv* priv)
9017{
5f53d8ca
JC		 9018 cancel_work_sync(&priv->reset_wq);
9019 cancel_work_sync(&priv->qos_activate);
9020 cancel_delayed_work(&priv->watch_dog_wq);
9021 cancel_delayed_work(&priv->update_beacon_wq);
9022 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
9023 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
9024 //cancel_work_sync(&priv->SetBWModeWorkItem);
9025 //cancel_work_sync(&priv->SwChnlWorkItem);
5f53d8ca
JC		 9026}
9027
5f53d8ca 9028static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf)
5f53d8ca 9029{
5f53d8ca 9030 struct net_device *dev = usb_get_intfdata(intf);
5f53d8ca
JC		 9031 struct r8192_priv *priv = ieee80211_priv(dev);
9032 if(dev){
9033
9034 unregister_netdev(dev);
9035
9036 RT_TRACE(COMP_DOWN, "=============>wlan driver to be removed\n");
9037 rtl8192_proc_remove_one(dev);
9038
9039 rtl8192_down(dev);
9040 if (priv->pFirmware)
9041 {
9042 vfree(priv->pFirmware);
9043 priv->pFirmware = NULL;
9044 }
9045 // priv->rf_close(dev);
9046// rtl8192_SetRFPowerState(dev, eRfOff);
5f53d8ca 9047 destroy_workqueue(priv->priv_wq);
5f53d8ca
JC		 9048 //rtl8192_irq_disable(dev);
9049 //rtl8192_reset(dev);
9050 mdelay(10);
9051
9052 }
9053 free_ieee80211(dev);
9054 RT_TRACE(COMP_DOWN, "wlan driver removed\n");
9055}
9056
9057static int __init rtl8192_usb_module_init(void)
9058{
9059 printk(KERN_INFO "\nLinux kernel driver for RTL8192 based WLAN cards\n");
9060 printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan\n");
9061 RT_TRACE(COMP_INIT, "Initializing module");
9062 RT_TRACE(COMP_INIT, "Wireless extensions version %d", WIRELESS_EXT);
9063 rtl8192_proc_module_init();
9064 return usb_register(&rtl8192_usb_driver);
9065}
9066
9067
9068static void __exit rtl8192_usb_module_exit(void)
9069{
9070 usb_deregister(&rtl8192_usb_driver);
9071
9072 RT_TRACE(COMP_DOWN, "Exiting");
9073 rtl8192_proc_module_remove();
9074}
9075
9076
9077void rtl8192_try_wake_queue(struct net_device *dev, int pri)
9078{
9079 unsigned long flags;
9080 short enough_desc;
9081 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9082
9083 spin_lock_irqsave(&priv->tx_lock,flags);
9084 enough_desc = check_nic_enough_desc(dev,pri);
9085 spin_unlock_irqrestore(&priv->tx_lock,flags);
9086
9087 if(enough_desc)
9088 ieee80211_wake_queue(priv->ieee80211);
9089}
9090
9091#if 0
9092void DisableHWSecurityConfig8192SUsb(struct net_device *dev)
9093{
9094 u8 SECR_value = 0x0;
9095 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
9096}
9097#endif
9098
9099void EnableHWSecurityConfig8192(struct net_device *dev)
9100{
9101 u8 SECR_value = 0x0;
9102 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
9103 struct ieee80211_device* ieee = priv->ieee80211;
9104
9105 SECR_value = SCR_TxEncEnable | SCR_RxDecEnable;
9106#if 1
9107 if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2))
9108 {
9109 SECR_value |= SCR_RxUseDK;
9110 SECR_value |= SCR_TxUseDK;
9111 }
9112 else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP)))
9113 {
9114 SECR_value |= SCR_RxUseDK;
9115 SECR_value |= SCR_TxUseDK;
9116 }
9117#endif
9118 //add HWSec active enable here.
9119//default using hwsec. when peer AP is in N mode only and pairwise_key_type is none_aes(which HT_IOT_ACT_PURE_N_MODE indicates it), use software security. when peer AP is in b,g,n mode mixed and pairwise_key_type is none_aes, use g mode hw security. WB on 2008.7.4
9120
9121 ieee->hwsec_active = 1;
9122
9123 if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep)//!ieee->hwsec_support) //add hwsec_support flag to totol control hw_sec on/off
9124 {
9125 ieee->hwsec_active = 0;
9126 SECR_value &= ~SCR_RxDecEnable;
9127 }
9128
9129 RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__, \
9130 ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);
9131 {
9132 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
9133 }
9134}
9135
9136
9137void setKey( struct net_device *dev,
9138 u8 EntryNo,
9139 u8 KeyIndex,
9140 u16 KeyType,
9141 u8 *MacAddr,
9142 u8 DefaultKey,
9143 u32 *KeyContent )
9144{
9145 u32 TargetCommand = 0;
9146 u32 TargetContent = 0;
9147 u16 usConfig = 0;
9148 u8 i;
9149 if (EntryNo >= TOTAL_CAM_ENTRY)
9150 RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n");
9151
9152 RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr));
9153
9154 if (DefaultKey)
9155 usConfig |= BIT15 | (KeyType<<2);
9156 else
9157 usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
9158// usConfig |= BIT15 | (KeyType<<2) | (DefaultKey<<5) | KeyIndex;
9159
9160
9161 for(i=0 ; i<CAM_CONTENT_COUNT; i++){
9162 TargetCommand = i+CAM_CONTENT_COUNT*EntryNo;
9163 TargetCommand |= BIT31|BIT16;
9164
9165 if(i==0){//MAC|Config
9166 TargetContent = (u32)(*(MacAddr+0)) << 16|
9167 (u32)(*(MacAddr+1)) << 24|
9168 (u32)usConfig;
9169
9170 write_nic_dword(dev, WCAMI, TargetContent);
9171 write_nic_dword(dev, RWCAM, TargetCommand);
9172 // printk("setkey cam =%8x\n", read_cam(dev, i+6*EntryNo));
9173 }
9174 else if(i==1){//MAC
9175 TargetContent = (u32)(*(MacAddr+2)) |
9176 (u32)(*(MacAddr+3)) << 8|
9177 (u32)(*(MacAddr+4)) << 16|
9178 (u32)(*(MacAddr+5)) << 24;
9179 write_nic_dword(dev, WCAMI, TargetContent);
9180 write_nic_dword(dev, RWCAM, TargetCommand);
9181 }
9182 else {
9183 //Key Material
9184 if(KeyContent !=NULL){
9185 write_nic_dword(dev, WCAMI, (u32)(*(KeyContent+i-2)) );
9186 write_nic_dword(dev, RWCAM, TargetCommand);
9187 }
9188 }
9189 }
9190
9191}
9192
9193/***************************************************************************
9194 ------------------- module init / exit stubs ----------------
9195****************************************************************************/
9196module_init(rtl8192_usb_module_init);
9197module_exit(rtl8192_usb_module_exit);
Linux kernel - Deliverables
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