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Merge branches 'pm-domains' and 'pm-cpufreq'
[deliverable/linux.git] / drivers / staging / rtl8192u / r819xU_phy.c
CommitLineData
8fc8598e
JC		 1#include "r8192U.h"
2#include "r8192U_hw.h"
3#include "r819xU_phy.h"
4#include "r819xU_phyreg.h"
5#include "r8190_rtl8256.h"
6#include "r8192U_dm.h"
7#include "r819xU_firmware_img.h"
8
8fc8598e 9#include "dot11d.h"
391c72a3
XR		 10#include <linux/bitops.h>
11
8fc8598e
JC		 12static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
13 0,
5f2392b8
XR		 14 0x085c, /* 2412 1 */
15 0x08dc, /* 2417 2 */
16 0x095c, /* 2422 3 */
17 0x09dc, /* 2427 4 */
18 0x0a5c, /* 2432 5 */
19 0x0adc, /* 2437 6 */
20 0x0b5c, /* 2442 7 */
21 0x0bdc, /* 2447 8 */
22 0x0c5c, /* 2452 9 */
23 0x0cdc, /* 2457 10 */
24 0x0d5c, /* 2462 11 */
25 0x0ddc, /* 2467 12 */
26 0x0e5c, /* 2472 13 */
27 0x0f72, /* 2484 */
8fc8598e
JC		 28};
29
30
31#define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
32#define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
33#define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
34#define rtl819XRadioA_Array Rtl8192UsbRadioA_Array
35#define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
36#define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
37#define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
38#define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
39
40/******************************************************************************
5f2392b8
XR		 41 * function: This function reads BB parameters from header file we generate,
42 * and does register read/write
43 * input: u32 bitmask //taget bit pos in the addr to be modified
44 * output: none
45 * return: u32 return the shift bit position of the mask
46 ******************************************************************************/
c92f473d 47static u32 rtl8192_CalculateBitShift(u32 bitmask)
8fc8598e
JC		 48{
49 u32 i;
0081fcc6 50
9f66ddb5 51 i = ffs(bitmask) - 1;
8fc8598e
JC		 52 return i;
53}
0081fcc6 54
8fc8598e 55/******************************************************************************
5f2392b8
XR		 56 * function: This function checks different RF type to execute legal judgement.
57 * If RF Path is illegal, we will return false.
58 * input: net_device *dev
59 * u32 eRFPath
60 * output: none
61 * return: 0(illegal, false), 1(legal, true)
62 *****************************************************************************/
88d8fe29 63u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
8fc8598e
JC		 64{
65 u8 ret = 1;
66 struct r8192_priv *priv = ieee80211_priv(dev);
0081fcc6 67
4a6094c3 68 if (priv->rf_type == RF_2T4R) {
8fc8598e 69 ret = 0;
4a6094c3 70 } else if (priv->rf_type == RF_1T2R) {
8fc8598e
JC		 71 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
72 ret = 1;
73 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
74 ret = 0;
75 }
76 return ret;
77}
0081fcc6 78
8fc8598e 79/******************************************************************************
5f2392b8
XR		 80 * function: This function sets specific bits to BB register
81 * input: net_device *dev
82 * u32 reg_addr //target addr to be modified
83 * u32 bitmask //taget bit pos to be modified
84 * u32 data //value to be write
85 * output: none
86 * return: none
87 * notice:
88 ******************************************************************************/
79931639
XR		 89void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
90 u32 data)
8fc8598e
JC		 91{
92
79931639 93 u32 reg, bitshift;
8fc8598e 94
5f2392b8 95 if (bitmask != bMaskDWord) {
79931639
XR		 96 read_nic_dword(dev, reg_addr, &reg);
97 bitshift = rtl8192_CalculateBitShift(bitmask);
9f66ddb5 98 reg &= ~bitmask;
79931639
XR		 99 reg |= data << bitshift;
100 write_nic_dword(dev, reg_addr, reg);
4a6094c3 101 } else {
79931639 102 write_nic_dword(dev, reg_addr, data);
4a6094c3 103 }
8fc8598e 104}
0081fcc6 105
8fc8598e 106/******************************************************************************
5f2392b8
XR		 107 * function: This function reads specific bits from BB register
108 * input: net_device *dev
98bedd77
KS		 109 * u32 reg_addr //target addr to be readback
110 * u32 bitmask //taget bit pos to be readback
5f2392b8 111 * output: none
98bedd77 112 * return: u32 data //the readback register value
5f2392b8
XR		 113 * notice:
114 ******************************************************************************/
79931639 115u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
8fc8598e 116{
c4b5eb8c 117 u32 reg, bitshift;
8fc8598e 118
79931639
XR		 119 read_nic_dword(dev, reg_addr, &reg);
120 bitshift = rtl8192_CalculateBitShift(bitmask);
8fc8598e 121
c4b5eb8c 122 return (reg & bitmask) >> bitshift;
8fc8598e 123}
0081fcc6 124
442543d7 125static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
79931639 126 u32 offset);
8fc8598e 127
442543d7 128static void phy_FwRFSerialWrite(struct net_device *dev,
79931639
XR		 129 RF90_RADIO_PATH_E eRFPath, u32 offset,
130 u32 data);
8fc8598e
JC		 131
132/******************************************************************************
5f2392b8
XR		 133 * function: This function reads register from RF chip
134 * input: net_device *dev
135 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
136 * u32 offset //target address to be read
137 * output: none
138 * return: u32 readback value
139 * notice: There are three types of serial operations:
140 * (1) Software serial write.
141 * (2)Hardware LSSI-Low Speed Serial Interface.
142 * (3)Hardware HSSI-High speed serial write.
143 * Driver here need to implement (1) and (2)
144 * ---need more spec for this information.
145 ******************************************************************************/
c92f473d
AR		 146static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
147 RF90_RADIO_PATH_E eRFPath, u32 offset)
8fc8598e
JC		 148{
149 struct r8192_priv *priv = ieee80211_priv(dev);
150 u32 ret = 0;
79931639 151 u32 new_offset = 0;
88d8fe29 152 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
0081fcc6 153
8fc8598e 154 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
5f2392b8 155 /* Make sure RF register offset is correct */
79931639 156 offset &= 0x3f;
8fc8598e 157
5f2392b8 158 /* Switch page for 8256 RF IC */
4a6094c3 159 if (priv->rf_chip == RF_8256) {
79931639 160 if (offset >= 31) {
8fc8598e 161 priv->RfReg0Value[eRFPath] |= 0x140;
5f2392b8 162 /* Switch to Reg_Mode2 for Reg 31-45 */
1db5aa05
XR		 163 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
164 bMaskDWord,
165 priv->RfReg0Value[eRFPath]<<16);
5f2392b8 166 /* Modify offset */
79931639
XR		 167 new_offset = offset - 30;
168 } else if (offset >= 16) {
8fc8598e
JC		 169 priv->RfReg0Value[eRFPath] |= 0x100;
170 priv->RfReg0Value[eRFPath] &= (~0x40);
5f2392b8 171 /* Switch to Reg_Mode1 for Reg16-30 */
1db5aa05
XR		 172 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
173 bMaskDWord,
174 priv->RfReg0Value[eRFPath]<<16);
8fc8598e 175
79931639 176 new_offset = offset - 15;
4a6094c3 177 } else {
79931639 178 new_offset = offset;
4a6094c3
XR		 179 }
180 } else {
1db5aa05
XR		 181 RT_TRACE((COMP_PHY|COMP_ERR),
182 "check RF type here, need to be 8256\n");
79931639 183 new_offset = offset;
8fc8598e 184 }
5f2392b8 185 /* Put desired read addr to LSSI control Register */
1db5aa05
XR		 186 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
187 new_offset);
5f2392b8 188 /* Issue a posedge trigger */
8fc8598e
JC		 189 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
190 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
191
192
5f2392b8 193 /* TODO: we should not delay such a long time. Ask for help from SD3 */
26f3561d 194 usleep_range(1000, 1000);
8fc8598e 195
1db5aa05
XR		 196 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
197 bLSSIReadBackData);
8fc8598e
JC		 198
199
5f2392b8 200 /* Switch back to Reg_Mode0 */
1111b876 201 if (priv->rf_chip == RF_8256) {
8fc8598e
JC		 202 priv->RfReg0Value[eRFPath] &= 0xebf;
203
1db5aa05
XR		 204 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
205 priv->RfReg0Value[eRFPath] << 16);
8fc8598e
JC		 206 }
207
208 return ret;
8fc8598e
JC		 209}
210
211/******************************************************************************
5f2392b8
XR		 212 * function: This function writes data to RF register
213 * input: net_device *dev
214 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
215 * u32 offset //target address to be written
216 * u32 data //the new register data to be written
217 * output: none
218 * return: none
219 * notice: For RF8256 only.
220 * ===========================================================================
221 * Reg Mode RegCTL[1] RegCTL[0] Note
8fc8598e 222 * (Reg00[12]) (Reg00[10])
5f2392b8
XR		 223 * ===========================================================================
224 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf)
225 * ---------------------------------------------------------------------------
226 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf)
227 * ---------------------------------------------------------------------------
8fc8598e 228 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
5f2392b8
XR		 229 * ---------------------------------------------------------------------------
230 *****************************************************************************/
c92f473d
AR		 231static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
232 RF90_RADIO_PATH_E eRFPath, u32 offset,
233 u32 data)
8fc8598e
JC		 234{
235 struct r8192_priv *priv = ieee80211_priv(dev);
79931639 236 u32 DataAndAddr = 0, new_offset = 0;
8fc8598e
JC		 237 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
238
79931639 239 offset &= 0x3f;
4a6094c3 240 if (priv->rf_chip == RF_8256) {
8fc8598e 241
79931639 242 if (offset >= 31) {
8fc8598e 243 priv->RfReg0Value[eRFPath] |= 0x140;
1db5aa05
XR		 244 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
245 bMaskDWord,
246 priv->RfReg0Value[eRFPath] << 16);
79931639
XR		 247 new_offset = offset - 30;
248 } else if (offset >= 16) {
8fc8598e
JC		 249 priv->RfReg0Value[eRFPath] |= 0x100;
250 priv->RfReg0Value[eRFPath] &= (~0x40);
1db5aa05
XR		 251 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
252 bMaskDWord,
253 priv->RfReg0Value[eRFPath]<<16);
79931639 254 new_offset = offset - 15;
4a6094c3 255 } else {
79931639 256 new_offset = offset;
4a6094c3
XR		 257 }
258 } else {
1db5aa05
XR		 259 RT_TRACE((COMP_PHY|COMP_ERR),
260 "check RF type here, need to be 8256\n");
79931639 261 new_offset = offset;
8fc8598e
JC		 262 }
263
5f2392b8 264 /* Put write addr in [5:0] and write data in [31:16] */
79931639 265 DataAndAddr = (data<<16) | (new_offset&0x3f);
8fc8598e 266
5f2392b8 267 /* Write operation */
8fc8598e
JC		 268 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
269
270
79931639
XR		 271 if (offset == 0x0)
272 priv->RfReg0Value[eRFPath] = data;
8fc8598e 273
5f2392b8 274 /* Switch back to Reg_Mode0 */
1111b876 275 if (priv->rf_chip == RF_8256) {
79931639 276 if (offset != 0) {
8fc8598e 277 priv->RfReg0Value[eRFPath] &= 0xebf;
1db5aa05
XR		 278 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
279 bMaskDWord,
280 priv->RfReg0Value[eRFPath] << 16);
8fc8598e
JC		 281 }
282 }
8fc8598e
JC		 283}
284
285/******************************************************************************
5f2392b8
XR		 286 * function: This function set specific bits to RF register
287 * input: net_device dev
288 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
289 * u32 reg_addr //target addr to be modified
290 * u32 bitmask //taget bit pos to be modified
291 * u32 data //value to be written
292 * output: none
293 * return: none
294 * notice:
295 *****************************************************************************/
442543d7 296void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
79931639 297 u32 reg_addr, u32 bitmask, u32 data)
8fc8598e
JC		 298{
299 struct r8192_priv *priv = ieee80211_priv(dev);
79931639 300 u32 reg, bitshift;
8fc8598e
JC		 301
302 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
303 return;
304
4a6094c3 305 if (priv->Rf_Mode == RF_OP_By_FW) {
5f2392b8
XR		 306 if (bitmask != bMask12Bits) {
307 /* RF data is 12 bits only */
79931639
XR		 308 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
309 bitshift = rtl8192_CalculateBitShift(bitmask);
9f66ddb5 310 reg &= ~bitmask;
79931639 311 reg |= data << bitshift;
8fc8598e 312
79931639 313 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
4a6094c3 314 } else {
79931639 315 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
4a6094c3 316 }
8fc8598e
JC		 317
318 udelay(200);
319
4a6094c3 320 } else {
5f2392b8
XR		 321 if (bitmask != bMask12Bits) {
322 /* RF data is 12 bits only */
79931639
XR		 323 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
324 bitshift = rtl8192_CalculateBitShift(bitmask);
9f66ddb5 325 reg &= ~bitmask;
79931639 326 reg |= data << bitshift;
8fc8598e 327
79931639 328 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
4a6094c3 329 } else {
79931639 330 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
4a6094c3 331 }
8fc8598e 332 }
8fc8598e
JC		 333}
334
335/******************************************************************************
5f2392b8
XR		 336 * function: This function reads specific bits from RF register
337 * input: net_device *dev
338 * u32 reg_addr //target addr to be readback
339 * u32 bitmask //taget bit pos to be readback
340 * output: none
341 * return: u32 data //the readback register value
342 * notice:
343 *****************************************************************************/
442543d7 344u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
79931639 345 u32 reg_addr, u32 bitmask)
8fc8598e 346{
79931639 347 u32 reg, bitshift;
8fc8598e
JC		 348 struct r8192_priv *priv = ieee80211_priv(dev);
349
350
351 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
352 return 0;
4a6094c3 353 if (priv->Rf_Mode == RF_OP_By_FW) {
79931639 354 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
8fc8598e 355 udelay(200);
4a6094c3 356 } else {
79931639 357 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
8fc8598e 358 }
d0049dfc
KS		 359 bitshift = rtl8192_CalculateBitShift(bitmask);
360 reg = (reg & bitmask) >> bitshift;
361 return reg;
362
8fc8598e 363}
0081fcc6 364
8fc8598e 365/******************************************************************************
5f2392b8
XR		 366 * function: We support firmware to execute RF-R/W.
367 * input: net_device *dev
368 * RF90_RADIO_PATH_E eRFPath
369 * u32 offset
370 * output: none
371 * return: u32
372 * notice:
373 ****************************************************************************/
442543d7 374static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
79931639 375 u32 offset)
8fc8598e 376{
07ecbbf1 377 u32 reg = 0;
79931639 378 u32 data = 0;
8fc8598e 379 u8 time = 0;
b3d42bf1 380 u32 tmp;
0081fcc6 381
5f2392b8
XR		 382 /* Firmware RF Write control.
383 * We can not execute the scheme in the initial step.
384 * Otherwise, RF-R/W will waste much time.
385 * This is only for site survey. */
386 /* 1. Read operation need not insert data. bit 0-11 */
387 /* 2. Write RF register address. bit 12-19 */
79931639 388 data |= ((offset&0xFF)<<12);
5f2392b8 389 /* 3. Write RF path. bit 20-21 */
79931639 390 data |= ((eRFPath&0x3)<<20);
5f2392b8
XR		 391 /* 4. Set RF read indicator. bit 22=0 */
392 /* 5. Trigger Fw to operate the command. bit 31 */
79931639 393 data |= 0x80000000;
5f2392b8 394 /* 6. We can not execute read operation if bit 31 is 1. */
b3d42bf1 395 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 396 while (tmp & 0x80000000) {
5f2392b8
XR		 397 /* If FW can not finish RF-R/W for more than ?? times.
398 We must reset FW. */
4a6094c3 399 if (time++ < 100) {
8fc8598e 400 udelay(10);
b3d42bf1 401 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 402 } else {
8fc8598e 403 break;
4a6094c3 404 }
8fc8598e 405 }
5f2392b8 406 /* 7. Execute read operation. */
79931639 407 write_nic_dword(dev, QPNR, data);
5f2392b8 408 /* 8. Check if firmware send back RF content. */
b3d42bf1 409 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 410 while (tmp & 0x80000000) {
5f2392b8
XR		 411 /* If FW can not finish RF-R/W for more than ?? times.
412 We must reset FW. */
4a6094c3 413 if (time++ < 100) {
8fc8598e 414 udelay(10);
b3d42bf1 415 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 416 } else {
4c8dd926 417 return 0;
4a6094c3 418 }
8fc8598e 419 }
07ecbbf1 420 read_nic_dword(dev, RF_DATA, &reg);
8fc8598e 421
07ecbbf1 422 return reg;
5f2392b8 423}
8fc8598e
JC		 424
425/******************************************************************************
5f2392b8
XR		 426 * function: We support firmware to execute RF-R/W.
427 * input: net_device *dev
428 * RF90_RADIO_PATH_E eRFPath
429 * u32 offset
430 * u32 data
431 * output: none
432 * return: none
433 * notice:
434 ****************************************************************************/
442543d7 435static void phy_FwRFSerialWrite(struct net_device *dev,
79931639 436 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
8fc8598e
JC		 437{
438 u8 time = 0;
b3d42bf1 439 u32 tmp;
8fc8598e 440
5f2392b8
XR		 441 /* Firmware RF Write control.
442 * We can not execute the scheme in the initial step.
443 * Otherwise, RF-R/W will waste much time.
444 * This is only for site survey. */
8fc8598e 445
5f2392b8
XR		 446 /* 1. Set driver write bit and 12 bit data. bit 0-11 */
447 /* 2. Write RF register address. bit 12-19 */
79931639 448 data |= ((offset&0xFF)<<12);
5f2392b8 449 /* 3. Write RF path. bit 20-21 */
79931639 450 data |= ((eRFPath&0x3)<<20);
5f2392b8 451 /* 4. Set RF write indicator. bit 22=1 */
79931639 452 data |= 0x400000;
5f2392b8 453 /* 5. Trigger Fw to operate the command. bit 31=1 */
79931639 454 data |= 0x80000000;
8fc8598e 455
5f2392b8 456 /* 6. Write operation. We can not write if bit 31 is 1. */
b3d42bf1 457 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 458 while (tmp & 0x80000000) {
5f2392b8
XR		 459 /* If FW can not finish RF-R/W for more than ?? times.
460 We must reset FW. */
4a6094c3 461 if (time++ < 100) {
8fc8598e 462 udelay(10);
b3d42bf1 463 read_nic_dword(dev, QPNR, &tmp);
4a6094c3 464 } else {
8fc8598e 465 break;
4a6094c3 466 }
8fc8598e 467 }
5f2392b8
XR		 468 /* 7. No matter check bit. We always force the write.
469 Because FW will not accept the command. */
79931639 470 write_nic_dword(dev, QPNR, data);
5f2392b8 471 /* According to test, we must delay 20us to wait firmware
8fc8598e 472 to finish RF write operation. */
5f2392b8 473 /* We support delay in firmware side now. */
5f2392b8 474}
8fc8598e 475
8fc8598e 476/******************************************************************************
5f2392b8
XR		 477 * function: This function reads BB parameters from header file we generate,
478 * and do register read/write
98bedd77 479 * input: net_device *dev
5f2392b8
XR		 480 * output: none
481 * return: none
482 * notice: BB parameters may change all the time, so please make
483 * sure it has been synced with the newest.
484 *****************************************************************************/
88d8fe29 485void rtl8192_phy_configmac(struct net_device *dev)
8fc8598e
JC		 486{
487 u32 dwArrayLen = 0, i;
88d8fe29 488 u32 *pdwArray = NULL;
8fc8598e
JC		 489 struct r8192_priv *priv = ieee80211_priv(dev);
490
1111b876 491 if (priv->btxpowerdata_readfromEEPORM) {
8fc8598e
JC		 492 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
493 dwArrayLen = MACPHY_Array_PGLength;
494 pdwArray = rtl819XMACPHY_Array_PG;
495
4a6094c3 496 } else {
8fc8598e
JC		 497 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
498 dwArrayLen = MACPHY_ArrayLength;
499 pdwArray = rtl819XMACPHY_Array;
500 }
9d8e79ed 501 for (i = 0; i < dwArrayLen; i = i+3) {
2930d0b9 502 if (pdwArray[i] == 0x318)
8fc8598e 503 pdwArray[i+2] = 0x00000800;
8fc8598e 504
1db5aa05
XR		 505 RT_TRACE(COMP_DBG,
506 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
507 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
508 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
509 pdwArray[i+2]);
8fc8598e 510 }
8fc8598e
JC		 511}
512
513/******************************************************************************
5f2392b8
XR		 514 * function: This function does dirty work
515 * input: net_device *dev
516 * u8 ConfigType
517 * output: none
518 * return: none
519 * notice: BB parameters may change all the time, so please make
520 * sure it has been synced with the newest.
521 *****************************************************************************/
88d8fe29 522void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
8fc8598e
JC		 523{
524 u32 i;
525
526#ifdef TO_DO_LIST
527 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
0081fcc6 528
1111b876 529 if (Adapter->bInHctTest) {
8fc8598e
JC		 530 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
531 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
532 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
533 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
534 }
535#endif
4a6094c3 536 if (ConfigType == BaseBand_Config_PHY_REG) {
9d8e79ed 537 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
1db5aa05
XR		 538 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
539 bMaskDWord,
540 rtl819XPHY_REG_1T2RArray[i+1]);
541 RT_TRACE(COMP_DBG,
542 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
543 i, rtl819XPHY_REG_1T2RArray[i],
544 rtl819XPHY_REG_1T2RArray[i+1]);
8fc8598e 545 }
4a6094c3 546 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
9d8e79ed 547 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
1db5aa05
XR		 548 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
549 bMaskDWord, rtl819XAGCTAB_Array[i+1]);
550 RT_TRACE(COMP_DBG,
551 "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
552 i, rtl819XAGCTAB_Array[i],
553 rtl819XAGCTAB_Array[i+1]);
8fc8598e
JC		 554 }
555 }
8fc8598e 556}
0081fcc6 557
8fc8598e 558/******************************************************************************
5f2392b8
XR		 559 * function: This function initializes Register definition offset for
560 * Radio Path A/B/C/D
561 * input: net_device *dev
562 * output: none
563 * return: none
564 * notice: Initialization value here is constant and it should never
565 * be changed
566 *****************************************************************************/
c92f473d 567static void rtl8192_InitBBRFRegDef(struct net_device *dev)
8fc8598e
JC		 568{
569 struct r8192_priv *priv = ieee80211_priv(dev);
0081fcc6 570
5f2392b8
XR		 571 /* RF Interface Software Control */
572 /* 16 LSBs if read 32-bit from 0x870 */
573 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
574 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
575 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
576 /* 16 LSBs if read 32-bit from 0x874 */
577 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
578 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
579 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
580
581 /* RF Interface Readback Value */
582 /* 16 LSBs if read 32-bit from 0x8E0 */
583 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
584 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
585 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
586 /* 16 LSBs if read 32-bit from 0x8E4 */
587 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
588 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
589 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
590
591 /* RF Interface Output (and Enable) */
592 /* 16 LSBs if read 32-bit from 0x860 */
593 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
594 /* 16 LSBs if read 32-bit from 0x864 */
595 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
596 /* 16 LSBs if read 32-bit from 0x868 */
597 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
598 /* 16 LSBs if read 32-bit from 0x86C */
599 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
600
601 /* RF Interface (Output and) Enable */
602 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
603 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
604 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
605 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
606 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
607 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
608 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
609 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
610
611 /* Addr of LSSI. Write RF register by driver */
612 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
8fc8598e
JC		 613 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
614 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
615 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
616
5f2392b8
XR		 617 /* RF parameter */
618 /* BB Band Select */
619 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
8fc8598e
JC		 620 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
621 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
622 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
623
5f2392b8
XR		 624 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
625 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
626 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
627 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
628 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
629
630 /* Tranceiver A~D HSSI Parameter-1 */
631 /* wire control parameter1 */
632 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
633 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
634 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
635 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
636
637 /* Tranceiver A~D HSSI Parameter-2 */
638 /* wire control parameter2 */
639 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
640 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
641 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
642 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
643
644 /* RF Switch Control */
645 /* TR/Ant switch control */
646 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
8fc8598e
JC		 647 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
648 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
649 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
650
5f2392b8 651 /* AGC control 1 */
8fc8598e
JC		 652 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
653 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
654 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
655 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
656
5f2392b8 657 /* AGC control 2 */
8fc8598e
JC		 658 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
659 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
660 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
661 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
662
5f2392b8 663 /* RX AFE control 1 */
8fc8598e
JC		 664 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
665 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
666 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
667 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
668
5f2392b8 669 /* RX AFE control 1 */
8fc8598e
JC		 670 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
671 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
672 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
673 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
674
5f2392b8 675 /* Tx AFE control 1 */
8fc8598e
JC		 676 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
677 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
678 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
679 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
680
5f2392b8 681 /* Tx AFE control 2 */
8fc8598e
JC		 682 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
683 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
684 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
685 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
686
5f2392b8 687 /* Tranceiver LSSI Readback */
8fc8598e
JC		 688 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
689 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
690 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
691 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
8fc8598e 692}
0081fcc6 693
8fc8598e 694/******************************************************************************
5f2392b8
XR		 695 * function: This function is to write register and then readback to make
696 * sure whether BB and RF is OK
697 * input: net_device *dev
698 * HW90_BLOCK_E CheckBlock
699 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is
700 * //HW90_BLOCK_RF
701 * output: none
702 * return: return whether BB and RF is ok (0:OK, 1:Fail)
703 * notice: This function may be removed in the ASIC
704 ******************************************************************************/
442543d7
XR		 705u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
706 RF90_RADIO_PATH_E eRFPath)
8fc8598e 707{
8fc8598e 708 u8 ret = 0;
a60d4d68 709 u32 i, CheckTimes = 4, reg = 0;
8fc8598e
JC		 710 u32 WriteAddr[4];
711 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
0081fcc6 712
5f2392b8 713 /* Initialize register address offset to be checked */
8fc8598e
JC		 714 WriteAddr[HW90_BLOCK_MAC] = 0x100;
715 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
716 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
717 WriteAddr[HW90_BLOCK_RF] = 0x3;
08a4cdea 718 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
111857c9 719 for (i = 0; i < CheckTimes; i++) {
8fc8598e 720
5f2392b8 721 /* Write data to register and readback */
4a6094c3 722 switch (CheckBlock) {
8fc8598e 723 case HW90_BLOCK_MAC:
1db5aa05 724 RT_TRACE(COMP_ERR,
0081fcc6 725 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
8fc8598e
JC		 726 break;
727
728 case HW90_BLOCK_PHY0:
729 case HW90_BLOCK_PHY1:
1db5aa05
XR		 730 write_nic_dword(dev, WriteAddr[CheckBlock],
731 WriteData[i]);
a60d4d68 732 read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
8fc8598e
JC		 733 break;
734
735 case HW90_BLOCK_RF:
736 WriteData[i] &= 0xfff;
1db5aa05
XR		 737 rtl8192_phy_SetRFReg(dev, eRFPath,
738 WriteAddr[HW90_BLOCK_RF],
739 bMask12Bits, WriteData[i]);
5f2392b8
XR		 740 /* TODO: we should not delay for such a long time.
741 Ask SD3 */
26f3561d 742 usleep_range(1000, 1000);
a60d4d68
XR		 743 reg = rtl8192_phy_QueryRFReg(dev, eRFPath,
744 WriteAddr[HW90_BLOCK_RF],
745 bMask12Bits);
26f3561d 746 usleep_range(1000, 1000);
8fc8598e
JC		 747 break;
748
749 default:
750 ret = 1;
751 break;
752 }
753
754
5f2392b8 755 /* Check whether readback data is correct */
a60d4d68 756 if (reg != WriteData[i]) {
1db5aa05 757 RT_TRACE((COMP_PHY|COMP_ERR),
a60d4d68
XR		 758 "error reg: %x, WriteData: %x\n",
759 reg, WriteData[i]);
8fc8598e
JC		 760 ret = 1;
761 break;
762 }
763 }
764
765 return ret;
766}
767
8fc8598e 768/******************************************************************************
5f2392b8
XR		 769 * function: This function initializes BB&RF
770 * input: net_device *dev
771 * output: none
772 * return: none
773 * notice: Initialization value may change all the time, so please make
774 * sure it has been synced with the newest.
775 ******************************************************************************/
c92f473d 776static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
8fc8598e
JC		 777{
778 struct r8192_priv *priv = ieee80211_priv(dev);
a60d4d68 779 u8 reg_u8 = 0, eCheckItem = 0, status = 0;
07ecbbf1 780 u32 reg_u32 = 0;
0081fcc6 781
8fc8598e 782 /**************************************
5f2392b8
XR		 783 * <1> Initialize BaseBand
784 *************************************/
8fc8598e 785
5f2392b8 786 /* --set BB Global Reset-- */
07ecbbf1 787 read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
83e6d9e2 788 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
8fc8598e 789 mdelay(50);
5f2392b8 790 /* ---set BB reset Active--- */
07ecbbf1
XR		 791 read_nic_dword(dev, CPU_GEN, &reg_u32);
792 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
8fc8598e 793
5f2392b8
XR		 794 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
795 /* TODO: this function should be removed on ASIC */
1db5aa05
XR		 796 for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
797 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
798 /* don't care RF path */
a60d4d68
XR		 799 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
800 (RF90_RADIO_PATH_E)0);
801 if (status != 0) {
1db5aa05
XR		 802 RT_TRACE((COMP_ERR | COMP_PHY),
803 "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
804 eCheckItem-1);
111857c9 805 return;
8fc8598e
JC		 806 }
807 }
5f2392b8 808 /* ---- Set CCK and OFDM Block "OFF"---- */
8fc8598e 809 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
5f2392b8
XR		 810 /* ----BB Register Initilazation---- */
811 /* ==m==>Set PHY REG From Header<==m== */
8fc8598e
JC		 812 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
813
5f2392b8 814 /* ----Set BB reset de-Active---- */
07ecbbf1
XR		 815 read_nic_dword(dev, CPU_GEN, &reg_u32);
816 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
8fc8598e 817
5f2392b8
XR		 818 /* ----BB AGC table Initialization---- */
819 /* ==m==>Set PHY REG From Header<==m== */
8fc8598e
JC		 820 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
821
5f2392b8 822 /* ----Enable XSTAL ---- */
8fc8598e 823 write_nic_byte_E(dev, 0x5e, 0x00);
4a6094c3 824 if (priv->card_8192_version == (u8)VERSION_819xU_A) {
5f2392b8 825 /* Antenna gain offset from B/C/D to A */
2060f31a
HM		 826 reg_u32 = priv->AntennaTxPwDiff[1]<<4 |
827 priv->AntennaTxPwDiff[0];
1db5aa05
XR		 828 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
829 reg_u32);
8fc8598e 830
5f2392b8 831 /* XSTALLCap */
07ecbbf1 832 reg_u32 = priv->CrystalCap & 0xf;
1db5aa05
XR		 833 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
834 reg_u32);
8fc8598e
JC		 835 }
836
5f2392b8
XR		 837 /* Check if the CCK HighPower is turned ON.
838 This is used to calculate PWDB. */
1db5aa05
XR		 839 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
840 rFPGA0_XA_HSSIParameter2,
841 0x200);
8fc8598e 842}
0081fcc6 843
8fc8598e 844/******************************************************************************
5f2392b8
XR		 845 * function: This function initializes BB&RF
846 * input: net_device *dev
847 * output: none
848 * return: none
849 * notice: Initialization value may change all the time, so please make
850 * sure it has been synced with the newest.
851 *****************************************************************************/
88d8fe29 852void rtl8192_BBConfig(struct net_device *dev)
8fc8598e
JC		 853{
854 rtl8192_InitBBRFRegDef(dev);
5f2392b8
XR		 855 /* config BB&RF. As hardCode based initialization has not been well
856 * implemented, so use file first.
857 * FIXME: should implement it for hardcode? */
8fc8598e 858 rtl8192_BB_Config_ParaFile(dev);
8fc8598e
JC		 859}
860
0081fcc6 861
8fc8598e 862/******************************************************************************
5f2392b8
XR		 863 * function: This function obtains the initialization value of Tx power Level
864 * offset
865 * input: net_device *dev
866 * output: none
867 * return: none
868 *****************************************************************************/
88d8fe29 869void rtl8192_phy_getTxPower(struct net_device *dev)
8fc8598e
JC		 870{
871 struct r8192_priv *priv = ieee80211_priv(dev);
b3d42bf1 872 u8 tmp;
0081fcc6 873
1db5aa05
XR		 874 read_nic_dword(dev, rTxAGC_Rate18_06,
875 &priv->MCSTxPowerLevelOriginalOffset[0]);
876 read_nic_dword(dev, rTxAGC_Rate54_24,
877 &priv->MCSTxPowerLevelOriginalOffset[1]);
878 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
879 &priv->MCSTxPowerLevelOriginalOffset[2]);
880 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
881 &priv->MCSTxPowerLevelOriginalOffset[3]);
882 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
883 &priv->MCSTxPowerLevelOriginalOffset[4]);
884 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
885 &priv->MCSTxPowerLevelOriginalOffset[5]);
8fc8598e 886
5f2392b8 887 /* Read rx initial gain */
b3d42bf1
XR		 888 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
889 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
890 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
891 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
1db5aa05
XR		 892 RT_TRACE(COMP_INIT,
893 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
894 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
895 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
8fc8598e 896
5f2392b8 897 /* Read framesync */
b3d42bf1
XR		 898 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
899 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
900 priv->framesyncC34 = tmp;
d5133e75 901 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
8fc8598e
JC		 902 rOFDM0_RxDetector3, priv->framesync);
903
5f2392b8 904 /* Read SIFS (save the value read fome MACPHY_REG.txt) */
b3d42bf1 905 read_nic_word(dev, SIFS, &priv->SifsTime);
8fc8598e
JC		 906}
907
908/******************************************************************************
5f2392b8
XR		 909 * function: This function sets the initialization value of Tx power Level
910 * offset
911 * input: net_device *dev
912 * u8 channel
913 * output: none
914 * return: none
915 ******************************************************************************/
88d8fe29 916void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
8fc8598e
JC		 917{
918 struct r8192_priv *priv = ieee80211_priv(dev);
919 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
920 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
921
4a6094c3 922 switch (priv->rf_chip) {
8fc8598e 923 case RF_8256:
1db5aa05
XR		 924 /* need further implement */
925 PHY_SetRF8256CCKTxPower(dev, powerlevel);
8fc8598e
JC		 926 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
927 break;
928 default:
1db5aa05
XR		 929 RT_TRACE((COMP_PHY|COMP_ERR),
930 "error RF chipID(8225 or 8258) in function %s()\n",
08a4cdea 931 __func__);
8fc8598e
JC		 932 break;
933 }
8fc8598e
JC		 934}
935
936/******************************************************************************
5f2392b8
XR		 937 * function: This function checks Rf chip to do RF config
938 * input: net_device *dev
939 * output: none
940 * return: only 8256 is supported
941 ******************************************************************************/
88d8fe29 942void rtl8192_phy_RFConfig(struct net_device *dev)
8fc8598e
JC		 943{
944 struct r8192_priv *priv = ieee80211_priv(dev);
945
4a6094c3 946 switch (priv->rf_chip) {
16ec1a20 947 case RF_8256:
948 PHY_RF8256_Config(dev);
949 break;
950 default:
951 RT_TRACE(COMP_ERR, "error chip id\n");
952 break;
8fc8598e 953 }
8fc8598e
JC		 954}
955
956/******************************************************************************
5f2392b8
XR		 957 * function: This function updates Initial gain
958 * input: net_device *dev
959 * output: none
960 * return: As Windows has not implemented this, wait for complement
961 ******************************************************************************/
88d8fe29 962void rtl8192_phy_updateInitGain(struct net_device *dev)
8fc8598e 963{
8fc8598e
JC		 964}
965
966/******************************************************************************
5f2392b8
XR		 967 * function: This function read RF parameters from general head file,
968 * and do RF 3-wire
969 * input: net_device *dev
970 * RF90_RADIO_PATH_E eRFPath
971 * output: none
972 * return: return code show if RF configuration is successful(0:pass, 1:fail)
973 * notice: Delay may be required for RF configuration
974 *****************************************************************************/
442543d7
XR		 975u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
976 RF90_RADIO_PATH_E eRFPath)
8fc8598e
JC		 977{
978
979 int i;
8fc8598e 980
4a6094c3 981 switch (eRFPath) {
24fbe875 982 case RF90_PATH_A:
9d8e79ed 983 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
8fc8598e 984
1111b876 985 if (rtl819XRadioA_Array[i] == 0xfe) {
1db5aa05
XR		 986 mdelay(100);
987 continue;
8fc8598e 988 }
1db5aa05
XR		 989 rtl8192_phy_SetRFReg(dev, eRFPath,
990 rtl819XRadioA_Array[i],
991 bMask12Bits,
992 rtl819XRadioA_Array[i+1]);
24fbe875 993 mdelay(1);
8fc8598e 994
24fbe875
SH		 995 }
996 break;
997 case RF90_PATH_B:
9d8e79ed 998 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
8fc8598e 999
1111b876 1000 if (rtl819XRadioB_Array[i] == 0xfe) {
1db5aa05
XR		 1001 mdelay(100);
1002 continue;
8fc8598e 1003 }
1db5aa05
XR		 1004 rtl8192_phy_SetRFReg(dev, eRFPath,
1005 rtl819XRadioB_Array[i],
1006 bMask12Bits,
1007 rtl819XRadioB_Array[i+1]);
24fbe875 1008 mdelay(1);
8fc8598e 1009
24fbe875
SH		 1010 }
1011 break;
1012 case RF90_PATH_C:
9d8e79ed 1013 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
8fc8598e 1014
1111b876 1015 if (rtl819XRadioC_Array[i] == 0xfe) {
1db5aa05
XR		 1016 mdelay(100);
1017 continue;
8fc8598e 1018 }
1db5aa05
XR		 1019 rtl8192_phy_SetRFReg(dev, eRFPath,
1020 rtl819XRadioC_Array[i],
1021 bMask12Bits,
1022 rtl819XRadioC_Array[i+1]);
24fbe875 1023 mdelay(1);
8fc8598e 1024
24fbe875
SH		 1025 }
1026 break;
1027 case RF90_PATH_D:
9d8e79ed 1028 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
8fc8598e 1029
1111b876 1030 if (rtl819XRadioD_Array[i] == 0xfe) {
1db5aa05
XR		 1031 mdelay(100);
1032 continue;
8fc8598e 1033 }
1db5aa05
XR		 1034 rtl8192_phy_SetRFReg(dev, eRFPath,
1035 rtl819XRadioD_Array[i],
1036 bMask12Bits,
1037 rtl819XRadioD_Array[i+1]);
24fbe875
SH		 1038 mdelay(1);
1039
1040 }
1041 break;
1042 default:
1043 break;
8fc8598e
JC		 1044 }
1045
4764ca98 1046 return 0;
8fc8598e
JC		 1047
1048}
0081fcc6 1049
8fc8598e 1050/******************************************************************************
5f2392b8
XR		 1051 * function: This function sets Tx Power of the channel
1052 * input: net_device *dev
1053 * u8 channel
1054 * output: none
1055 * return: none
1056 * notice:
1057 ******************************************************************************/
c92f473d 1058static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
8fc8598e
JC		 1059{
1060 struct r8192_priv *priv = ieee80211_priv(dev);
1061 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1062 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1063
4a6094c3 1064 switch (priv->rf_chip) {
8fc8598e
JC		 1065 case RF_8225:
1066#ifdef TO_DO_LIST
1067 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1068 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1069#endif
1070 break;
1071
1072 case RF_8256:
1073 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1074 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1075 break;
1076
1077 case RF_8258:
1078 break;
1079 default:
1db5aa05 1080 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
8fc8598e
JC		 1081 break;
1082 }
8fc8598e
JC		 1083}
1084
1085/******************************************************************************
5f2392b8
XR		 1086 * function: This function sets RF state on or off
1087 * input: net_device *dev
1088 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1089 * output: none
1090 * return: none
1091 * notice:
1092 *****************************************************************************/
442543d7
XR		 1093bool rtl8192_SetRFPowerState(struct net_device *dev,
1094 RT_RF_POWER_STATE eRFPowerState)
8fc8598e
JC		 1095{
1096 bool bResult = true;
8fc8598e
JC		 1097 struct r8192_priv *priv = ieee80211_priv(dev);
1098
1111b876 1099 if (eRFPowerState == priv->ieee80211->eRFPowerState)
8fc8598e
JC		 1100 return false;
1101
a0886f73 1102 if (priv->SetRFPowerStateInProgress)
8fc8598e
JC		 1103 return false;
1104
1105 priv->SetRFPowerStateInProgress = true;
1106
4a6094c3 1107 switch (priv->rf_chip) {
1db5aa05 1108 case RF_8256:
ceb56597 1109 switch (eRFPowerState) {
1db5aa05
XR		 1110 case eRfOn:
1111 /* RF-A, RF-B */
1112 /* enable RF-Chip A/B - 0x860[4] */
56b3152e 1113 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1db5aa05
XR		 1114 0x1);
1115 /* analog to digital on - 0x88c[9:8] */
1116 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1117 0x3);
1118 /* digital to analog on - 0x880[4:3] */
1119 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1120 0x3);
1121 /* rx antenna on - 0xc04[1:0] */
1122 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1123 /* rx antenna on - 0xd04[1:0] */
1124 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1125 /* analog to digital part2 on - 0x880[6:5] */
1126 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1127 0x3);
8fc8598e 1128
1db5aa05 1129 break;
8fc8598e 1130
1db5aa05 1131 case eRfSleep:
8fc8598e 1132
1db5aa05 1133 break;
8fc8598e 1134
1db5aa05
XR		 1135 case eRfOff:
1136 /* RF-A, RF-B */
1137 /* disable RF-Chip A/B - 0x860[4] */
56b3152e 1138 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1db5aa05
XR		 1139 0x0);
1140 /* analog to digital off, for power save */
1141 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1142 0x0); /* 0x88c[11:8] */
1143 /* digital to analog off, for power save - 0x880[4:3] */
1144 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1145 0x0);
1146 /* rx antenna off - 0xc04[3:0] */
1147 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1148 /* rx antenna off - 0xd04[3:0] */
1149 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1150 /* analog to digital part2 off, for power save */
1151 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1152 0x0); /* 0x880[6:5] */
8fc8598e 1153
8fc8598e 1154 break;
1db5aa05 1155
8fc8598e 1156 default:
1db5aa05
XR		 1157 bResult = false;
1158 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1159 __func__, eRFPowerState);
8fc8598e 1160 break;
1db5aa05
XR		 1161 }
1162 break;
1163 default:
1164 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1165 break;
8fc8598e
JC		 1166 }
1167#ifdef TO_DO_LIST
1111b876 1168 if (bResult) {
5f2392b8 1169 /* Update current RF state variable. */
8fc8598e 1170 pHalData->eRFPowerState = eRFPowerState;
ceb56597 1171 switch (pHalData->RFChipID) {
1db5aa05
XR		 1172 case RF_8256:
1173 switch (pHalData->eRFPowerState) {
1174 case eRfOff:
1175 /* If Rf off reason is from IPS,
1176 LED should blink with no link */
1177 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1178 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1179 else
1180 /* Turn off LED if RF is not ON. */
1181 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
8fc8598e
JC		 1182 break;
1183
1db5aa05
XR		 1184 case eRfOn:
1185 /* Turn on RF we are still linked, which might
1186 happen when we quickly turn off and on HW RF.
1187 */
352e579d 1188 if (pMgntInfo->bMediaConnect)
1db5aa05
XR		 1189 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1190 else
1191 /* Turn off LED if RF is not ON. */
1192 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1193 break;
1194
1195 default:
1196 break;
8fc8598e 1197 }
1db5aa05
XR		 1198 break;
1199
1200 default:
1201 RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1202 __func__);
1203 break;
1204 }
8fc8598e
JC		 1205
1206 }
1207#endif
1208 priv->SetRFPowerStateInProgress = false;
1209
1210 return bResult;
1211}
1212
5f2392b8
XR		 1213/******************************************************************************
1214 * function: This function sets command table variable (struct SwChnlCmd).
1215 * input: SwChnlCmd *CmdTable //table to be set
1216 * u32 CmdTableIdx //variable index in table to be set
1217 * u32 CmdTableSz //table size
1218 * SwChnlCmdID CmdID //command ID to set
1219 * u32 Para1
1220 * u32 Para2
1221 * u32 msDelay
1222 * output:
1223 * return: true if finished, false otherwise
1224 * notice:
1225 ******************************************************************************/
c92f473d
AR		 1226static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1227 u32 CmdTableSz, SwChnlCmdID CmdID,
1228 u32 Para1, u32 Para2, u32 msDelay)
8fc8598e 1229{
88d8fe29 1230 SwChnlCmd *pCmd;
8fc8598e 1231
1111b876 1232 if (CmdTable == NULL) {
1db5aa05 1233 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
8fc8598e
JC		 1234 return false;
1235 }
1111b876 1236 if (CmdTableIdx >= CmdTableSz) {
1db5aa05
XR		 1237 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1238 __func__, CmdTableIdx, CmdTableSz);
8fc8598e
JC		 1239 return false;
1240 }
1241
1242 pCmd = CmdTable + CmdTableIdx;
1243 pCmd->CmdID = CmdID;
1244 pCmd->Para1 = Para1;
1245 pCmd->Para2 = Para2;
1246 pCmd->msDelay = msDelay;
1247
1248 return true;
1249}
0081fcc6 1250
8fc8598e 1251/******************************************************************************
5f2392b8
XR		 1252 * function: This function sets channel step by step
1253 * input: net_device *dev
1254 * u8 channel
1255 * u8 *stage //3 stages
1256 * u8 *step
1257 * u32 *delay //whether need to delay
1258 * output: store new stage, step and delay for next step
1259 * (combine with function above)
1260 * return: true if finished, false otherwise
1261 * notice: Wait for simpler function to replace it
1262 *****************************************************************************/
c92f473d
AR		 1263static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1264 u8 *stage, u8 *step, u32 *delay)
8fc8598e
JC		 1265{
1266 struct r8192_priv *priv = ieee80211_priv(dev);
1db5aa05
XR		 1267 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1268 u32 PreCommonCmdCnt;
1269 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1270 u32 PostCommonCmdCnt;
1271 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1272 u32 RfDependCmdCnt;
1273 SwChnlCmd *CurrentCmd = NULL;
8fc8598e 1274 u8 eRFPath;
8fc8598e 1275
1db5aa05 1276 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
08a4cdea 1277 __func__, *stage, *step, channel);
4a6094c3 1278 if (!IsLegalChannel(priv->ieee80211, channel)) {
1db5aa05 1279 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
5f2392b8
XR		 1280 /* return true to tell upper caller function this channel
1281 setting is finished! Or it will in while loop. */
1282 return true;
8fc8598e 1283 }
1db5aa05 1284 /* FIXME: need to check whether channel is legal or not here */
8fc8598e
JC		 1285
1286
1db5aa05
XR		 1287 /* <1> Fill up pre common command. */
1288 PreCommonCmdCnt = 0;
1289 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1290 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1291 0, 0, 0);
1292 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1293 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
8fc8598e 1294
1db5aa05
XR		 1295 /* <2> Fill up post common command. */
1296 PostCommonCmdCnt = 0;
8fc8598e 1297
1db5aa05
XR		 1298 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1299 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
8fc8598e 1300
1db5aa05
XR		 1301 /* <3> Fill up RF dependent command. */
1302 RfDependCmdCnt = 0;
1303 switch (priv->rf_chip) {
1304 case RF_8225:
1305 if (!(channel >= 1 && channel <= 14)) {
1306 RT_TRACE(COMP_ERR,
1307 "illegal channel for Zebra 8225: %d\n",
1308 channel);
1309 return true;
1310 }
1311 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1312 MAX_RFDEPENDCMD_CNT,
1313 CmdID_RF_WriteReg,
1314 rZebra1_Channel,
1315 RF_CHANNEL_TABLE_ZEBRA[channel],
1316 10);
1317 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1318 MAX_RFDEPENDCMD_CNT,
1319 CmdID_End, 0, 0, 0);
1320 break;
8fc8598e 1321
1db5aa05
XR		 1322 case RF_8256:
1323 /* TEST!! This is not the table for 8256!! */
1324 if (!(channel >= 1 && channel <= 14)) {
1325 RT_TRACE(COMP_ERR,
1326 "illegal channel for Zebra 8256: %d\n",
1327 channel);
8fc8598e 1328 return true;
8fc8598e 1329 }
1db5aa05
XR		 1330 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1331 MAX_RFDEPENDCMD_CNT,
1332 CmdID_RF_WriteReg,
1333 rZebra1_Channel, channel, 10);
1334 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1335 MAX_RFDEPENDCMD_CNT,
1336 CmdID_End, 0, 0, 0);
1337 break;
8fc8598e 1338
1db5aa05
XR		 1339 case RF_8258:
1340 break;
8fc8598e 1341
1db5aa05
XR		 1342 default:
1343 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1344 return true;
1db5aa05 1345 }
8fc8598e 1346
8fc8598e 1347
1db5aa05
XR		 1348 do {
1349 switch (*stage) {
1350 case 0:
1351 CurrentCmd = &PreCommonCmd[*step];
1352 break;
1353 case 1:
1354 CurrentCmd = &RfDependCmd[*step];
1355 break;
1356 case 2:
1357 CurrentCmd = &PostCommonCmd[*step];
1358 break;
1359 }
1360
1361 if (CurrentCmd->CmdID == CmdID_End) {
1362 if ((*stage) == 2) {
1363 (*delay) = CurrentCmd->msDelay;
1364 return true;
8fc8598e 1365 }
bf1c66e8
KS		 1366 (*stage)++;
1367 (*step) = 0;
1368 continue;
1db5aa05 1369 }
8fc8598e 1370
1db5aa05
XR		 1371 switch (CurrentCmd->CmdID) {
1372 case CmdID_SetTxPowerLevel:
1373 if (priv->card_8192_version == (u8)VERSION_819xU_A)
1374 /* consider it later! */
1375 rtl8192_SetTxPowerLevel(dev, channel);
8fc8598e 1376 break;
1db5aa05
XR		 1377 case CmdID_WritePortUlong:
1378 write_nic_dword(dev, CurrentCmd->Para1,
1379 CurrentCmd->Para2);
1380 break;
1381 case CmdID_WritePortUshort:
1382 write_nic_word(dev, CurrentCmd->Para1,
1383 (u16)CurrentCmd->Para2);
1384 break;
1385 case CmdID_WritePortUchar:
1386 write_nic_byte(dev, CurrentCmd->Para1,
1387 (u8)CurrentCmd->Para2);
1388 break;
1389 case CmdID_RF_WriteReg:
1390 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1391 rtl8192_phy_SetRFReg(dev,
1392 (RF90_RADIO_PATH_E)eRFPath,
1393 CurrentCmd->Para1,
1394 bZebra1_ChannelNum,
1395 CurrentCmd->Para2);
1396 }
1397 break;
1398 default:
1399 break;
1400 }
1401
1402 break;
1403 } while (true);
8fc8598e 1404
ec5d319b 1405 (*delay) = CurrentCmd->msDelay;
8fc8598e
JC		 1406 (*step)++;
1407 return false;
1408}
1409
1410/******************************************************************************
5f2392b8
XR		 1411 * function: This function does actually set channel work
1412 * input: net_device *dev
1413 * u8 channel
1414 * output: none
1415 * return: none
1416 * notice: We should not call this function directly
1417 *****************************************************************************/
c92f473d 1418static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
8fc8598e
JC		 1419{
1420 struct r8192_priv *priv = ieee80211_priv(dev);
1421 u32 delay = 0;
1422
1db5aa05
XR		 1423 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1424 &priv->SwChnlStep, &delay)) {
1111b876 1425 if (!priv->up)
8fc8598e
JC		 1426 break;
1427 }
1428}
0081fcc6 1429
8fc8598e 1430/******************************************************************************
5f2392b8
XR		 1431 * function: Callback routine of the work item for switch channel.
1432 * input: net_device *dev
8fc8598e 1433 *
5f2392b8
XR		 1434 * output: none
1435 * return: none
1436 *****************************************************************************/
8fc8598e
JC		 1437void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1438{
1439
1440 struct r8192_priv *priv = ieee80211_priv(dev);
1441
1db5aa05
XR		 1442 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1443 priv->chan);
8fc8598e
JC		 1444
1445
83e6d9e2 1446 rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
8fc8598e
JC		 1447
1448 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1449}
1450
1451/******************************************************************************
5f2392b8
XR		 1452 * function: This function scheduled actual work item to set channel
1453 * input: net_device *dev
1454 * u8 channel //channel to set
1455 * output: none
1456 * return: return code show if workitem is scheduled (1:pass, 0:fail)
1457 * notice: Delay may be required for RF configuration
1458 ******************************************************************************/
88d8fe29 1459u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
8fc8598e
JC		 1460{
1461 struct r8192_priv *priv = ieee80211_priv(dev);
657eb979 1462
08a4cdea 1463 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1db5aa05 1464 priv->SwChnlInProgress);
1111b876 1465 if (!priv->up)
8fc8598e 1466 return false;
1111b876 1467 if (priv->SwChnlInProgress)
8fc8598e
JC		 1468 return false;
1469
5f2392b8 1470 /* -------------------------------------------- */
4a6094c3 1471 switch (priv->ieee80211->mode) {
8fc8598e
JC		 1472 case WIRELESS_MODE_A:
1473 case WIRELESS_MODE_N_5G:
9d8e79ed 1474 if (channel <= 14) {
0081fcc6 1475 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
8fc8598e
JC		 1476 return false;
1477 }
1478 break;
1479 case WIRELESS_MODE_B:
9d8e79ed 1480 if (channel > 14) {
0081fcc6 1481 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
8fc8598e
JC		 1482 return false;
1483 }
1484 break;
1485 case WIRELESS_MODE_G:
1486 case WIRELESS_MODE_N_24G:
9d8e79ed 1487 if (channel > 14) {
0081fcc6 1488 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
8fc8598e
JC		 1489 return false;
1490 }
1491 break;
1492 }
5f2392b8 1493 /* -------------------------------------------- */
8fc8598e
JC		 1494
1495 priv->SwChnlInProgress = true;
1111b876 1496 if (channel == 0)
8fc8598e
JC		 1497 channel = 1;
1498
ec5d319b 1499 priv->chan = channel;
8fc8598e 1500
ec5d319b
XR		 1501 priv->SwChnlStage = 0;
1502 priv->SwChnlStep = 0;
d75340eb 1503 if (priv->up)
1db5aa05 1504 rtl8192_SwChnl_WorkItem(dev);
8fc8598e
JC		 1505
1506 priv->SwChnlInProgress = false;
1507 return true;
1508}
1509
8fc8598e 1510/******************************************************************************
5f2392b8
XR		 1511 * function: Callback routine of the work item for set bandwidth mode.
1512 * input: net_device *dev
1513 * output: none
1514 * return: none
1515 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1516 * test whether current work in the queue or not.//do I?
1517 *****************************************************************************/
8fc8598e
JC		 1518void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1519{
1520
1521 struct r8192_priv *priv = ieee80211_priv(dev);
1522 u8 regBwOpMode;
1523
1db5aa05 1524 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__,
4a8d1135 1525 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
8fc8598e
JC		 1526
1527
1111b876 1528 if (priv->rf_chip == RF_PSEUDO_11N) {
ec5d319b 1529 priv->SetBWModeInProgress = false;
8fc8598e
JC		 1530 return;
1531 }
1532
5f2392b8 1533 /* <1> Set MAC register */
b3d42bf1 1534 read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
8fc8598e 1535
4a6094c3 1536 switch (priv->CurrentChannelBW) {
1db5aa05
XR		 1537 case HT_CHANNEL_WIDTH_20:
1538 regBwOpMode |= BW_OPMODE_20MHZ;
1539 /* We have not verify whether this register works */
1540 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1541 break;
8fc8598e 1542
1db5aa05
XR		 1543 case HT_CHANNEL_WIDTH_20_40:
1544 regBwOpMode &= ~BW_OPMODE_20MHZ;
1545 /* We have not verify whether this register works */
1546 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1547 break;
8fc8598e 1548
1db5aa05
XR		 1549 default:
1550 RT_TRACE(COMP_ERR,
1551 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1552 priv->CurrentChannelBW);
1553 break;
8fc8598e
JC		 1554 }
1555
5f2392b8 1556 /* <2> Set PHY related register */
4a6094c3 1557 switch (priv->CurrentChannelBW) {
1db5aa05
XR		 1558 case HT_CHANNEL_WIDTH_20:
1559 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1560 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1561 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1562 0x00100000, 1);
1563
1564 /* Correct the tx power for CCK rate in 20M. */
1565 priv->cck_present_attentuation =
1566 priv->cck_present_attentuation_20Mdefault +
1567 priv->cck_present_attentuation_difference;
1568
1569 if (priv->cck_present_attentuation > 22)
1570 priv->cck_present_attentuation = 22;
1571 if (priv->cck_present_attentuation < 0)
1572 priv->cck_present_attentuation = 0;
1573 RT_TRACE(COMP_INIT,
1574 "20M, pHalData->CCKPresentAttentuation = %d\n",
1575 priv->cck_present_attentuation);
1576
1577 if (priv->chan == 14 && !priv->bcck_in_ch14) {
4b2faf80 1578 priv->bcck_in_ch14 = true;
1db5aa05
XR		 1579 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1580 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
4b2faf80 1581 priv->bcck_in_ch14 = false;
1db5aa05
XR		 1582 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1583 } else {
1584 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1585 }
8fc8598e 1586
1db5aa05
XR		 1587 break;
1588 case HT_CHANNEL_WIDTH_20_40:
1589 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1590 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1591 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1592 priv->nCur40MhzPrimeSC>>1);
1593 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1594 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1595 priv->nCur40MhzPrimeSC);
1596 priv->cck_present_attentuation =
1597 priv->cck_present_attentuation_40Mdefault +
1598 priv->cck_present_attentuation_difference;
1599
1600 if (priv->cck_present_attentuation > 22)
1601 priv->cck_present_attentuation = 22;
1602 if (priv->cck_present_attentuation < 0)
1603 priv->cck_present_attentuation = 0;
1604
1605 RT_TRACE(COMP_INIT,
1606 "40M, pHalData->CCKPresentAttentuation = %d\n",
1607 priv->cck_present_attentuation);
1608 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1609 priv->bcck_in_ch14 = true;
1610 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1611 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1612 priv->bcck_in_ch14 = false;
1613 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1614 } else {
1615 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1616 }
8fc8598e 1617
1db5aa05
XR		 1618 break;
1619 default:
1620 RT_TRACE(COMP_ERR,
1621 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1622 priv->CurrentChannelBW);
1623 break;
8fc8598e
JC		 1624
1625 }
5f2392b8
XR		 1626 /* Skip over setting of J-mode in BB register here.
1627 Default value is "None J mode". */
8fc8598e 1628
5f2392b8 1629 /* <3> Set RF related register */
ceb56597 1630 switch (priv->rf_chip) {
1db5aa05 1631 case RF_8225:
8fc8598e 1632#ifdef TO_DO_LIST
1db5aa05 1633 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
8fc8598e 1634#endif
1db5aa05 1635 break;
8fc8598e 1636
1db5aa05
XR		 1637 case RF_8256:
1638 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1639 break;
8fc8598e 1640
1db5aa05
XR		 1641 case RF_8258:
1642 break;
8fc8598e 1643
1db5aa05
XR		 1644 case RF_PSEUDO_11N:
1645 break;
8fc8598e 1646
1db5aa05
XR		 1647 default:
1648 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1649 break;
8fc8598e 1650 }
ec5d319b 1651 priv->SetBWModeInProgress = false;
8fc8598e 1652
0081fcc6 1653 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1db5aa05 1654 atomic_read(&priv->ieee80211->atm_swbw));
8fc8598e
JC		 1655}
1656
1657/******************************************************************************
5f2392b8
XR		 1658 * function: This function schedules bandwidth switch work.
1659 * input: struct net_deviceq *dev
1660 * HT_CHANNEL_WIDTH bandwidth //20M or 40M
1661 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care
1662 * output: none
1663 * return: none
1664 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1665 * test whether current work in the queue or not.//do I?
1666 *****************************************************************************/
79931639
XR		 1667void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1668 HT_EXTCHNL_OFFSET offset)
8fc8598e
JC		 1669{
1670 struct r8192_priv *priv = ieee80211_priv(dev);
1671
1111b876 1672 if (priv->SetBWModeInProgress)
8fc8598e 1673 return;
ec5d319b 1674 priv->SetBWModeInProgress = true;
8fc8598e 1675
79931639 1676 priv->CurrentChannelBW = bandwidth;
8fc8598e 1677
79931639 1678 if (offset == HT_EXTCHNL_OFFSET_LOWER)
8fc8598e 1679 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
79931639 1680 else if (offset == HT_EXTCHNL_OFFSET_UPPER)
8fc8598e
JC		 1681 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1682 else
1683 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1684
8fc8598e
JC		 1685 rtl8192_SetBWModeWorkItem(dev);
1686
1687}
1688
1689void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1690{
1691 struct r8192_priv *priv = ieee80211_priv(dev);
1692
1693 priv->InitialGainOperateType = Operation;
1694
1111b876 1695 if (priv->up)
83e6d9e2 1696 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
8fc8598e
JC		 1697}
1698
a115ee41 1699void InitialGainOperateWorkItemCallBack(struct work_struct *work)
8fc8598e 1700{
1db5aa05
XR		 1701 struct delayed_work *dwork = container_of(work, struct delayed_work,
1702 work);
1703 struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1704 initialgain_operate_wq);
1705 struct net_device *dev = priv->ieee80211->dev;
8fc8598e
JC		 1706#define SCAN_RX_INITIAL_GAIN 0x17
1707#define POWER_DETECTION_TH 0x08
9f66ddb5 1708 u32 bitmask;
8fc8598e
JC		 1709 u8 initial_gain;
1710 u8 Operation;
1711
1712 Operation = priv->InitialGainOperateType;
1713
4a6094c3 1714 switch (Operation) {
1db5aa05
XR		 1715 case IG_Backup:
1716 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1717 initial_gain = SCAN_RX_INITIAL_GAIN;
1718 bitmask = bMaskByte0;
1719 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1720 /* FW DIG OFF */
1721 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1722 priv->initgain_backup.xaagccore1 =
1723 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1724 priv->initgain_backup.xbagccore1 =
1725 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1726 priv->initgain_backup.xcagccore1 =
1727 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1728 priv->initgain_backup.xdagccore1 =
1729 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1730 bitmask = bMaskByte2;
1731 priv->initgain_backup.cca =
1732 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1733
1734 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1735 priv->initgain_backup.xaagccore1);
1736 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1737 priv->initgain_backup.xbagccore1);
1738 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1739 priv->initgain_backup.xcagccore1);
1740 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1741 priv->initgain_backup.xdagccore1);
1742 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1743 priv->initgain_backup.cca);
1744
d5133e75 1745 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1db5aa05
XR		 1746 initial_gain);
1747 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1748 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1749 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1750 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
d5133e75 1751 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1db5aa05
XR		 1752 POWER_DETECTION_TH);
1753 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1754 break;
1755 case IG_Restore:
1756 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1757 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1758 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1759 /* FW DIG OFF */
1760 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1761
1762 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1763 (u32)priv->initgain_backup.xaagccore1);
1764 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1765 (u32)priv->initgain_backup.xbagccore1);
1766 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1767 (u32)priv->initgain_backup.xcagccore1);
1768 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1769 (u32)priv->initgain_backup.xdagccore1);
1770 bitmask = bMaskByte2;
1771 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1772 (u32)priv->initgain_backup.cca);
1773
1774 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1775 priv->initgain_backup.xaagccore1);
1776 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1777 priv->initgain_backup.xbagccore1);
1778 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1779 priv->initgain_backup.xcagccore1);
1780 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1781 priv->initgain_backup.xdagccore1);
1782 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1783 priv->initgain_backup.cca);
8fc8598e 1784
1db5aa05 1785 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
8fc8598e 1786
1db5aa05
XR		 1787 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1788 /* FW DIG ON */
1789 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1790 break;
1791 default:
d5133e75 1792 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1db5aa05 1793 break;
8fc8598e
JC		 1794 }
1795}
Linux kernel - Deliverables
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