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staging: rtl8723au: ODM_IC_11N_SERIES is always true for SupportICType
[deliverable/linux.git] / drivers / staging / rtl8723au / hal / odm.c
CommitLineData
f7c92d2c
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15
16#include "odm_precomp.h"
050abc45 17#include "usb_ops_linux.h"
f7c92d2c
LF		 18
19static const u16 dB_Invert_Table[8][12] = {
20 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
21 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
22 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
23 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
24 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
25 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
26 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
27 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
28};
29
30static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { /* UL DL */
31 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
32 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
33 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
34 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
35 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
36 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
37 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
38 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP => 92U AP */
40 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
41};
42
43/* EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22 */
44
45/* Global var */
46u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
47 0x7f8001fe, /* 0, +6.0dB */
48 0x788001e2, /* 1, +5.5dB */
49 0x71c001c7, /* 2, +5.0dB */
50 0x6b8001ae, /* 3, +4.5dB */
51 0x65400195, /* 4, +4.0dB */
52 0x5fc0017f, /* 5, +3.5dB */
53 0x5a400169, /* 6, +3.0dB */
54 0x55400155, /* 7, +2.5dB */
55 0x50800142, /* 8, +2.0dB */
56 0x4c000130, /* 9, +1.5dB */
57 0x47c0011f, /* 10, +1.0dB */
58 0x43c0010f, /* 11, +0.5dB */
59 0x40000100, /* 12, +0dB */
60 0x3c8000f2, /* 13, -0.5dB */
61 0x390000e4, /* 14, -1.0dB */
62 0x35c000d7, /* 15, -1.5dB */
63 0x32c000cb, /* 16, -2.0dB */
64 0x300000c0, /* 17, -2.5dB */
65 0x2d4000b5, /* 18, -3.0dB */
66 0x2ac000ab, /* 19, -3.5dB */
67 0x288000a2, /* 20, -4.0dB */
68 0x26000098, /* 21, -4.5dB */
69 0x24000090, /* 22, -5.0dB */
70 0x22000088, /* 23, -5.5dB */
71 0x20000080, /* 24, -6.0dB */
72 0x1e400079, /* 25, -6.5dB */
73 0x1c800072, /* 26, -7.0dB */
74 0x1b00006c, /* 27. -7.5dB */
75 0x19800066, /* 28, -8.0dB */
76 0x18000060, /* 29, -8.5dB */
77 0x16c0005b, /* 30, -9.0dB */
78 0x15800056, /* 31, -9.5dB */
79 0x14400051, /* 32, -10.0dB */
80 0x1300004c, /* 33, -10.5dB */
81 0x12000048, /* 34, -11.0dB */
82 0x11000044, /* 35, -11.5dB */
83 0x10000040, /* 36, -12.0dB */
84 0x0f00003c,/* 37, -12.5dB */
85 0x0e400039,/* 38, -13.0dB */
86 0x0d800036,/* 39, -13.5dB */
87 0x0cc00033,/* 40, -14.0dB */
88 0x0c000030,/* 41, -14.5dB */
89 0x0b40002d,/* 42, -15.0dB */
90};
91
92u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
93 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
94 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
95 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
96 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
97 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
98 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
99 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
100 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
101 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
102 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
103 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
104 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
105 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
106 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
107 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
108 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
109 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
110 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
111 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
112 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
113 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
114 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
115 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
116 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
117 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
118 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
119 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
120 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
121 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
122 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
123 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
124 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
125 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
126};
127
128u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
129 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
130 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
131 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
132 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
133 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
134 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
135 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
136 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
137 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
138 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
139 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
140 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
141 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
142 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
143 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
144 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
145 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
146 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
147 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
148 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
149 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
150 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
151 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
152 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
153 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
154 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
155 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
156 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
157 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
158 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
159 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
160 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
161 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
162};
163
164/* Local Function predefine. */
165
166/* START------------COMMON INFO RELATED--------------- */
167void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
168
169void odm_CommonInfoSelfUpdate23a(struct dm_odm_t *pDM_Odm);
170
171void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
172
173void odm_CmnInfoHook_Debug23a(struct dm_odm_t *pDM_Odm);
174
175void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
176
177/* START---------------DIG--------------------------- */
178void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
179
180void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
181
182void odm_DIG23a(struct dm_odm_t *pDM_Odm);
183
184void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
185/* END---------------DIG--------------------------- */
186
187/* START-------BB POWER SAVE----------------------- */
188void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
189
190void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
191
192void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm);
193/* END---------BB POWER SAVE----------------------- */
194
195void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm);
196
197void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm);
198
199void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm);
200
201void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
202
f7c92d2c
LF		 203void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm);
204
205void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm);
206
207void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm);
208void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm);
209
210void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
211void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
212
213void odm_SwAntDivInit(struct dm_odm_t *pDM_Odm);
214
215void odm_SwAntDivInit_NIC(struct dm_odm_t *pDM_Odm);
216
217void odm_SwAntDivChkAntSwitch(struct dm_odm_t *pDM_Odm, u8 Step);
218
219void odm_SwAntDivChkAntSwitchNIC(struct dm_odm_t *pDM_Odm,
220 u8 Step
221 );
222
223void odm_SwAntDivChkAntSwitchCallback23a(unsigned long data);
224
f7c92d2c
LF		 225void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
226
227void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
228
229void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm);
230
231void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
232
233void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
234
235void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
236
237void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm);
238
239void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
240
241void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
242void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
243
244void odm_EdcaTurboCheck23aCE23a(struct dm_odm_t *pDM_Odm);
245
246#define RxDefaultAnt1 0x65a9
247#define RxDefaultAnt2 0x569a
248
249void odm_InitHybridAntDiv23a(struct dm_odm_t *pDM_Odm);
250
251bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
252 u32 OFDM_Ant1_Cnt,
253 u32 OFDM_Ant2_Cnt,
254 u32 CCK_Ant1_Cnt,
255 u32 CCK_Ant2_Cnt,
256 u8 *pDefAnt
257 );
258
259void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
260 u8 Ant,
261 bool bDualPath
262);
263
264void odm_HwAntDiv23a(struct dm_odm_t *pDM_Odm);
265
266/* 3 Export Interface */
267
268/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
269void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
270{
271 /* For all IC series */
272 odm_CommonInfoSelfInit23a(pDM_Odm);
273 odm_CmnInfoInit_Debug23a(pDM_Odm);
274 odm_DIG23aInit(pDM_Odm);
275 odm_RateAdaptiveMaskInit23a(pDM_Odm);
276
344af82c
JS		 277 odm23a_DynBBPSInit(pDM_Odm);
278 odm_DynamicTxPower23aInit(pDM_Odm);
279 odm_TXPowerTrackingInit23a(pDM_Odm);
280 ODM_EdcaTurboInit23a(pDM_Odm);
281 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
282 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
283 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
284 odm_InitHybridAntDiv23a(pDM_Odm);
285 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
286 odm_SwAntDivInit(pDM_Odm);
f7c92d2c
LF		 287}
288
289/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
290/* You can not add any dummy function here, be care, you can only use DM structure */
291/* to perform any new ODM_DM. */
292void ODM_DMWatchdog23a(struct dm_odm_t *pDM_Odm)
293{
294 /* 2012.05.03 Luke: For all IC series */
f7c92d2c
LF		 295 odm_CmnInfoHook_Debug23a(pDM_Odm);
296 odm_CmnInfoUpdate_Debug23a(pDM_Odm);
297 odm_CommonInfoSelfUpdate23a(pDM_Odm);
298 odm_FalseAlarmCounterStatistics23a(pDM_Odm);
299 odm_RSSIMonitorCheck23a(pDM_Odm);
300
301 /* 8723A or 8189ES platform */
302 /* NeilChen--2012--08--24-- */
303 /* Fix Leave LPS issue */
304 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */
344af82c 305 (pDM_Odm->SupportICType & ODM_RTL8723A)) {
f7c92d2c
LF		 306 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
307 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
308 odm_DIG23abyRSSI_LPS(pDM_Odm);
309 } else {
310 odm_DIG23a(pDM_Odm);
311 }
312
313 odm_CCKPacketDetectionThresh23a(pDM_Odm);
314
315 if (*(pDM_Odm->pbPowerSaving))
316 return;
317
318 odm_RefreshRateAdaptiveMask23a(pDM_Odm);
319
320 odm_DynamicBBPowerSaving23a(pDM_Odm);
321 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
322 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
323 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
324 odm_HwAntDiv23a(pDM_Odm);
325 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
326 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
327
344af82c
JS		 328 ODM_TXPowerTrackingCheck23a(pDM_Odm);
329 odm_EdcaTurboCheck23a(pDM_Odm);
f7c92d2c
LF		 330
331 odm_dtc(pDM_Odm);
332}
333
334/* */
335/* Init /.. Fixed HW value. Only init time. */
336/* */
337void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
338 enum odm_cmninfo CmnInfo,
339 u32 Value
340 )
341{
342 /* ODM_RT_TRACE(pDM_Odm,); */
343
344 /* */
345 /* This section is used for init value */
346 /* */
347 switch (CmnInfo) {
348 /* Fixed ODM value. */
349 case ODM_CMNINFO_ABILITY:
350 pDM_Odm->SupportAbility = (u32)Value;
351 break;
352 case ODM_CMNINFO_PLATFORM:
353 break;
354 case ODM_CMNINFO_INTERFACE:
355 pDM_Odm->SupportInterface = (u8)Value;
356 break;
357 case ODM_CMNINFO_MP_TEST_CHIP:
358 pDM_Odm->bIsMPChip = (u8)Value;
359 break;
360 case ODM_CMNINFO_IC_TYPE:
361 pDM_Odm->SupportICType = Value;
362 break;
363 case ODM_CMNINFO_CUT_VER:
364 pDM_Odm->CutVersion = (u8)Value;
365 break;
366 case ODM_CMNINFO_FAB_VER:
367 pDM_Odm->FabVersion = (u8)Value;
368 break;
369 case ODM_CMNINFO_RF_TYPE:
370 pDM_Odm->RFType = (u8)Value;
371 break;
372 case ODM_CMNINFO_RF_ANTENNA_TYPE:
373 pDM_Odm->AntDivType = (u8)Value;
374 break;
375 case ODM_CMNINFO_BOARD_TYPE:
376 pDM_Odm->BoardType = (u8)Value;
377 break;
378 case ODM_CMNINFO_EXT_LNA:
379 pDM_Odm->ExtLNA = (u8)Value;
380 break;
381 case ODM_CMNINFO_EXT_PA:
382 pDM_Odm->ExtPA = (u8)Value;
383 break;
384 case ODM_CMNINFO_EXT_TRSW:
385 pDM_Odm->ExtTRSW = (u8)Value;
386 break;
387 case ODM_CMNINFO_PATCH_ID:
388 pDM_Odm->PatchID = (u8)Value;
389 break;
390 case ODM_CMNINFO_BINHCT_TEST:
391 pDM_Odm->bInHctTest = (bool)Value;
392 break;
393 case ODM_CMNINFO_BWIFI_TEST:
394 pDM_Odm->bWIFITest = (bool)Value;
395 break;
396 case ODM_CMNINFO_SMART_CONCURRENT:
397 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
398 break;
399 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
400 default:
401 /* do nothing */
402 break;
403 }
404
405 /* */
406 /* Tx power tracking BB swing table. */
407 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
408 /* */
409 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */
410 pDM_Odm->BbSwingIdxOfdmCurrent = 12;
411 pDM_Odm->BbSwingFlagOfdm = false;
412
413}
414
415void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm,
416 enum odm_cmninfo CmnInfo,
417 void *pValue
418 )
419{
420 /* Hook call by reference pointer. */
421 switch (CmnInfo) {
422 /* Dynamic call by reference pointer. */
423 case ODM_CMNINFO_MAC_PHY_MODE:
424 pDM_Odm->pMacPhyMode = (u8 *)pValue;
425 break;
426 case ODM_CMNINFO_TX_UNI:
427 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue;
428 break;
429 case ODM_CMNINFO_RX_UNI:
430 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue;
431 break;
432 case ODM_CMNINFO_WM_MODE:
433 pDM_Odm->pWirelessMode = (u8 *)pValue;
434 break;
435 case ODM_CMNINFO_BAND:
436 pDM_Odm->pBandType = (u8 *)pValue;
437 break;
438 case ODM_CMNINFO_SEC_CHNL_OFFSET:
439 pDM_Odm->pSecChOffset = (u8 *)pValue;
440 break;
441 case ODM_CMNINFO_SEC_MODE:
442 pDM_Odm->pSecurity = (u8 *)pValue;
443 break;
444 case ODM_CMNINFO_BW:
445 pDM_Odm->pBandWidth = (u8 *)pValue;
446 break;
447 case ODM_CMNINFO_CHNL:
448 pDM_Odm->pChannel = (u8 *)pValue;
449 break;
450 case ODM_CMNINFO_DMSP_GET_VALUE:
451 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue;
452 break;
453 case ODM_CMNINFO_BUDDY_ADAPTOR:
454 pDM_Odm->pBuddyAdapter = (struct rtw_adapter **)pValue;
455 break;
456 case ODM_CMNINFO_DMSP_IS_MASTER:
457 pDM_Odm->pbMasterOfDMSP = (bool *)pValue;
458 break;
459 case ODM_CMNINFO_SCAN:
460 pDM_Odm->pbScanInProcess = (bool *)pValue;
461 break;
462 case ODM_CMNINFO_POWER_SAVING:
463 pDM_Odm->pbPowerSaving = (bool *)pValue;
464 break;
465 case ODM_CMNINFO_ONE_PATH_CCA:
466 pDM_Odm->pOnePathCCA = (u8 *)pValue;
467 break;
468 case ODM_CMNINFO_DRV_STOP:
469 pDM_Odm->pbDriverStopped = (bool *)pValue;
470 break;
471 case ODM_CMNINFO_PNP_IN:
472 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue;
473 break;
474 case ODM_CMNINFO_INIT_ON:
475 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue;
476 break;
477 case ODM_CMNINFO_ANT_TEST:
478 pDM_Odm->pAntennaTest = (u8 *)pValue;
479 break;
480 case ODM_CMNINFO_NET_CLOSED:
481 pDM_Odm->pbNet_closed = (bool *)pValue;
482 break;
483 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
484 default:
485 /* do nothing */
486 break;
487 }
488}
489
490void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
491 u16 Index, void *pValue)
492{
493 /* Hook call by reference pointer. */
494 switch (CmnInfo) {
495 /* Dynamic call by reference pointer. */
496 case ODM_CMNINFO_STA_STATUS:
497 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
498 break;
499 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
500 default:
501 /* do nothing */
502 break;
503 }
504}
505
506/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */
507void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
508{
509 /* This init variable may be changed in run time. */
510 switch (CmnInfo) {
511 case ODM_CMNINFO_ABILITY:
512 pDM_Odm->SupportAbility = (u32)Value;
513 break;
514 case ODM_CMNINFO_RF_TYPE:
515 pDM_Odm->RFType = (u8)Value;
516 break;
517 case ODM_CMNINFO_WIFI_DIRECT:
518 pDM_Odm->bWIFI_Direct = (bool)Value;
519 break;
520 case ODM_CMNINFO_WIFI_DISPLAY:
521 pDM_Odm->bWIFI_Display = (bool)Value;
522 break;
523 case ODM_CMNINFO_LINK:
524 pDM_Odm->bLinked = (bool)Value;
525 break;
526 case ODM_CMNINFO_RSSI_MIN:
527 pDM_Odm->RSSI_Min = (u8)Value;
528 break;
529 case ODM_CMNINFO_DBG_COMP:
530 pDM_Odm->DebugComponents = Value;
531 break;
532 case ODM_CMNINFO_DBG_LEVEL:
533 pDM_Odm->DebugLevel = (u32)Value;
534 break;
535 case ODM_CMNINFO_RA_THRESHOLD_HIGH:
536 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
537 break;
538 case ODM_CMNINFO_RA_THRESHOLD_LOW:
539 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
540 break;
541 }
542
543}
544
545void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
546 )
547{
fc8b7c8c 548 pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT(9));
f7c92d2c 549 pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
344af82c 550 if (pDM_Odm->SupportICType & ODM_RTL8723A)
f7c92d2c
LF		 551 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
552
553 ODM_InitDebugSetting23a(pDM_Odm);
554}
555
556void odm_CommonInfoSelfUpdate23a(struct dm_odm_t *pDM_Odm)
557{
558 u8 EntryCnt = 0;
559 u8 i;
560 struct sta_info *pEntry;
561
562 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) {
563 if (*(pDM_Odm->pSecChOffset) == 1)
564 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
565 else if (*(pDM_Odm->pSecChOffset) == 2)
566 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
567 } else {
568 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
569 }
570
571 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
572 pEntry = pDM_Odm->pODM_StaInfo[i];
573 if (IS_STA_VALID(pEntry))
574 EntryCnt++;
575 }
576 if (EntryCnt == 1)
577 pDM_Odm->bOneEntryOnly = true;
578 else
579 pDM_Odm->bOneEntryOnly = false;
580}
581
582void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
583{
584 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
585 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
586 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
587 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
588 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
589 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
590 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType =%d\n", pDM_Odm->RFType));
591 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
592 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
593 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
594 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
595 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
596 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
597 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
598 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
599
600}
601
602void odm_CmnInfoHook_Debug23a(struct dm_odm_t *pDM_Odm)
603{
604 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug23a ==>\n"));
605 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast =%llu\n", *(pDM_Odm->pNumTxBytesUnicast)));
606 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast =%llu\n", *(pDM_Odm->pNumRxBytesUnicast)));
607 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode = 0x%x\n", *(pDM_Odm->pWirelessMode)));
608 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset =%d\n", *(pDM_Odm->pSecChOffset)));
609 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity =%d\n", *(pDM_Odm->pSecurity)));
610 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth =%d\n", *(pDM_Odm->pBandWidth)));
611 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel =%d\n", *(pDM_Odm->pChannel)));
612
613 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess =%d\n", *(pDM_Odm->pbScanInProcess)));
614 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving =%d\n", *(pDM_Odm->pbPowerSaving)));
615}
616
617void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
618{
619 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
620 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
621 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
622 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
623 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
624}
625
626void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
627 u8 CurrentIGI
628 )
629{
630 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
631
632 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
633 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
634
635 if (pDM_DigTable->CurIGValue != CurrentIGI) {
636 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
637 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
638 pDM_DigTable->CurIGValue = CurrentIGI;
639 }
640 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
641 ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
642}
643
644/* Need LPS mode for CE platform --2012--08--24--- */
645/* 8723AS/8189ES */
646void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
647{
648 struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
649 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
650 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */
651 u8 bFwCurrentInPSMode = false;
652 u8 CurrentIGI = pDM_Odm->RSSI_Min;
653
344af82c 654 if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
f7c92d2c
LF		 655 return;
656
657 CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
658 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
659
660 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
661
662 /* Using FW PS mode to make IGI */
663 if (bFwCurrentInPSMode) {
664 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
665 /* Adjust by FA in LPS MODE */
666 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
667 CurrentIGI = CurrentIGI+2;
668 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
669 CurrentIGI = CurrentIGI+1;
670 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
671 CurrentIGI = CurrentIGI-1;
672 } else {
673 CurrentIGI = RSSI_Lower;
674 }
675
676 /* Lower bound checking */
677
678 /* RSSI Lower bound check */
679 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
680 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
681 else
682 RSSI_Lower = DM_DIG_MIN_NIC;
683
684 /* Upper and Lower Bound checking */
685 if (CurrentIGI > DM_DIG_MAX_NIC)
686 CurrentIGI = DM_DIG_MAX_NIC;
687 else if (CurrentIGI < RSSI_Lower)
688 CurrentIGI = RSSI_Lower;
689
690 ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
691
692}
693
694void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
695{
696 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
697
698 pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
699 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
700 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
701 pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW;
702 pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH;
703 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
704 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
705 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
706 } else {
707 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
708 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
709 }
710 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
711 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
712 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
713 pDM_DigTable->PreCCK_CCAThres = 0xFF;
714 pDM_DigTable->CurCCK_CCAThres = 0x83;
715 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
716 pDM_DigTable->LargeFAHit = 0;
717 pDM_DigTable->Recover_cnt = 0;
718 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
719 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
720 pDM_DigTable->bMediaConnect_0 = false;
721 pDM_DigTable->bMediaConnect_1 = false;
722
723 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
724 pDM_Odm->bDMInitialGainEnable = true;
725
726}
727
728void odm_DIG23a(struct dm_odm_t *pDM_Odm)
729{
730
731 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
732 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
733 u8 DIG_Dynamic_MIN;
734 u8 DIG_MaxOfMin;
735 bool FirstConnect, FirstDisConnect;
736 u8 dm_dig_max, dm_dig_min;
737 u8 CurrentIGI = pDM_DigTable->CurIGValue;
738
739 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
740 /* if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) */
741 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
742 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
743 ("odm_DIG23a() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
744 return;
745 }
746
747 if (*(pDM_Odm->pbScanInProcess)) {
748 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
749 return;
750 }
751
752 /* add by Neil Chen to avoid PSD is processing */
753 if (!pDM_Odm->bDMInitialGainEnable) {
754 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: PSD is Processing \n"));
755 return;
756 }
757
758 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
759 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
760 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
761
762 /* 1 Boundary Decision */
344af82c 763 if ((pDM_Odm->SupportICType & ODM_RTL8723A) &&
f7c92d2c
LF		 764 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
765 dm_dig_max = DM_DIG_MAX_NIC_HP;
766 dm_dig_min = DM_DIG_MIN_NIC_HP;
767 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
768 } else {
769 dm_dig_max = DM_DIG_MAX_NIC;
770 dm_dig_min = DM_DIG_MIN_NIC;
771 DIG_MaxOfMin = DM_DIG_MAX_AP;
772 }
773
774 if (pDM_Odm->bLinked) {
775 /* 2 8723A Series, offset need to be 10 */
344af82c 776 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
f7c92d2c
LF		 777 /* 2 Upper Bound */
778 if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
779 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
780 else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
781 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
782 else
783 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
784
785 /* 2 If BT is Concurrent, need to set Lower Bound */
786 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
787 } else {
788 /* 2 Modify DIG upper bound */
789 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
790 pDM_DigTable->rx_gain_range_max = dm_dig_max;
791 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
792 pDM_DigTable->rx_gain_range_max = dm_dig_min;
793 else
794 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
795
796 /* 2 Modify DIG lower bound */
797 if (pDM_Odm->bOneEntryOnly) {
798 if (pDM_Odm->RSSI_Min < dm_dig_min)
799 DIG_Dynamic_MIN = dm_dig_min;
800 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
801 DIG_Dynamic_MIN = DIG_MaxOfMin;
802 else
803 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
804 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
805 ("odm_DIG23a() : bOneEntryOnly = true, DIG_Dynamic_MIN = 0x%x\n",
806 DIG_Dynamic_MIN));
807 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
808 ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
809 pDM_Odm->RSSI_Min));
810 } else {
811 DIG_Dynamic_MIN = dm_dig_min;
812 }
813 }
814 } else {
815 pDM_DigTable->rx_gain_range_max = dm_dig_max;
816 DIG_Dynamic_MIN = dm_dig_min;
817 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
818 }
819
820 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
821 if (pFalseAlmCnt->Cnt_all > 10000) {
822 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
823 ("dm_DIG(): Abnornally false alarm case. \n"));
824
825 if (pDM_DigTable->LargeFAHit != 3)
826 pDM_DigTable->LargeFAHit++;
827 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
828 pDM_DigTable->ForbiddenIGI = CurrentIGI;
829 pDM_DigTable->LargeFAHit = 1;
830 }
831
832 if (pDM_DigTable->LargeFAHit >= 3) {
833 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
834 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
835 else
836 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
837 pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
838 }
839 } else {
840 /* Recovery mechanism for IGI lower bound */
841 if (pDM_DigTable->Recover_cnt != 0) {
842 pDM_DigTable->Recover_cnt--;
843 } else {
844 if (pDM_DigTable->LargeFAHit < 3) {
845 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
846 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
847 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
848 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
849 ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
850 } else {
851 pDM_DigTable->ForbiddenIGI--;
852 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
853 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
854 ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
855 }
856 } else {
857 pDM_DigTable->LargeFAHit = 0;
858 }
859 }
860 }
861 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
862
863 /* 1 Adjust initial gain by false alarm */
864 if (pDM_Odm->bLinked) {
865 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
866 if (FirstConnect) {
867 CurrentIGI = pDM_Odm->RSSI_Min;
868 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
869 } else {
870 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
871 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
872 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
873 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
874 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
875 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
876 }
877 } else {
878 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
879 if (FirstDisConnect) {
880 CurrentIGI = pDM_DigTable->rx_gain_range_min;
881 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
882 } else {
883 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
884 if (pFalseAlmCnt->Cnt_all > 10000)
885 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
886 else if (pFalseAlmCnt->Cnt_all > 8000)
887 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
888 else if (pFalseAlmCnt->Cnt_all < 500)
889 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
890 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
891 }
892 }
893 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
894 /* 1 Check initial gain by upper/lower bound */
895 if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
896 CurrentIGI = pDM_DigTable->rx_gain_range_max;
897 if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
898 CurrentIGI = pDM_DigTable->rx_gain_range_min;
899
900 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
901 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
902 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
903 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
904
905 /* 2 High power RSSI threshold */
906
907 ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
908 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
909 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
910}
911
912/* 3 ============================================================ */
913/* 3 FASLE ALARM CHECK */
914/* 3 ============================================================ */
915
916void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
917{
918 u32 ret_value;
919 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
920
921 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
922 return;
923
344af82c
JS		 924 /* hold ofdm counter */
925 /* hold page C counter */
926 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
927 /* hold page D counter */
928 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
929 ret_value =
930 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
931 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
932 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
933 ret_value =
934 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
935 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
936 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
937 ret_value =
938 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
939 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
940 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
941 ret_value =
942 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
943 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
944
945 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
946 FalseAlmCnt->Cnt_Rate_Illegal +
947 FalseAlmCnt->Cnt_Crc8_fail +
948 FalseAlmCnt->Cnt_Mcs_fail +
949 FalseAlmCnt->Cnt_Fast_Fsync +
950 FalseAlmCnt->Cnt_SB_Search_fail;
951 /* hold cck counter */
952 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
953 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
f7c92d2c
LF		 954
955 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
956 FalseAlmCnt->Cnt_Cck_fail = ret_value;
957 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
958 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff) << 8;
959
960 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
344af82c
JS		 961 FalseAlmCnt->Cnt_CCK_CCA =
962 ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
f7c92d2c
LF		 963
964 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
965 FalseAlmCnt->Cnt_SB_Search_fail +
966 FalseAlmCnt->Cnt_Parity_Fail +
967 FalseAlmCnt->Cnt_Rate_Illegal +
968 FalseAlmCnt->Cnt_Crc8_fail +
969 FalseAlmCnt->Cnt_Mcs_fail +
970 FalseAlmCnt->Cnt_Cck_fail);
971
344af82c
JS		 972 FalseAlmCnt->Cnt_CCA_all =
973 FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
f7c92d2c
LF		 974
975 if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
976 /* reset false alarm counter registers */
fc8b7c8c
JS		 977 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
978 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
979 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
980 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
f7c92d2c 981 /* update ofdm counter */
344af82c
JS		 982 /* update page C counter */
983 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
984 /* update page D counter */
985 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
f7c92d2c
LF		 986
987 /* reset CCK CCA counter */
fc8b7c8c
JS		 988 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
989 BIT(13) | BIT(12), 0);
990 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
991 BIT(13) | BIT(12), 2);
f7c92d2c 992 /* reset CCK FA counter */
fc8b7c8c
JS		 993 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
994 BIT(15) | BIT(14), 0);
995 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
996 BIT(15) | BIT(14), 2);
f7c92d2c
LF		 997 }
998
344af82c
JS		 999 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
1000 ("Enter odm_FalseAlarmCounterStatistics23a\n"));
1001 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
1002 ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
1003 FalseAlmCnt->Cnt_Fast_Fsync,
1004 FalseAlmCnt->Cnt_SB_Search_fail));
1005 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
1006 ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
1007 FalseAlmCnt->Cnt_Parity_Fail,
1008 FalseAlmCnt->Cnt_Rate_Illegal));
1009 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
1010 ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
1011 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
1012
f7c92d2c
LF		 1013 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
1014 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
1015 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
1016}
1017
1018/* 3 ============================================================ */
1019/* 3 CCK Packet Detect Threshold */
1020/* 3 ============================================================ */
1021
1022void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
1023{
1024 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
1025 u8 CurCCK_CCAThres;
1026
1027 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
1028 return;
1029
1030 if (pDM_Odm->ExtLNA)
1031 return;
1032
1033 if (pDM_Odm->bLinked) {
1034 if (pDM_Odm->RSSI_Min > 25) {
1035 CurCCK_CCAThres = 0xcd;
1036 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
1037 CurCCK_CCAThres = 0x83;
1038 } else {
1039 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
1040 CurCCK_CCAThres = 0x83;
1041 else
1042 CurCCK_CCAThres = 0x40;
1043 }
1044 } else {
1045 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
1046 CurCCK_CCAThres = 0x83;
1047 else
1048 CurCCK_CCAThres = 0x40;
1049 }
1050
1051 ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
1052}
1053
1054void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
1055{
1056 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
1057
1058 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
1059 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
1060 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
1061 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
1062
1063}
1064
1065/* 3 ============================================================ */
1066/* 3 BB Power Save */
1067/* 3 ============================================================ */
1068void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
1069{
1070 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1071
1072 pDM_PSTable->PreCCAState = CCA_MAX;
1073 pDM_PSTable->CurCCAState = CCA_MAX;
1074 pDM_PSTable->PreRFState = RF_MAX;
1075 pDM_PSTable->CurRFState = RF_MAX;
1076 pDM_PSTable->Rssi_val_min = 0;
1077 pDM_PSTable->initialize = 0;
1078}
1079
1080void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
1081{
1082 return;
1083}
1084
1085void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm)
1086{
1087 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1088
1089 if (pDM_Odm->RSSI_Min != 0xFF) {
1090 if (pDM_PSTable->PreCCAState == CCA_2R) {
1091 if (pDM_Odm->RSSI_Min >= 35)
1092 pDM_PSTable->CurCCAState = CCA_1R;
1093 else
1094 pDM_PSTable->CurCCAState = CCA_2R;
1095 } else {
1096 if (pDM_Odm->RSSI_Min <= 30)
1097 pDM_PSTable->CurCCAState = CCA_2R;
1098 else
1099 pDM_PSTable->CurCCAState = CCA_1R;
1100 }
1101 } else {
1102 pDM_PSTable->CurCCAState = CCA_MAX;
1103 }
1104
1105 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) {
1106 if (pDM_PSTable->CurCCAState == CCA_1R) {
1107 if (pDM_Odm->RFType == ODM_2T2R)
1108 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13);
1109 else
1110 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23);
1111 } else {
1112 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33);
1113 /* PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x63); */
1114 }
1115 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
1116 }
1117}
1118
1119void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
1120{
1121 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1122 u8 Rssi_Up_bound = 30 ;
1123 u8 Rssi_Low_bound = 25;
1124 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
1125 Rssi_Up_bound = 50 ;
1126 Rssi_Low_bound = 45;
1127 }
1128 if (pDM_PSTable->initialize == 0) {
1129
1130 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
fc8b7c8c
JS		 1131 pDM_PSTable->RegC70 =
1132 (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >>3;
f7c92d2c
LF		 1133 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
1134 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
1135 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
1136 pDM_PSTable->initialize = 1;
1137 }
1138
1139 if (!bForceInNormal) {
1140 if (pDM_Odm->RSSI_Min != 0xFF) {
1141 if (pDM_PSTable->PreRFState == RF_Normal) {
1142 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
1143 pDM_PSTable->CurRFState = RF_Save;
1144 else
1145 pDM_PSTable->CurRFState = RF_Normal;
1146 } else {
1147 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
1148 pDM_PSTable->CurRFState = RF_Normal;
1149 else
1150 pDM_PSTable->CurRFState = RF_Save;
1151 }
1152 } else {
1153 pDM_PSTable->CurRFState = RF_MAX;
1154 }
1155 } else {
1156 pDM_PSTable->CurRFState = RF_Normal;
1157 }
1158
1159 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
1160 if (pDM_PSTable->CurRFState == RF_Save) {
1161 /* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
1162 /* Suggested by SD3 Yu-Nan. 2011.01.20. */
1163 if (pDM_Odm->SupportICType == ODM_RTL8723A)
fc8b7c8c 1164 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]= 1b'1 */
f7c92d2c 1165 ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
fc8b7c8c 1166 ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]= 1'b0 */
f7c92d2c
LF		 1167 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
1168 ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
1169 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
fc8b7c8c
JS		 1170 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]= 1'b0 */
1171 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]= 1'b1 */
f7c92d2c
LF		 1172 } else {
1173 ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
fc8b7c8c 1174 ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);
f7c92d2c
LF		 1175 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
1176 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
fc8b7c8c 1177 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
f7c92d2c
LF		 1178
1179 if (pDM_Odm->SupportICType == ODM_RTL8723A)
fc8b7c8c 1180 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]= 1b'0 */
f7c92d2c
LF		 1181 }
1182 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
1183 }
1184}
1185
1186/* 3 ============================================================ */
1187/* 3 RATR MASK */
1188/* 3 ============================================================ */
1189/* 3 ============================================================ */
1190/* 3 Rate Adaptive */
1191/* 3 ============================================================ */
1192
1193void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
1194{
1195 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1196
1197 pOdmRA->Type = DM_Type_ByDriver;
1198 if (pOdmRA->Type == DM_Type_ByDriver)
1199 pDM_Odm->bUseRAMask = true;
1200 else
1201 pDM_Odm->bUseRAMask = false;
1202
1203 pOdmRA->RATRState = DM_RATR_STA_INIT;
1204 pOdmRA->HighRSSIThresh = 50;
1205 pOdmRA->LowRSSIThresh = 20;
1206}
1207
1208u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm,
1209 u32 macid,
1210 u32 ra_mask,
1211 u8 rssi_level)
1212{
1213 struct sta_info *pEntry;
1214 u32 rate_bitmap = 0x0fffffff;
1215 u8 WirelessMode;
1216 /* u8 WirelessMode =*(pDM_Odm->pWirelessMode); */
1217
1218 pEntry = pDM_Odm->pODM_StaInfo[macid];
1219 if (!IS_STA_VALID(pEntry))
1220 return ra_mask;
1221
1222 WirelessMode = pEntry->wireless_mode;
1223
1224 switch (WirelessMode) {
1225 case ODM_WM_B:
1226 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
1227 rate_bitmap = 0x0000000d;
1228 else
1229 rate_bitmap = 0x0000000f;
1230 break;
1231 case (ODM_WM_A|ODM_WM_G):
1232 if (rssi_level == DM_RATR_STA_HIGH)
1233 rate_bitmap = 0x00000f00;
1234 else
1235 rate_bitmap = 0x00000ff0;
1236 break;
1237 case (ODM_WM_B|ODM_WM_G):
1238 if (rssi_level == DM_RATR_STA_HIGH)
1239 rate_bitmap = 0x00000f00;
1240 else if (rssi_level == DM_RATR_STA_MIDDLE)
1241 rate_bitmap = 0x00000ff0;
1242 else
1243 rate_bitmap = 0x00000ff5;
1244 break;
1245 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1246 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1247 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1248 if (rssi_level == DM_RATR_STA_HIGH) {
1249 rate_bitmap = 0x000f0000;
1250 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1251 rate_bitmap = 0x000ff000;
1252 } else {
1253 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1254 rate_bitmap = 0x000ff015;
1255 else
1256 rate_bitmap = 0x000ff005;
1257 }
1258 } else {
1259 if (rssi_level == DM_RATR_STA_HIGH) {
1260 rate_bitmap = 0x0f8f0000;
1261 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1262 rate_bitmap = 0x0f8ff000;
1263 } else {
1264 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1265 rate_bitmap = 0x0f8ff015;
1266 else
1267 rate_bitmap = 0x0f8ff005;
1268 }
1269 }
1270 break;
1271 default:
1272 /* case WIRELESS_11_24N: */
1273 /* case WIRELESS_11_5N: */
1274 if (pDM_Odm->RFType == RF_1T2R)
1275 rate_bitmap = 0x000fffff;
1276 else
1277 rate_bitmap = 0x0fffffff;
1278 break;
1279 }
1280
f8628a47 1281 /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __func__, rssi_level, WirelessMode, rate_bitmap); */
f7c92d2c
LF		 1282 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1283
1284 return rate_bitmap;
1285
1286}
1287
1288/*-----------------------------------------------------------------------------
1289 * Function: odm_RefreshRateAdaptiveMask23a()
1290 *
1291 * Overview: Update rate table mask according to rssi
1292 *
1293 * Input: NONE
1294 *
1295 * Output: NONE
1296 *
1297 * Return: NONE
1298 *
1299 * Revised History:
1300 *When Who Remark
1301 *05/27/2009 hpfan Create Version 0.
1302 *
1303 *---------------------------------------------------------------------------*/
1304void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1305{
1306 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1307 return;
1308 /* */
1309 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1310 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1311 /* HW dynamic mechanism. */
1312 /* */
1313 odm_RefreshRateAdaptiveMask23aCE23a(pDM_Odm);
1314}
1315
1316void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm)
1317{
1318}
1319
1320void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm)
1321{
1322 u8 i;
1323 struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
1324
1325 if (pAdapter->bDriverStopped) {
1326 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1327 ("<---- odm_RefreshRateAdaptiveMask23a(): driver is going to unload\n"));
1328 return;
1329 }
1330
1331 if (!pDM_Odm->bUseRAMask) {
1332 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1333 ("<---- odm_RefreshRateAdaptiveMask23a(): driver does not control rate adaptive mask\n"));
1334 return;
1335 }
1336
f8628a47 1337 /* printk("==> %s \n", __func__); */
f7c92d2c
LF		 1338
1339 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1340 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1341 if (IS_STA_VALID(pstat)) {
1342 if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1343 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1344 ("RSSI:%d, RSSI_LEVEL:%d\n",
1345 pstat->rssi_stat.UndecoratedSmoothedPWDB,
1346 pstat->rssi_level));
1347 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1348 }
1349
1350 }
1351 }
1352
1353}
1354
1355void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm)
1356{
1357}
1358
1359/* Return Value: bool */
1360/* - true: RATRState is changed. */
1361bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1362 u8 *pRATRState)
1363{
1364 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1365 const u8 GoUpGap = 5;
1366 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1367 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1368 u8 RATRState;
1369
1370 /* Threshold Adjustment: */
1371 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1372 /* Here GoUpGap is added to solve the boundary's level alternation issue. */
1373 switch (*pRATRState) {
1374 case DM_RATR_STA_INIT:
1375 case DM_RATR_STA_HIGH:
1376 break;
1377 case DM_RATR_STA_MIDDLE:
1378 HighRSSIThreshForRA += GoUpGap;
1379 break;
1380 case DM_RATR_STA_LOW:
1381 HighRSSIThreshForRA += GoUpGap;
1382 LowRSSIThreshForRA += GoUpGap;
1383 break;
1384 default:
1385 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1386 break;
1387 }
1388
1389 /* Decide RATRState by RSSI. */
1390 if (RSSI > HighRSSIThreshForRA)
1391 RATRState = DM_RATR_STA_HIGH;
1392 else if (RSSI > LowRSSIThreshForRA)
1393 RATRState = DM_RATR_STA_MIDDLE;
1394 else
1395 RATRState = DM_RATR_STA_LOW;
1396
1397 if (*pRATRState != RATRState || bForceUpdate) {
1398 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1399 ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1400 *pRATRState = RATRState;
1401 return true;
1402 }
1403 return false;
1404}
1405
1406/* 3 ============================================================ */
1407/* 3 Dynamic Tx Power */
1408/* 3 ============================================================ */
1409
1410void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1411{
1412 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1413 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1414 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1415
13b2beb3
JS		 1416 /*
1417 * This is never changed, so we should be able to clean up the
1418 * code checking for different values in rtl8723a_rf6052.c
1419 */
f7c92d2c
LF		 1420 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1421}
1422
f7c92d2c
LF		 1423/* 3 ============================================================ */
1424/* 3 RSSI Monitor */
1425/* 3 ============================================================ */
1426
1427void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm)
1428{
1429}
1430
1431void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1432{
1433 /* For AP/ADSL use struct rtl8723a_priv * */
1434 /* For CE/NIC use struct rtw_adapter * */
1435
1436 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1437 return;
1438
1439 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1440 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1441 /* HW dynamic mechanism. */
1442 odm_RSSIMonitorCheck23aCE(pDM_Odm);
1443} /* odm_RSSIMonitorCheck23a */
1444
1445void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm)
1446{
1447}
1448
1449static void
1450FindMinimumRSSI(
1451 struct rtw_adapter *pAdapter
1452 )
1453{
1454 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1455 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1456 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1457
1458 /* 1 1.Determine the minimum RSSI */
1459
1460 if ((!pDM_Odm->bLinked) &&
1461 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1462 pdmpriv->MinUndecoratedPWDBForDM = 0;
1463 else
1464 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1465}
1466
1467void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm)
1468{
1469 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1470 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1471 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1472 int i;
1473 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1474 u8 sta_cnt = 0;
1475 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1476 struct sta_info *psta;
1477
1478 if (!pDM_Odm->bLinked)
1479 return;
1480
1481 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1482 psta = pDM_Odm->pODM_StaInfo[i];
1483 if (IS_STA_VALID(psta)) {
1484 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1485 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1486
1487 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1488 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1489
1490 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1491 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1492 }
1493 }
1494
1495 for (i = 0; i < sta_cnt; i++) {
1496 if (PWDB_rssi[i] != (0)) {
1497 if (pHalData->fw_ractrl) /* Report every sta's RSSI to FW */
1498 rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1499 }
1500 }
1501
1502 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */
1503 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1504 else
1505 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1506
1507 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
1508 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1509 else
1510 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1511
1512 FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1513
1514 ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1515}
1516
1517void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm)
1518{
1519}
1520
f7c92d2c
LF		 1521/* endif */
1522/* 3 ============================================================ */
1523/* 3 Tx Power Tracking */
1524/* 3 ============================================================ */
1525
1526void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1527{
1528 odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1529}
1530
1531void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1532{
1533 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1534 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1535 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1536
1537 pdmpriv->bTXPowerTracking = true;
1538 pdmpriv->TXPowercount = 0;
1539 pdmpriv->bTXPowerTrackingInit = false;
1540 pdmpriv->TxPowerTrackControl = true;
1541 MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1542
1543 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1544}
1545
1546void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1547{
1548 /* For AP/ADSL use struct rtl8723a_priv * */
1549 /* For CE/NIC use struct rtw_adapter * */
1550
1551 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1552 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1553 /* HW dynamic mechanism. */
1554 odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1555}
1556
1557void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1558{
1559}
1560
1561void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm)
1562{
1563}
1564
1565void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm)
1566{
1567}
1568
1569/* antenna mapping info */
1570/* 1: right-side antenna */
1571/* 2/0: left-side antenna */
1572/* PpDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */
1573/* PpDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */
1574/* We select left antenna as default antenna in initial process, modify it as needed */
1575/* */
1576
1577/* 3 ============================================================ */
1578/* 3 SW Antenna Diversity */
1579/* 3 ============================================================ */
1580void odm_SwAntDivInit(struct dm_odm_t *pDM_Odm)
1581{
1582}
1583
c7fff4e4
JS		 1584void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID,
1585 struct phy_info *pPhyInfo)
f7c92d2c
LF		 1586{
1587}
1588
1589void odm_SwAntDivChkAntSwitch(struct dm_odm_t *pDM_Odm, u8 Step)
1590{
1591}
1592
1593void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm)
1594{
1595}
1596
1597void odm_SwAntDivChkAntSwitchCallback23a(unsigned long data)
1598{
1599}
1600
1601/* 3 ============================================================ */
1602/* 3 SW Antenna Diversity */
1603/* 3 ============================================================ */
1604
1605void odm_InitHybridAntDiv23a(struct dm_odm_t *pDM_Odm)
1606{
1607}
1608
1609void odm_HwAntDiv23a(struct dm_odm_t *pDM_Odm)
1610{
1611}
1612
1613/* EDCA Turbo */
1614void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1615{
1616
1617 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1618 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1619 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1620 Adapter->recvpriv.bIsAnyNonBEPkts = false;
1621
1622 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1623 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1624 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1625 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1626
1627} /* ODM_InitEdcaTurbo */
1628
1629void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1630{
1631 /* For AP/ADSL use struct rtl8723a_priv * */
1632 /* For CE/NIC use struct rtw_adapter * */
1633
1634 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1635 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1636 /* HW dynamic mechanism. */
1637 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck23a ========================>\n"));
1638
1639 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1640 return;
1641
1642 odm_EdcaTurboCheck23aCE23a(pDM_Odm);
1643 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<======================== odm_EdcaTurboCheck23a\n"));
1644
1645} /* odm_CheckEdcaTurbo */
1646
1647void odm_EdcaTurboCheck23aCE23a(struct dm_odm_t *pDM_Odm)
1648{
1649 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1650
1651 u32 trafficIndex;
1652 u32 edca_param;
1653 u64 cur_tx_bytes = 0;
1654 u64 cur_rx_bytes = 0;
1655 u8 bbtchange = false;
1656 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1657 struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1658 struct recv_priv *precvpriv = &Adapter->recvpriv;
1659 struct registry_priv *pregpriv = &Adapter->registrypriv;
1660 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1661 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1662
1663 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */
1664 goto dm_CheckEdcaTurbo_EXIT;
1665
1666 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
1667 goto dm_CheckEdcaTurbo_EXIT;
1668
dddeff3f 1669 if (rtl8723a_BT_disable_EDCA_turbo(Adapter))
f7c92d2c 1670 goto dm_CheckEdcaTurbo_EXIT;
f7c92d2c
LF		 1671
1672 /* Check if the status needs to be changed. */
1673 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1674 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1675 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1676
1677 /* traffic, TX or RX */
1678 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1679 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1680 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1681 /* Uplink TP is present. */
1682 trafficIndex = UP_LINK;
1683 } else { /* Balance TP is present. */
1684 trafficIndex = DOWN_LINK;
1685 }
1686 } else {
1687 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1688 /* Downlink TP is present. */
1689 trafficIndex = DOWN_LINK;
1690 } else { /* Balance TP is present. */
1691 trafficIndex = UP_LINK;
1692 }
1693 }
1694
1695 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1696 (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1697 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1698 (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1699 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1700 else
1701 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
edbfd672
JS		 1702 rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1703 edca_param);
f7c92d2c
LF		 1704
1705 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1706 }
1707
1708 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1709 } else {
1710 /* Turn Off EDCA turbo here. */
1711 /* Restore original EDCA according to the declaration of AP. */
1712 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
edbfd672
JS		 1713 rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1714 pHalData->AcParam_BE);
f7c92d2c
LF		 1715 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1716 }
1717 }
1718
1719dm_CheckEdcaTurbo_EXIT:
1720 /* Set variables for next time. */
1721 precvpriv->bIsAnyNonBEPkts = false;
1722 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1723 precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1724}
1725
1726u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1727{
1728 u32 psd_report;
1729
1730 /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1731 ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1732
1733 /* Start PSD calculation, Reg808[22]= 0->1 */
fc8b7c8c 1734 ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
f7c92d2c
LF		 1735 /* Need to wait for HW PSD report */
1736 udelay(30);
fc8b7c8c 1737 ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
f7c92d2c
LF		 1738 /* Read PSD report, Reg8B4[15:0] */
1739 psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1740
1741 psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1742
1743 return psd_report;
1744}
1745
1746u32
1747ConvertTo_dB23a(
1748 u32 Value)
1749{
1750 u8 i;
1751 u8 j;
1752 u32 dB;
1753
1754 Value = Value & 0xFFFF;
1755
1756 for (i = 0; i < 8; i++) {
1757 if (Value <= dB_Invert_Table[i][11])
1758 break;
1759 }
1760
1761 if (i >= 8)
1762 return 96; /* maximum 96 dB */
1763
1764 for (j = 0; j < 12; j++) {
1765 if (Value <= dB_Invert_Table[i][j])
1766 break;
1767 }
1768
1769 dB = i*12 + j + 1;
1770
1771 return dB;
1772}
1773
f7c92d2c
LF		 1774/* */
1775/* Description: */
1776/*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1777/* */
1778/* Added by Joseph, 2012.03.22 */
1779/* */
1780void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1781{
1782 struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1783 pDM_SWAT_Table->ANTA_ON = true;
1784 pDM_SWAT_Table->ANTB_ON = true;
1785}
1786
1787/* 2 8723A ANT DETECT */
1788
1789static void odm_PHY_SaveAFERegisters(
1790 struct dm_odm_t *pDM_Odm,
1791 u32 *AFEReg,
1792 u32 *AFEBackup,
1793 u32 RegisterNum
1794 )
1795{
1796 u32 i;
1797
1798 /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1799 for (i = 0 ; i < RegisterNum ; i++)
1800 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1801}
1802
1803static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1804 u32 *AFEBackup, u32 RegiesterNum)
1805{
1806 u32 i;
1807
1808 for (i = 0 ; i < RegiesterNum; i++)
1809 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1810}
1811
1812/* 2 8723A ANT DETECT */
1813/* Description: */
1814/* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1815/* This function is cooperated with BB team Neil. */
1816bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1817{
1818 struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1819 u32 CurrentChannel, RfLoopReg;
1820 u8 n;
1821 u32 Reg88c, Regc08, Reg874, Regc50;
1822 u8 initial_gain = 0x5a;
1823 u32 PSD_report_tmp;
1824 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1825 bool bResult = true;
1826 u32 AFE_Backup[16];
1827 u32 AFE_REG_8723A[16] = {
1828 rRx_Wait_CCA, rTx_CCK_RFON,
1829 rTx_CCK_BBON, rTx_OFDM_RFON,
1830 rTx_OFDM_BBON, rTx_To_Rx,
1831 rTx_To_Tx, rRx_CCK,
1832 rRx_OFDM, rRx_Wait_RIFS,
1833 rRx_TO_Rx, rStandby,
1834 rSleep, rPMPD_ANAEN,
1835 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1836
344af82c 1837 if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
f7c92d2c
LF		 1838 return bResult;
1839
1840 if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1841 return bResult;
1842 /* 1 Backup Current RF/BB Settings */
1843
1844 CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1845 RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1846 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */
1847 /* Step 1: USE IQK to transmitter single tone */
1848
1849 udelay(10);
1850
1851 /* Store A Path Register 88c, c08, 874, c50 */
1852 Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1853 Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1854 Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1855 Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1856
1857 /* Store AFE Registers */
1858 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1859
1860 /* Set PSD 128 pts */
fc8b7c8c 1861 ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0);
f7c92d2c
LF		 1862
1863 /* To SET CH1 to do */
1864 ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */
1865
1866 /* AFE all on step */
1867 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1868 ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1869 ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1870 ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1871 ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1872 ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1873 ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1874 ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1875 ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1876 ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1877 ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1878 ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1879 ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1880 ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1881 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1882 ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1883
1884 /* 3 wire Disable */
1885 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1886
1887 /* BB IQK Setting */
1888 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1889 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1890
1891 /* IQK setting tone@ 4.34Mhz */
1892 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1893 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1894
1895 /* Page B init */
1896 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1897 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1898 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1899 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1900 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1901 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1902 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1903
1904 /* RF loop Setting */
1905 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1906
1907 /* IQK Single tone start */
1908 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1909 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1910 udelay(1000);
1911 PSD_report_tmp = 0x0;
1912
1913 for (n = 0; n < 2; n++) {
1914 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1915 if (PSD_report_tmp > AntA_report)
1916 AntA_report = PSD_report_tmp;
1917 }
1918
1919 PSD_report_tmp = 0x0;
1920
1921 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */
1922 udelay(10);
1923
1924 for (n = 0; n < 2; n++) {
1925 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1926 if (PSD_report_tmp > AntB_report)
1927 AntB_report = PSD_report_tmp;
1928 }
1929
1930 /* change to open case */
1931 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */
1932 udelay(10);
1933
1934 for (n = 0; n < 2; n++) {
1935 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1936 if (PSD_report_tmp > AntO_report)
1937 AntO_report = PSD_report_tmp;
1938 }
1939
1940 /* Close IQK Single Tone function */
1941 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1942 PSD_report_tmp = 0x0;
1943
1944 /* 1 Return to antanna A */
1945 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1946 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1947 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1948 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1949 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1950 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1951 ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1952 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1953
1954 /* Reload AFE Registers */
1955 odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1956
1957 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
1958 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
1959 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
1960
1961 /* 2 Test Ant B based on Ant A is ON */
1962 if (mode == ANTTESTB) {
1963 if (AntA_report >= 100) {
1964 if (AntB_report > (AntA_report+1)) {
1965 pDM_SWAT_Table->ANTB_ON = false;
1966 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
1967 } else {
1968 pDM_SWAT_Table->ANTB_ON = true;
1969 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
1970 }
1971 } else {
1972 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1973 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
1974 bResult = false;
1975 }
1976 } else if (mode == ANTTESTALL) {
1977 /* 2 Test Ant A and B based on DPDT Open */
1978 if ((AntO_report >= 100) & (AntO_report < 118)) {
1979 if (AntA_report > (AntO_report+1)) {
1980 pDM_SWAT_Table->ANTA_ON = false;
1981 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
1982 } else {
1983 pDM_SWAT_Table->ANTA_ON = true;
1984 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
1985 }
1986
1987 if (AntB_report > (AntO_report+2)) {
1988 pDM_SWAT_Table->ANTB_ON = false;
1989 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
1990 } else {
1991 pDM_SWAT_Table->ANTB_ON = true;
1992 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
1993 }
1994 }
1995 } else {
1996 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1997 pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */
1998 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
1999 bResult = false;
2000 }
2001 return bResult;
2002}
2003
2004/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
2005void odm_dtc(struct dm_odm_t *pDM_Odm)
2006{
2007}
Linux kernel - Deliverables
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