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1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | ******************************************************************************/ | |
15 | #define _RTL8723A_PHYCFG_C_ | |
16 | ||
17 | #include <osdep_service.h> | |
18 | #include <drv_types.h> | |
19 | ||
20 | #include <rtl8723a_hal.h> | |
050abc45 | 21 | #include <usb_ops_linux.h> |
f7c92d2c LF |
22 | |
23 | /*---------------------------Define Local Constant---------------------------*/ | |
24 | /* Channel switch:The size of command tables for switch channel*/ | |
25 | #define MAX_PRECMD_CNT 16 | |
26 | #define MAX_RFDEPENDCMD_CNT 16 | |
27 | #define MAX_POSTCMD_CNT 16 | |
28 | ||
29 | #define MAX_DOZE_WAITING_TIMES_9x 64 | |
30 | ||
31 | /*---------------------------Define Local Constant---------------------------*/ | |
32 | ||
33 | /*------------------------Define global variable-----------------------------*/ | |
34 | ||
35 | /*------------------------Define local variable------------------------------*/ | |
36 | ||
37 | /*--------------------Define export function prototype-----------------------*/ | |
38 | /* Please refer to header file */ | |
39 | /*--------------------Define export function prototype-----------------------*/ | |
40 | ||
41 | /*----------------------------Function Body----------------------------------*/ | |
42 | /* */ | |
43 | /* 1. BB register R/W API */ | |
44 | /* */ | |
45 | ||
46 | /** | |
47 | * Function: phy_CalculateBitShift | |
48 | * | |
49 | * OverView: Get shifted position of the BitMask | |
50 | * | |
51 | * Input: | |
52 | * u32 BitMask, | |
53 | * | |
54 | * Output: none | |
55 | * Return: u32 Return the shift bit bit position of the mask | |
56 | */ | |
57 | static u32 phy_CalculateBitShift(u32 BitMask) | |
58 | { | |
59 | u32 i; | |
60 | ||
61 | for (i = 0; i <= 31; i++) { | |
62 | if (((BitMask>>i) & 0x1) == 1) | |
63 | break; | |
64 | } | |
65 | ||
66 | return i; | |
67 | } | |
68 | ||
69 | /** | |
70 | * Function: PHY_QueryBBReg | |
71 | * | |
72 | * OverView: Read "sepcific bits" from BB register | |
73 | * | |
74 | * Input: | |
75 | * struct rtw_adapter * Adapter, | |
76 | * u32 RegAddr, Target address to be readback | |
77 | * u32 BitMask Target bit position in the | |
78 | * target address to be readback | |
79 | * Output: | |
80 | * None | |
81 | * Return: | |
82 | * u32 Data The readback register value | |
83 | * Note: | |
84 | * This function is equal to "GetRegSetting" in PHY programming guide | |
85 | */ | |
86 | u32 | |
87 | PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr, u32 BitMask) | |
88 | { | |
89 | u32 ReturnValue = 0, OriginalValue, BitShift; | |
90 | ||
050abc45 | 91 | OriginalValue = rtl8723au_read32(Adapter, RegAddr); |
f7c92d2c LF |
92 | BitShift = phy_CalculateBitShift(BitMask); |
93 | ReturnValue = (OriginalValue & BitMask) >> BitShift; | |
94 | return ReturnValue; | |
95 | } | |
96 | ||
97 | /** | |
98 | * Function: PHY_SetBBReg | |
99 | * | |
100 | * OverView: Write "Specific bits" to BB register (page 8~) | |
101 | * | |
102 | * Input: | |
103 | * struct rtw_adapter * Adapter, | |
104 | * u32 RegAddr, Target address to be modified | |
105 | * u32 BitMask Target bit position in the | |
106 | * target address to be modified | |
107 | * u32 Data The new register value in the | |
108 | * target bit position of the | |
109 | * target address | |
110 | * | |
111 | * Output: | |
112 | * None | |
113 | * Return: | |
114 | * None | |
115 | * Note: | |
116 | * This function is equal to "PutRegSetting" in PHY programming guide | |
117 | */ | |
118 | ||
119 | void | |
120 | PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) | |
121 | { | |
122 | u32 OriginalValue, BitShift; | |
123 | ||
124 | /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */ | |
125 | ||
126 | if (BitMask != bMaskDWord) {/* if not "double word" write */ | |
050abc45 | 127 | OriginalValue = rtl8723au_read32(Adapter, RegAddr); |
f7c92d2c LF |
128 | BitShift = phy_CalculateBitShift(BitMask); |
129 | Data = ((OriginalValue & (~BitMask)) | (Data << BitShift)); | |
130 | } | |
131 | ||
edbfd672 | 132 | rtl8723au_write32(Adapter, RegAddr, Data); |
f7c92d2c LF |
133 | |
134 | /* RTPRINT(FPHY, PHY_BBW, ("BBW MASK = 0x%lx Addr[0x%lx]= 0x%lx\n", BitMask, RegAddr, Data)); */ | |
135 | /* RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */ | |
136 | } | |
137 | ||
138 | /* */ | |
139 | /* 2. RF register R/W API */ | |
140 | /* */ | |
141 | ||
142 | /** | |
143 | * Function: phy_RFSerialRead | |
144 | * | |
145 | * OverView: Read regster from RF chips | |
146 | * | |
147 | * Input: | |
148 | * struct rtw_adapter * Adapter, | |
149 | * enum RF_RADIO_PATH eRFPath, Radio path of A/B/C/D | |
150 | * u32 Offset, The target address to be read | |
151 | * | |
152 | * Output: None | |
153 | * Return: u32 reback value | |
154 | * Note: Threre are three types of serial operations: | |
155 | * 1. Software serial write | |
156 | * 2. Hardware LSSI-Low Speed Serial Interface | |
157 | * 3. Hardware HSSI-High speed | |
158 | * serial write. Driver need to implement (1) and (2). | |
159 | * This function is equal to the combination of RF_ReadReg() and | |
160 | * RFLSSIRead() | |
161 | */ | |
162 | static u32 | |
163 | phy_RFSerialRead(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, | |
164 | u32 Offset) | |
165 | { | |
166 | u32 retValue = 0; | |
167 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
168 | struct bb_reg_define *pPhyReg = &pHalData->PHYRegDef[eRFPath]; | |
169 | u32 NewOffset; | |
170 | u32 tmplong, tmplong2; | |
171 | u8 RfPiEnable = 0; | |
172 | /* */ | |
173 | /* Make sure RF register offset is correct */ | |
174 | /* */ | |
175 | Offset &= 0x3f; | |
176 | ||
177 | /* */ | |
178 | /* Switch page for 8256 RF IC */ | |
179 | /* */ | |
180 | NewOffset = Offset; | |
181 | ||
182 | /* 2009/06/17 MH We can not execute IO for power save or | |
183 | other accident mode. */ | |
184 | /* if (RT_CANNOT_IO(Adapter)) */ | |
185 | /* */ | |
186 | /* RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n")); */ | |
187 | /* return 0xFFFFFFFF; */ | |
188 | /* */ | |
189 | ||
190 | /* For 92S LSSI Read RFLSSIRead */ | |
191 | /* For RF A/B write 0x824/82c(does not work in the future) */ | |
192 | /* We must use 0x824 for RF A and B to execute read trigger */ | |
193 | tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); | |
194 | if (eRFPath == RF_PATH_A) | |
195 | tmplong2 = tmplong; | |
196 | else | |
197 | tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, | |
198 | bMaskDWord); | |
199 | ||
200 | tmplong2 = (tmplong2 & ~bLSSIReadAddress) | | |
201 | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */ | |
202 | ||
203 | PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, | |
204 | bMaskDWord, tmplong & (~bLSSIReadEdge)); | |
205 | udelay(10);/* PlatformStallExecution(10); */ | |
206 | ||
207 | PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); | |
208 | udelay(100);/* PlatformStallExecution(100); */ | |
209 | ||
210 | PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, | |
211 | tmplong | bLSSIReadEdge); | |
212 | udelay(10);/* PlatformStallExecution(10); */ | |
213 | ||
214 | if (eRFPath == RF_PATH_A) | |
215 | RfPiEnable = (u8)PHY_QueryBBReg(Adapter, | |
8f7654c1 JS |
216 | rFPGA0_XA_HSSIParameter1, |
217 | BIT(8)); | |
f7c92d2c LF |
218 | else if (eRFPath == RF_PATH_B) |
219 | RfPiEnable = (u8)PHY_QueryBBReg(Adapter, | |
8f7654c1 JS |
220 | rFPGA0_XB_HSSIParameter1, |
221 | BIT(8)); | |
f7c92d2c LF |
222 | |
223 | if (RfPiEnable) { | |
224 | /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ | |
225 | retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, | |
226 | bLSSIReadBackData); | |
227 | /* DBG_8723A("Readback from RF-PI : 0x%x\n", retValue); */ | |
228 | } else { | |
229 | /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ | |
230 | retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, | |
231 | bLSSIReadBackData); | |
232 | /* DBG_8723A("Readback from RF-SI : 0x%x\n", retValue); */ | |
233 | } | |
234 | /* DBG_8723A("RFR-%d Addr[0x%x]= 0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue); */ | |
235 | ||
236 | return retValue; | |
237 | } | |
238 | ||
239 | /** | |
240 | * Function: phy_RFSerialWrite | |
241 | * | |
242 | * OverView: Write data to RF register (page 8~) | |
243 | * | |
244 | * Input: | |
245 | * struct rtw_adapter * Adapter, | |
246 | * enum RF_RADIO_PATH eRFPath, Radio path of A/B/C/D | |
247 | * u32 Offset, The target address to be read | |
248 | * u32 Data The new register Data in the target | |
249 | * bit position of the target to be read | |
250 | * | |
251 | * Output: | |
252 | * None | |
253 | * Return: | |
254 | * None | |
255 | * Note: | |
256 | * Threre are three types of serial operations: | |
257 | * 1. Software serial write | |
258 | * 2. Hardware LSSI-Low Speed Serial Interface | |
259 | * 3. Hardware HSSI-High speed | |
260 | * serial write. Driver need to implement (1) and (2). | |
261 | * This function is equal to the combination of RF_ReadReg() and | |
262 | * RFLSSIRead() | |
263 | * | |
264 | * Note: For RF8256 only | |
265 | * The total count of RTL8256(Zebra4) register is around 36 bit it only employs | |
266 | * 4-bit RF address. RTL8256 uses "register mode control bit" | |
267 | * (Reg00[12], Reg00[10]) to access register address bigger than 0xf. | |
268 | * See "Appendix-4 in PHY Configuration programming guide" for more details. | |
269 | * Thus, we define a sub-finction for RTL8526 register address conversion | |
270 | * =========================================================== | |
271 | * Register Mode: RegCTL[1] RegCTL[0] Note | |
272 | * (Reg00[12]) (Reg00[10]) | |
273 | * =========================================================== | |
274 | * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) | |
275 | * ------------------------------------------------------------------ | |
276 | * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) | |
277 | * ------------------------------------------------------------------ | |
278 | * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) | |
279 | * ------------------------------------------------------------------ | |
280 | * | |
281 | * 2008/09/02 MH Add 92S RF definition | |
282 | */ | |
283 | static void | |
284 | phy_RFSerialWrite(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, | |
285 | u32 Offset, u32 Data) | |
286 | { | |
287 | u32 DataAndAddr = 0; | |
288 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
289 | struct bb_reg_define *pPhyReg = &pHalData->PHYRegDef[eRFPath]; | |
290 | u32 NewOffset; | |
291 | ||
292 | /* 2009/06/17 MH We can not execute IO for power save or | |
293 | other accident mode. */ | |
294 | /* if (RT_CANNOT_IO(Adapter)) */ | |
295 | /* */ | |
296 | /* RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n")); */ | |
297 | /* return; */ | |
298 | /* */ | |
299 | ||
300 | Offset &= 0x3f; | |
301 | ||
302 | /* */ | |
303 | /* Shadow Update */ | |
304 | /* */ | |
305 | /* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */ | |
306 | ||
307 | /* */ | |
308 | /* Switch page for 8256 RF IC */ | |
309 | /* */ | |
310 | NewOffset = Offset; | |
311 | ||
312 | /* */ | |
313 | /* Put write addr in [5:0] and write data in [31:16] */ | |
314 | /* */ | |
315 | /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */ | |
316 | /* T65 RF */ | |
317 | DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; | |
318 | ||
319 | /* */ | |
320 | /* Write Operation */ | |
321 | /* */ | |
322 | PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); | |
323 | /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]= 0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */ | |
324 | ||
325 | } | |
326 | ||
327 | /** | |
328 | * Function: PHY_QueryRFReg | |
329 | * | |
330 | * OverView: Query "Specific bits" to RF register (page 8~) | |
331 | * | |
332 | * Input: | |
333 | * struct rtw_adapter * Adapter, | |
334 | * enum RF_RADIO_PATH eRFPath, Radio path of A/B/C/D | |
335 | * u32 RegAddr, The target address to be read | |
336 | * u32BitMask The target bit position in the target | |
337 | * address to be read | |
338 | * | |
339 | * Output: | |
340 | * None | |
341 | * Return: | |
342 | * u32 Readback value | |
343 | * Note: | |
344 | * This function is equal to "GetRFRegSetting" in PHY programming guide | |
345 | */ | |
346 | u32 | |
347 | PHY_QueryRFReg(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, | |
348 | u32 RegAddr, u32 BitMask) | |
349 | { | |
350 | u32 Original_Value, Readback_Value, BitShift; | |
351 | /* struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); */ | |
352 | /* u8 RFWaitCounter = 0; */ | |
353 | /* _irqL irqL; */ | |
354 | ||
355 | Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); | |
356 | ||
357 | BitShift = phy_CalculateBitShift(BitMask); | |
358 | Readback_Value = (Original_Value & BitMask) >> BitShift; | |
359 | ||
360 | return Readback_Value; | |
361 | } | |
362 | ||
363 | /** | |
364 | * Function: PHY_SetRFReg | |
365 | * | |
366 | * OverView: Write "Specific bits" to RF register (page 8~) | |
367 | * | |
368 | * Input: | |
369 | * struct rtw_adapter * Adapter, | |
370 | * enum RF_RADIO_PATH eRFPath, Radio path of A/B/C/D | |
371 | * u32 RegAddr, The target address to be modified | |
372 | * u32 BitMask The target bit position in the target | |
373 | * address to be modified | |
374 | * u32 Data The new register Data in the target | |
375 | * bit position of the target address | |
376 | * | |
377 | * Output: | |
378 | * None | |
379 | * Return: | |
380 | * None | |
381 | * Note: This function is equal to "PutRFRegSetting" in PHY programming guide | |
382 | */ | |
383 | void | |
384 | PHY_SetRFReg(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, | |
385 | u32 RegAddr, u32 BitMask, u32 Data) | |
386 | { | |
387 | /* struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); */ | |
388 | /* u8 RFWaitCounter = 0; */ | |
389 | u32 Original_Value, BitShift; | |
390 | ||
391 | /* RF data is 12 bits only */ | |
392 | if (BitMask != bRFRegOffsetMask) { | |
393 | Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); | |
394 | BitShift = phy_CalculateBitShift(BitMask); | |
395 | Data = ((Original_Value & (~BitMask)) | (Data << BitShift)); | |
396 | } | |
397 | ||
398 | phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data); | |
399 | } | |
400 | ||
401 | /* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */ | |
402 | ||
403 | /*----------------------------------------------------------------------------- | |
404 | * Function: PHY_MACConfig8723A | |
405 | * | |
406 | * Overview: Condig MAC by header file or parameter file. | |
407 | * | |
408 | * Input: NONE | |
409 | * | |
410 | * Output: NONE | |
411 | * | |
412 | * Return: NONE | |
413 | * | |
414 | * Revised History: | |
415 | * When Who Remark | |
416 | * 08/12/2008 MHC Create Version 0. | |
417 | * | |
418 | *---------------------------------------------------------------------------*/ | |
c691ec33 | 419 | int PHY_MACConfig8723A(struct rtw_adapter *Adapter) |
f7c92d2c LF |
420 | { |
421 | int rtStatus = _SUCCESS; | |
422 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
f7c92d2c LF |
423 | bool is92C = IS_92C_SERIAL(pHalData->VersionID); |
424 | ||
f7c92d2c LF |
425 | /* */ |
426 | /* Config MAC */ | |
427 | /* */ | |
9464cac7 | 428 | ODM_ReadAndConfig_MAC_REG_8723A(&pHalData->odmpriv); |
f7c92d2c LF |
429 | |
430 | /* 2010.07.13 AMPDU aggregation number 9 */ | |
431 | /* rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ | |
edbfd672 | 432 | rtl8723au_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); |
f7c92d2c | 433 | if (is92C && (BOARD_USB_DONGLE == pHalData->BoardType)) |
edbfd672 | 434 | rtl8723au_write8(Adapter, 0x40, 0x04); |
f7c92d2c LF |
435 | |
436 | return rtStatus; | |
437 | } | |
438 | ||
439 | /** | |
440 | * Function: phy_InitBBRFRegisterDefinition | |
441 | * | |
442 | * OverView: Initialize Register definition offset for Radio Path A/B/C/D | |
443 | * | |
444 | * Input: | |
445 | * struct rtw_adapter * Adapter, | |
446 | * | |
447 | * Output: None | |
448 | * Return: None | |
449 | * Note: | |
450 | * The initialization value is constant and it should never be changes | |
451 | */ | |
452 | static void | |
453 | phy_InitBBRFRegisterDefinition(struct rtw_adapter *Adapter) | |
454 | { | |
455 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
456 | ||
457 | /* RF Interface Sowrtware Control */ | |
458 | /* 16 LSBs if read 32-bit from 0x870 */ | |
459 | pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; | |
460 | /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ | |
461 | pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; | |
f7c92d2c LF |
462 | |
463 | /* RF Interface Readback Value */ | |
464 | /* 16 LSBs if read 32-bit from 0x8E0 */ | |
465 | pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; | |
466 | /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ | |
467 | pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; | |
f7c92d2c LF |
468 | |
469 | /* RF Interface Output (and Enable) */ | |
470 | /* 16 LSBs if read 32-bit from 0x860 */ | |
471 | pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; | |
472 | /* 16 LSBs if read 32-bit from 0x864 */ | |
473 | pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; | |
474 | ||
475 | /* RF Interface (Output and) Enable */ | |
476 | /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ | |
477 | pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; | |
478 | /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ | |
479 | pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; | |
480 | ||
481 | /* Addr of LSSI. Wirte RF register by driver */ | |
482 | pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; | |
483 | pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; | |
484 | ||
485 | /* RF parameter */ | |
486 | /* BB Band Select */ | |
487 | pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; | |
488 | pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; | |
f7c92d2c LF |
489 | |
490 | /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ | |
491 | pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; | |
492 | pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; | |
f7c92d2c LF |
493 | |
494 | /* Tranceiver A~D HSSI Parameter-1 */ | |
495 | /* wire control parameter1 */ | |
496 | pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; | |
497 | /* wire control parameter1 */ | |
498 | pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; | |
499 | ||
500 | /* Tranceiver A~D HSSI Parameter-2 */ | |
501 | /* wire control parameter2 */ | |
502 | pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; | |
503 | /* wire control parameter2 */ | |
504 | pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; | |
505 | ||
506 | /* RF switch Control */ | |
507 | pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = | |
508 | rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */ | |
509 | pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = | |
510 | rFPGA0_XAB_SwitchControl; | |
f7c92d2c LF |
511 | |
512 | /* AGC control 1 */ | |
513 | pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; | |
514 | pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; | |
f7c92d2c LF |
515 | |
516 | /* AGC control 2 */ | |
517 | pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; | |
518 | pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; | |
f7c92d2c LF |
519 | |
520 | /* RX AFE control 1 */ | |
521 | pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; | |
522 | pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; | |
f7c92d2c LF |
523 | |
524 | /* RX AFE control 1 */ | |
525 | pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; | |
526 | pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; | |
f7c92d2c LF |
527 | |
528 | /* Tx AFE control 1 */ | |
529 | pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; | |
530 | pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; | |
f7c92d2c LF |
531 | |
532 | /* Tx AFE control 2 */ | |
533 | pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; | |
534 | pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; | |
f7c92d2c LF |
535 | |
536 | /* Tranceiver LSSI Readback SI mode */ | |
537 | pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; | |
538 | pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; | |
f7c92d2c LF |
539 | |
540 | /* Tranceiver LSSI Readback PI mode */ | |
541 | pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = | |
542 | TransceiverA_HSPI_Readback; | |
543 | pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = | |
544 | TransceiverB_HSPI_Readback; | |
f7c92d2c LF |
545 | } |
546 | ||
547 | /* The following is for High Power PA */ | |
548 | static void | |
549 | storePwrIndexDiffRateOffset(struct rtw_adapter *Adapter, u32 RegAddr, | |
550 | u32 BitMask, u32 Data) | |
551 | { | |
552 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
553 | ||
554 | if (RegAddr == rTxAGC_A_Rate18_06) { | |
555 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data; | |
556 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
557 | ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%lx\n", | |
558 | pHalData->pwrGroupCnt, */ | |
559 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
560 | pHalData->pwrGroupCnt][0])); */ | |
561 | } | |
562 | if (RegAddr == rTxAGC_A_Rate54_24) { | |
563 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data; | |
564 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
565 | ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%lx\n", | |
566 | pHalData->pwrGroupCnt, */ | |
567 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
568 | pHalData->pwrGroupCnt][1])); */ | |
569 | } | |
570 | if (RegAddr == rTxAGC_A_CCK1_Mcs32) { | |
571 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data; | |
572 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
573 | ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%lx\n", | |
574 | pHalData->pwrGroupCnt, */ | |
575 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
576 | pHalData->pwrGroupCnt][6])); */ | |
577 | } | |
578 | if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00) { | |
579 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data; | |
580 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
581 | ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%lx\n", | |
582 | pHalData->pwrGroupCnt, */ | |
583 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
584 | pHalData->pwrGroupCnt][7])); */ | |
585 | } | |
586 | if (RegAddr == rTxAGC_A_Mcs03_Mcs00) { | |
587 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data; | |
588 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
589 | ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%lx\n", | |
590 | pHalData->pwrGroupCnt, */ | |
591 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
592 | pHalData->pwrGroupCnt][2])); */ | |
593 | } | |
594 | if (RegAddr == rTxAGC_A_Mcs07_Mcs04) { | |
595 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data; | |
596 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
597 | ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%lx\n", | |
598 | pHalData->pwrGroupCnt, */ | |
599 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
600 | pHalData->pwrGroupCnt][3])); */ | |
601 | } | |
602 | if (RegAddr == rTxAGC_A_Mcs11_Mcs08) { | |
603 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data; | |
604 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
605 | ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%lx\n", | |
606 | pHalData->pwrGroupCnt, */ | |
607 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
608 | pHalData->pwrGroupCnt][4])); */ | |
609 | } | |
610 | if (RegAddr == rTxAGC_A_Mcs15_Mcs12) { | |
611 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data; | |
612 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
613 | ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%lx\n", | |
614 | pHalData->pwrGroupCnt, */ | |
615 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
616 | pHalData->pwrGroupCnt][5])); */ | |
617 | } | |
618 | if (RegAddr == rTxAGC_B_Rate18_06) { | |
619 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data; | |
620 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
621 | ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%lx\n", | |
622 | pHalData->pwrGroupCnt, */ | |
623 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
624 | pHalData->pwrGroupCnt][8])); */ | |
625 | } | |
626 | if (RegAddr == rTxAGC_B_Rate54_24) { | |
627 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data; | |
628 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
629 | ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%lx\n", | |
630 | pHalData->pwrGroupCnt, */ | |
631 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
632 | pHalData->pwrGroupCnt][9])); */ | |
633 | } | |
634 | if (RegAddr == rTxAGC_B_CCK1_55_Mcs32) { | |
635 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data; | |
636 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
637 | ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%lx\n", | |
638 | pHalData->pwrGroupCnt, */ | |
639 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
640 | pHalData->pwrGroupCnt][14])); */ | |
641 | } | |
642 | if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff) { | |
643 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data; | |
644 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
645 | ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%lx\n", | |
646 | pHalData->pwrGroupCnt, */ | |
647 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
648 | pHalData->pwrGroupCnt][15])); */ | |
649 | } | |
650 | if (RegAddr == rTxAGC_B_Mcs03_Mcs00) { | |
651 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data; | |
652 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
653 | ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%lx\n", | |
654 | pHalData->pwrGroupCnt, */ | |
655 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
656 | pHalData->pwrGroupCnt][10])); */ | |
657 | } | |
658 | if (RegAddr == rTxAGC_B_Mcs07_Mcs04) { | |
659 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data; | |
660 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
661 | ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%lx\n", | |
662 | pHalData->pwrGroupCnt, */ | |
663 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
664 | pHalData->pwrGroupCnt][11])); */ | |
665 | } | |
666 | if (RegAddr == rTxAGC_B_Mcs11_Mcs08) { | |
667 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data; | |
668 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
669 | ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%lx\n", | |
670 | pHalData->pwrGroupCnt, */ | |
671 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
672 | pHalData->pwrGroupCnt][12])); */ | |
673 | } | |
674 | if (RegAddr == rTxAGC_B_Mcs15_Mcs12) { | |
675 | pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data; | |
676 | /* RT_TRACE(COMP_INIT, DBG_TRACE, | |
677 | ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%lx\n", | |
678 | pHalData->pwrGroupCnt, */ | |
679 | /* pHalData->MCSTxPowerLevelOriginalOffset[ | |
680 | pHalData->pwrGroupCnt][13])); */ | |
681 | pHalData->pwrGroupCnt++; | |
682 | } | |
683 | } | |
684 | ||
685 | /*----------------------------------------------------------------------------- | |
686 | * Function: phy_ConfigBBWithPgHeaderFile | |
687 | * | |
688 | * Overview: Config PHY_REG_PG array | |
689 | * | |
690 | * Input: NONE | |
691 | * | |
692 | * Output: NONE | |
693 | * | |
694 | * Return: NONE | |
695 | * | |
696 | * Revised History: | |
697 | * When Who Remark | |
698 | * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!! | |
699 | * 11/10/2008 tynli Modify to mew files. | |
700 | *---------------------------------------------------------------------------*/ | |
701 | static int | |
702 | phy_ConfigBBWithPgHeaderFile(struct rtw_adapter *Adapter, u8 ConfigType) | |
703 | { | |
704 | int i; | |
705 | u32 *Rtl819XPHY_REGArray_Table_PG; | |
706 | u16 PHY_REGArrayPGLen; | |
707 | ||
708 | PHY_REGArrayPGLen = Rtl8723_PHY_REG_Array_PGLength; | |
709 | Rtl819XPHY_REGArray_Table_PG = (u32 *)Rtl8723_PHY_REG_Array_PG; | |
710 | ||
711 | if (ConfigType == BaseBand_Config_PHY_REG) { | |
712 | for (i = 0; i < PHY_REGArrayPGLen; i = i + 3) { | |
713 | storePwrIndexDiffRateOffset(Adapter, | |
714 | Rtl819XPHY_REGArray_Table_PG[i], | |
715 | Rtl819XPHY_REGArray_Table_PG[i+1], | |
716 | Rtl819XPHY_REGArray_Table_PG[i+2]); | |
717 | } | |
718 | } | |
719 | ||
720 | return _SUCCESS; | |
721 | } /* phy_ConfigBBWithPgHeaderFile */ | |
722 | ||
723 | static void | |
724 | phy_BB8192C_Config_1T(struct rtw_adapter *Adapter) | |
725 | { | |
726 | /* for path - B */ | |
727 | PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2); | |
728 | PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022); | |
729 | ||
730 | /* 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, | |
731 | Jenyu and Yunan. */ | |
732 | PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45); | |
733 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23); | |
734 | /* B path first AGC */ | |
735 | PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); | |
736 | ||
737 | PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2); | |
738 | PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2); | |
739 | PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2); | |
740 | PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2); | |
741 | PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2); | |
742 | } | |
743 | ||
744 | static int | |
745 | phy_BB8723a_Config_ParaFile(struct rtw_adapter *Adapter) | |
746 | { | |
747 | struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); | |
748 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
749 | int rtStatus = _SUCCESS; | |
750 | ||
f7c92d2c LF |
751 | /* */ |
752 | /* 1. Read PHY_REG.TXT BB INIT!! */ | |
753 | /* We will seperate as 88C / 92C according to chip version */ | |
754 | /* */ | |
79756e68 | 755 | ODM_ReadAndConfig_PHY_REG_1T_8723A(&pHalData->odmpriv); |
f7c92d2c LF |
756 | |
757 | /* */ | |
758 | /* 20100318 Joseph: Config 2T2R to 1T2R if necessary. */ | |
759 | /* */ | |
760 | if (pHalData->rf_type == RF_1T2R) { | |
761 | phy_BB8192C_Config_1T(Adapter); | |
762 | DBG_8723A("phy_BB8723a_Config_ParaFile():Config to 1T!!\n"); | |
763 | } | |
764 | ||
765 | /* */ | |
766 | /* 2. If EEPROM or EFUSE autoload OK, We must config by | |
767 | PHY_REG_PG.txt */ | |
768 | /* */ | |
769 | if (pEEPROM->bautoload_fail_flag == false) { | |
770 | pHalData->pwrGroupCnt = 0; | |
771 | ||
772 | rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, | |
773 | BaseBand_Config_PHY_REG); | |
774 | } | |
775 | ||
776 | if (rtStatus != _SUCCESS) | |
777 | goto phy_BB8190_Config_ParaFile_Fail; | |
778 | ||
779 | /* */ | |
780 | /* 3. BB AGC table Initialization */ | |
781 | /* */ | |
79756e68 | 782 | ODM_ReadAndConfig_AGC_TAB_1T_8723A(&pHalData->odmpriv); |
f7c92d2c LF |
783 | |
784 | phy_BB8190_Config_ParaFile_Fail: | |
785 | ||
786 | return rtStatus; | |
787 | } | |
788 | ||
789 | int | |
790 | PHY_BBConfig8723A(struct rtw_adapter *Adapter) | |
791 | { | |
792 | int rtStatus = _SUCCESS; | |
793 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
794 | u8 TmpU1B = 0; | |
795 | u8 CrystalCap; | |
796 | ||
797 | phy_InitBBRFRegisterDefinition(Adapter); | |
798 | ||
799 | /* Suggested by Scott. tynli_test. 2010.12.30. */ | |
800 | /* 1. 0x28[1] = 1 */ | |
050abc45 | 801 | TmpU1B = rtl8723au_read8(Adapter, REG_AFE_PLL_CTRL); |
f7c92d2c | 802 | udelay(2); |
edbfd672 | 803 | rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, TmpU1B | BIT(1)); |
f7c92d2c LF |
804 | udelay(2); |
805 | ||
806 | /* 2. 0x29[7:0] = 0xFF */ | |
edbfd672 | 807 | rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff); |
f7c92d2c LF |
808 | udelay(2); |
809 | ||
810 | /* 3. 0x02[1:0] = 2b'11 */ | |
050abc45 | 811 | TmpU1B = rtl8723au_read8(Adapter, REG_SYS_FUNC_EN); |
edbfd672 JS |
812 | rtl8723au_write8(Adapter, REG_SYS_FUNC_EN, |
813 | (TmpU1B | FEN_BB_GLB_RSTn | FEN_BBRSTB)); | |
f7c92d2c LF |
814 | |
815 | /* 4. 0x25[6] = 0 */ | |
050abc45 | 816 | TmpU1B = rtl8723au_read8(Adapter, REG_AFE_XTAL_CTRL + 1); |
edbfd672 | 817 | rtl8723au_write8(Adapter, REG_AFE_XTAL_CTRL+1, TmpU1B & ~BIT(6)); |
f7c92d2c LF |
818 | |
819 | /* 5. 0x24[20] = 0 Advised by SD3 Alex Wang. 2011.02.09. */ | |
050abc45 | 820 | TmpU1B = rtl8723au_read8(Adapter, REG_AFE_XTAL_CTRL+2); |
edbfd672 | 821 | rtl8723au_write8(Adapter, REG_AFE_XTAL_CTRL+2, TmpU1B & ~BIT(4)); |
f7c92d2c LF |
822 | |
823 | /* 6. 0x1f[7:0] = 0x07 */ | |
edbfd672 | 824 | rtl8723au_write8(Adapter, REG_RF_CTRL, 0x07); |
f7c92d2c LF |
825 | |
826 | /* */ | |
827 | /* Config BB and AGC */ | |
828 | /* */ | |
829 | rtStatus = phy_BB8723a_Config_ParaFile(Adapter); | |
830 | ||
831 | /* only for B-cut */ | |
832 | if (pHalData->EEPROMVersion >= 0x01) { | |
833 | CrystalCap = pHalData->CrystalCap & 0x3F; | |
834 | PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, | |
835 | (CrystalCap | (CrystalCap << 6))); | |
836 | } | |
837 | ||
838 | PHY_SetBBReg(Adapter, REG_LDOA15_CTRL, bMaskDWord, 0x01572505); | |
839 | return rtStatus; | |
840 | } | |
841 | ||
f7c92d2c LF |
842 | static void getTxPowerIndex(struct rtw_adapter *Adapter, |
843 | u8 channel, u8 *cckPowerLevel, u8 *ofdmPowerLevel) | |
844 | { | |
845 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
846 | u8 index = (channel - 1); | |
847 | /* 1. CCK */ | |
848 | cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; | |
849 | cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; | |
850 | ||
851 | /* 2. OFDM for 1S or 2S */ | |
852 | if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R) { | |
853 | /* Read HT 40 OFDM TX power */ | |
854 | ofdmPowerLevel[RF_PATH_A] = | |
855 | pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index]; | |
856 | ofdmPowerLevel[RF_PATH_B] = | |
857 | pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index]; | |
858 | } else if (GET_RF_TYPE(Adapter) == RF_2T2R) { | |
859 | /* Read HT 40 OFDM TX power */ | |
860 | ofdmPowerLevel[RF_PATH_A] = | |
861 | pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index]; | |
862 | ofdmPowerLevel[RF_PATH_B] = | |
863 | pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index]; | |
864 | } | |
865 | } | |
866 | ||
867 | static void ccxPowerIndexCheck(struct rtw_adapter *Adapter, u8 channel, | |
868 | u8 *cckPowerLevel, u8 *ofdmPowerLevel) | |
869 | { | |
870 | } | |
871 | ||
872 | /*----------------------------------------------------------------------------- | |
873 | * Function: SetTxPowerLevel8723A() | |
874 | * | |
875 | * Overview: This function is export to "HalCommon" moudule | |
876 | * We must consider RF path later!!!!!!! | |
877 | * | |
878 | * Input: struct rtw_adapter * Adapter | |
879 | * u8 channel | |
880 | * | |
881 | * Output: NONE | |
882 | * | |
883 | * Return: NONE | |
884 | * | |
885 | *---------------------------------------------------------------------------*/ | |
886 | void PHY_SetTxPowerLevel8723A(struct rtw_adapter *Adapter, u8 channel) | |
887 | { | |
888 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
889 | u8 cckPowerLevel[2], ofdmPowerLevel[2]; /* [0]:RF-A, [1]:RF-B */ | |
890 | ||
891 | if (pHalData->bTXPowerDataReadFromEEPORM == false) | |
892 | return; | |
893 | ||
894 | getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], | |
895 | &ofdmPowerLevel[0]); | |
896 | ||
897 | ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], | |
898 | &ofdmPowerLevel[0]); | |
899 | ||
900 | rtl823a_phy_rf6052setccktxpower(Adapter, &cckPowerLevel[0]); | |
901 | rtl8723a_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel); | |
902 | } | |
903 | ||
904 | /*----------------------------------------------------------------------------- | |
905 | * Function: PHY_SetBWMode23aCallback8192C() | |
906 | * | |
907 | * Overview: Timer callback function for SetSetBWMode23a | |
908 | * | |
909 | * Input: PRT_TIMER pTimer | |
910 | * | |
911 | * Output: NONE | |
912 | * | |
913 | * Return: NONE | |
914 | * | |
915 | * Note: | |
916 | * (1) We do not take j mode into consideration now | |
917 | * (2) Will two workitem of "switch channel" and | |
918 | * "switch channel bandwidth" run concurrently? | |
919 | *---------------------------------------------------------------------------*/ | |
920 | static void | |
921 | _PHY_SetBWMode23a92C(struct rtw_adapter *Adapter) | |
922 | { | |
923 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
924 | u8 regBwOpMode; | |
925 | u8 regRRSR_RSC; | |
926 | ||
927 | if (pHalData->rf_chip == RF_PSEUDO_11N) | |
928 | return; | |
929 | ||
930 | /* There is no 40MHz mode in RF_8225. */ | |
931 | if (pHalData->rf_chip == RF_8225) | |
932 | return; | |
933 | ||
934 | if (Adapter->bDriverStopped) | |
935 | return; | |
936 | ||
937 | /* 3 */ | |
938 | /* 3<1>Set MAC register */ | |
939 | /* 3 */ | |
940 | ||
050abc45 JS |
941 | regBwOpMode = rtl8723au_read8(Adapter, REG_BWOPMODE); |
942 | regRRSR_RSC = rtl8723au_read8(Adapter, REG_RRSR+2); | |
f7c92d2c LF |
943 | |
944 | switch (pHalData->CurrentChannelBW) { | |
945 | case HT_CHANNEL_WIDTH_20: | |
946 | regBwOpMode |= BW_OPMODE_20MHZ; | |
edbfd672 | 947 | rtl8723au_write8(Adapter, REG_BWOPMODE, regBwOpMode); |
f7c92d2c LF |
948 | break; |
949 | case HT_CHANNEL_WIDTH_40: | |
950 | regBwOpMode &= ~BW_OPMODE_20MHZ; | |
edbfd672 | 951 | rtl8723au_write8(Adapter, REG_BWOPMODE, regBwOpMode); |
f7c92d2c LF |
952 | regRRSR_RSC = (regRRSR_RSC & 0x90) | |
953 | (pHalData->nCur40MhzPrimeSC << 5); | |
edbfd672 | 954 | rtl8723au_write8(Adapter, REG_RRSR+2, regRRSR_RSC); |
f7c92d2c LF |
955 | break; |
956 | ||
957 | default: | |
958 | break; | |
959 | } | |
960 | ||
961 | /* 3 */ | |
962 | /* 3<2>Set PHY related register */ | |
963 | /* 3 */ | |
964 | switch (pHalData->CurrentChannelBW) { | |
965 | /* 20 MHz channel*/ | |
966 | case HT_CHANNEL_WIDTH_20: | |
967 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); | |
968 | PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); | |
8f7654c1 | 969 | PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT(10), 1); |
f7c92d2c LF |
970 | |
971 | break; | |
972 | ||
973 | /* 40 MHz channel*/ | |
974 | case HT_CHANNEL_WIDTH_40: | |
975 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); | |
976 | PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); | |
977 | ||
978 | /* Set Control channel to upper or lower. These settings | |
979 | are required only for 40MHz */ | |
980 | PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, | |
981 | (pHalData->nCur40MhzPrimeSC >> 1)); | |
982 | PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, | |
983 | pHalData->nCur40MhzPrimeSC); | |
8f7654c1 | 984 | PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT(10), 0); |
f7c92d2c | 985 | |
8f7654c1 | 986 | PHY_SetBBReg(Adapter, 0x818, BIT(26) | BIT(27), |
f7c92d2c LF |
987 | (pHalData->nCur40MhzPrimeSC == |
988 | HAL_PRIME_CHNL_OFFSET_LOWER) ? 2:1); | |
989 | break; | |
990 | ||
991 | default: | |
992 | /*RT_TRACE(COMP_DBG, DBG_LOUD, | |
993 | ("PHY_SetBWMode23aCallback8192C(): unknown Bandwidth: %#X\n" \ | |
994 | , pHalData->CurrentChannelBW));*/ | |
995 | break; | |
996 | } | |
997 | /* Skip over setting of J-mode in BB register here. Default value | |
998 | is "None J mode". Emily 20070315 */ | |
999 | ||
1000 | /* Added it for 20/40 mhz switch time evaluation by guangan 070531 */ | |
1001 | /* NowL = PlatformEFIORead4Byte(Adapter, TSFR); */ | |
1002 | /* NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); */ | |
1003 | /* EndTime = ((u64)NowH << 32) + NowL; */ | |
1004 | /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode23aCallback8190Pci: time | |
1005 | of SetBWMode23a = %I64d us!\n", (EndTime - BeginTime))); */ | |
1006 | ||
1007 | /* 3<3>Set RF related register */ | |
1008 | switch (pHalData->rf_chip) { | |
1009 | case RF_8225: | |
1010 | /* PHY_SetRF8225Bandwidth(Adapter, | |
1011 | pHalData->CurrentChannelBW); */ | |
1012 | break; | |
1013 | ||
1014 | case RF_8256: | |
1015 | /* Please implement this function in Hal8190PciPhy8256.c */ | |
1016 | /* PHY_SetRF8256Bandwidth(Adapter, | |
1017 | pHalData->CurrentChannelBW); */ | |
1018 | break; | |
1019 | ||
1020 | case RF_8258: | |
1021 | /* Please implement this function in Hal8190PciPhy8258.c */ | |
1022 | /* PHY_SetRF8258Bandwidth(); */ | |
1023 | break; | |
1024 | ||
1025 | case RF_PSEUDO_11N: | |
1026 | /* Do Nothing */ | |
1027 | break; | |
1028 | ||
1029 | case RF_6052: | |
1030 | rtl8723a_phy_rf6052set_bw(Adapter, pHalData->CurrentChannelBW); | |
1031 | break; | |
1032 | ||
1033 | default: | |
1034 | /* RT_ASSERT(false, ("Unknown RFChipID: %d\n", | |
1035 | pHalData->RFChipID)); */ | |
1036 | break; | |
1037 | } | |
1038 | ||
1039 | /* pHalData->SetBWMode23aInProgress = false; */ | |
1040 | ||
1041 | /* RT_TRACE(COMP_SCAN, DBG_LOUD, | |
1042 | ("<== PHY_SetBWMode23aCallback8192C() \n")); */ | |
1043 | } | |
1044 | ||
1045 | /*----------------------------------------------------------------------------- | |
1046 | * Function: SetBWMode23a8190Pci() | |
1047 | * | |
1048 | * Overview: This function is export to "HalCommon" moudule | |
1049 | * | |
1050 | * Input: struct rtw_adapter * Adapter | |
1051 | * enum ht_channel_width Bandwidth 20M or 40M | |
1052 | * | |
1053 | * Output: NONE | |
1054 | * | |
1055 | * Return: NONE | |
1056 | * | |
1057 | * Note: We do not take j mode into consideration now | |
1058 | *---------------------------------------------------------------------------*/ | |
1059 | void | |
1060 | PHY_SetBWMode23a8723A(struct rtw_adapter *Adapter, | |
1061 | enum ht_channel_width Bandwidth, unsigned char Offset) | |
1062 | { | |
1063 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
1064 | enum ht_channel_width tmpBW = pHalData->CurrentChannelBW; | |
1065 | ||
1066 | pHalData->CurrentChannelBW = Bandwidth; | |
1067 | ||
1068 | pHalData->nCur40MhzPrimeSC = Offset; | |
1069 | ||
1070 | if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) | |
1071 | _PHY_SetBWMode23a92C(Adapter); | |
1072 | else | |
1073 | pHalData->CurrentChannelBW = tmpBW; | |
1074 | } | |
1075 | ||
1076 | static void _PHY_SwChnl8723A(struct rtw_adapter *Adapter, u8 channel) | |
1077 | { | |
1078 | u8 eRFPath; | |
1079 | u32 param1, param2; | |
1080 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
1081 | ||
f7c92d2c LF |
1082 | /* s1. pre common command - CmdID_SetTxPowerLevel */ |
1083 | PHY_SetTxPowerLevel8723A(Adapter, channel); | |
1084 | ||
1085 | /* s2. RF dependent command - CmdID_RF_WriteReg, | |
1086 | param1 = RF_CHNLBW, param2 = channel */ | |
1087 | param1 = RF_CHNLBW; | |
1088 | param2 = channel; | |
1089 | for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { | |
1090 | pHalData->RfRegChnlVal[eRFPath] = | |
1091 | (pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2; | |
1092 | PHY_SetRFReg(Adapter, (enum RF_RADIO_PATH)eRFPath, param1, | |
1093 | bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); | |
1094 | } | |
1095 | ||
1096 | /* s3. post common command - CmdID_End, None */ | |
1097 | } | |
1098 | ||
1099 | void PHY_SwChnl8723A(struct rtw_adapter *Adapter, u8 channel) | |
1100 | { | |
1101 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); | |
1102 | u8 tmpchannel = pHalData->CurrentChannel; | |
1103 | bool result = true; | |
1104 | ||
1105 | if (pHalData->rf_chip == RF_PSEUDO_11N) { | |
1106 | /* return immediately if it is peudo-phy */ | |
1107 | return; | |
1108 | } | |
1109 | ||
1110 | if (channel == 0) | |
1111 | channel = 1; | |
1112 | ||
1113 | pHalData->CurrentChannel = channel; | |
1114 | ||
1115 | if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) { | |
1116 | _PHY_SwChnl8723A(Adapter, channel); | |
1117 | ||
1118 | if (!result) | |
1119 | pHalData->CurrentChannel = tmpchannel; | |
1120 | } else { | |
1121 | pHalData->CurrentChannel = tmpchannel; | |
1122 | } | |
1123 | } |