projects / deliverable / linux.git / blame
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|---|---|---|
| 364e30eb LF |
1 | /****************************************************************************** |
| 2 | * | |
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify it | |
| 6 | * under the terms of version 2 of the GNU General Public License as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 12 | * more details. | |
| 13 | * | |
| 14 | * | |
| 15 | ******************************************************************************/ | |
| 16 | #ifndef __HALPWRSEQCMD_H__ | |
| 17 | #define __HALPWRSEQCMD_H__ | |
| 18 | ||
| 19 | #include <drv_types.h> | |
| 20 | ||
| 21 | /*---------------------------------------------*/ | |
| 22 | /*---------------------------------------------*/ | |
| 23 | #define PWR_CMD_READ 0x00 | |
| 24 | /* offset: the read register offset */ | |
| 25 | /* msk: the mask of the read value */ | |
| 26 | /* value: N/A, left by 0 */ | |
| 27 | /* note: dirver shall implement this function by read & msk */ | |
| 28 | ||
| 29 | #define PWR_CMD_WRITE 0x01 | |
| 30 | /* offset: the read register offset */ | |
| 31 | /* msk: the mask of the write bits */ | |
| 32 | /* value: write value */ | |
| 33 | /* note: driver shall implement this cmd by read & msk after write */ | |
| 34 | ||
| 35 | #define PWR_CMD_POLLING 0x02 | |
| 36 | /* offset: the read register offset */ | |
| 37 | /* msk: the mask of the polled value */ | |
| 38 | /* value: the value to be polled, masked by the msd field. */ | |
| 39 | /* note: driver shall implement this cmd by */ | |
| 40 | /* do{ */ | |
| 41 | /* if( (Read(offset) & msk) == (value & msk) ) */ | |
| 42 | /* break; */ | |
| 43 | /* } while(not timeout); */ | |
| 44 | ||
| 45 | #define PWR_CMD_DELAY 0x03 | |
| 46 | /* offset: the value to delay */ | |
| 47 | /* msk: N/A */ | |
| 48 | /* value: the unit of delay, 0: us, 1: ms */ | |
| 49 | ||
| 50 | #define PWR_CMD_END 0x04 | |
| 51 | /* offset: N/A */ | |
| 52 | /* msk: N/A */ | |
| 53 | /* value: N/A */ | |
| 54 | ||
| 55 | /*---------------------------------------------*/ | |
| 56 | /* 3 The value of base: 4 bits */ | |
| 57 | /*---------------------------------------------*/ | |
| 58 | /* define the base address of each block */ | |
| 59 | #define PWR_BASEADDR_MAC 0x00 | |
| 60 | #define PWR_BASEADDR_USB 0x01 | |
| 61 | #define PWR_BASEADDR_PCIE 0x02 | |
| 62 | #define PWR_BASEADDR_SDIO 0x03 | |
| 63 | ||
| 64 | /*---------------------------------------------*/ | |
| 65 | /* 3 The value of interface_msk: 4 bits */ | |
| 66 | /*---------------------------------------------*/ | |
| 67 | #define PWR_INTF_SDIO_MSK BIT(0) | |
| 68 | #define PWR_INTF_USB_MSK BIT(1) | |
| 69 | #define PWR_INTF_PCI_MSK BIT(2) | |
| 70 | #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) | |
| 71 | ||
| 72 | /*---------------------------------------------*/ | |
| 73 | /* 3 The value of fab_msk: 4 bits */ | |
| 74 | /*---------------------------------------------*/ | |
| 75 | #define PWR_FAB_TSMC_MSK BIT(0) | |
| 76 | #define PWR_FAB_UMC_MSK BIT(1) | |
| 77 | #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) | |
| 78 | ||
| 79 | /*---------------------------------------------*/ | |
| 80 | /* 3 The value of cut_msk: 8 bits */ | |
| 81 | /*---------------------------------------------*/ | |
| 82 | #define PWR_CUT_TESTCHIP_MSK BIT(0) | |
| 83 | #define PWR_CUT_A_MSK BIT(1) | |
| 84 | #define PWR_CUT_B_MSK BIT(2) | |
| 85 | #define PWR_CUT_C_MSK BIT(3) | |
| 86 | #define PWR_CUT_D_MSK BIT(4) | |
| 87 | #define PWR_CUT_E_MSK BIT(5) | |
| 88 | #define PWR_CUT_F_MSK BIT(6) | |
| 89 | #define PWR_CUT_G_MSK BIT(7) | |
| 90 | #define PWR_CUT_ALL_MSK 0xFF | |
| 91 | ||
| 92 | ||
| 93 | enum pwrseq_delay_unit { | |
| 94 | PWRSEQ_DELAY_US, | |
| 95 | PWRSEQ_DELAY_MS, | |
| 96 | }; | |
| 97 | ||
| 98 | struct wlan_pwr_cfg { | |
| 99 | u16 offset; | |
| 100 | u8 cut_msk; | |
| 101 | u8 fab_msk:4; | |
| 102 | u8 interface_msk:4; | |
| 103 | u8 base:4; | |
| 104 | u8 cmd:4; | |
| 105 | u8 msk; | |
| 106 | u8 value; | |
| 107 | }; | |
| 108 | ||
| 109 | ||
| 110 | #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset | |
| 111 | #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk | |
| 112 | #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk | |
| 113 | #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk | |
| 114 | #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base | |
| 115 | #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd | |
| 116 | #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk | |
| 117 | #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value | |
| 118 | ||
| 119 | ||
| 120 | /* */ | |
| 121 | /* Prototype of protected function. */ | |
| 122 | /* */ | |
| 123 | u8 HalPwrSeqCmdParsing23a( | |
| 124 | struct rtw_adapter *padapter, | |
| 125 | u8 CutVersion, | |
| 126 | u8 FabVersion, | |
| 127 | u8 InterfaceType, | |
| 128 | struct wlan_pwr_cfg PwrCfgCmd[]); | |
| 129 | ||
| 130 | #endif |