[deliverable/linux.git] / drivers / staging / rtl8723au / include / odm.h

/******************************************************************************
 *
 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 ******************************************************************************/


#ifndef	__HALDMOUTSRC_H__
#define __HALDMOUTSRC_H__

/*  */
/*  Definition */
/*  */
/*  */
/*  2011/09/22 MH Define all team supprt ability. */
/*  */

/*  */
/*  2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */
/*  */
/* define		DM_ODM_SUPPORT_AP			0 */
/* define		DM_ODM_SUPPORT_ADSL			0 */
/* define		DM_ODM_SUPPORT_CE			0 */
/* define		DM_ODM_SUPPORT_MP			1 */

#define	TP_MODE		0
#define	RSSI_MODE		1
#define	TRAFFIC_LOW	0
#define	TRAFFIC_HIGH	1


/*  */
/* 3 Tx Power Tracking */
/* 3============================================================ */
#define		DPK_DELTA_MAPPING_NUM	13
#define		index_mapping_HP_NUM	15


/*  */
/* 3 PSD Handler */
/* 3============================================================ */

#define	AFH_PSD		1	/* 0:normal PSD scan, 1: only do 20 pts PSD */
#define	MODE_40M		0	/* 0:20M, 1:40M */
#define	PSD_TH2		3
#define	PSD_CHMIN		20   /*  Minimum channel number for BT AFH */
#define	SIR_STEP_SIZE	3
#define   Smooth_Size_1		5
#define	Smooth_TH_1	3
#define   Smooth_Size_2		10
#define	Smooth_TH_2	4
#define   Smooth_Size_3		20
#define	Smooth_TH_3	4
#define   Smooth_Step_Size 5
#define	Adaptive_SIR	1
#define	PSD_RESCAN		4
#define	PSD_SCAN_INTERVAL	700 /* ms */

/* 8723A High Power IGI Setting */
#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND	0x22
#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
#define DM_DIG_HIGH_PWR_THRESHOLD	0x3a

/*  LPS define */
#define DM_DIG_FA_TH0_LPS				4 /*  4 in lps */
#define DM_DIG_FA_TH1_LPS				15 /*  15 lps */
#define DM_DIG_FA_TH2_LPS				30 /*  30 lps */
#define RSSI_OFFSET_DIG					0x05;

/* ANT Test */
#define			ANTTESTALL		0x00		/* Ant A or B will be Testing */
#define		ANTTESTA		0x01		/* Ant A will be Testing */
#define		ANTTESTB		0x02		/* Ant B will be testing */


/*  */
/*  structure and define */
/*  */

struct  dig_t {
	u8		Dig_Enable_Flag;
	u8		Dig_Ext_Port_Stage;

	int		RssiLowThresh;
	int		RssiHighThresh;

	u32		FALowThresh;
	u32		FAHighThresh;

	u8		CurSTAConnectState;
	u8		PreSTAConnectState;
	u8		CurMultiSTAConnectState;

	u8		PreIGValue;
	u8		CurIGValue;
	u8		BackupIGValue;

	s8		BackoffVal;
	s8		BackoffVal_range_max;
	s8		BackoffVal_range_min;
	u8		rx_gain_range_max;
	u8		rx_gain_range_min;
	u8		Rssi_val_min;

	u8		PreCCK_CCAThres;
	u8		CurCCK_CCAThres;
	u8		PreCCKPDState;
	u8		CurCCKPDState;

	u8		LargeFAHit;
	u8		ForbiddenIGI;
	u32		Recover_cnt;

	u8		DIG_Dynamic_MIN_0;
	u8		DIG_Dynamic_MIN_1;
	bool		bMediaConnect_0;
	bool		bMediaConnect_1;

	u32		AntDiv_RSSI_max;
	u32		RSSI_max;
};

struct dynamic_pwr_sav {
	u8		PreCCAState;
	u8		CurCCAState;

	u8		PreRFState;
	u8		CurRFState;

	int		    Rssi_val_min;

	u8		initialize;
	u32		Reg874,RegC70,Reg85C,RegA74;
};

struct false_alarm_stats {
	u32	Cnt_Parity_Fail;
	u32	Cnt_Rate_Illegal;
	u32	Cnt_Crc8_fail;
	u32	Cnt_Mcs_fail;
	u32	Cnt_Ofdm_fail;
	u32	Cnt_Cck_fail;
	u32	Cnt_all;
	u32	Cnt_Fast_Fsync;
	u32	Cnt_SB_Search_fail;
	u32	Cnt_OFDM_CCA;
	u32	Cnt_CCK_CCA;
	u32	Cnt_CCA_all;
	u32	Cnt_BW_USC;	/* Gary */
	u32	Cnt_BW_LSC;	/* Gary */
};

struct pri_cca {
	u8		PriCCA_flag;
	u8		intf_flag;
	u8		intf_type;
	u8		DupRTS_flag;
	u8		Monitor_flag;
};

struct rx_hp {
	u8		RXHP_flag;
	u8		PSD_func_trigger;
	u8		PSD_bitmap_RXHP[80];
	u8		Pre_IGI;
	u8		Cur_IGI;
	u8		Pre_pw_th;
	u8		Cur_pw_th;
	bool		First_time_enter;
	bool		RXHP_enable;
	u8		TP_Mode;
};

#define ASSOCIATE_ENTRY_NUM					32 /*  Max size of AsocEntry[]. */
#define	ODM_ASSOCIATE_ENTRY_NUM				ASSOCIATE_ENTRY_NUM

/*  This indicates two different the steps. */
/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
/*  with original RSSI to determine if it is necessary to switch antenna. */
#define SWAW_STEP_PEAK		0
#define SWAW_STEP_DETERMINE	1

#define	TP_MODE		0
#define	RSSI_MODE		1
#define	TRAFFIC_LOW	0
#define	TRAFFIC_HIGH	1

struct sw_ant_sw {
	u8		try_flag;
	s32		PreRSSI;
	u8		CurAntenna;
	u8		PreAntenna;
	u8		RSSI_Trying;
	u8		TestMode;
	u8		bTriggerAntennaSwitch;
	u8		SelectAntennaMap;
	u8		RSSI_target;

	/*  Before link Antenna Switch check */
	u8		SWAS_NoLink_State;
	u32		SWAS_NoLink_BK_Reg860;
	bool		ANTA_ON;	/* To indicate Ant A is or not */
	bool		ANTB_ON;	/* To indicate Ant B is on or not */

	s32		RSSI_sum_A;
	s32		RSSI_sum_B;
	s32		RSSI_cnt_A;
	s32		RSSI_cnt_B;

	u64		lastTxOkCnt;
	u64		lastRxOkCnt;
	u64		TXByteCnt_A;
	u64		TXByteCnt_B;
	u64		RXByteCnt_A;
	u64		RXByteCnt_B;
	u8		TrafficLoad;
};

struct edca_turbo {
	bool bCurrentTurboEDCA;
	bool bIsCurRDLState;
	u32	prv_traffic_idx; /*  edca turbo */
};

struct odm_rate_adapt {
	u8	Type;		/*  DM_Type_ByFW/DM_Type_ByDriver */
	u8	HighRSSIThresh;	/*  if RSSI > HighRSSIThresh	=> RATRState is DM_RATR_STA_HIGH */
	u8	LowRSSIThresh;	/*  if RSSI <= LowRSSIThresh	=> RATRState is DM_RATR_STA_LOW */
	u8	RATRState;	/*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
	u32	LastRATR;	/*  RATR Register Content */
};

#define IQK_MAC_REG_NUM		4
#define IQK_ADDA_REG_NUM		16
#define IQK_BB_REG_NUM_MAX	10
#define IQK_BB_REG_NUM		9
#define HP_THERMAL_NUM		8

#define AVG_THERMAL_NUM		8
#define IQK_Matrix_REG_NUM	8
#define IQK_Matrix_Settings_NUM	1+24+21

#define		DM_Type_ByFW			0
#define		DM_Type_ByDriver		1

/*  Declare for common info */

struct odm_phy_dbg_info {
	/* ODM Write,debug info */
	s8		RxSNRdB[RF_PATH_MAX];
	u64		NumQryPhyStatus;
	u64		NumQryPhyStatusCCK;
	u64		NumQryPhyStatusOFDM;
	/* Others */
	s32		RxEVM[RF_PATH_MAX];

};

struct odm_packet_info {
	u8		Rate;
	u8		StationID;
	bool		bPacketMatchBSSID;
	bool		bPacketToSelf;
	bool		bPacketBeacon;
};


enum {
	/*  BB Team */
	ODM_DIG			= 0x00000001,
	ODM_HIGH_POWER		= 0x00000002,
	ODM_CCK_CCA_TH		= 0x00000004,
	ODM_FA_STATISTICS	= 0x00000008,
	ODM_RAMASK		= 0x00000010,
	ODM_RSSI_MONITOR	= 0x00000020,
	ODM_SW_ANTDIV		= 0x00000040,
	ODM_HW_ANTDIV		= 0x00000080,
	ODM_BB_PWRSV		= 0x00000100,
	ODM_2TPATHDIV		= 0x00000200,
	ODM_1TPATHDIV		= 0x00000400,
	ODM_PSD2AFH		= 0x00000800
};

/*  */
/*  2011/10/20 MH Define Common info enum for all team. */
/*  */

enum odm_cmninfo {
	/*  Fixed value: */
	/*  */

	ODM_CMNINFO_PLATFORM = 0,
	ODM_CMNINFO_ABILITY,					/*  enum odm_ability */
	ODM_CMNINFO_INTERFACE,				/*  enum odm_interface_def */
	ODM_CMNINFO_MP_TEST_CHIP,
	ODM_CMNINFO_IC_TYPE,					/*  enum odm_ic_type_def */
	ODM_CMNINFO_CUT_VER,					/*  enum odm_cut_version */
	ODM_CMNINFO_FAB_VER,					/*  enum odm_fab_version */
	ODM_CMNINFO_RF_TYPE,					/*  enum rf_path_def or enum odm_rf_type? */
	ODM_CMNINFO_BOARD_TYPE,				/*  enum odm_board_type */
	ODM_CMNINFO_EXT_LNA,					/*  true */
	ODM_CMNINFO_EXT_PA,
	ODM_CMNINFO_EXT_TRSW,
	ODM_CMNINFO_PATCH_ID,				/* CUSTOMER ID */
	ODM_CMNINFO_BINHCT_TEST,
	ODM_CMNINFO_BWIFI_TEST,
	ODM_CMNINFO_SMART_CONCURRENT,


	/*  */
	/*  Dynamic value: */
	/*  */
	ODM_CMNINFO_SEC_CHNL_OFFSET,		/*  enum odm_sec_chnl_offset */
	ODM_CMNINFO_BW,				/*  enum odm_band_width */
	ODM_CMNINFO_CHNL,

	ODM_CMNINFO_SCAN,
	ODM_CMNINFO_POWER_SAVING,
	ODM_CMNINFO_MP_MODE,

	ODM_CMNINFO_WIFI_DIRECT,
	ODM_CMNINFO_WIFI_DISPLAY,
	ODM_CMNINFO_LINK,
	ODM_CMNINFO_RSSI_MIN,
	ODM_CMNINFO_DBG_COMP,				/*  u64 */
	ODM_CMNINFO_DBG_LEVEL,				/*  u32 */
	ODM_CMNINFO_RA_THRESHOLD_HIGH,		/*  u8 */
	ODM_CMNINFO_RA_THRESHOLD_LOW,		/*  u8 */
	ODM_CMNINFO_RF_ANTENNA_TYPE,		/*  u8 */
	ODM_CMNINFO_BT_DISABLED,
	ODM_CMNINFO_BT_OPERATION,
	ODM_CMNINFO_BT_DIG,
	ODM_CMNINFO_BT_BUSY,					/* Check Bt is using or not */
	ODM_CMNINFO_BT_DISABLE_EDCA,

	/*  */
	/*  Dynamic ptr array hook itms. */
	/*  */
	ODM_CMNINFO_STA_STATUS,
	ODM_CMNINFO_PHY_STATUS,
	ODM_CMNINFO_MAC_STATUS,

	ODM_CMNINFO_MAX,
};

/*  Define ODM support ability.  ODM_CMNINFO_ABILITY */
enum {
	/*  BB ODM section BIT 0-15 */
	ODM_BB_DIG				= BIT(0),
	ODM_BB_RA_MASK				= BIT(1),
	ODM_BB_DYNAMIC_TXPWR			= BIT(2),
	ODM_BB_FA_CNT				= BIT(3),
	ODM_BB_RSSI_MONITOR			= BIT(4),
	ODM_BB_CCK_PD				= BIT(5),
	ODM_BB_ANT_DIV				= BIT(6),
	ODM_BB_PWR_SAVE				= BIT(7),
	ODM_BB_PWR_TRAIN			= BIT(8),
	ODM_BB_RATE_ADAPTIVE			= BIT(9),
	ODM_BB_PATH_DIV				= BIT(10),
	ODM_BB_PSD				= BIT(11),
	ODM_BB_RXHP				= BIT(12),

	/*  MAC DM section BIT 16-23 */
	ODM_MAC_EDCA_TURBO			= BIT(16),
	ODM_MAC_EARLY_MODE			= BIT(17),

	/*  RF ODM section BIT 24-31 */
	ODM_RF_TX_PWR_TRACK			= BIT(24),
	ODM_RF_RX_GAIN_TRACK			= BIT(25),
	ODM_RF_CALIBRATION			= BIT(26),

};

/*	ODM_CMNINFO_INTERFACE */
enum odm_interface_def {
	ODM_ITRF_PCIE	=	0x1,
	ODM_ITRF_USB	=	0x2,
	ODM_ITRF_SDIO	=	0x4,
	ODM_ITRF_ALL	=	0x7,
};

/*  ODM_CMNINFO_IC_TYPE */
enum odm_ic_type_def {
	ODM_RTL8192S	=	BIT(0),
	ODM_RTL8192C	=	BIT(1),
	ODM_RTL8192D	=	BIT(2),
	ODM_RTL8723A	=	BIT(3),
	ODM_RTL8188E	=	BIT(4),
	ODM_RTL8812	=	BIT(5),
	ODM_RTL8821	=	BIT(6),
};

/* ODM_CMNINFO_CUT_VER */
enum odm_cut_version {
	ODM_CUT_A		=	1,
	ODM_CUT_B		=	2,
	ODM_CUT_C		=	3,
	ODM_CUT_D		=	4,
	ODM_CUT_E		=	5,
	ODM_CUT_F		=	6,
	ODM_CUT_TEST		=	7,
};

/*  ODM_CMNINFO_FAB_VER */
enum odm_fab_version {
	ODM_TSMC	=	0,
	ODM_UMC		=	1,
};

/*  ODM_CMNINFO_RF_TYPE */
/*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
enum rf_path_def {
	ODM_RF_TX_A	=	BIT(0),
	ODM_RF_TX_B	=	BIT(1),
	ODM_RF_TX_C	=	BIT(2),
	ODM_RF_TX_D	=	BIT(3),
	ODM_RF_RX_A	=	BIT(4),
	ODM_RF_RX_B	=	BIT(5),
	ODM_RF_RX_C	=	BIT(6),
	ODM_RF_RX_D	=	BIT(7),
};


enum odm_rf_type {
	ODM_1T1R	=	0,
	ODM_1T2R	=	1,
	ODM_2T2R	=	2,
	ODM_2T3R	=	3,
	ODM_2T4R	=	4,
	ODM_3T3R	=	5,
	ODM_3T4R	=	6,
	ODM_4T4R	=	7,
};

/*  ODM Dynamic common info value definition */

enum odm_mac_phy_mode {
	ODM_SMSP	= 0,
	ODM_DMSP	= 1,
	ODM_DMDP	= 2,
};


enum odm_bt_coexist {
	ODM_BT_BUSY		= 1,
	ODM_BT_ON		= 2,
	ODM_BT_OFF		= 3,
	ODM_BT_NONE		= 4,
};

/*  ODM_CMNINFO_OP_MODE */
enum odm_operation_mode {
	ODM_NO_LINK		= BIT(0),
	ODM_LINK		= BIT(1),
	ODM_SCAN		= BIT(2),
	ODM_POWERSAVE		= BIT(3),
	ODM_AP_MODE		= BIT(4),
	ODM_CLIENT_MODE		= BIT(5),
	ODM_AD_HOC		= BIT(6),
	ODM_WIFI_DIRECT		= BIT(7),
	ODM_WIFI_DISPLAY	= BIT(8),
};

/*  ODM_CMNINFO_WM_MODE */
enum odm_wireless_mode {
	ODM_WM_UNKNOW		= 0x0,
	ODM_WM_B		= BIT(0),
	ODM_WM_G		= BIT(1),
	ODM_WM_A		= BIT(2),
	ODM_WM_N24G		= BIT(3),
	ODM_WM_N5G		= BIT(4),
	ODM_WM_AUTO		= BIT(5),
	ODM_WM_AC		= BIT(6),
};

/*  ODM_CMNINFO_BAND */
enum odm_band_type {
	ODM_BAND_2_4G		= BIT(0),
	ODM_BAND_5G		= BIT(1),

};

/*  ODM_CMNINFO_SEC_CHNL_OFFSET */
enum odm_sec_chnl_offset {
	ODM_DONT_CARE		= 0,
	ODM_BELOW		= 1,
	ODM_ABOVE		= 2
};

/*  ODM_CMNINFO_BW */
enum odm_band_width {
	ODM_BW20M		= 0,
	ODM_BW40M		= 1,
	ODM_BW80M		= 2,
	ODM_BW160M		= 3,
	ODM_BW10M		= 4,
};

/*  ODM_CMNINFO_CHNL */

/*  ODM_CMNINFO_BOARD_TYPE */
enum odm_board_type {
	ODM_BOARD_NORMAL	= 0,
	ODM_BOARD_HIGHPWR	= 1,
	ODM_BOARD_MINICARD	= 2,
	ODM_BOARD_SLIM		= 3,
	ODM_BOARD_COMBO		= 4,

};

/*  ODM_CMNINFO_ONE_PATH_CCA */
enum odm_cca_path {
	ODM_CCA_2R			= 0,
	ODM_CCA_1R_A			= 1,
	ODM_CCA_1R_B			= 2,
};

struct iqk_matrix_regs_set {
	bool	bIQKDone;
	s32	Value[1][IQK_Matrix_REG_NUM];
};

struct odm_rf_cal_t {
	/* for tx power tracking */

	u32	RegA24; /*  for TempCCK */
	s32	RegE94;
	s32	RegE9C;
	s32	RegEB4;
	s32	RegEBC;

	/* u8 bTXPowerTracking; */
	u8		TXPowercount;
	bool bTXPowerTrackingInit;
	bool bTXPowerTracking;
	u8		TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
	u8		TM_Trigger;
	u8		InternalPA5G[2];	/* pathA / pathB */

	u8		ThermalMeter[2];    /*  ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
	u8		ThermalValue;
	u8		ThermalValue_LCK;
	u8		ThermalValue_IQK;
	u8	ThermalValue_DPK;
	u8	ThermalValue_AVG[AVG_THERMAL_NUM];
	u8	ThermalValue_AVG_index;
	u8	ThermalValue_RxGain;
	u8	ThermalValue_Crystal;
	u8	ThermalValue_DPKstore;
	u8	ThermalValue_DPKtrack;
	bool	TxPowerTrackingInProgress;
	bool	bDPKenable;

	bool	bReloadtxpowerindex;
	u8	bRfPiEnable;
	u32	TXPowerTrackingCallbackCnt; /* cosa add for debug */

	u8	bCCKinCH14;
	u8	CCK_index;
	u8	OFDM_index[2];
	bool bDoneTxpower;

	u8	ThermalValue_HP[HP_THERMAL_NUM];
	u8	ThermalValue_HP_index;
	struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];

	u8	Delta_IQK;
	u8	Delta_LCK;

	/* for IQK */
	u32	RegC04;
	u32	Reg874;
	u32	RegC08;
	u32	RegB68;
	u32	RegB6C;
	u32	Reg870;
	u32	Reg860;
	u32	Reg864;

	bool	bIQKInitialized;
	bool bLCKInProgress;
	bool	bAntennaDetected;
	u32	ADDA_backup[IQK_ADDA_REG_NUM];
	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
	u32	IQK_BB_backup_recover[9];
	u32	IQK_BB_backup[IQK_BB_REG_NUM];

	/* for APK */
	u32	APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
	u8	bAPKdone;
	u8	bAPKThermalMeterIgnore;
	u8	bDPdone;
	u8	bDPPathAOK;
	u8	bDPPathBOK;
};

/*  ODM Dynamic common info value definition */
struct odm_fat_t {
	u8	Bssid[6];
	u8	antsel_rx_keep_0;
	u8	antsel_rx_keep_1;
	u8	antsel_rx_keep_2;
	u32	antSumRSSI[7];
	u32	antRSSIcnt[7];
	u32	antAveRSSI[7];
	u8	FAT_State;
	u32	TrainIdx;
	u8	antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
	u8	antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
	u8	antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
	u32	MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
	u32	AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
	u32	MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
	u32	AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
	u8	RxIdleAnt;
	bool	bBecomeLinked;
};

enum fat_state {
	FAT_NORMAL_STATE		= 0,
	FAT_TRAINING_STATE		= 1,
};

enum ant_dif_type {
	NO_ANTDIV			= 0xFF,
	CG_TRX_HW_ANTDIV		= 0x01,
	CGCS_RX_HW_ANTDIV		= 0x02,
	FIXED_HW_ANTDIV			= 0x03,
	CG_TRX_SMART_ANTDIV		= 0x04,
	CGCS_RX_SW_ANTDIV		= 0x05,
};

/*  2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
struct dm_odm_t {
	/*  */
	/*	Add for different team use temporarily */
	/*  */
	struct rtw_adapter	*Adapter;		/*  For CE/NIC team */

	u64			DebugComponents;
	u32			DebugLevel;

/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
	bool			bCckHighPower;
	u8			RFPathRxEnable;		/*  ODM_CMNINFO_RFPATH_ENABLE */
	u8			ControlChannel;
/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */

/* 1  COMMON INFORMATION */

	/*  Init Value */
/* HOOK BEFORE REG INIT----------- */
Commit	Line	Data
364e30eb LF	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	******************************************************************************/
	15
	16
	17	#ifndef __HALDMOUTSRC_H__
	18	#define __HALDMOUTSRC_H__
	19
	20	/* */
	21	/* Definition */
	22	/* */
	23	/* */
	24	/* 2011/09/22 MH Define all team supprt ability. */
	25	/* */
	26
	27	/* */
	28	/* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */
	29	/* */
	30	/* define DM_ODM_SUPPORT_AP 0 */
	31	/* define DM_ODM_SUPPORT_ADSL 0 */
	32	/* define DM_ODM_SUPPORT_CE 0 */
	33	/* define DM_ODM_SUPPORT_MP 1 */
	34
	35	#define TP_MODE 0
	36	#define RSSI_MODE 1
	37	#define TRAFFIC_LOW 0
	38	#define TRAFFIC_HIGH 1
	39
	40
	41	/* */
	42	/* 3 Tx Power Tracking */
	43	/* 3============================================================ */
	44	#define DPK_DELTA_MAPPING_NUM 13
	45	#define index_mapping_HP_NUM 15
	46
	47
	48	/* */
	49	/* 3 PSD Handler */
	50	/* 3============================================================ */
	51
	52	#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
	53	#define MODE_40M 0 /* 0:20M, 1:40M */
	54	#define PSD_TH2 3
	55	#define PSD_CHMIN 20 /* Minimum channel number for BT AFH */
	56	#define SIR_STEP_SIZE 3
	57	#define Smooth_Size_1 5
	58	#define Smooth_TH_1 3
	59	#define Smooth_Size_2 10
	60	#define Smooth_TH_2 4
	61	#define Smooth_Size_3 20
	62	#define Smooth_TH_3 4
	63	#define Smooth_Step_Size 5
	64	#define Adaptive_SIR 1
65	#define PSD_RESCAN 4
66	#define PSD_SCAN_INTERVAL 700 /* ms */
67
68	/* 8723A High Power IGI Setting */
69	#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
70	#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
71	#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
72
73	/* LPS define */
74	#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
75	#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
76	#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
77	#define RSSI_OFFSET_DIG 0x05;
78
79	/* ANT Test */
80	#define ANTTESTALL 0x00 /* Ant A or B will be Testing */
81	#define ANTTESTA 0x01 /* Ant A will be Testing */
82	#define ANTTESTB 0x02 /* Ant B will be testing */
83
84
85	/* */
86	/* structure and define */
87	/* */
88
364e30eb LF	89	struct dig_t {
	90	u8 Dig_Enable_Flag;
	91	u8 Dig_Ext_Port_Stage;
	92
	93	int RssiLowThresh;
	94	int RssiHighThresh;
	95
	96	u32 FALowThresh;
	97	u32 FAHighThresh;
	98
	99	u8 CurSTAConnectState;
	100	u8 PreSTAConnectState;
	101	u8 CurMultiSTAConnectState;
	102
	103	u8 PreIGValue;
	104	u8 CurIGValue;
	105	u8 BackupIGValue;
	106
	107	s8 BackoffVal;
	108	s8 BackoffVal_range_max;
	109	s8 BackoffVal_range_min;
	110	u8 rx_gain_range_max;
	111	u8 rx_gain_range_min;
	112	u8 Rssi_val_min;
	113
	114	u8 PreCCK_CCAThres;
	115	u8 CurCCK_CCAThres;
	116	u8 PreCCKPDState;
	117	u8 CurCCKPDState;
	118
	119	u8 LargeFAHit;
	120	u8 ForbiddenIGI;
	121	u32 Recover_cnt;
	122
	123	u8 DIG_Dynamic_MIN_0;
	124	u8 DIG_Dynamic_MIN_1;
	125	bool bMediaConnect_0;
	126	bool bMediaConnect_1;
	127
	128	u32 AntDiv_RSSI_max;
	129	u32 RSSI_max;
	130	};
	131
	132	struct dynamic_pwr_sav {
	133	u8 PreCCAState;
	134	u8 CurCCAState;
	135
	136	u8 PreRFState;
	137	u8 CurRFState;
	138
	139	int Rssi_val_min;
	140
	141	u8 initialize;
	142	u32 Reg874,RegC70,Reg85C,RegA74;
	143	};
	144
	145	struct false_alarm_stats {
	146	u32 Cnt_Parity_Fail;
	147	u32 Cnt_Rate_Illegal;
	148	u32 Cnt_Crc8_fail;
	149	u32 Cnt_Mcs_fail;
	150	u32 Cnt_Ofdm_fail;
	151	u32 Cnt_Cck_fail;
	152	u32 Cnt_all;
153	u32 Cnt_Fast_Fsync;
154	u32 Cnt_SB_Search_fail;
155	u32 Cnt_OFDM_CCA;
156	u32 Cnt_CCK_CCA;
157	u32 Cnt_CCA_all;
158	u32 Cnt_BW_USC; /* Gary */
159	u32 Cnt_BW_LSC; /* Gary */
160	};
161
162	struct pri_cca {
163	u8 PriCCA_flag;
164	u8 intf_flag;
165	u8 intf_type;
166	u8 DupRTS_flag;
167	u8 Monitor_flag;
168	};
169
170	struct rx_hp {
171	u8 RXHP_flag;
172	u8 PSD_func_trigger;
173	u8 PSD_bitmap_RXHP[80];
174	u8 Pre_IGI;
175	u8 Cur_IGI;
176	u8 Pre_pw_th;
177	u8 Cur_pw_th;
178	bool First_time_enter;
179	bool RXHP_enable;
180	u8 TP_Mode;
364e30eb LF	181	};
	182
	183	#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
	184	#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
	185
	186	/* This indicates two different the steps. */
	187	/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
	188	/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
	189	/* with original RSSI to determine if it is necessary to switch antenna. */
	190	#define SWAW_STEP_PEAK 0
	191	#define SWAW_STEP_DETERMINE 1
	192
	193	#define TP_MODE 0
	194	#define RSSI_MODE 1
	195	#define TRAFFIC_LOW 0
	196	#define TRAFFIC_HIGH 1
	197
	198	struct sw_ant_sw {
	199	u8 try_flag;
	200	s32 PreRSSI;
	201	u8 CurAntenna;
	202	u8 PreAntenna;
	203	u8 RSSI_Trying;
	204	u8 TestMode;
	205	u8 bTriggerAntennaSwitch;
	206	u8 SelectAntennaMap;
	207	u8 RSSI_target;
	208
	209	/* Before link Antenna Switch check */
	210	u8 SWAS_NoLink_State;
	211	u32 SWAS_NoLink_BK_Reg860;
	212	bool ANTA_ON; /* To indicate Ant A is or not */
	213	bool ANTB_ON; /* To indicate Ant B is on or not */
	214
	215	s32 RSSI_sum_A;
	216	s32 RSSI_sum_B;
	217	s32 RSSI_cnt_A;
	218	s32 RSSI_cnt_B;
	219
	220	u64 lastTxOkCnt;
	221	u64 lastRxOkCnt;
	222	u64 TXByteCnt_A;
	223	u64 TXByteCnt_B;
	224	u64 RXByteCnt_A;
	225	u64 RXByteCnt_B;
	226	u8 TrafficLoad;
364e30eb LF	227	};
	228
	229	struct edca_turbo {
	230	bool bCurrentTurboEDCA;
	231	bool bIsCurRDLState;
	232	u32 prv_traffic_idx; /* edca turbo */
364e30eb LF	233	};
	234
	235	struct odm_rate_adapt {
	236	u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
	237	u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
	238	u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
	239	u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
	240	u32 LastRATR; /* RATR Register Content */
	241	};
	242
	243	#define IQK_MAC_REG_NUM 4
	244	#define IQK_ADDA_REG_NUM 16
	245	#define IQK_BB_REG_NUM_MAX 10
	246	#define IQK_BB_REG_NUM 9
	247	#define HP_THERMAL_NUM 8
	248
	249	#define AVG_THERMAL_NUM 8
	250	#define IQK_Matrix_REG_NUM 8
	251	#define IQK_Matrix_Settings_NUM 1+24+21
	252
	253	#define DM_Type_ByFW 0
	254	#define DM_Type_ByDriver 1
	255
364e30eb	256	/* Declare for common info */
364e30eb	257
364e30eb LF	258	struct odm_phy_dbg_info {
364e30eb LF	259	/* ODM Write,debug info */
c17416ef	260	s8 RxSNRdB[RF_PATH_MAX];
364e30eb LF	261	u64 NumQryPhyStatus;
	262	u64 NumQryPhyStatusCCK;
	263	u64 NumQryPhyStatusOFDM;
	264	/* Others */
c17416ef	265	s32 RxEVM[RF_PATH_MAX];
364e30eb LF	266
	267	};
	268
	269	struct odm_packet_info {
	270	u8 Rate;
	271	u8 StationID;
	272	bool bPacketMatchBSSID;
	273	bool bPacketToSelf;
	274	bool bPacketBeacon;
	275	};
	276
364e30eb LF	277
	278	enum {
	279	/* BB Team */
	280	ODM_DIG = 0x00000001,
	281	ODM_HIGH_POWER = 0x00000002,
	282	ODM_CCK_CCA_TH = 0x00000004,
	283	ODM_FA_STATISTICS = 0x00000008,
	284	ODM_RAMASK = 0x00000010,
	285	ODM_RSSI_MONITOR = 0x00000020,
	286	ODM_SW_ANTDIV = 0x00000040,
	287	ODM_HW_ANTDIV = 0x00000080,
	288	ODM_BB_PWRSV = 0x00000100,
	289	ODM_2TPATHDIV = 0x00000200,
	290	ODM_1TPATHDIV = 0x00000400,
	291	ODM_PSD2AFH = 0x00000800
	292	};
	293
364e30eb LF	294	/* */
	295	/* 2011/10/20 MH Define Common info enum for all team. */
	296	/* */
	297
	298	enum odm_cmninfo {
	299	/* Fixed value: */
	300	/* */
	301
	302	ODM_CMNINFO_PLATFORM = 0,
	303	ODM_CMNINFO_ABILITY, /* enum odm_ability */
	304	ODM_CMNINFO_INTERFACE, /* enum odm_interface_def */
	305	ODM_CMNINFO_MP_TEST_CHIP,
	306	ODM_CMNINFO_IC_TYPE, /* enum odm_ic_type_def */
	307	ODM_CMNINFO_CUT_VER, /* enum odm_cut_version */
	308	ODM_CMNINFO_FAB_VER, /* enum odm_fab_version */
	309	ODM_CMNINFO_RF_TYPE, /* enum rf_path_def or enum odm_rf_type? */
	310	ODM_CMNINFO_BOARD_TYPE, /* enum odm_board_type */
	311	ODM_CMNINFO_EXT_LNA, /* true */
	312	ODM_CMNINFO_EXT_PA,
	313	ODM_CMNINFO_EXT_TRSW,
	314	ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
	315	ODM_CMNINFO_BINHCT_TEST,
	316	ODM_CMNINFO_BWIFI_TEST,
	317	ODM_CMNINFO_SMART_CONCURRENT,
	318
	319
	320	/* */
	321	/* Dynamic value: */
	322	/* */
364e30eb	323	ODM_CMNINFO_SEC_CHNL_OFFSET, /* enum odm_sec_chnl_offset */
c5f3dc2f	324	ODM_CMNINFO_BW, /* enum odm_band_width */
364e30eb LF	325	ODM_CMNINFO_CHNL,
364e30eb LF	326
364e30eb LF	327	ODM_CMNINFO_SCAN,
364e30eb LF	328	ODM_CMNINFO_POWER_SAVING,
364e30eb LF	329	ODM_CMNINFO_MP_MODE,
	330
	331	ODM_CMNINFO_WIFI_DIRECT,
	332	ODM_CMNINFO_WIFI_DISPLAY,
	333	ODM_CMNINFO_LINK,
	334	ODM_CMNINFO_RSSI_MIN,
	335	ODM_CMNINFO_DBG_COMP, /* u64 */
	336	ODM_CMNINFO_DBG_LEVEL, /* u32 */
	337	ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
	338	ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
	339	ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
	340	ODM_CMNINFO_BT_DISABLED,
	341	ODM_CMNINFO_BT_OPERATION,
	342	ODM_CMNINFO_BT_DIG,
	343	ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */
	344	ODM_CMNINFO_BT_DISABLE_EDCA,
	345
	346	/* */
	347	/* Dynamic ptr array hook itms. */
	348	/* */
	349	ODM_CMNINFO_STA_STATUS,
	350	ODM_CMNINFO_PHY_STATUS,
	351	ODM_CMNINFO_MAC_STATUS,
	352
	353	ODM_CMNINFO_MAX,
	354	};
	355
	356	/* Define ODM support ability. ODM_CMNINFO_ABILITY */
	357	enum {
	358	/* BB ODM section BIT 0-15 */
93748447 JS	359	ODM_BB_DIG = BIT(0),
	360	ODM_BB_RA_MASK = BIT(1),
	361	ODM_BB_DYNAMIC_TXPWR = BIT(2),
	362	ODM_BB_FA_CNT = BIT(3),
	363	ODM_BB_RSSI_MONITOR = BIT(4),
	364	ODM_BB_CCK_PD = BIT(5),
	365	ODM_BB_ANT_DIV = BIT(6),
	366	ODM_BB_PWR_SAVE = BIT(7),
	367	ODM_BB_PWR_TRAIN = BIT(8),
	368	ODM_BB_RATE_ADAPTIVE = BIT(9),
	369	ODM_BB_PATH_DIV = BIT(10),
	370	ODM_BB_PSD = BIT(11),
	371	ODM_BB_RXHP = BIT(12),
364e30eb LF	372
364e30eb LF	373	/* MAC DM section BIT 16-23 */
93748447 JS	374	ODM_MAC_EDCA_TURBO = BIT(16),
93748447 JS	375	ODM_MAC_EARLY_MODE = BIT(17),
364e30eb LF	376
364e30eb LF	377	/* RF ODM section BIT 24-31 */
93748447 JS	378	ODM_RF_TX_PWR_TRACK = BIT(24),
	379	ODM_RF_RX_GAIN_TRACK = BIT(25),
	380	ODM_RF_CALIBRATION = BIT(26),
364e30eb LF	381
	382	};
	383
	384	/* ODM_CMNINFO_INTERFACE */
	385	enum odm_interface_def {
	386	ODM_ITRF_PCIE = 0x1,
	387	ODM_ITRF_USB = 0x2,
	388	ODM_ITRF_SDIO = 0x4,
	389	ODM_ITRF_ALL = 0x7,
	390	};
	391
	392	/* ODM_CMNINFO_IC_TYPE */
	393	enum odm_ic_type_def {
93748447 JS	394	ODM_RTL8192S = BIT(0),
	395	ODM_RTL8192C = BIT(1),
	396	ODM_RTL8192D = BIT(2),
	397	ODM_RTL8723A = BIT(3),
	398	ODM_RTL8188E = BIT(4),
	399	ODM_RTL8812 = BIT(5),
	400	ODM_RTL8821 = BIT(6),
364e30eb LF	401	};
364e30eb LF	402
364e30eb LF	403	/* ODM_CMNINFO_CUT_VER */
	404	enum odm_cut_version {
	405	ODM_CUT_A = 1,
	406	ODM_CUT_B = 2,
	407	ODM_CUT_C = 3,
	408	ODM_CUT_D = 4,
	409	ODM_CUT_E = 5,
	410	ODM_CUT_F = 6,
	411	ODM_CUT_TEST = 7,
	412	};
	413
	414	/* ODM_CMNINFO_FAB_VER */
	415	enum odm_fab_version {
	416	ODM_TSMC = 0,
	417	ODM_UMC = 1,
	418	};
	419
	420	/* ODM_CMNINFO_RF_TYPE */
	421	/* For example 1T2R (A+AB = BIT0\|BIT4\|BIT5) */
	422	enum rf_path_def {
93748447 JS	423	ODM_RF_TX_A = BIT(0),
	424	ODM_RF_TX_B = BIT(1),
	425	ODM_RF_TX_C = BIT(2),
	426	ODM_RF_TX_D = BIT(3),
	427	ODM_RF_RX_A = BIT(4),
	428	ODM_RF_RX_B = BIT(5),
	429	ODM_RF_RX_C = BIT(6),
	430	ODM_RF_RX_D = BIT(7),
364e30eb LF	431	};
	432
	433
	434	enum odm_rf_type {
	435	ODM_1T1R = 0,
	436	ODM_1T2R = 1,
	437	ODM_2T2R = 2,
	438	ODM_2T3R = 3,
	439	ODM_2T4R = 4,
	440	ODM_3T3R = 5,
	441	ODM_3T4R = 6,
	442	ODM_4T4R = 7,
	443	};
	444
	445	/* ODM Dynamic common info value definition */
	446
	447	enum odm_mac_phy_mode {
	448	ODM_SMSP = 0,
	449	ODM_DMSP = 1,
	450	ODM_DMDP = 2,
	451	};
	452
	453
	454	enum odm_bt_coexist {
	455	ODM_BT_BUSY = 1,
	456	ODM_BT_ON = 2,
	457	ODM_BT_OFF = 3,
	458	ODM_BT_NONE = 4,
	459	};
	460
	461	/* ODM_CMNINFO_OP_MODE */
	462	enum odm_operation_mode {
93748447 JS	463	ODM_NO_LINK = BIT(0),
	464	ODM_LINK = BIT(1),
	465	ODM_SCAN = BIT(2),
	466	ODM_POWERSAVE = BIT(3),
	467	ODM_AP_MODE = BIT(4),
	468	ODM_CLIENT_MODE = BIT(5),
	469	ODM_AD_HOC = BIT(6),
	470	ODM_WIFI_DIRECT = BIT(7),
	471	ODM_WIFI_DISPLAY = BIT(8),
364e30eb LF	472	};
	473
	474	/* ODM_CMNINFO_WM_MODE */
	475	enum odm_wireless_mode {
	476	ODM_WM_UNKNOW = 0x0,
93748447 JS	477	ODM_WM_B = BIT(0),
	478	ODM_WM_G = BIT(1),
	479	ODM_WM_A = BIT(2),
	480	ODM_WM_N24G = BIT(3),
	481	ODM_WM_N5G = BIT(4),
	482	ODM_WM_AUTO = BIT(5),
	483	ODM_WM_AC = BIT(6),
364e30eb LF	484	};
	485
	486	/* ODM_CMNINFO_BAND */
	487	enum odm_band_type {
93748447 JS	488	ODM_BAND_2_4G = BIT(0),
93748447 JS	489	ODM_BAND_5G = BIT(1),
364e30eb LF	490
	491	};
	492
	493	/* ODM_CMNINFO_SEC_CHNL_OFFSET */
	494	enum odm_sec_chnl_offset {
	495	ODM_DONT_CARE = 0,
	496	ODM_BELOW = 1,
	497	ODM_ABOVE = 2
	498	};
	499
364e30eb LF	500	/* ODM_CMNINFO_BW */
	501	enum odm_band_width {
	502	ODM_BW20M = 0,
	503	ODM_BW40M = 1,
	504	ODM_BW80M = 2,
	505	ODM_BW160M = 3,
	506	ODM_BW10M = 4,
	507	};
	508
	509	/* ODM_CMNINFO_CHNL */
	510
	511	/* ODM_CMNINFO_BOARD_TYPE */
	512	enum odm_board_type {
	513	ODM_BOARD_NORMAL = 0,
	514	ODM_BOARD_HIGHPWR = 1,
	515	ODM_BOARD_MINICARD = 2,
	516	ODM_BOARD_SLIM = 3,
	517	ODM_BOARD_COMBO = 4,
	518
	519	};
	520
	521	/* ODM_CMNINFO_ONE_PATH_CCA */
	522	enum odm_cca_path {
	523	ODM_CCA_2R = 0,
	524	ODM_CCA_1R_A = 1,
	525	ODM_CCA_1R_B = 2,
	526	};
	527
364e30eb LF	528	struct iqk_matrix_regs_set {
	529	bool bIQKDone;
	530	s32 Value[1][IQK_Matrix_REG_NUM];
	531	};
	532
	533	struct odm_rf_cal_t {
	534	/* for tx power tracking */
	535
	536	u32 RegA24; /* for TempCCK */
	537	s32 RegE94;
	538	s32 RegE9C;
	539	s32 RegEB4;
	540	s32 RegEBC;
	541
	542	/* u8 bTXPowerTracking; */
	543	u8 TXPowercount;
	544	bool bTXPowerTrackingInit;
	545	bool bTXPowerTracking;
	546	u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
	547	u8 TM_Trigger;
	548	u8 InternalPA5G[2]; /* pathA / pathB */
	549
	550	u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
	551	u8 ThermalValue;
	552	u8 ThermalValue_LCK;
	553	u8 ThermalValue_IQK;
	554	u8 ThermalValue_DPK;
	555	u8 ThermalValue_AVG[AVG_THERMAL_NUM];
	556	u8 ThermalValue_AVG_index;
	557	u8 ThermalValue_RxGain;
	558	u8 ThermalValue_Crystal;
	559	u8 ThermalValue_DPKstore;
	560	u8 ThermalValue_DPKtrack;
	561	bool TxPowerTrackingInProgress;
	562	bool bDPKenable;
	563
	564	bool bReloadtxpowerindex;
	565	u8 bRfPiEnable;
	566	u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
	567
	568	u8 bCCKinCH14;
	569	u8 CCK_index;
	570	u8 OFDM_index[2];
	571	bool bDoneTxpower;
	572
	573	u8 ThermalValue_HP[HP_THERMAL_NUM];
	574	u8 ThermalValue_HP_index;
	575	struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
	576
	577	u8 Delta_IQK;
	578	u8 Delta_LCK;
	579
	580	/* for IQK */
	581	u32 RegC04;
	582	u32 Reg874;
	583	u32 RegC08;
	584	u32 RegB68;
	585	u32 RegB6C;
	586	u32 Reg870;
	587	u32 Reg860;
	588	u32 Reg864;
	589
	590	bool bIQKInitialized;
	591	bool bLCKInProgress;
592	bool bAntennaDetected;
593	u32 ADDA_backup[IQK_ADDA_REG_NUM];
594	u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
595	u32 IQK_BB_backup_recover[9];
596	u32 IQK_BB_backup[IQK_BB_REG_NUM];
597
598	/* for APK */
599	u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
600	u8 bAPKdone;
601	u8 bAPKThermalMeterIgnore;
602	u8 bDPdone;
603	u8 bDPPathAOK;
604	u8 bDPPathBOK;
605	};
606
607	/* ODM Dynamic common info value definition */
608	struct odm_fat_t {
609	u8 Bssid[6];
610	u8 antsel_rx_keep_0;
611	u8 antsel_rx_keep_1;
612	u8 antsel_rx_keep_2;
613	u32 antSumRSSI[7];
614	u32 antRSSIcnt[7];
615	u32 antAveRSSI[7];
616	u8 FAT_State;
617	u32 TrainIdx;
618	u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
619	u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
620	u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
621	u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
622	u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
623	u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
624	u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
625	u8 RxIdleAnt;
626	bool bBecomeLinked;
627	};
628
629	enum fat_state {
630	FAT_NORMAL_STATE = 0,
631	FAT_TRAINING_STATE = 1,
632	};
633
634	enum ant_dif_type {
635	NO_ANTDIV = 0xFF,
636	CG_TRX_HW_ANTDIV = 0x01,
637	CGCS_RX_HW_ANTDIV = 0x02,
638	FIXED_HW_ANTDIV = 0x03,
639	CG_TRX_SMART_ANTDIV = 0x04,
640	CGCS_RX_SW_ANTDIV = 0x05,
641	};
642
643	/* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
644	struct dm_odm_t {
364e30eb LF	645	/* */
	646	/* Add for different team use temporarily */
	647	/* */
	648	struct rtw_adapter Adapter; / For CE/NIC team */
364e30eb LF	649
	650	u64 DebugComponents;
	651	u32 DebugLevel;
	652
	653	/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
	654	bool bCckHighPower;
	655	u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
	656	u8 ControlChannel;
	657	/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
	658
	659	/* 1 COMMON INFORMATION */
	660
	661	/* Init Value */
	662	/* HOOK BEFORE REG INIT----------- */