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staging: rts_pstor: use bitwise operator instead of logical one
[deliverable/linux.git] / drivers / staging / rts_pstor / sd.c
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77d89b08 1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/blkdev.h>
24#include <linux/kthread.h>
25#include <linux/sched.h>
26
27#include "rtsx.h"
28#include "rtsx_transport.h"
29#include "rtsx_scsi.h"
30#include "rtsx_card.h"
31#include "sd.h"
32
33#define SD_MAX_RETRY_COUNT 3
34
6680d2ca 35static u16 REG_SD_CFG1;
36static u16 REG_SD_CFG2;
37static u16 REG_SD_CFG3;
38static u16 REG_SD_STAT1;
39static u16 REG_SD_STAT2;
40static u16 REG_SD_BUS_STAT;
41static u16 REG_SD_PAD_CTL;
42static u16 REG_SD_SAMPLE_POINT_CTL;
43static u16 REG_SD_PUSH_POINT_CTL;
44static u16 REG_SD_CMD0;
45static u16 REG_SD_CMD1;
46static u16 REG_SD_CMD2;
47static u16 REG_SD_CMD3;
48static u16 REG_SD_CMD4;
49static u16 REG_SD_CMD5;
50static u16 REG_SD_BYTE_CNT_L;
51static u16 REG_SD_BYTE_CNT_H;
52static u16 REG_SD_BLOCK_CNT_L;
53static u16 REG_SD_BLOCK_CNT_H;
54static u16 REG_SD_TRANSFER;
55static u16 REG_SD_VPCLK0_CTL;
56static u16 REG_SD_VPCLK1_CTL;
57static u16 REG_SD_DCMPS0_CTL;
58static u16 REG_SD_DCMPS1_CTL;
77d89b08 59
60static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
61{
62 struct sd_info *sd_card = &(chip->sd_card);
63
64 sd_card->err_code |= err_code;
65}
66
67static inline void sd_clr_err_code(struct rtsx_chip *chip)
68{
69 struct sd_info *sd_card = &(chip->sd_card);
70
71 sd_card->err_code = 0;
72}
73
74static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
75{
76 struct sd_info *sd_card = &(chip->sd_card);
77
78 return sd_card->err_code & err_code;
79}
80
81static void sd_init_reg_addr(struct rtsx_chip *chip)
82{
83 if (CHECK_PID(chip, 0x5209)) {
84 REG_SD_CFG1 = SD_CFG1;
85 REG_SD_CFG2 = SD_CFG2;
86 REG_SD_CFG3 = SD_CFG3;
87 REG_SD_STAT1 = SD_STAT1;
88 REG_SD_STAT2 = SD_STAT2;
89 REG_SD_BUS_STAT = SD_BUS_STAT;
90 REG_SD_PAD_CTL = SD_PAD_CTL;
91 REG_SD_SAMPLE_POINT_CTL = SD_SAMPLE_POINT_CTL;
92 REG_SD_PUSH_POINT_CTL = SD_PUSH_POINT_CTL;
93 REG_SD_CMD0 = SD_CMD0;
94 REG_SD_CMD1 = SD_CMD1;
95 REG_SD_CMD2 = SD_CMD2;
96 REG_SD_CMD3 = SD_CMD3;
97 REG_SD_CMD4 = SD_CMD4;
98 REG_SD_CMD5 = SD_CMD5;
99 REG_SD_BYTE_CNT_L = SD_BYTE_CNT_L;
100 REG_SD_BYTE_CNT_H = SD_BYTE_CNT_H;
101 REG_SD_BLOCK_CNT_L = SD_BLOCK_CNT_L;
102 REG_SD_BLOCK_CNT_H = SD_BLOCK_CNT_H;
103 REG_SD_TRANSFER = SD_TRANSFER;
104 REG_SD_VPCLK0_CTL = SD_VPCLK0_CTL;
105 REG_SD_VPCLK1_CTL = SD_VPCLK1_CTL;
106 REG_SD_DCMPS0_CTL = SD_DCMPS0_CTL;
107 REG_SD_DCMPS1_CTL = SD_DCMPS1_CTL;
108 } else {
109 REG_SD_CFG1 = 0xFD31;
110 REG_SD_CFG2 = 0xFD33;
111 REG_SD_CFG3 = 0xFD3E;
112 REG_SD_STAT1 = 0xFD30;
113 REG_SD_STAT2 = 0;
114 REG_SD_BUS_STAT = 0;
115 REG_SD_PAD_CTL = 0;
116 REG_SD_SAMPLE_POINT_CTL = 0;
117 REG_SD_PUSH_POINT_CTL = 0;
118 REG_SD_CMD0 = 0xFD34;
119 REG_SD_CMD1 = 0xFD35;
120 REG_SD_CMD2 = 0xFD36;
121 REG_SD_CMD3 = 0xFD37;
122 REG_SD_CMD4 = 0xFD38;
123 REG_SD_CMD5 = 0xFD5A;
124 REG_SD_BYTE_CNT_L = 0xFD39;
125 REG_SD_BYTE_CNT_H = 0xFD3A;
126 REG_SD_BLOCK_CNT_L = 0xFD3B;
127 REG_SD_BLOCK_CNT_H = 0xFD3C;
128 REG_SD_TRANSFER = 0xFD32;
129 REG_SD_VPCLK0_CTL = 0;
130 REG_SD_VPCLK1_CTL = 0;
131 REG_SD_DCMPS0_CTL = 0;
132 REG_SD_DCMPS1_CTL = 0;
133 }
134}
135
136static int sd_check_data0_status(struct rtsx_chip *chip)
137{
138 u8 stat;
139
140 if (CHECK_PID(chip, 0x5209)) {
141 RTSX_READ_REG(chip, REG_SD_BUS_STAT, &stat);
142 } else {
143 RTSX_READ_REG(chip, REG_SD_STAT1, &stat);
144 }
145
146 if (!(stat & SD_DAT0_STATUS)) {
147 sd_set_err_code(chip, SD_BUSY);
148 TRACE_RET(chip, STATUS_FAIL);
149 }
150
151 return STATUS_SUCCESS;
152}
153
154static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
155 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
156{
157 struct sd_info *sd_card = &(chip->sd_card);
158 int retval;
159 int timeout = 100;
160 u16 reg_addr;
161 u8 *ptr;
162 int stat_idx = 0;
163 int rty_cnt = 0;
164
165 sd_clr_err_code(chip);
166
167 RTSX_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
168
169 if (rsp_type == SD_RSP_TYPE_R1b)
170 timeout = 3000;
171
172RTY_SEND_CMD:
173
174 rtsx_init_cmd(chip);
175
176 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
177 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
178 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
179 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
180 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
181
182 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
183 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
184 0x01, PINGPONG_BUFFER);
185 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
186 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
187 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
188 SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
189
190 if (rsp_type == SD_RSP_TYPE_R2) {
191 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
192 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
193 }
194 stat_idx = 16;
195 } else if (rsp_type != SD_RSP_TYPE_R0) {
196 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
197 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
198 }
199 stat_idx = 5;
200 }
201
202 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
203
204 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
205 if (retval < 0) {
206 u8 val;
207
208 rtsx_read_register(chip, REG_SD_STAT1, &val);
209 RTSX_DEBUGP("SD_STAT1: 0x%x\n", val);
210
211 if (CHECK_PID(chip, 0x5209)) {
212 rtsx_read_register(chip, REG_SD_STAT2, &val);
213 RTSX_DEBUGP("SD_STAT2: 0x%x\n", val);
214
215 if (val & SD_RSP_80CLK_TIMEOUT) {
216 rtsx_clear_sd_error(chip);
217 sd_set_err_code(chip, SD_RSP_TIMEOUT);
218 TRACE_RET(chip, STATUS_FAIL);
219 }
220
221 rtsx_read_register(chip, REG_SD_BUS_STAT, &val);
222 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
223 } else {
224 rtsx_read_register(chip, REG_SD_CFG3, &val);
225 RTSX_DEBUGP("SD_CFG3: 0x%x\n", val);
226 }
227
228 if (retval == -ETIMEDOUT) {
229 if (rsp_type & SD_WAIT_BUSY_END) {
230 retval = sd_check_data0_status(chip);
231 if (retval != STATUS_SUCCESS) {
232 rtsx_clear_sd_error(chip);
233 TRACE_RET(chip, retval);
234 }
235 } else {
236 sd_set_err_code(chip, SD_TO_ERR);
237 }
238 retval = STATUS_TIMEDOUT;
239 } else {
240 retval = STATUS_FAIL;
241 }
242 rtsx_clear_sd_error(chip);
243
244 TRACE_RET(chip, retval);
245 }
246
247 if (rsp_type == SD_RSP_TYPE_R0)
248 return STATUS_SUCCESS;
249
250 ptr = rtsx_get_cmd_data(chip) + 1;
251
252 if ((ptr[0] & 0xC0) != 0) {
253 sd_set_err_code(chip, SD_STS_ERR);
254 TRACE_RET(chip, STATUS_FAIL);
255 }
256
257 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
258 if (ptr[stat_idx] & SD_CRC7_ERR) {
259 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
260 sd_set_err_code(chip, SD_CRC_ERR);
261 TRACE_RET(chip, STATUS_FAIL);
262 }
263 if (rty_cnt < SD_MAX_RETRY_COUNT) {
264 wait_timeout(20);
265 rty_cnt++;
266 goto RTY_SEND_CMD;
267 } else {
268 sd_set_err_code(chip, SD_CRC_ERR);
269 TRACE_RET(chip, STATUS_FAIL);
270 }
271 }
272 }
273
274 if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
275 if ((cmd_idx != SEND_RELATIVE_ADDR) && (cmd_idx != SEND_IF_COND)) {
276 if (cmd_idx != STOP_TRANSMISSION) {
277 if (ptr[1] & 0x80) {
278 TRACE_RET(chip, STATUS_FAIL);
279 }
280 }
281#ifdef SUPPORT_SD_LOCK
282 if (ptr[1] & 0x7D)
283#else
284 if (ptr[1] & 0x7F)
285#endif
286 {
287 RTSX_DEBUGP("ptr[1]: 0x%02x\n", ptr[1]);
288 TRACE_RET(chip, STATUS_FAIL);
289 }
290 if (ptr[2] & 0xFF) {
291 RTSX_DEBUGP("ptr[2]: 0x%02x\n", ptr[2]);
292 TRACE_RET(chip, STATUS_FAIL);
293 }
294 if (ptr[3] & 0x80) {
295 RTSX_DEBUGP("ptr[3]: 0x%02x\n", ptr[3]);
296 TRACE_RET(chip, STATUS_FAIL);
297 }
298 if (ptr[3] & 0x01) {
299 sd_card->sd_data_buf_ready = 1;
300 } else {
301 sd_card->sd_data_buf_ready = 0;
302 }
303 }
304 }
305
306 if (rsp && rsp_len)
307 memcpy(rsp, ptr, rsp_len);
308
309 return STATUS_SUCCESS;
310}
311
312static int sd_read_data(struct rtsx_chip *chip,
313 u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
314 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
315 int timeout)
316{
317 struct sd_info *sd_card = &(chip->sd_card);
318 int retval;
319 int i;
320
321 sd_clr_err_code(chip);
322
323 if (!buf)
324 buf_len = 0;
325
326 if (buf_len > 512) {
327 TRACE_RET(chip, STATUS_FAIL);
328 }
329
330 rtsx_init_cmd(chip);
331
332 if (cmd_len) {
333 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
334 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
335 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 0xFF, cmd[i]);
336 }
337 }
338 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
339 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
340 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
341 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
342
343 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
344
345 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
346 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
347 SD_CHECK_CRC7 | SD_RSP_LEN_6);
348 if (trans_mode != SD_TM_AUTO_TUNING) {
349 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
350 }
351 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
352 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
353
354 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
355 if (retval < 0) {
356 if (retval == -ETIMEDOUT) {
357 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
358 SD_RSP_TYPE_R1, NULL, 0);
359 }
360
361 TRACE_RET(chip, STATUS_FAIL);
362 }
363
364 if (buf && buf_len) {
365 retval = rtsx_read_ppbuf(chip, buf, buf_len);
366 if (retval != STATUS_SUCCESS) {
367 TRACE_RET(chip, STATUS_FAIL);
368 }
369 }
370
371 return STATUS_SUCCESS;
372}
373
374static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
375 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
376 u8 *buf, int buf_len, int timeout)
377{
378 struct sd_info *sd_card = &(chip->sd_card);
379 int retval;
380 int i;
381
382 sd_clr_err_code(chip);
383
384 if (!buf)
385 buf_len = 0;
386
387 if (buf_len > 512) {
388 /* This function can't write data more than one page */
389 TRACE_RET(chip, STATUS_FAIL);
390 }
391
392 if (buf && buf_len) {
393 retval = rtsx_write_ppbuf(chip, buf, buf_len);
394 if (retval != STATUS_SUCCESS) {
395 TRACE_RET(chip, STATUS_FAIL);
396 }
397 }
398
399 rtsx_init_cmd(chip);
400
401 if (cmd_len) {
402 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
403 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
404 rtsx_add_cmd(chip, WRITE_REG_CMD,
405 REG_SD_CMD0 + i, 0xFF, cmd[i]);
406 }
407 }
408 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
409 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
410 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
411 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
412
413 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
414
415 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
416 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
417 SD_CHECK_CRC7 | SD_RSP_LEN_6);
418
419 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
420 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
421
422 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
423 if (retval < 0) {
424 if (retval == -ETIMEDOUT) {
425 sd_send_cmd_get_rsp(chip, SEND_STATUS,
426 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
427 }
428
429 TRACE_RET(chip, STATUS_FAIL);
430 }
431
432 return STATUS_SUCCESS;
433}
434
435static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
436{
437 struct sd_info *sd_card = &(chip->sd_card);
438 int retval;
439 int i;
440 u8 csd_ver, trans_speed;
441 u8 rsp[16];
442
443 for (i = 0; i < 6; i++) {
444 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
445 sd_set_err_code(chip, SD_NO_CARD);
446 TRACE_RET(chip, STATUS_FAIL);
447 }
448
449 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, SD_RSP_TYPE_R2, rsp, 16);
450 if (retval == STATUS_SUCCESS)
451 break;
452 }
453
454 if (i == 6) {
455 TRACE_RET(chip, STATUS_FAIL);
456 }
457
458 memcpy(sd_card->raw_csd, rsp + 1, 15);
459
460 if (CHECK_PID(chip, 0x5209)) {
461 RTSX_READ_REG(chip, REG_SD_CMD5, sd_card->raw_csd + 15);
462 }
463
464 RTSX_DEBUGP("CSD Response:\n");
465 RTSX_DUMP(sd_card->raw_csd, 16);
466
467 csd_ver = (rsp[1] & 0xc0) >> 6;
468 RTSX_DEBUGP("csd_ver = %d\n", csd_ver);
469
470 trans_speed = rsp[4];
471 if ((trans_speed & 0x07) == 0x02) {
472 if ((trans_speed & 0xf8) >= 0x30) {
473 if (chip->asic_code) {
474 sd_card->sd_clock = 47;
475 } else {
476 sd_card->sd_clock = CLK_50;
477 }
478 } else if ((trans_speed & 0xf8) == 0x28) {
479 if (chip->asic_code) {
480 sd_card->sd_clock = 39;
481 } else {
482 sd_card->sd_clock = CLK_40;
483 }
484 } else if ((trans_speed & 0xf8) == 0x20) {
485 if (chip->asic_code) {
486 sd_card->sd_clock = 29;
487 } else {
488 sd_card->sd_clock = CLK_30;
489 }
490 } else if ((trans_speed & 0xf8) >= 0x10) {
491 if (chip->asic_code) {
492 sd_card->sd_clock = 23;
493 } else {
494 sd_card->sd_clock = CLK_20;
495 }
496 } else if ((trans_speed & 0x08) >= 0x08) {
497 if (chip->asic_code) {
498 sd_card->sd_clock = 19;
499 } else {
500 sd_card->sd_clock = CLK_20;
501 }
502 } else {
503 TRACE_RET(chip, STATUS_FAIL);
504 }
505 } else {
506 TRACE_RET(chip, STATUS_FAIL);
507 }
508
509 if (CHK_MMC_SECTOR_MODE(sd_card)) {
510 sd_card->capacity = 0;
511 } else {
512 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
513 u8 blk_size, c_size_mult;
514 u16 c_size;
515 blk_size = rsp[6] & 0x0F;
516 c_size = ((u16)(rsp[7] & 0x03) << 10)
517 + ((u16)rsp[8] << 2)
518 + ((u16)(rsp[9] & 0xC0) >> 6);
519 c_size_mult = (u8)((rsp[10] & 0x03) << 1);
520 c_size_mult += (rsp[11] & 0x80) >> 7;
521 sd_card->capacity = (((u32)(c_size + 1)) * (1 << (c_size_mult + 2))) << (blk_size - 9);
522 } else {
523 u32 total_sector = 0;
524 total_sector = (((u32)rsp[8] & 0x3f) << 16) |
525 ((u32)rsp[9] << 8) | (u32)rsp[10];
526 sd_card->capacity = (total_sector + 1) << 10;
527 }
528 }
529
530 if (check_wp) {
531 if (rsp[15] & 0x30) {
532 chip->card_wp |= SD_CARD;
533 }
534 RTSX_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]);
535 }
536
537 return STATUS_SUCCESS;
538}
539
540static int sd_set_sample_push_timing(struct rtsx_chip *chip)
541{
542 struct sd_info *sd_card = &(chip->sd_card);
543
544 if (CHECK_PID(chip, 0x5209)) {
545 if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
546 RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
547 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
548 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
549 RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
550 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
551 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
552 } else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
553 RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
554 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
555 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
556 RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
557 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
558 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
559 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, DDR_VAR_TX_CMD_DAT,
560 DDR_VAR_TX_CMD_DAT);
561 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
562 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
563 } else {
564 u8 val = 0;
565
566 RTSX_WRITE_REG(chip, SD_CFG1, 0x0C, SD_20_MODE);
567 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
568 RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
569 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
570 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
571
572 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_AUTO) {
573 val = SD20_TX_NEG_EDGE;
574 } else if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) {
575 val = SD20_TX_14_AHEAD;
576 } else {
577 val = SD20_TX_NEG_EDGE;
578 }
579 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, SD20_TX_SEL_MASK, val);
580
581 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
582 if (chip->asic_code) {
583 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
584 val = SD20_RX_14_DELAY;
585 } else {
586 val = SD20_RX_POS_EDGE;
587 }
588 } else {
589 val = SD20_RX_14_DELAY;
590 }
591 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
592 val = SD20_RX_14_DELAY;
593 } else {
594 val = SD20_RX_POS_EDGE;
595 }
596 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, SD20_RX_SEL_MASK, val);
597 }
598 } else {
599 u8 val = 0;
600
601 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) {
602 val |= 0x10;
603 }
604
605 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
606 if (chip->asic_code) {
607 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
608 if (val & 0x10) {
609 val |= 0x04;
610 } else {
611 val |= 0x08;
612 }
613 }
614 } else {
615 if (val & 0x10) {
616 val |= 0x04;
617 } else {
618 val |= 0x08;
619 }
620 }
621 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
622 if (val & 0x10) {
623 val |= 0x04;
624 } else {
625 val |= 0x08;
626 }
627 }
628
629 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val);
630 }
631
632 return STATUS_SUCCESS;
633}
634
635static void sd_choose_proper_clock(struct rtsx_chip *chip)
636{
637 struct sd_info *sd_card = &(chip->sd_card);
638
639 if (CHK_SD_SDR104(sd_card)) {
640 if (chip->asic_code) {
641 sd_card->sd_clock = chip->asic_sd_sdr104_clk;
642 } else {
643 sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
644 }
645 } else if (CHK_SD_DDR50(sd_card)) {
646 if (chip->asic_code) {
647 sd_card->sd_clock = chip->asic_sd_ddr50_clk;
648 } else {
649 sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
650 }
651 } else if (CHK_SD_SDR50(sd_card)) {
652 if (chip->asic_code) {
653 sd_card->sd_clock = chip->asic_sd_sdr50_clk;
654 } else {
655 sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
656 }
657 } else if (CHK_SD_HS(sd_card)) {
658 if (chip->asic_code) {
659 sd_card->sd_clock = chip->asic_sd_hs_clk;
660 } else {
661 sd_card->sd_clock = chip->fpga_sd_hs_clk;
662 }
663 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
664 if (chip->asic_code) {
665 sd_card->sd_clock = chip->asic_mmc_52m_clk;
666 } else {
667 sd_card->sd_clock = chip->fpga_mmc_52m_clk;
668 }
669 } else if (CHK_MMC_26M(sd_card)) {
670 if (chip->asic_code) {
671 sd_card->sd_clock = 48;
672 } else {
673 sd_card->sd_clock = CLK_50;
674 }
675 }
676}
677
678static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
679{
680 u8 mask = 0, val = 0;
681
682 if (CHECK_PID(chip, 0x5209)) {
683 mask = SD_CLK_DIVIDE_MASK;
684 val = clk_div;
685 } else {
686 mask = 0x60;
687 if (clk_div == SD_CLK_DIVIDE_0) {
688 val = 0x00;
689 } else if (clk_div == SD_CLK_DIVIDE_128) {
690 val = 0x40;
691 } else if (clk_div == SD_CLK_DIVIDE_256) {
692 val = 0x20;
693 }
694 }
695
696 RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val);
697
698 return STATUS_SUCCESS;
699}
700
701static int sd_set_init_para(struct rtsx_chip *chip)
702{
703 struct sd_info *sd_card = &(chip->sd_card);
704 int retval;
705
706 retval = sd_set_sample_push_timing(chip);
707 if (retval != STATUS_SUCCESS) {
708 TRACE_RET(chip, STATUS_FAIL);
709 }
710
711 sd_choose_proper_clock(chip);
712
713 retval = switch_clock(chip, sd_card->sd_clock);
714 if (retval != STATUS_SUCCESS) {
715 TRACE_RET(chip, STATUS_FAIL);
716 }
717
718 return STATUS_SUCCESS;
719}
720
721int sd_select_card(struct rtsx_chip *chip, int select)
722{
723 struct sd_info *sd_card = &(chip->sd_card);
724 int retval;
725 u8 cmd_idx, cmd_type;
726 u32 addr;
727
728 if (select) {
729 cmd_idx = SELECT_CARD;
730 cmd_type = SD_RSP_TYPE_R1;
731 addr = sd_card->sd_addr;
732 } else {
733 cmd_idx = DESELECT_CARD;
734 cmd_type = SD_RSP_TYPE_R0;
735 addr = 0;
736 }
737
738 retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
739 if (retval != STATUS_SUCCESS) {
740 TRACE_RET(chip, STATUS_FAIL);
741 }
742
743 return STATUS_SUCCESS;
744}
745
746#ifdef SUPPORT_SD_LOCK
747static int sd_update_lock_status(struct rtsx_chip *chip)
748{
749 struct sd_info *sd_card = &(chip->sd_card);
750 int retval;
751 u8 rsp[5];
752
753 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
754 if (retval != STATUS_SUCCESS) {
755 TRACE_RET(chip, STATUS_FAIL);
756 }
757
758 if (rsp[1] & 0x02) {
759 sd_card->sd_lock_status |= SD_LOCKED;
760 } else {
761 sd_card->sd_lock_status &= ~SD_LOCKED;
762 }
763
764 RTSX_DEBUGP("sd_card->sd_lock_status = 0x%x\n", sd_card->sd_lock_status);
765
766 if (rsp[1] & 0x01) {
767 TRACE_RET(chip, STATUS_FAIL);
768 }
769
770 return STATUS_SUCCESS;
771}
772#endif
773
774static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, u8 data_ready, int polling_cnt)
775{
776 struct sd_info *sd_card = &(chip->sd_card);
777 int retval, i;
778 u8 rsp[5];
779
780 for (i = 0; i < polling_cnt; i++) {
781 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
782 sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
783 if (retval != STATUS_SUCCESS) {
784 TRACE_RET(chip, STATUS_FAIL);
785 }
786
787 if (((rsp[3] & 0x1E) == state) && ((rsp[3] & 0x01) == data_ready)) {
788 return STATUS_SUCCESS;
789 }
790 }
791
792 TRACE_RET(chip, STATUS_FAIL);
793}
794
795static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
796{
797 int retval;
798
799 if (voltage == SD_IO_3V3) {
800 if (chip->asic_code) {
801 retval = rtsx_write_phy_register(chip, 0x08, 0x4FC0 | chip->phy_voltage);
802 if (retval != STATUS_SUCCESS) {
803 TRACE_RET(chip, STATUS_FAIL);
804 }
805 } else {
806 RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
807 }
808 } else if (voltage == SD_IO_1V8) {
809 if (chip->asic_code) {
810 retval = rtsx_write_phy_register(chip, 0x08, 0x4C40 | chip->phy_voltage);
811 if (retval != STATUS_SUCCESS) {
812 TRACE_RET(chip, STATUS_FAIL);
813 }
814 } else {
815 RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, SD_IO_USING_1V8);
816 }
817 } else {
818 TRACE_RET(chip, STATUS_FAIL);
819 }
820
821 return STATUS_SUCCESS;
822}
823
824static int sd_voltage_switch(struct rtsx_chip *chip)
825{
826 int retval;
827 u8 stat;
828
829 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, SD_CLK_TOGGLE_EN);
830
831 retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL, 0);
832 if (retval != STATUS_SUCCESS) {
833 TRACE_RET(chip, STATUS_FAIL);
834 }
835
836 udelay(chip->sd_voltage_switch_delay);
837
838 RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
839 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
840 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
841 TRACE_RET(chip, STATUS_FAIL);
842 }
843
844 RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP);
845 retval = sd_change_bank_voltage(chip, SD_IO_1V8);
846 if (retval != STATUS_SUCCESS) {
847 TRACE_RET(chip, STATUS_FAIL);
848 }
849 wait_timeout(50);
850
851 RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
852 wait_timeout(10);
853
854 RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
855 if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
856 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
857 (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
858 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
859 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", stat);
860 rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
861 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
862 TRACE_RET(chip, STATUS_FAIL);
863 }
864
865 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
866
867 return STATUS_SUCCESS;
868}
869
870static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
871{
872 if (tune_dir == TUNE_RX) {
873 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX);
874 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
875 } else {
876 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX);
877 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
878 }
879
880 return STATUS_SUCCESS;
881}
882
883static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
884{
885 struct sd_info *sd_card = &(chip->sd_card);
886 u16 SD_VP_CTL, SD_DCMPS_CTL;
887 u8 val;
888 int retval;
889 int ddr_rx = 0;
890
891 RTSX_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
892 sample_point, tune_dir);
893
894 if (tune_dir == TUNE_RX) {
895 SD_VP_CTL = SD_VPRX_CTL;
896 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
897 if (CHK_SD_DDR50(sd_card)) {
898 ddr_rx = 1;
899 }
900 } else {
901 SD_VP_CTL = SD_VPTX_CTL;
902 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
903 }
904
905 if (chip->asic_code) {
906 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
907 RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
908 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
909 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
910 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
911 } else {
1035117d 912#ifdef CONFIG_RTS_PSTOR_DEBUG
77d89b08 913 rtsx_read_register(chip, SD_VP_CTL, &val);
914 RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
915 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
916 RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
917#endif
918
919 if (ddr_rx) {
920 RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, PHASE_CHANGE);
921 udelay(50);
922 RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
923 PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
924 } else {
925 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
926 udelay(50);
927 RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
928 PHASE_NOT_RESET | sample_point);
929 }
930 udelay(100);
931
932 rtsx_init_cmd(chip);
933 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, DCMPS_CHANGE);
934 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
935 retval = rtsx_send_cmd(chip, SD_CARD, 100);
936 if (retval != STATUS_SUCCESS) {
937 TRACE_GOTO(chip, Fail);
938 }
939
940 val = *rtsx_get_cmd_data(chip);
941 if (val & DCMPS_ERROR) {
942 TRACE_GOTO(chip, Fail);
943 }
944 if ((val & DCMPS_CURRENT_PHASE) != sample_point) {
945 TRACE_GOTO(chip, Fail);
946 }
947 RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
948 if (ddr_rx) {
949 RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
950 } else {
951 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
952 }
953 udelay(50);
954 }
955
956 RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
957
958 return STATUS_SUCCESS;
959
960Fail:
1035117d 961#ifdef CONFIG_RTS_PSTOR_DEBUG
77d89b08 962 rtsx_read_register(chip, SD_VP_CTL, &val);
963 RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
964 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
965 RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
966#endif
967
968 rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
969 rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
970 wait_timeout(10);
971 sd_reset_dcm(chip, tune_dir);
972 return STATUS_FAIL;
973}
974
975static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
976{
977 struct sd_info *sd_card = &(chip->sd_card);
978 int retval;
979 u8 cmd[5], buf[8];
980
981 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
982 if (retval != STATUS_SUCCESS) {
983 TRACE_RET(chip, STATUS_FAIL);
984 }
985
986 cmd[0] = 0x40 | SEND_SCR;
987 cmd[1] = 0;
988 cmd[2] = 0;
989 cmd[3] = 0;
990 cmd[4] = 0;
991
992 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf, 8, 250);
993 if (retval != STATUS_SUCCESS) {
994 rtsx_clear_sd_error(chip);
995 TRACE_RET(chip, STATUS_FAIL);
996 }
997
998 memcpy(sd_card->raw_scr, buf, 8);
999
1000 if ((buf[0] & 0x0F) == 0) {
1001 TRACE_RET(chip, STATUS_FAIL);
1002 }
1003
1004 return STATUS_SUCCESS;
1005}
1006
1007static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, u8 func_to_switch,
1008 u8 *buf, int buf_len)
1009{
1010 u8 support_mask = 0, query_switch = 0, switch_busy = 0;
1011 int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
1012
1013 if (func_group == SD_FUNC_GROUP_1) {
1014 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
1015 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
1016 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
1017
1018 switch (func_to_switch) {
1019 case HS_SUPPORT:
1020 support_mask = HS_SUPPORT_MASK;
1021 query_switch = HS_QUERY_SWITCH_OK;
1022 switch_busy = HS_SWITCH_BUSY;
1023 break;
1024
1025 case SDR50_SUPPORT:
1026 support_mask = SDR50_SUPPORT_MASK;
1027 query_switch = SDR50_QUERY_SWITCH_OK;
1028 switch_busy = SDR50_SWITCH_BUSY;
1029 break;
1030
1031 case SDR104_SUPPORT:
1032 support_mask = SDR104_SUPPORT_MASK;
1033 query_switch = SDR104_QUERY_SWITCH_OK;
1034 switch_busy = SDR104_SWITCH_BUSY;
1035 break;
1036
1037 case DDR50_SUPPORT:
1038 support_mask = DDR50_SUPPORT_MASK;
1039 query_switch = DDR50_QUERY_SWITCH_OK;
1040 switch_busy = DDR50_SWITCH_BUSY;
1041 break;
1042
1043 default:
1044 TRACE_RET(chip, STATUS_FAIL);
1045 }
1046 } else if (func_group == SD_FUNC_GROUP_3) {
1047 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1048 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1049 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1050
1051 switch (func_to_switch) {
1052 case DRIVING_TYPE_A:
1053 support_mask = DRIVING_TYPE_A_MASK;
1054 query_switch = TYPE_A_QUERY_SWITCH_OK;
1055 switch_busy = TYPE_A_SWITCH_BUSY;
1056 break;
1057
1058 case DRIVING_TYPE_C:
1059 support_mask = DRIVING_TYPE_C_MASK;
1060 query_switch = TYPE_C_QUERY_SWITCH_OK;
1061 switch_busy = TYPE_C_SWITCH_BUSY;
1062 break;
1063
1064 case DRIVING_TYPE_D:
1065 support_mask = DRIVING_TYPE_D_MASK;
1066 query_switch = TYPE_D_QUERY_SWITCH_OK;
1067 switch_busy = TYPE_D_SWITCH_BUSY;
1068 break;
1069
1070 default:
1071 TRACE_RET(chip, STATUS_FAIL);
1072 }
1073 } else if (func_group == SD_FUNC_GROUP_4) {
1074 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1075 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1076 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1077
1078 switch (func_to_switch) {
1079 case CURRENT_LIMIT_400:
1080 support_mask = CURRENT_LIMIT_400_MASK;
1081 query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1082 switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1083 break;
1084
1085 case CURRENT_LIMIT_600:
1086 support_mask = CURRENT_LIMIT_600_MASK;
1087 query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1088 switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1089 break;
1090
1091 case CURRENT_LIMIT_800:
1092 support_mask = CURRENT_LIMIT_800_MASK;
1093 query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1094 switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1095 break;
1096
1097 default:
1098 TRACE_RET(chip, STATUS_FAIL);
1099 }
1100 } else {
1101 TRACE_RET(chip, STATUS_FAIL);
1102 }
1103
1104 if (func_group == SD_FUNC_GROUP_1) {
1105 if (!(buf[support_offset] & support_mask) ||
1106 ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1107 TRACE_RET(chip, STATUS_FAIL);
1108 }
1109 }
1110
1111 /* Check 'Busy Status' */
1112 if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1113 ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1114 TRACE_RET(chip, STATUS_FAIL);
1115 }
1116
1117 return STATUS_SUCCESS;
1118}
1119
1120static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode,
1121 u8 func_group, u8 func_to_switch, u8 bus_width)
1122{
1123 struct sd_info *sd_card = &(chip->sd_card);
1124 int retval;
1125 u8 cmd[5], buf[64];
1126
1127 RTSX_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1128 mode, func_group, func_to_switch);
1129
1130 cmd[0] = 0x40 | SWITCH;
1131 cmd[1] = mode;
1132
1133 if (func_group == SD_FUNC_GROUP_1) {
1134 cmd[2] = 0xFF;
1135 cmd[3] = 0xFF;
1136 cmd[4] = 0xF0 + func_to_switch;
1137 } else if (func_group == SD_FUNC_GROUP_3) {
1138 cmd[2] = 0xFF;
1139 cmd[3] = 0xF0 + func_to_switch;
1140 cmd[4] = 0xFF;
1141 } else if (func_group == SD_FUNC_GROUP_4) {
1142 cmd[2] = 0xFF;
1143 cmd[3] = 0x0F + (func_to_switch << 4);
1144 cmd[4] = 0xFF;
1145 } else {
1146 cmd[1] = SD_CHECK_MODE;
1147 cmd[2] = 0xFF;
1148 cmd[3] = 0xFF;
1149 cmd[4] = 0xFF;
1150 }
1151
1152 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, buf, 64, 250);
1153 if (retval != STATUS_SUCCESS) {
1154 rtsx_clear_sd_error(chip);
1155 TRACE_RET(chip, STATUS_FAIL);
1156 }
1157
1158 RTSX_DUMP(buf, 64);
1159
1160 if (func_group == NO_ARGUMENT) {
1161 sd_card->func_group1_mask = buf[0x0D];
1162 sd_card->func_group2_mask = buf[0x0B];
1163 sd_card->func_group3_mask = buf[0x09];
1164 sd_card->func_group4_mask = buf[0x07];
1165
1166 RTSX_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]);
1167 RTSX_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]);
1168 RTSX_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]);
1169 RTSX_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]);
1170 } else {
1171 /* Maximum current consumption, check whether current is acceptable;
1172 * bit[511:496] = 0x0000 means some error happaned.
1173 */
1174 u16 cc = ((u16)buf[0] << 8) | buf[1];
1175 RTSX_DEBUGP("Maximum current consumption: %dmA\n", cc);
1176 if ((cc == 0) || (cc > 800)) {
1177 TRACE_RET(chip, STATUS_FAIL);
1178 }
1179 retval = sd_query_switch_result(chip, func_group, func_to_switch, buf, 64);
1180 if (retval != STATUS_SUCCESS) {
1181 TRACE_RET(chip, STATUS_FAIL);
1182 }
1183
1184 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1185 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_800mA_ocp_thd);
1186 RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK, PMOS_STRG_800mA);
1187 }
1188 }
1189
1190 return STATUS_SUCCESS;
1191}
1192
1193static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1194{
1195 if (func_group == SD_FUNC_GROUP_1) {
1196 if (func_to_switch > HS_SUPPORT) {
1197 func_to_switch--;
1198 }
1199 } else if (func_group == SD_FUNC_GROUP_4) {
1200 if (func_to_switch > CURRENT_LIMIT_200) {
1201 func_to_switch--;
1202 }
1203 }
1204
1205 return func_to_switch;
1206}
1207
1208static int sd_check_switch(struct rtsx_chip *chip,
1209 u8 func_group, u8 func_to_switch, u8 bus_width)
1210{
1211 int retval;
1212 int i;
1213 int switch_good = 0;
1214
1215 for (i = 0; i < 3; i++) {
1216 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1217 sd_set_err_code(chip, SD_NO_CARD);
1218 TRACE_RET(chip, STATUS_FAIL);
1219 }
1220
1221 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1222 func_to_switch, bus_width);
1223 if (retval == STATUS_SUCCESS) {
1224 u8 stat;
1225
1226 retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1227 func_group, func_to_switch, bus_width);
1228 if (retval == STATUS_SUCCESS) {
1229 switch_good = 1;
1230 break;
1231 }
1232
1233 RTSX_READ_REG(chip, SD_STAT1, &stat);
1234 if (stat & SD_CRC16_ERR) {
1235 RTSX_DEBUGP("SD CRC16 error when switching mode\n");
1236 TRACE_RET(chip, STATUS_FAIL);
1237 }
1238 }
1239
1240 func_to_switch = downgrade_switch_mode(func_group, func_to_switch);
1241
1242 wait_timeout(20);
1243 }
1244
1245 if (!switch_good) {
1246 TRACE_RET(chip, STATUS_FAIL);
1247 }
1248
1249 return STATUS_SUCCESS;
1250}
1251
1252static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1253{
1254 struct sd_info *sd_card = &(chip->sd_card);
1255 int retval;
1256 int i;
1257 u8 func_to_switch = 0;
1258
1259 /* Get supported functions */
1260 retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1261 NO_ARGUMENT, NO_ARGUMENT, bus_width);
1262 if (retval != STATUS_SUCCESS) {
1263 TRACE_RET(chip, STATUS_FAIL);
1264 }
1265
1266 sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1267
2d2322b2 1268 /* Function Group 1: Access Mode */
77d89b08 1269 for (i = 0; i < 4; i++) {
1270 switch ((u8)(chip->sd_speed_prior >> (i*8))) {
1271 case SDR104_SUPPORT:
1272 if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK)
1273 && chip->sdr104_en) {
1274 func_to_switch = SDR104_SUPPORT;
1275 }
1276 break;
1277
1278 case DDR50_SUPPORT:
1279 if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1280 && chip->ddr50_en) {
1281 func_to_switch = DDR50_SUPPORT;
1282 }
1283 break;
1284
1285 case SDR50_SUPPORT:
1286 if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1287 && chip->sdr50_en) {
1288 func_to_switch = SDR50_SUPPORT;
1289 }
1290 break;
1291
1292 case HS_SUPPORT:
1293 if (sd_card->func_group1_mask & HS_SUPPORT_MASK) {
1294 func_to_switch = HS_SUPPORT;
1295 }
1296 break;
1297
1298 default:
1299 continue;
1300 }
1301
1302
1303 if (func_to_switch) {
1304 break;
1305 }
1306 }
1307 RTSX_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x", func_to_switch);
1308
1309#ifdef SUPPORT_SD_LOCK
1310 if ((sd_card->sd_lock_status & SD_SDR_RST)
1311 && (DDR50_SUPPORT == func_to_switch)
1312 && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1313 func_to_switch = SDR50_SUPPORT;
1314 RTSX_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n");
1315 }
1316#endif
1317
1318 if (func_to_switch) {
1319 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, bus_width);
1320 if (retval != STATUS_SUCCESS) {
1321 if (func_to_switch == SDR104_SUPPORT) {
1322 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1323 } else if (func_to_switch == DDR50_SUPPORT) {
1324 sd_card->sd_switch_fail =
1325 SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK;
1326 } else if (func_to_switch == SDR50_SUPPORT) {
1327 sd_card->sd_switch_fail =
1328 SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK |
1329 SDR50_SUPPORT_MASK;
1330 }
1331 TRACE_RET(chip, STATUS_FAIL);
1332 }
1333
1334 if (func_to_switch == SDR104_SUPPORT) {
1335 SET_SD_SDR104(sd_card);
1336 } else if (func_to_switch == DDR50_SUPPORT) {
1337 SET_SD_DDR50(sd_card);
1338 } else if (func_to_switch == SDR50_SUPPORT) {
1339 SET_SD_SDR50(sd_card);
1340 } else {
1341 SET_SD_HS(sd_card);
1342 }
1343 }
1344
1345 if (CHK_SD_DDR50(sd_card)) {
1346 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04);
1347 retval = sd_set_sample_push_timing(chip);
1348 if (retval != STATUS_SUCCESS) {
1349 TRACE_RET(chip, STATUS_FAIL);
1350 }
1351 }
1352
2d2322b2 1353 if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1354 /* Do not try to switch current limit if the card doesn't
1355 * support UHS mode or we don't want it to support UHS mode
1356 */
1357 return STATUS_SUCCESS;
1358 }
1359
1360 /* Function Group 4: Current Limit */
77d89b08 1361 func_to_switch = 0xFF;
1362
1363 for (i = 0; i < 4; i++) {
1364 switch ((u8)(chip->sd_current_prior >> (i*8))) {
1365 case CURRENT_LIMIT_800:
1366 if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK) {
1367 func_to_switch = CURRENT_LIMIT_800;
1368 }
1369 break;
1370
1371 case CURRENT_LIMIT_600:
1372 if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK) {
1373 func_to_switch = CURRENT_LIMIT_600;
1374 }
1375 break;
1376
1377 case CURRENT_LIMIT_400:
1378 if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK) {
1379 func_to_switch = CURRENT_LIMIT_400;
1380 }
1381 break;
1382
1383 case CURRENT_LIMIT_200:
1384 if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK) {
1385 func_to_switch = CURRENT_LIMIT_200;
1386 }
1387 break;
1388
1389 default:
1390 continue;
1391 }
1392
1393 if (func_to_switch != 0xFF) {
1394 break;
1395 }
1396 }
1397
1398 RTSX_DEBUGP("SD_FUNC_GROUP_4: func_to_switch = 0x%02x", func_to_switch);
1399
1400 if (func_to_switch <= CURRENT_LIMIT_800) {
1401 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, bus_width);
1402 if (retval != STATUS_SUCCESS) {
1403 if (sd_check_err_code(chip, SD_NO_CARD)) {
1404 TRACE_RET(chip, STATUS_FAIL);
1405 }
1406 }
1407 RTSX_DEBUGP("Switch current limit finished! (%d)\n", retval);
1408 }
1409
1410 if (CHK_SD_DDR50(sd_card)) {
1411 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1412 }
1413
1414 return STATUS_SUCCESS;
1415}
1416
1417static int sd_wait_data_idle(struct rtsx_chip *chip)
1418{
1419 int retval = STATUS_TIMEDOUT;
1420 int i;
1421 u8 val = 0;
1422
1423 for (i = 0; i < 100; i++) {
1424 RTSX_READ_REG(chip, SD_DATA_STATE, &val);
1425 if (val & SD_DATA_IDLE) {
1426 retval = STATUS_SUCCESS;
1427 break;
1428 }
1429 udelay(100);
1430 }
1431 RTSX_DEBUGP("SD_DATA_STATE: 0x%02x\n", val);
1432
1433 return retval;
1434}
1435
1436static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1437{
1438 int retval;
1439 u8 cmd[5];
1440
1441 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1442 if (retval != STATUS_SUCCESS) {
1443 TRACE_RET(chip, STATUS_FAIL);
1444 }
1445
1446 cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1447 cmd[1] = 0;
1448 cmd[2] = 0;
1449 cmd[3] = 0;
1450 cmd[4] = 0;
1451
1452 retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1453 cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1454 if (retval != STATUS_SUCCESS) {
1455 (void)sd_wait_data_idle(chip);
1456
1457 rtsx_clear_sd_error(chip);
1458 TRACE_RET(chip, STATUS_FAIL);
1459 }
1460
1461 return STATUS_SUCCESS;
1462}
1463
1464static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1465{
1466 struct sd_info *sd_card = &(chip->sd_card);
1467 int retval;
1468 u8 cmd[5];
1469
1470 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1471 if (retval != STATUS_SUCCESS) {
1472 TRACE_RET(chip, STATUS_FAIL);
1473 }
1474
1475 RTSX_DEBUGP("sd ddr tuning rx\n");
1476
1477 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1478 if (retval != STATUS_SUCCESS) {
1479 TRACE_RET(chip, STATUS_FAIL);
1480 }
1481
1482 cmd[0] = 0x40 | SD_STATUS;
1483 cmd[1] = 0;
1484 cmd[2] = 0;
1485 cmd[3] = 0;
1486 cmd[4] = 0;
1487
1488 retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1489 cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1490 if (retval != STATUS_SUCCESS) {
1491 (void)sd_wait_data_idle(chip);
1492
1493 rtsx_clear_sd_error(chip);
1494 TRACE_RET(chip, STATUS_FAIL);
1495 }
1496
1497 return STATUS_SUCCESS;
1498}
1499
1500static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1501{
1502 struct sd_info *sd_card = &(chip->sd_card);
1503 int retval;
1504 u8 cmd[5], bus_width;
1505
1506 if (CHK_MMC_8BIT(sd_card)) {
1507 bus_width = SD_BUS_WIDTH_8;
1508 } else if (CHK_MMC_4BIT(sd_card)) {
1509 bus_width = SD_BUS_WIDTH_4;
1510 } else {
1511 bus_width = SD_BUS_WIDTH_1;
1512 }
1513
1514 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1515 if (retval != STATUS_SUCCESS) {
1516 TRACE_RET(chip, STATUS_FAIL);
1517 }
1518
1519 RTSX_DEBUGP("mmc ddr tuning rx\n");
1520
1521 cmd[0] = 0x40 | SEND_EXT_CSD;
1522 cmd[1] = 0;
1523 cmd[2] = 0;
1524 cmd[3] = 0;
1525 cmd[4] = 0;
1526
1527 retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1528 cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1529 if (retval != STATUS_SUCCESS) {
1530 (void)sd_wait_data_idle(chip);
1531
1532 rtsx_clear_sd_error(chip);
1533 TRACE_RET(chip, STATUS_FAIL);
1534 }
1535
1536 return STATUS_SUCCESS;
1537}
1538
1539static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1540{
1541 struct sd_info *sd_card = &(chip->sd_card);
1542 int retval;
1543
1544 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1545 if (retval != STATUS_SUCCESS) {
1546 TRACE_RET(chip, STATUS_FAIL);
1547 }
1548
1549 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1550
1551 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1552 SD_RSP_TYPE_R1, NULL, 0);
1553 if (retval != STATUS_SUCCESS) {
1554 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1555 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1556 TRACE_RET(chip, STATUS_FAIL);
1557 }
1558 }
1559
1560 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1561
1562 return STATUS_SUCCESS;
1563}
1564
1565static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1566{
1567 struct sd_info *sd_card = &(chip->sd_card);
1568 int retval;
1569 u8 cmd[5], bus_width;
1570
1571 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1572 if (retval != STATUS_SUCCESS) {
1573 TRACE_RET(chip, STATUS_FAIL);
1574 }
1575
1576 if (CHK_SD(sd_card)) {
1577 bus_width = SD_BUS_WIDTH_4;
1578 } else {
1579 if (CHK_MMC_8BIT(sd_card)) {
1580 bus_width = SD_BUS_WIDTH_8;
1581 } else if (CHK_MMC_4BIT(sd_card)) {
1582 bus_width = SD_BUS_WIDTH_4;
1583 } else {
1584 bus_width = SD_BUS_WIDTH_1;
1585 }
1586 }
1587
1588 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1589 if (retval != STATUS_SUCCESS) {
1590 TRACE_RET(chip, STATUS_FAIL);
1591 }
1592
1593 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1594
1595 cmd[0] = 0x40 | PROGRAM_CSD;
1596 cmd[1] = 0;
1597 cmd[2] = 0;
1598 cmd[3] = 0;
1599 cmd[4] = 0;
1600
1601 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1602 cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1603 if (retval != STATUS_SUCCESS) {
1604 rtsx_clear_sd_error(chip);
1605 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1606 TRACE_RET(chip, STATUS_FAIL);
1607 }
1608
1609 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1610
1611 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1612
1613 return STATUS_SUCCESS;
1614}
1615
1616static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, u8 tune_dir)
1617{
1618 struct sd_info *sd_card = &(chip->sd_card);
1619 struct timing_phase_path path[MAX_PHASE + 1];
1620 int i, j, cont_path_cnt;
1621 int new_block, max_len, final_path_idx;
1622 u8 final_phase = 0xFF;
1623
1624 if (phase_map == 0xFFFFFFFF) {
1625 if (tune_dir == TUNE_RX) {
1626 final_phase = (u8)chip->sd_default_rx_phase;
1627 } else {
1628 final_phase = (u8)chip->sd_default_tx_phase;
1629 }
1630
1631 goto Search_Finish;
1632 }
1633
1634 cont_path_cnt = 0;
1635 new_block = 1;
1636 j = 0;
1637 for (i = 0; i < MAX_PHASE + 1; i++) {
1638 if (phase_map & (1 << i)) {
1639 if (new_block) {
1640 new_block = 0;
1641 j = cont_path_cnt++;
1642 path[j].start = i;
1643 path[j].end = i;
1644 } else {
1645 path[j].end = i;
1646 }
1647 } else {
1648 new_block = 1;
1649 if (cont_path_cnt) {
1650 int idx = cont_path_cnt - 1;
1651 path[idx].len = path[idx].end - path[idx].start + 1;
1652 path[idx].mid = path[idx].start + path[idx].len / 2;
1653 }
1654 }
1655 }
1656
1657 if (cont_path_cnt == 0) {
1658 RTSX_DEBUGP("No continuous phase path\n");
1659 goto Search_Finish;
1660 } else {
1661 int idx = cont_path_cnt - 1;
1662 path[idx].len = path[idx].end - path[idx].start + 1;
1663 path[idx].mid = path[idx].start + path[idx].len / 2;
1664 }
1665
1666 if ((path[0].start == 0) && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1667 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1668 path[0].len += path[cont_path_cnt - 1].len;
1669 path[0].mid = path[0].start + path[0].len / 2;
1670 if (path[0].mid < 0) {
1671 path[0].mid += MAX_PHASE + 1;
1672 }
1673 cont_path_cnt--;
1674 }
1675
1676 max_len = 0;
1677 final_phase = 0;
1678 final_path_idx = 0;
1679 for (i = 0; i < cont_path_cnt; i++) {
1680 if (path[i].len > max_len) {
1681 max_len = path[i].len;
1682 final_phase = (u8)path[i].mid;
1683 final_path_idx = i;
1684 }
1685
1686 RTSX_DEBUGP("path[%d].start = %d\n", i, path[i].start);
1687 RTSX_DEBUGP("path[%d].end = %d\n", i, path[i].end);
1688 RTSX_DEBUGP("path[%d].len = %d\n", i, path[i].len);
1689 RTSX_DEBUGP("path[%d].mid = %d\n", i, path[i].mid);
1690 RTSX_DEBUGP("\n");
1691 }
1692
1693 if (tune_dir == TUNE_TX) {
1694 if (CHK_SD_SDR104(sd_card)) {
1695 if (max_len > 15) {
1696 int temp_mid = (max_len - 16) / 2;
1697 int temp_final_phase =
1698 path[final_path_idx].end - (max_len - (6 + temp_mid));
1699
1700 if (temp_final_phase < 0) {
1701 final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1702 } else {
1703 final_phase = (u8)temp_final_phase;
1704 }
1705 }
1706 } else if (CHK_SD_SDR50(sd_card)) {
1707 if (max_len > 12) {
1708 int temp_mid = (max_len - 13) / 2;
1709 int temp_final_phase =
1710 path[final_path_idx].end - (max_len - (3 + temp_mid));
1711
1712 if (temp_final_phase < 0) {
1713 final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1714 } else {
1715 final_phase = (u8)temp_final_phase;
1716 }
1717 }
1718 }
1719 }
1720
1721Search_Finish:
25985edc 1722 RTSX_DEBUGP("Final chosen phase: %d\n", final_phase);
77d89b08 1723 return final_phase;
1724}
1725
1726static int sd_tuning_rx(struct rtsx_chip *chip)
1727{
1728 struct sd_info *sd_card = &(chip->sd_card);
1729 int retval;
1730 int i, j;
1731 u32 raw_phase_map[3], phase_map;
1732 u8 final_phase;
1733 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1734
1735 if (CHK_SD(sd_card)) {
1736 if (CHK_SD_DDR50(sd_card)) {
1737 tuning_cmd = sd_ddr_tuning_rx_cmd;
1738 } else {
1739 tuning_cmd = sd_sdr_tuning_rx_cmd;
1740 }
1741 } else {
1742 if (CHK_MMC_DDR52(sd_card)) {
1743 tuning_cmd = mmc_ddr_tunning_rx_cmd;
1744 } else {
1745 TRACE_RET(chip, STATUS_FAIL);
1746 }
1747 }
1748
1749 for (i = 0; i < 3; i++) {
1750 raw_phase_map[i] = 0;
1751 for (j = MAX_PHASE; j >= 0; j--) {
1752 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1753 sd_set_err_code(chip, SD_NO_CARD);
1754 TRACE_RET(chip, STATUS_FAIL);
1755 }
1756
1757 retval = tuning_cmd(chip, (u8)j);
1758 if (retval == STATUS_SUCCESS) {
1759 raw_phase_map[i] |= 1 << j;
1760 }
1761 }
1762 }
1763
1764 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1765 for (i = 0; i < 3; i++) {
1766 RTSX_DEBUGP("RX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1767 }
1768 RTSX_DEBUGP("RX phase_map = 0x%08x\n", phase_map);
1769
1770 final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1771 if (final_phase == 0xFF) {
1772 TRACE_RET(chip, STATUS_FAIL);
1773 }
1774
1775 retval = sd_change_phase(chip, final_phase, TUNE_RX);
1776 if (retval != STATUS_SUCCESS) {
1777 TRACE_RET(chip, STATUS_FAIL);
1778 }
1779
1780 return STATUS_SUCCESS;
1781}
1782
1783static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1784{
1785 struct sd_info *sd_card = &(chip->sd_card);
1786 int retval;
1787 int i;
1788 u32 phase_map;
1789 u8 final_phase;
1790
1791 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1792
1793 phase_map = 0;
1794 for (i = MAX_PHASE; i >= 0; i--) {
1795 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1796 sd_set_err_code(chip, SD_NO_CARD);
1797 rtsx_write_register(chip, SD_CFG3,
1798 SD_RSP_80CLK_TIMEOUT_EN, 0);
1799 TRACE_RET(chip, STATUS_FAIL);
1800 }
1801
1802 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1803 if (retval != STATUS_SUCCESS) {
1804 continue;
1805 }
1806
1807 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1808 SD_RSP_TYPE_R1, NULL, 0);
1809 if ((retval == STATUS_SUCCESS) || !sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1810 phase_map |= 1 << i;
1811 }
1812 }
1813
1814 RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1815
1816 RTSX_DEBUGP("DDR TX pre tune phase_map = 0x%08x\n", phase_map);
1817
1818 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1819 if (final_phase == 0xFF) {
1820 TRACE_RET(chip, STATUS_FAIL);
1821 }
1822
1823 retval = sd_change_phase(chip, final_phase, TUNE_TX);
1824 if (retval != STATUS_SUCCESS) {
1825 TRACE_RET(chip, STATUS_FAIL);
1826 }
1827
1828 RTSX_DEBUGP("DDR TX pre tune phase: %d\n", (int)final_phase);
1829
1830 return STATUS_SUCCESS;
1831}
1832
1833static int sd_tuning_tx(struct rtsx_chip *chip)
1834{
1835 struct sd_info *sd_card = &(chip->sd_card);
1836 int retval;
1837 int i, j;
1838 u32 raw_phase_map[3], phase_map;
1839 u8 final_phase;
1840 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1841
1842 if (CHK_SD(sd_card)) {
1843 if (CHK_SD_DDR50(sd_card)) {
1844 tuning_cmd = sd_ddr_tuning_tx_cmd;
1845 } else {
1846 tuning_cmd = sd_sdr_tuning_tx_cmd;
1847 }
1848 } else {
1849 if (CHK_MMC_DDR52(sd_card)) {
1850 tuning_cmd = sd_ddr_tuning_tx_cmd;
1851 } else {
1852 TRACE_RET(chip, STATUS_FAIL);
1853 }
1854 }
1855
1856 for (i = 0; i < 3; i++) {
1857 raw_phase_map[i] = 0;
1858 for (j = MAX_PHASE; j >= 0; j--) {
1859 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1860 sd_set_err_code(chip, SD_NO_CARD);
1861 rtsx_write_register(chip, SD_CFG3,
1862 SD_RSP_80CLK_TIMEOUT_EN, 0);
1863 TRACE_RET(chip, STATUS_FAIL);
1864 }
1865
1866 retval = tuning_cmd(chip, (u8)j);
1867 if (retval == STATUS_SUCCESS) {
1868 raw_phase_map[i] |= 1 << j;
1869 }
1870 }
1871 }
1872
1873 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1874 for (i = 0; i < 3; i++) {
1875 RTSX_DEBUGP("TX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1876 }
1877 RTSX_DEBUGP("TX phase_map = 0x%08x\n", phase_map);
1878
1879 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1880 if (final_phase == 0xFF) {
1881 TRACE_RET(chip, STATUS_FAIL);
1882 }
1883
1884 retval = sd_change_phase(chip, final_phase, TUNE_TX);
1885 if (retval != STATUS_SUCCESS) {
1886 TRACE_RET(chip, STATUS_FAIL);
1887 }
1888
1889 return STATUS_SUCCESS;
1890}
1891
1892static int sd_sdr_tuning(struct rtsx_chip *chip)
1893{
1894 int retval;
1895
1896 retval = sd_tuning_tx(chip);
1897 if (retval != STATUS_SUCCESS) {
1898 TRACE_RET(chip, STATUS_FAIL);
1899 }
1900
1901 retval = sd_tuning_rx(chip);
1902 if (retval != STATUS_SUCCESS) {
1903 TRACE_RET(chip, STATUS_FAIL);
1904 }
1905
1906 return STATUS_SUCCESS;
1907}
1908
1909static int sd_ddr_tuning(struct rtsx_chip *chip)
1910{
1911 int retval;
1912
1913 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1914 retval = sd_ddr_pre_tuning_tx(chip);
1915 if (retval != STATUS_SUCCESS) {
1916 TRACE_RET(chip, STATUS_FAIL);
1917 }
1918 } else {
1919 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, TUNE_TX);
1920 if (retval != STATUS_SUCCESS) {
1921 TRACE_RET(chip, STATUS_FAIL);
1922 }
1923 }
1924
1925 retval = sd_tuning_rx(chip);
1926 if (retval != STATUS_SUCCESS) {
1927 TRACE_RET(chip, STATUS_FAIL);
1928 }
1929
1930 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1931 retval = sd_tuning_tx(chip);
1932 if (retval != STATUS_SUCCESS) {
1933 TRACE_RET(chip, STATUS_FAIL);
1934 }
1935 }
1936
1937 return STATUS_SUCCESS;
1938}
1939
1940static int mmc_ddr_tuning(struct rtsx_chip *chip)
1941{
1942 int retval;
1943
1944 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1945 retval = sd_ddr_pre_tuning_tx(chip);
1946 if (retval != STATUS_SUCCESS) {
1947 TRACE_RET(chip, STATUS_FAIL);
1948 }
1949 } else {
1950 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, TUNE_TX);
1951 if (retval != STATUS_SUCCESS) {
1952 TRACE_RET(chip, STATUS_FAIL);
1953 }
1954 }
1955
1956 retval = sd_tuning_rx(chip);
1957 if (retval != STATUS_SUCCESS) {
1958 TRACE_RET(chip, STATUS_FAIL);
1959 }
1960
1961 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1962 retval = sd_tuning_tx(chip);
1963 if (retval != STATUS_SUCCESS) {
1964 TRACE_RET(chip, STATUS_FAIL);
1965 }
1966 }
1967
1968 return STATUS_SUCCESS;
1969}
1970
1971int sd_switch_clock(struct rtsx_chip *chip)
1972{
1973 struct sd_info *sd_card = &(chip->sd_card);
1974 int retval;
1975 int re_tuning = 0;
1976
1977 retval = select_card(chip, SD_CARD);
1978 if (retval != STATUS_SUCCESS) {
1979 TRACE_RET(chip, STATUS_FAIL);
1980 }
1981
1982 if (CHECK_PID(chip, 0x5209) &&
1983 (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))) {
1984 if (sd_card->need_retune && (sd_card->sd_clock != chip->cur_clk)) {
1985 re_tuning = 1;
1986 sd_card->need_retune = 0;
1987 }
1988 }
1989
1990 retval = switch_clock(chip, sd_card->sd_clock);
1991 if (retval != STATUS_SUCCESS) {
1992 TRACE_RET(chip, STATUS_FAIL);
1993 }
1994
1995 if (re_tuning) {
1996 if (CHK_SD(sd_card)) {
1997 if (CHK_SD_DDR50(sd_card)) {
1998 retval = sd_ddr_tuning(chip);
1999 } else {
2000 retval = sd_sdr_tuning(chip);
2001 }
2002 } else {
2003 if (CHK_MMC_DDR52(sd_card)) {
2004 retval = mmc_ddr_tuning(chip);
2005 }
2006 }
2007
2008 if (retval != STATUS_SUCCESS) {
2009 TRACE_RET(chip, STATUS_FAIL);
2010 }
2011 }
2012
2013 return STATUS_SUCCESS;
2014}
2015
2016static int sd_prepare_reset(struct rtsx_chip *chip)
2017{
2018 struct sd_info *sd_card = &(chip->sd_card);
2019 int retval;
2020
2021 if (chip->asic_code) {
2022 sd_card->sd_clock = 29;
2023 } else {
2024 sd_card->sd_clock = CLK_30;
2025 }
2026
2d2322b2 2027 sd_card->sd_type = 0;
2028 sd_card->seq_mode = 0;
2029 sd_card->sd_data_buf_ready = 0;
2030 sd_card->capacity = 0;
2031
2032#ifdef SUPPORT_SD_LOCK
2033 sd_card->sd_lock_status = 0;
2034 sd_card->sd_erase_status = 0;
2035#endif
2036
2037 chip->capacity[chip->card2lun[SD_CARD]] = 0;
77d89b08 2038 chip->sd_io = 0;
2039
2040 retval = sd_set_init_para(chip);
2041 if (retval != STATUS_SUCCESS) {
2042 TRACE_RET(chip, retval);
2043 }
2044
2045 if (CHECK_PID(chip, 0x5209)) {
2046 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF,
2047 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1);
2048 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, 0xFF, SD20_RX_POS_EDGE);
2049 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0xFF, 0);
2050 } else {
2051 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40);
2052 }
2053
2054 RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
2055
2056 retval = select_card(chip, SD_CARD);
2057 if (retval != STATUS_SUCCESS) {
2058 TRACE_RET(chip, STATUS_FAIL);
2059 }
2060
2061 return STATUS_SUCCESS;
2062}
2063
2064static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2065{
2066 if (CHECK_PID(chip, 0x5209)) {
2067 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2068 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2069 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5);
2070 } else if (CHECK_PID(chip, 0x5208)) {
2071 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
2072 XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD);
2073 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
2074 SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD);
2075 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
2076 SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2077 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
2078 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
2079 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
2080 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
2081 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2082 } else if (CHECK_PID(chip, 0x5288)) {
2083 if (CHECK_BARO_PKG(chip, QFN)) {
2084 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2085 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2086 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
2087 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
2088 }
2089 }
2090
2091 return STATUS_SUCCESS;
2092}
2093
2094int sd_pull_ctl_enable(struct rtsx_chip *chip)
2095{
2096 int retval;
2097
2098 rtsx_init_cmd(chip);
2099
2100 if (CHECK_PID(chip, 0x5209)) {
2101 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
2102 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
2103 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xE9);
2104 } else if (CHECK_PID(chip, 0x5208)) {
2105 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2106 XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2107 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2108 SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2109 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2110 SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2111 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2112 XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2113 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2114 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2115 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2116 } else if (CHECK_PID(chip, 0x5288)) {
2117 if (CHECK_BARO_PKG(chip, QFN)) {
2118 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA8);
2119 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x5A);
2120 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
2121 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xAA);
2122 }
2123 }
2124
2125 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2126 if (retval < 0) {
2127 TRACE_RET(chip, STATUS_FAIL);
2128 }
2129
2130 return STATUS_SUCCESS;
2131}
2132
2133static int sd_init_power(struct rtsx_chip *chip)
2134{
2135 int retval;
2136
2137 if (CHECK_PID(chip, 0x5209)) {
2138 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
2139 }
2140
2141 retval = sd_power_off_card3v3(chip);
2142 if (retval != STATUS_SUCCESS) {
2143 TRACE_RET(chip, STATUS_FAIL);
2144 }
2145
2146 if (!chip->ft2_fast_mode) {
2147 wait_timeout(250);
2148 }
2149
2150 retval = enable_card_clock(chip, SD_CARD);
2151 if (retval != STATUS_SUCCESS) {
2152 TRACE_RET(chip, STATUS_FAIL);
2153 }
2154
2155 if (chip->asic_code) {
2156 retval = sd_pull_ctl_enable(chip);
2157 if (retval != STATUS_SUCCESS) {
2158 TRACE_RET(chip, STATUS_FAIL);
2159 }
2160 } else {
2161 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2162 }
2163
2164 if (chip->ft2_fast_mode) {
2165 if (CHECK_PID(chip, 0x5209)) {
2166 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
2167 }
2168 } else {
2169 retval = card_power_on(chip, SD_CARD);
2170 if (retval != STATUS_SUCCESS) {
2171 TRACE_RET(chip, STATUS_FAIL);
2172 }
2173 wait_timeout(260);
2174
2175#ifdef SUPPORT_OCP
2176 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2177 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
2178 TRACE_RET(chip, STATUS_FAIL);
2179 }
2180#endif
2181 }
2182
2183 RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
2184
2185 return STATUS_SUCCESS;
2186}
2187
2188static int sd_dummy_clock(struct rtsx_chip *chip)
2189{
2190 if (CHECK_PID(chip, 0x5209)) {
2191 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
2192 wait_timeout(5);
2193 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00);
2194 } else {
2195 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01);
2196 wait_timeout(5);
2197 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0);
2198 }
2199
2200 return STATUS_SUCCESS;
2201}
2202
2203static int sd_read_lba0(struct rtsx_chip *chip)
2204{
2205 struct sd_info *sd_card = &(chip->sd_card);
2206 int retval;
2207 u8 cmd[5], bus_width;
2208
2209 cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2210 cmd[1] = 0;
2211 cmd[2] = 0;
2212 cmd[3] = 0;
2213 cmd[4] = 0;
2214
2215 if (CHK_SD(sd_card)) {
2216 bus_width = SD_BUS_WIDTH_4;
2217 } else {
2218 if (CHK_MMC_8BIT(sd_card)) {
2219 bus_width = SD_BUS_WIDTH_8;
2220 } else if (CHK_MMC_4BIT(sd_card)) {
2221 bus_width = SD_BUS_WIDTH_4;
2222 } else {
2223 bus_width = SD_BUS_WIDTH_1;
2224 }
2225 }
2226
2227 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2228 5, 512, 1, bus_width, NULL, 0, 100);
2229 if (retval != STATUS_SUCCESS) {
e0ce58d7 2230 rtsx_clear_sd_error(chip);
77d89b08 2231 TRACE_RET(chip, STATUS_FAIL);
2232 }
2233
2234 return STATUS_SUCCESS;
2235}
2236
2237static int sd_check_wp_state(struct rtsx_chip *chip)
2238{
2239 struct sd_info *sd_card = &(chip->sd_card);
2240 int retval;
2241 u32 val;
2242 u16 sd_card_type;
2243 u8 cmd[5], buf[64];
2244
2245 retval = sd_send_cmd_get_rsp(chip, APP_CMD,
2246 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2247 if (retval != STATUS_SUCCESS) {
2248 TRACE_RET(chip, STATUS_FAIL);
2249 }
2250
2251 cmd[0] = 0x40 | SD_STATUS;
2252 cmd[1] = 0;
2253 cmd[2] = 0;
2254 cmd[3] = 0;
2255 cmd[4] = 0;
2256
2257 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, SD_BUS_WIDTH_4, buf, 64, 250);
2258 if (retval != STATUS_SUCCESS) {
2259 rtsx_clear_sd_error(chip);
2260
2261 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2262 TRACE_RET(chip, STATUS_FAIL);
2263 }
2264
2265 RTSX_DEBUGP("ACMD13:\n");
2266 RTSX_DUMP(buf, 64);
2267
2268 sd_card_type = ((u16)buf[2] << 8) | buf[3];
2269 RTSX_DEBUGP("sd_card_type = 0x%04x\n", sd_card_type);
2270 if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2271 /* ROM card or OTP */
2272 chip->card_wp |= SD_CARD;
2273 }
2274
2275 /* Check SD Machanical Write-Protect Switch */
2276 val = rtsx_readl(chip, RTSX_BIPR);
2277 if (val & SD_WRITE_PROTECT) {
2278 chip->card_wp |= SD_CARD;
2279 }
2280
2281 return STATUS_SUCCESS;
2282}
2283
2284static int reset_sd(struct rtsx_chip *chip)
2285{
2286 struct sd_info *sd_card = &(chip->sd_card);
2287 int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
2288 int sd_dont_switch = 0;
2289 int support_1v8 = 0;
2290 int try_sdio = 1;
2291 u8 rsp[16];
2292 u8 switch_bus_width;
2293 u32 voltage = 0;
2294 int sd20_mode = 0;
2295
2296 SET_SD(sd_card);
2297
2298Switch_Fail:
2299
2300 i = 0;
2301 j = 0;
2302 k = 0;
2303 hi_cap_flow = 0;
2304
2305#ifdef SUPPORT_SD_LOCK
2306 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2307 goto SD_UNLOCK_ENTRY;
2308#endif
2309
2310 retval = sd_prepare_reset(chip);
2311 if (retval != STATUS_SUCCESS) {
2312 TRACE_RET(chip, STATUS_FAIL);
2313 }
2314
2315 retval = sd_dummy_clock(chip);
2316 if (retval != STATUS_SUCCESS) {
2317 TRACE_RET(chip, STATUS_FAIL);
2318 }
2319
2320 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2321 int rty_cnt = 0;
2322
2323 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2324 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2325 sd_set_err_code(chip, SD_NO_CARD);
2326 TRACE_RET(chip, STATUS_FAIL);
2327 }
2328
2329 retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, SD_RSP_TYPE_R4, rsp, 5);
2330 if (retval == STATUS_SUCCESS) {
cddac88f 2331 int func_num = (rsp[1] >> 4) & 0x07;
77d89b08 2332 if (func_num) {
2333 RTSX_DEBUGP("SD_IO card (Function number: %d)!\n", func_num);
2334 chip->sd_io = 1;
2335 TRACE_RET(chip, STATUS_FAIL);
2336 }
2337
2338 break;
2339 }
2340
2341 sd_init_power(chip);
2342
2343 sd_dummy_clock(chip);
2344 }
2345
2346 RTSX_DEBUGP("Normal card!\n");
2347 }
2348
2349 /* Start Initialization Process of SD Card */
2350RTY_SD_RST:
2351 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2352 if (retval != STATUS_SUCCESS) {
2353 TRACE_RET(chip, STATUS_FAIL);
2354 }
2355
2356 wait_timeout(20);
2357
2358 retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, SD_RSP_TYPE_R7, rsp, 5);
2359 if (retval == STATUS_SUCCESS) {
2360 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2361 hi_cap_flow = 1;
2362 if (CHECK_PID(chip, 0x5209)) {
2363 if (sd20_mode) {
2364 voltage = SUPPORT_VOLTAGE |
2365 SUPPORT_HIGH_AND_EXTENDED_CAPACITY;
2366 } else {
2367 voltage = SUPPORT_VOLTAGE |
2368 SUPPORT_HIGH_AND_EXTENDED_CAPACITY |
2369 SUPPORT_MAX_POWER_PERMANCE | SUPPORT_1V8;
2370 }
2371 } else {
2372 voltage = SUPPORT_VOLTAGE | 0x40000000;
2373 }
2374 }
2375 }
2376
2377 if (!hi_cap_flow) {
2378 voltage = SUPPORT_VOLTAGE;
2379
2380 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2381 if (retval != STATUS_SUCCESS) {
2382 TRACE_RET(chip, STATUS_FAIL);
2383 }
2384
2385 wait_timeout(20);
2386 }
2387
2388 do {
2389 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, NULL, 0);
2390 if (retval != STATUS_SUCCESS) {
2391 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2392 sd_set_err_code(chip, SD_NO_CARD);
2393 TRACE_RET(chip, STATUS_FAIL);
2394 }
2395
2396 j++;
2397 if (j < 3) {
2398 goto RTY_SD_RST;
2399 } else {
2400 TRACE_RET(chip, STATUS_FAIL);
2401 }
2402 }
2403
2404 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, SD_RSP_TYPE_R3, rsp, 5);
2405 if (retval != STATUS_SUCCESS) {
2406 k++;
2407 if (k < 3) {
2408 goto RTY_SD_RST;
2409 } else {
2410 TRACE_RET(chip, STATUS_FAIL);
2411 }
2412 }
2413
2414 i++;
2415 wait_timeout(20);
2416 } while (!(rsp[1] & 0x80) && (i < 255));
2417
2418 if (i == 255) {
2419 TRACE_RET(chip, STATUS_FAIL);
2420 }
2421
2422 if (hi_cap_flow) {
2423 if (rsp[1] & 0x40) {
2424 SET_SD_HCXC(sd_card);
2425 } else {
2426 CLR_SD_HCXC(sd_card);
2427 }
2428 if (CHECK_PID(chip, 0x5209) && CHK_SD_HCXC(sd_card) && !sd20_mode) {
2429 support_1v8 = (rsp[1] & 0x01) ? 1 : 0;
2430 } else {
2431 support_1v8 = 0;
2432 }
2433 } else {
2434 CLR_SD_HCXC(sd_card);
2435 support_1v8 = 0;
2436 }
2437 RTSX_DEBUGP("support_1v8 = %d\n", support_1v8);
2438
2439 if (support_1v8) {
2440 retval = sd_voltage_switch(chip);
2441 if (retval != STATUS_SUCCESS) {
2442 TRACE_RET(chip, STATUS_FAIL);
2443 }
2444 }
2445
2446 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2447 if (retval != STATUS_SUCCESS) {
2448 TRACE_RET(chip, STATUS_FAIL);
2449 }
2450
2451 for (i = 0; i < 3; i++) {
2452 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, SD_RSP_TYPE_R6, rsp, 5);
2453 if (retval != STATUS_SUCCESS) {
2454 TRACE_RET(chip, STATUS_FAIL);
2455 }
2456
2457 sd_card->sd_addr = (u32)rsp[1] << 24;
2458 sd_card->sd_addr += (u32)rsp[2] << 16;
2459
2460 if (sd_card->sd_addr) {
2461 break;
2462 }
2463 }
2464
2465 retval = sd_check_csd(chip, 1);
2466 if (retval != STATUS_SUCCESS) {
2467 TRACE_RET(chip, STATUS_FAIL);
2468 }
2469
2470 retval = sd_select_card(chip, 1);
2471 if (retval != STATUS_SUCCESS) {
2472 TRACE_RET(chip, STATUS_FAIL);
2473 }
2474
2475#ifdef SUPPORT_SD_LOCK
2476SD_UNLOCK_ENTRY:
2477 retval = sd_update_lock_status(chip);
2478 if (retval != STATUS_SUCCESS) {
2479 TRACE_RET(chip, STATUS_FAIL);
2480 }
2481
2482 if (sd_card->sd_lock_status & SD_LOCKED) {
2483 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2484 return STATUS_SUCCESS;
2485 } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2486 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2487 }
2488#endif
2489
2490 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2491 if (retval != STATUS_SUCCESS) {
2492 TRACE_RET(chip, STATUS_FAIL);
2493 }
2494 retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, SD_RSP_TYPE_R1, NULL, 0);
2495 if (retval != STATUS_SUCCESS) {
2496 TRACE_RET(chip, STATUS_FAIL);
2497 }
2498
2499 if (support_1v8) {
2500 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2501 if (retval != STATUS_SUCCESS) {
2502 TRACE_RET(chip, STATUS_FAIL);
2503 }
2504 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2505 if (retval != STATUS_SUCCESS) {
2506 TRACE_RET(chip, STATUS_FAIL);
2507 }
2508
2509 switch_bus_width = SD_BUS_WIDTH_4;
2510 } else {
2511 switch_bus_width = SD_BUS_WIDTH_1;
2512 }
2513
2514 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2515 if (retval != STATUS_SUCCESS) {
2516 TRACE_RET(chip, STATUS_FAIL);
2517 }
2518
2519 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2520 if (retval != STATUS_SUCCESS) {
2521 TRACE_RET(chip, STATUS_FAIL);
2522 }
2523
2524 if (!(sd_card->raw_csd[4] & 0x40))
2525 sd_dont_switch = 1;
2526
2527 if (!sd_dont_switch) {
2d2322b2 2528 if (sd20_mode) {
2529 /* Set sd_switch_fail here, because we needn't
2530 * switch to UHS mode
2531 */
2532 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2533 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2534 }
2535
2536 /* Check the card whether follow SD1.1 spec or higher */
77d89b08 2537 retval = sd_check_spec(chip, switch_bus_width);
2538 if (retval == STATUS_SUCCESS) {
2539 retval = sd_switch_function(chip, switch_bus_width);
2540 if (retval != STATUS_SUCCESS) {
2541 if (CHECK_PID(chip, 0x5209)) {
2542 sd_change_bank_voltage(chip, SD_IO_3V3);
2543 }
2544 sd_init_power(chip);
2545 sd_dont_switch = 1;
2546 try_sdio = 0;
2547
2548 goto Switch_Fail;
2549 }
2550 } else {
2551 if (support_1v8) {
2552 if (CHECK_PID(chip, 0x5209)) {
2553 sd_change_bank_voltage(chip, SD_IO_3V3);
2554 }
2555 sd_init_power(chip);
2556 sd_dont_switch = 1;
2557 try_sdio = 0;
2558
2559 goto Switch_Fail;
2560 }
2561 }
2562 }
2563
2564 if (!support_1v8) {
2565 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2566 if (retval != STATUS_SUCCESS) {
2567 TRACE_RET(chip, STATUS_FAIL);
2568 }
2569 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2570 if (retval != STATUS_SUCCESS) {
2571 TRACE_RET(chip, STATUS_FAIL);
2572 }
2573 }
2574
2575#ifdef SUPPORT_SD_LOCK
2576 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2577#endif
2578
2d2322b2 2579 if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
77d89b08 2580 int read_lba0 = 1;
2581
2582 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_1v8);
2583
2584 retval = sd_set_init_para(chip);
2585 if (retval != STATUS_SUCCESS) {
2586 TRACE_RET(chip, STATUS_FAIL);
2587 }
2588
2589 if (CHK_SD_DDR50(sd_card)) {
2590 retval = sd_ddr_tuning(chip);
2591 } else {
2592 retval = sd_sdr_tuning(chip);
2593 }
2594
2595 if (retval != STATUS_SUCCESS) {
2596 if (sd20_mode) {
2597 TRACE_RET(chip, STATUS_FAIL);
2598 } else {
2599 retval = sd_init_power(chip);
2600 if (retval != STATUS_SUCCESS) {
2601 TRACE_RET(chip, STATUS_FAIL);
2602 }
2603 try_sdio = 0;
2604 sd20_mode = 1;
2605 goto Switch_Fail;
2606 }
2607 }
2608
2609 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2610
2611 if (CHK_SD_DDR50(sd_card)) {
2612 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2613 if (retval != STATUS_SUCCESS) {
2614 read_lba0 = 0;
2615 }
2616 }
2617
2618 if (read_lba0) {
2619 retval = sd_read_lba0(chip);
2620 if (retval != STATUS_SUCCESS) {
2621 if (sd20_mode) {
2622 TRACE_RET(chip, STATUS_FAIL);
2623 } else {
2624 retval = sd_init_power(chip);
2625 if (retval != STATUS_SUCCESS) {
2626 TRACE_RET(chip, STATUS_FAIL);
2627 }
2628 try_sdio = 0;
2629 sd20_mode = 1;
2630 goto Switch_Fail;
2631 }
2632 }
2633 }
2634 }
2635
2636 retval = sd_check_wp_state(chip);
2637 if (retval != STATUS_SUCCESS) {
2638 TRACE_RET(chip, STATUS_FAIL);
2639 }
2640
2641 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2642
2643#ifdef SUPPORT_SD_LOCK
2644 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2645 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2646 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2647 }
2648#endif
2649
2650 return STATUS_SUCCESS;
2651}
2652
2653
2654static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2655{
2656 struct sd_info *sd_card = &(chip->sd_card);
2657 int retval;
2658 u8 buf[8] = {0}, bus_width, *ptr;
2659 u16 byte_cnt;
2660 int len;
2661
2662 retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 0);
2663 if (retval != STATUS_SUCCESS) {
2664 TRACE_RET(chip, STATUS_FAIL);
2665 }
2666
2667 if (width == MMC_8BIT_BUS) {
2668 buf[0] = 0x55;
2669 buf[1] = 0xAA;
2670 len = 8;
2671 byte_cnt = 8;
2672 bus_width = SD_BUS_WIDTH_8;
2673 } else {
2674 buf[0] = 0x5A;
2675 len = 4;
2676 byte_cnt = 4;
2677 bus_width = SD_BUS_WIDTH_4;
2678 }
2679
2680 if (!CHECK_PID(chip, 0x5209)) {
2681 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x02, 0x02);
2682 }
2683
2684 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2685 NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2686 if (retval != STATUS_SUCCESS) {
2687 if (CHECK_PID(chip, 0x5209)) {
2688 u8 val1 = 0, val2 = 0;
2689 rtsx_read_register(chip, REG_SD_STAT1, &val1);
2690 rtsx_read_register(chip, REG_SD_STAT2, &val2);
2691 rtsx_clear_sd_error(chip);
2692 if ((val1 & 0xE0) || val2) {
2693 TRACE_RET(chip, STATUS_FAIL);
2694 }
2695 } else {
2696 rtsx_clear_sd_error(chip);
2697 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2698 TRACE_RET(chip, STATUS_FAIL);
2699 }
2700 }
2701
2702 if (!CHECK_PID(chip, 0x5209)) {
2703 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x02, 0);
2704 }
2705
2706 RTSX_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R);
2707
2708 rtsx_init_cmd(chip);
2709
2710 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2711
2712 if (width == MMC_8BIT_BUS) {
2713 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x08);
2714 } else {
2715 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x04);
2716 }
2717
2718 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2719 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2720
2721 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2722 SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2723 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2724 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2725 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2726 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2727
2728 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2729 if (width == MMC_8BIT_BUS) {
2730 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2731 }
2732
2733 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2734 if (retval < 0) {
2735 rtsx_clear_sd_error(chip);
2736 TRACE_RET(chip, STATUS_FAIL);
2737 }
2738
2739 ptr = rtsx_get_cmd_data(chip) + 1;
2740
2741 if (width == MMC_8BIT_BUS) {
2742 RTSX_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n", ptr[0], ptr[1]);
2743 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2744 u8 rsp[5];
2745 u32 arg;
2746
2747 if (CHK_MMC_DDR52(sd_card)) {
2748 arg = 0x03B70600;
2749 } else {
2750 arg = 0x03B70200;
2751 }
2752 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2753 if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) {
2754 return STATUS_SUCCESS;
2755 }
2756 }
2757 } else {
2758 RTSX_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2759 if (ptr[0] == 0xA5) {
2760 u8 rsp[5];
2761 u32 arg;
2762
2763 if (CHK_MMC_DDR52(sd_card)) {
2764 arg = 0x03B70500;
2765 } else {
2766 arg = 0x03B70100;
2767 }
2768 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2769 if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) {
2770 return STATUS_SUCCESS;
2771 }
2772 }
2773 }
2774
2775 TRACE_RET(chip, STATUS_FAIL);
2776}
2777
2778
2779static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr)
2780{
2781 struct sd_info *sd_card = &(chip->sd_card);
2782 int retval;
2783 u8 *ptr, card_type, card_type_mask = 0;
2784
2785 CLR_MMC_HS(sd_card);
2786
2787 RTSX_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD);
2788
2789 rtsx_init_cmd(chip);
2790
2791 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | SEND_EXT_CSD);
2792 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2793 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2794 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2795 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2796
2797 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2798 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2799 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2800 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2801
2802 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2803 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2804 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2805 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2806 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2807 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2808
2809 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2810 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2811 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2812 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2813 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2814
2815 retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2816 if (retval < 0) {
2817 if (retval == -ETIMEDOUT) {
2818 rtsx_clear_sd_error(chip);
2819 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2820 SD_RSP_TYPE_R1, NULL, 0);
2821 }
2822 TRACE_RET(chip, STATUS_FAIL);
2823 }
2824
2825 ptr = rtsx_get_cmd_data(chip);
2826 if (ptr[0] & SD_TRANSFER_ERR) {
2827 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2828 TRACE_RET(chip, STATUS_FAIL);
2829 }
2830
2831 if (CHK_MMC_SECTOR_MODE(sd_card)) {
2832 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2833 ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2834 }
2835
2836 if (CHECK_PID(chip, 0x5209)) {
2837#ifdef SUPPORT_SD_LOCK
2838 if (!(sd_card->sd_lock_status & SD_SDR_RST) &&
2839 (chip->sd_ctl & SUPPORT_MMC_DDR_MODE)) {
2840 card_type_mask = 0x07;
2841 } else {
2842 card_type_mask = 0x03;
2843 }
2844#else
2845 if (chip->sd_ctl & SUPPORT_MMC_DDR_MODE) {
2846 card_type_mask = 0x07;
2847 } else {
2848 card_type_mask = 0x03;
2849 }
2850#endif
2851 } else {
2852 card_type_mask = 0x03;
2853 }
2854 card_type = ptr[1] & card_type_mask;
2855 if (card_type) {
2856 u8 rsp[5];
2857
2858 if (card_type & 0x04) {
2859 if (switch_ddr) {
2860 SET_MMC_DDR52(sd_card);
2861 } else {
2862 SET_MMC_52M(sd_card);
2863 }
2864 } else if (card_type & 0x02) {
2865 SET_MMC_52M(sd_card);
2866 } else {
2867 SET_MMC_26M(sd_card);
2868 }
2869
2870 retval = sd_send_cmd_get_rsp(chip, SWITCH,
2871 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5);
2872 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR)) {
2873 CLR_MMC_HS(sd_card);
2874 }
2875 }
2876
2877 sd_choose_proper_clock(chip);
2878 retval = switch_clock(chip, sd_card->sd_clock);
2879 if (retval != STATUS_SUCCESS) {
2880 TRACE_RET(chip, STATUS_FAIL);
2881 }
2882
2883 if (mmc_test_switch_bus(chip, MMC_8BIT_BUS) == STATUS_SUCCESS) {
2884 SET_MMC_8BIT(sd_card);
2885 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2886#ifdef SUPPORT_SD_LOCK
2887 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2888#endif
2889 } else if (mmc_test_switch_bus(chip, MMC_4BIT_BUS) == STATUS_SUCCESS) {
2890 SET_MMC_4BIT(sd_card);
2891 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2892#ifdef SUPPORT_SD_LOCK
2893 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2894#endif
2895 } else {
2896 CLR_MMC_8BIT(sd_card);
2897 CLR_MMC_4BIT(sd_card);
2898 }
2899
2900 return STATUS_SUCCESS;
2901}
2902
2903
2904static int reset_mmc(struct rtsx_chip *chip)
2905{
2906 struct sd_info *sd_card = &(chip->sd_card);
2907 int retval, i = 0, j = 0, k = 0;
2908 int switch_ddr = 1;
2909 u8 rsp[16];
2910 u8 spec_ver = 0;
2911 u32 temp;
2912
2913#ifdef SUPPORT_SD_LOCK
2914 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2915 goto MMC_UNLOCK_ENTRY;
2916#endif
2917
2918DDR_TUNING_FAIL:
2919
2920 retval = sd_prepare_reset(chip);
2921 if (retval != STATUS_SUCCESS) {
2922 TRACE_RET(chip, retval);
2923 }
2924
2925 SET_MMC(sd_card);
2926
2927RTY_MMC_RST:
2928 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2929 if (retval != STATUS_SUCCESS) {
2930 TRACE_RET(chip, STATUS_FAIL);
2931 }
2932
2933 do {
2934 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2935 sd_set_err_code(chip, SD_NO_CARD);
2936 TRACE_RET(chip, STATUS_FAIL);
2937 }
2938
2939 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2940 (SUPPORT_VOLTAGE|0x40000000), SD_RSP_TYPE_R3, rsp, 5);
2941 if (retval != STATUS_SUCCESS) {
2942 if (sd_check_err_code(chip, SD_BUSY) || sd_check_err_code(chip, SD_TO_ERR)) {
2943 k++;
2944 if (k < 20) {
2945 sd_clr_err_code(chip);
2946 goto RTY_MMC_RST;
2947 } else {
2948 TRACE_RET(chip, STATUS_FAIL);
2949 }
2950 } else {
2951 j++;
2952 if (j < 100) {
2953 sd_clr_err_code(chip);
2954 goto RTY_MMC_RST;
2955 } else {
2956 TRACE_RET(chip, STATUS_FAIL);
2957 }
2958 }
2959 }
2960
2961 wait_timeout(20);
2962 i++;
2963 } while (!(rsp[1] & 0x80) && (i < 255));
2964
2965 if (i == 255) {
2966 TRACE_RET(chip, STATUS_FAIL);
2967 }
2968
2969 if ((rsp[1] & 0x60) == 0x40) {
2970 SET_MMC_SECTOR_MODE(sd_card);
2971 } else {
2972 CLR_MMC_SECTOR_MODE(sd_card);
2973 }
2974
2975 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2976 if (retval != STATUS_SUCCESS) {
2977 TRACE_RET(chip, STATUS_FAIL);
2978 }
2979
2980 sd_card->sd_addr = 0x00100000;
2981 retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, SD_RSP_TYPE_R6, rsp, 5);
2982 if (retval != STATUS_SUCCESS) {
2983 TRACE_RET(chip, STATUS_FAIL);
2984 }
2985
2986 retval = sd_check_csd(chip, 1);
2987 if (retval != STATUS_SUCCESS) {
2988 TRACE_RET(chip, STATUS_FAIL);
2989 }
2990
2991 spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2992
2993 retval = sd_select_card(chip, 1);
2994 if (retval != STATUS_SUCCESS) {
2995 TRACE_RET(chip, STATUS_FAIL);
2996 }
2997
2998 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2999 if (retval != STATUS_SUCCESS) {
3000 TRACE_RET(chip, STATUS_FAIL);
3001 }
3002
3003#ifdef SUPPORT_SD_LOCK
3004MMC_UNLOCK_ENTRY:
3005 retval = sd_update_lock_status(chip);
3006 if (retval != STATUS_SUCCESS) {
3007 TRACE_RET(chip, STATUS_FAIL);
3008 }
3009#endif
3010
3011 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3012 if (retval != STATUS_SUCCESS) {
3013 TRACE_RET(chip, STATUS_FAIL);
3014 }
3015
3016 chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
3017
3018 if (!sd_card->mmc_dont_switch_bus) {
3019 if (spec_ver == 4) {
3020 (void)mmc_switch_timing_bus(chip, switch_ddr);
3021 }
3022
3023 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) {
3024 TRACE_RET(chip, STATUS_FAIL);
3025 }
3026
3027 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
3028 retval = sd_set_init_para(chip);
3029 if (retval != STATUS_SUCCESS) {
3030 TRACE_RET(chip, STATUS_FAIL);
3031 }
3032
3033 retval = mmc_ddr_tuning(chip);
3034 if (retval != STATUS_SUCCESS) {
3035 retval = sd_init_power(chip);
3036 if (retval != STATUS_SUCCESS) {
3037 TRACE_RET(chip, STATUS_FAIL);
3038 }
3039 switch_ddr = 0;
3040 goto DDR_TUNING_FAIL;
3041 }
3042
3043 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3044 if (retval == STATUS_SUCCESS) {
3045 retval = sd_read_lba0(chip);
3046 if (retval != STATUS_SUCCESS) {
3047 retval = sd_init_power(chip);
3048 if (retval != STATUS_SUCCESS) {
3049 TRACE_RET(chip, STATUS_FAIL);
3050 }
3051 switch_ddr = 0;
3052 goto DDR_TUNING_FAIL;
3053 }
3054 }
3055 }
3056 }
3057
3058#ifdef SUPPORT_SD_LOCK
3059 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3060 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
3061 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
3062 }
3063#endif
3064
3065 temp = rtsx_readl(chip, RTSX_BIPR);
3066 if (temp & SD_WRITE_PROTECT) {
3067 chip->card_wp |= SD_CARD;
3068 }
3069
3070 return STATUS_SUCCESS;
3071}
3072
77d89b08 3073int reset_sd_card(struct rtsx_chip *chip)
3074{
3075 struct sd_info *sd_card = &(chip->sd_card);
3076 int retval;
3077
3078 sd_init_reg_addr(chip);
3079
2d2322b2 3080 memset(sd_card, 0, sizeof(struct sd_info));
3081 chip->capacity[chip->card2lun[SD_CARD]] = 0;
77d89b08 3082
3083 retval = enable_card_clock(chip, SD_CARD);
3084 if (retval != STATUS_SUCCESS) {
3085 TRACE_RET(chip, STATUS_FAIL);
3086 }
3087
3088 if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
3089 if (chip->asic_code) {
3090 retval = sd_pull_ctl_enable(chip);
3091 if (retval != STATUS_SUCCESS) {
3092 TRACE_RET(chip, STATUS_FAIL);
3093 }
3094 } else {
3095 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3096 FPGA_SD_PULL_CTL_BIT | 0x20, 0);
3097 if (retval != STATUS_SUCCESS) {
3098 TRACE_RET(chip, STATUS_FAIL);
3099 }
3100 }
3101 retval = card_share_mode(chip, SD_CARD);
3102 if (retval != STATUS_SUCCESS) {
3103 TRACE_RET(chip, STATUS_FAIL);
3104 }
3105
3106 chip->sd_io = 1;
3107 TRACE_RET(chip, STATUS_FAIL);
3108 }
3109
3110 retval = sd_init_power(chip);
3111 if (retval != STATUS_SUCCESS) {
3112 TRACE_RET(chip, STATUS_FAIL);
3113 }
3114
3115 if (chip->sd_ctl & RESET_MMC_FIRST) {
3116 retval = reset_mmc(chip);
3117 if ((retval != STATUS_SUCCESS) && !sd_check_err_code(chip, SD_NO_CARD)) {
3118 retval = reset_sd(chip);
3119 if (retval != STATUS_SUCCESS) {
3120 if (CHECK_PID(chip, 0x5209)) {
3121 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
3122 if (retval != STATUS_SUCCESS) {
3123 TRACE_RET(chip, STATUS_FAIL);
3124 }
3125 }
3126 }
3127 }
3128 } else {
3129 retval = reset_sd(chip);
3130 if (retval != STATUS_SUCCESS) {
3131 if (sd_check_err_code(chip, SD_NO_CARD)) {
3132 TRACE_RET(chip, STATUS_FAIL);
3133 }
3134
3135 if (CHECK_PID(chip, 0x5209)) {
3136 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
3137 if (retval != STATUS_SUCCESS) {
3138 TRACE_RET(chip, STATUS_FAIL);
3139 }
3140 }
3141
3142 if (!chip->sd_io) {
3143 retval = reset_mmc(chip);
3144 }
3145 }
3146 }
3147
3148 if (retval != STATUS_SUCCESS) {
3149 TRACE_RET(chip, STATUS_FAIL);
3150 }
3151
3152 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3153 if (retval != STATUS_SUCCESS) {
3154 TRACE_RET(chip, STATUS_FAIL);
3155 }
3156 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3157 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3158
3159 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3160
3161 retval = sd_set_init_para(chip);
3162 if (retval != STATUS_SUCCESS) {
3163 TRACE_RET(chip, STATUS_FAIL);
3164 }
3165
3166 RTSX_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3167
3168 return STATUS_SUCCESS;
3169}
3170
3171static int reset_mmc_only(struct rtsx_chip *chip)
3172{
3173 struct sd_info *sd_card = &(chip->sd_card);
3174 int retval;
3175
3176 sd_card->sd_type = 0;
3177 sd_card->seq_mode = 0;
3178 sd_card->sd_data_buf_ready = 0;
3179 sd_card->capacity = 0;
3180 sd_card->sd_switch_fail = 0;
3181
3182#ifdef SUPPORT_SD_LOCK
3183 sd_card->sd_lock_status = 0;
3184 sd_card->sd_erase_status = 0;
3185#endif
3186
3187 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3188
3189 retval = enable_card_clock(chip, SD_CARD);
3190 if (retval != STATUS_SUCCESS) {
3191 TRACE_RET(chip, STATUS_FAIL);
3192 }
3193
3194 retval = sd_init_power(chip);
3195 if (retval != STATUS_SUCCESS) {
3196 TRACE_RET(chip, STATUS_FAIL);
3197 }
3198
3199 retval = reset_mmc(chip);
3200 if (retval != STATUS_SUCCESS) {
3201 TRACE_RET(chip, STATUS_FAIL);
3202 }
3203
3204 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3205 if (retval != STATUS_SUCCESS) {
3206 TRACE_RET(chip, STATUS_FAIL);
3207 }
3208 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3209 RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3210
3211 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3212
3213 retval = sd_set_init_para(chip);
3214 if (retval != STATUS_SUCCESS) {
3215 TRACE_RET(chip, STATUS_FAIL);
3216 }
3217
3218 RTSX_DEBUGP("In reset_mmc_only, sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3219
3220 return STATUS_SUCCESS;
3221}
3222
3223#define WAIT_DATA_READY_RTY_CNT 255
3224
3225static int wait_data_buf_ready(struct rtsx_chip *chip)
3226{
3227 struct sd_info *sd_card = &(chip->sd_card);
3228 int i, retval;
3229
3230 for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3231 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3232 sd_set_err_code(chip, SD_NO_CARD);
3233 TRACE_RET(chip, STATUS_FAIL);
3234 }
3235
3236 sd_card->sd_data_buf_ready = 0;
3237
3238 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3239 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3240 if (retval != STATUS_SUCCESS) {
3241 TRACE_RET(chip, STATUS_FAIL);
3242 }
3243
3244 if (sd_card->sd_data_buf_ready) {
3245 return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3246 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3247 }
3248 }
3249
3250 sd_set_err_code(chip, SD_TO_ERR);
3251
3252 TRACE_RET(chip, STATUS_FAIL);
3253}
3254
3255void sd_stop_seq_mode(struct rtsx_chip *chip)
3256{
3257 struct sd_info *sd_card = &(chip->sd_card);
3258 int retval;
3259
3260 if (sd_card->seq_mode) {
3261 retval = sd_switch_clock(chip);
3262 if (retval != STATUS_SUCCESS) {
3263 return;
3264 }
3265
3266 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3267 SD_RSP_TYPE_R1b, NULL, 0);
3268 if (retval != STATUS_SUCCESS) {
3269 sd_set_err_code(chip, SD_STS_ERR);
3270 }
3271 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3272 if (retval != STATUS_SUCCESS) {
3273 sd_set_err_code(chip, SD_STS_ERR);
3274 }
3275 sd_card->seq_mode = 0;
3276
3277 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3278 }
3279}
3280
3281static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3282{
3283 struct sd_info *sd_card = &(chip->sd_card);
3284 int retval;
3285
3286 if (chip->asic_code) {
3287 if (sd_card->sd_clock > 30) {
3288 sd_card->sd_clock -= 20;
3289 }
3290 } else {
3291 switch (sd_card->sd_clock) {
3292 case CLK_200:
3293 sd_card->sd_clock = CLK_150;
3294 break;
3295
3296 case CLK_150:
3297 sd_card->sd_clock = CLK_120;
3298 break;
3299
3300 case CLK_120:
3301 sd_card->sd_clock = CLK_100;
3302 break;
3303
3304 case CLK_100:
3305 sd_card->sd_clock = CLK_80;
3306 break;
3307
3308 case CLK_80:
3309 sd_card->sd_clock = CLK_60;
3310 break;
3311
3312 case CLK_60:
3313 sd_card->sd_clock = CLK_50;
3314 break;
3315
3316 default:
3317 break;
3318 }
3319 }
3320
3321 retval = sd_switch_clock(chip);
3322 if (retval != STATUS_SUCCESS) {
3323 TRACE_RET(chip, STATUS_FAIL);
3324 }
3325
3326 return STATUS_SUCCESS;
3327}
3328
3329int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3330{
3331 struct sd_info *sd_card = &(chip->sd_card);
3332 u32 data_addr;
3333 u8 cfg2;
3334 int retval;
3335
3336 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3337 RTSX_DEBUGP("sd_rw: Read %d %s from 0x%x\n", sector_cnt,
3338 (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3339 } else {
3340 RTSX_DEBUGP("sd_rw: Write %d %s to 0x%x\n", sector_cnt,
3341 (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3342 }
3343
3344 sd_card->cleanup_counter = 0;
3345
3346 if (!(chip->card_ready & SD_CARD)) {
3347 sd_card->seq_mode = 0;
3348
3349 retval = reset_sd_card(chip);
3350 if (retval == STATUS_SUCCESS) {
3351 chip->card_ready |= SD_CARD;
3352 chip->card_fail &= ~SD_CARD;
3353 } else {
3354 chip->card_ready &= ~SD_CARD;
3355 chip->card_fail |= SD_CARD;
3356 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3357 chip->rw_need_retry = 1;
3358 TRACE_RET(chip, STATUS_FAIL);
3359 }
3360 }
3361
3362 if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card)) {
3363 data_addr = start_sector << 9;
3364 } else {
3365 data_addr = start_sector;
3366 }
3367
3368 sd_clr_err_code(chip);
3369
3370 retval = sd_switch_clock(chip);
3371 if (retval != STATUS_SUCCESS) {
3372 sd_set_err_code(chip, SD_IO_ERR);
3373 TRACE_GOTO(chip, RW_FAIL);
3374 }
3375
3376 if (sd_card->seq_mode && ((sd_card->pre_dir != srb->sc_data_direction)
3377 || ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != start_sector))) {
3378 if ((sd_card->pre_sec_cnt < 0x80)
3379 && (sd_card->pre_dir == DMA_FROM_DEVICE)
3380 && !CHK_SD30_SPEED(sd_card)
3381 && !CHK_SD_HS(sd_card)
3382 && !CHK_MMC_HS(sd_card)) {
3383 sd_send_cmd_get_rsp(chip, SEND_STATUS,
3384 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3385 }
3386
3387 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3388 0, SD_RSP_TYPE_R1b, NULL, 0);
3389 if (retval != STATUS_SUCCESS) {
3390 chip->rw_need_retry = 1;
3391 sd_set_err_code(chip, SD_STS_ERR);
3392 TRACE_GOTO(chip, RW_FAIL);
3393 }
3394
3395 sd_card->seq_mode = 0;
3396
3397 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3398 if (retval != STATUS_SUCCESS) {
3399 sd_set_err_code(chip, SD_IO_ERR);
3400 TRACE_GOTO(chip, RW_FAIL);
3401 }
3402
3403 if ((sd_card->pre_sec_cnt < 0x80)
3404 && !CHK_SD30_SPEED(sd_card)
3405 && !CHK_SD_HS(sd_card)
3406 && !CHK_MMC_HS(sd_card)) {
3407 sd_send_cmd_get_rsp(chip, SEND_STATUS,
3408 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3409 }
3410 }
3411
3412 rtsx_init_cmd(chip);
3413
3414 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3415 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3416 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)sector_cnt);
3417 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(sector_cnt >> 8));
3418
3419 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3420
3421 if (CHK_MMC_8BIT(sd_card)) {
3422 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3423 } else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card)) {
3424 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3425 } else {
3426 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_1);
3427 }
3428
3429 if (sd_card->seq_mode) {
3430 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3431 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3432 if (CHECK_PID(chip, 0x5209)) {
3433 if (!CHK_SD30_SPEED(sd_card)) {
3434 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3435 }
3436 }
3437 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3438
3439 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3440
3441 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3442 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3443 SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3444 } else {
3445 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3446 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3447 }
3448
3449 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3450
3451 rtsx_send_cmd_no_wait(chip);
3452 } else {
3453 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3454 RTSX_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK);
3455 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3456 0x40 | READ_MULTIPLE_BLOCK);
3457 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(data_addr >> 24));
3458 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(data_addr >> 16));
3459 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(data_addr >> 8));
3460 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)data_addr);
3461
3462 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3463 SD_CHECK_CRC7 | SD_RSP_LEN_6;
3464 if (CHECK_PID(chip, 0x5209)) {
3465 if (!CHK_SD30_SPEED(sd_card)) {
3466 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3467 }
3468 }
3469 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3470
3471 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3472
3473 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3474 SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3475 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3476 SD_TRANSFER_END, SD_TRANSFER_END);
3477
3478 rtsx_send_cmd_no_wait(chip);
3479 } else {
3480 retval = rtsx_send_cmd(chip, SD_CARD, 50);
3481 if (retval < 0) {
3482 rtsx_clear_sd_error(chip);
3483
3484 chip->rw_need_retry = 1;
3485 sd_set_err_code(chip, SD_TO_ERR);
3486 TRACE_GOTO(chip, RW_FAIL);
3487 }
3488
3489 retval = wait_data_buf_ready(chip);
3490 if (retval != STATUS_SUCCESS) {
3491 chip->rw_need_retry = 1;
3492 sd_set_err_code(chip, SD_TO_ERR);
3493 TRACE_GOTO(chip, RW_FAIL);
3494 }
3495
3496 retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3497 data_addr, SD_RSP_TYPE_R1, NULL, 0);
3498 if (retval != STATUS_SUCCESS) {
3499 chip->rw_need_retry = 1;
3500 TRACE_GOTO(chip, RW_FAIL);
3501 }
3502
3503 rtsx_init_cmd(chip);
3504
3505 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3506 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3507 if (CHECK_PID(chip, 0x5209)) {
3508 if (!CHK_SD30_SPEED(sd_card)) {
3509 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3510 }
3511 }
3512 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3513
3514 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3515
3516 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3517 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3518 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3519 SD_TRANSFER_END, SD_TRANSFER_END);
3520
3521 rtsx_send_cmd_no_wait(chip);
3522 }
3523
3524 sd_card->seq_mode = 1;
3525 }
3526
3527 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
3528 scsi_sg_count(srb), srb->sc_data_direction, chip->sd_timeout);
3529 if (retval < 0) {
3530 u8 stat = 0;
3531 int err;
3532
3533 sd_card->seq_mode = 0;
3534
3535 if (retval == -ETIMEDOUT) {
3536 err = STATUS_TIMEDOUT;
3537 } else {
3538 err = STATUS_FAIL;
3539 }
3540
3541 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3542 rtsx_clear_sd_error(chip);
3543 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3544 chip->rw_need_retry = 0;
3545 RTSX_DEBUGP("No card exist, exit sd_rw\n");
3546 TRACE_RET(chip, STATUS_FAIL);
3547 }
3548
3549 chip->rw_need_retry = 1;
3550
3551 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, SD_RSP_TYPE_R1b, NULL, 0);
3552 if (retval != STATUS_SUCCESS) {
3553 sd_set_err_code(chip, SD_STS_ERR);
3554 TRACE_GOTO(chip, RW_FAIL);
3555 }
3556
3557 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3558 RTSX_DEBUGP("SD CRC error, tune clock!\n");
3559 sd_set_err_code(chip, SD_CRC_ERR);
3560 TRACE_GOTO(chip, RW_FAIL);
3561 }
3562
3563 if (err == STATUS_TIMEDOUT) {
3564 sd_set_err_code(chip, SD_TO_ERR);
3565 TRACE_GOTO(chip, RW_FAIL);
3566 }
3567
3568 TRACE_RET(chip, err);
3569 }
3570
3571 sd_card->pre_sec_addr = start_sector;
3572 sd_card->pre_sec_cnt = sector_cnt;
3573 sd_card->pre_dir = srb->sc_data_direction;
3574
3575 return STATUS_SUCCESS;
3576
3577RW_FAIL:
3578 sd_card->seq_mode = 0;
3579
3580 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3581 chip->rw_need_retry = 0;
3582 RTSX_DEBUGP("No card exist, exit sd_rw\n");
3583 TRACE_RET(chip, STATUS_FAIL);
3584 }
3585
3586 if (sd_check_err_code(chip, SD_CRC_ERR)) {
3587 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3588 sd_card->mmc_dont_switch_bus = 1;
3589 reset_mmc_only(chip);
3590 sd_card->mmc_dont_switch_bus = 0;
3591 } else {
3592 sd_card->need_retune = 1;
3593 sd_auto_tune_clock(chip);
3594 }
3595 } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3596 retval = reset_sd_card(chip);
3597 if (retval != STATUS_SUCCESS) {
3598 chip->card_ready &= ~SD_CARD;
3599 chip->card_fail |= SD_CARD;
3600 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3601 }
3602 }
3603
3604 TRACE_RET(chip, STATUS_FAIL);
3605}
3606
3607#ifdef SUPPORT_CPRM
3608int soft_reset_sd_card(struct rtsx_chip *chip)
3609{
3610 return reset_sd(chip);
3611}
3612
3613int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
3614 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check)
3615{
3616 int retval;
3617 int timeout = 100;
3618 u16 reg_addr;
3619 u8 *ptr;
3620 int stat_idx = 0;
3621 int rty_cnt = 0;
3622
3623 RTSX_DEBUGP("EXT SD/MMC CMD %d\n", cmd_idx);
3624
3625 if (rsp_type == SD_RSP_TYPE_R1b) {
3626 timeout = 3000;
3627 }
3628
3629RTY_SEND_CMD:
3630
3631 rtsx_init_cmd(chip);
3632
3633 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3634 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3635 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3636 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3637 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3638
3639 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3640 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3641 0x01, PINGPONG_BUFFER);
3642 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3643 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3644 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3645
3646 if (rsp_type == SD_RSP_TYPE_R2) {
3647 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
3648 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3649 }
3650 stat_idx = 17;
3651 } else if (rsp_type != SD_RSP_TYPE_R0) {
3652 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
3653 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3654 }
3655 stat_idx = 6;
3656 }
3657 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3658
3659 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3660
3661 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3662 if (retval < 0) {
3663 if (retval == -ETIMEDOUT) {
3664 rtsx_clear_sd_error(chip);
3665
3666 if (rsp_type & SD_WAIT_BUSY_END) {
3667 retval = sd_check_data0_status(chip);
3668 if (retval != STATUS_SUCCESS) {
3669 TRACE_RET(chip, retval);
3670 }
3671 } else {
3672 sd_set_err_code(chip, SD_TO_ERR);
3673 }
3674 }
3675 TRACE_RET(chip, STATUS_FAIL);
3676 }
3677
3678 if (rsp_type == SD_RSP_TYPE_R0) {
3679 return STATUS_SUCCESS;
3680 }
3681
3682 ptr = rtsx_get_cmd_data(chip) + 1;
3683
3684 if ((ptr[0] & 0xC0) != 0) {
3685 sd_set_err_code(chip, SD_STS_ERR);
3686 TRACE_RET(chip, STATUS_FAIL);
3687 }
3688
3689 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3690 if (ptr[stat_idx] & SD_CRC7_ERR) {
3691 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3692 sd_set_err_code(chip, SD_CRC_ERR);
3693 TRACE_RET(chip, STATUS_FAIL);
3694 }
3695 if (rty_cnt < SD_MAX_RETRY_COUNT) {
3696 wait_timeout(20);
3697 rty_cnt++;
3698 goto RTY_SEND_CMD;
3699 } else {
3700 sd_set_err_code(chip, SD_CRC_ERR);
3701 TRACE_RET(chip, STATUS_FAIL);
3702 }
3703 }
3704 }
3705
3706 if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3707 (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3708 if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) {
3709 if (ptr[1] & 0x80) {
3710 TRACE_RET(chip, STATUS_FAIL);
3711 }
3712 }
3713#ifdef SUPPORT_SD_LOCK
3714 if (ptr[1] & 0x7D)
3715#else
3716 if (ptr[1] & 0x7F)
3717#endif
3718 {
3719 TRACE_RET(chip, STATUS_FAIL);
3720 }
3721 if (ptr[2] & 0xF8) {
3722 TRACE_RET(chip, STATUS_FAIL);
3723 }
3724
3725 if (cmd_idx == SELECT_CARD) {
3726 if (rsp_type == SD_RSP_TYPE_R2) {
3727 if ((ptr[3] & 0x1E) != 0x04) {
3728 TRACE_RET(chip, STATUS_FAIL);
3729 }
3730 } else if (rsp_type == SD_RSP_TYPE_R2) {
3731 if ((ptr[3] & 0x1E) != 0x03) {
3732 TRACE_RET(chip, STATUS_FAIL);
3733 }
3734 }
3735 }
3736 }
3737
3738 if (rsp && rsp_len) {
3739 memcpy(rsp, ptr, rsp_len);
3740 }
3741
3742 return STATUS_SUCCESS;
3743}
3744
3745int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3746{
3747 int retval, rsp_len;
3748 u16 reg_addr;
3749
3750 if (rsp_type == SD_RSP_TYPE_R0) {
3751 return STATUS_SUCCESS;
3752 }
3753
3754 rtsx_init_cmd(chip);
3755
3756 if (rsp_type == SD_RSP_TYPE_R2) {
3757 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
3758 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3759 }
3760 rsp_len = 17;
3761 } else if (rsp_type != SD_RSP_TYPE_R0) {
3762 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
3763 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3764 }
3765 rsp_len = 6;
3766 }
3767 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3768
3769 retval = rtsx_send_cmd(chip, SD_CARD, 100);
3770 if (retval != STATUS_SUCCESS) {
3771 TRACE_RET(chip, STATUS_FAIL);
3772 }
3773
3774 if (rsp) {
3775 int min_len = (rsp_len < len) ? rsp_len : len;
3776
3777 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3778
3779 RTSX_DEBUGP("min_len = %d\n", min_len);
3780 RTSX_DEBUGP("Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3781 rsp[0], rsp[1], rsp[2], rsp[3]);
3782 }
3783
3784 return STATUS_SUCCESS;
3785}
3786
3787int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3788{
3789 struct sd_info *sd_card = &(chip->sd_card);
3790 unsigned int lun = SCSI_LUN(srb);
3791 int len;
3792 u8 buf[18] = {
3793 0x00,
3794 0x00,
3795 0x00,
3796 0x0E,
3797 0x00,
3798 0x00,
3799 0x00,
3800 0x00,
3801 0x53,
3802 0x44,
3803 0x20,
3804 0x43,
3805 0x61,
3806 0x72,
3807 0x64,
3808 0x00,
3809 0x00,
3810 0x00,
3811 };
3812
3813 sd_card->pre_cmd_err = 0;
3814
3815 if (!(CHK_BIT(chip->lun_mc, lun))) {
3816 SET_BIT(chip->lun_mc, lun);
3817 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3818 TRACE_RET(chip, TRANSPORT_FAILED);
3819 }
3820
3821 if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
3822 (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
3823 (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
3824 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3825 TRACE_RET(chip, TRANSPORT_FAILED);
3826 }
3827
3828 switch (srb->cmnd[1] & 0x0F) {
3829 case 0:
3830 sd_card->sd_pass_thru_en = 0;
3831 break;
3832
3833 case 1:
3834 sd_card->sd_pass_thru_en = 1;
3835 break;
3836
3837 default:
3838 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3839 TRACE_RET(chip, TRANSPORT_FAILED);
3840 }
3841
3842 buf[5] = (1 == CHK_SD(sd_card)) ? 0x01 : 0x02;
3843 if (chip->card_wp & SD_CARD) {
3844 buf[5] |= 0x80;
3845 }
3846
3847 buf[6] = (u8)(sd_card->sd_addr >> 16);
3848 buf[7] = (u8)(sd_card->sd_addr >> 24);
3849
3850 buf[15] = chip->max_lun;
3851
3852 len = min(18, (int)scsi_bufflen(srb));
3853 rtsx_stor_set_xfer_buf(buf, len, srb);
3854
3855 return TRANSPORT_GOOD;
3856}
3857
3858static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, int *rsp_len)
3859{
3860 if (!rsp_type || !rsp_len) {
3861 return STATUS_FAIL;
3862 }
3863
3864 switch (srb->cmnd[10]) {
3865 case 0x03:
3866 *rsp_type = SD_RSP_TYPE_R0;
3867 *rsp_len = 0;
3868 break;
3869
3870 case 0x04:
3871 *rsp_type = SD_RSP_TYPE_R1;
3872 *rsp_len = 6;
3873 break;
3874
3875 case 0x05:
3876 *rsp_type = SD_RSP_TYPE_R1b;
3877 *rsp_len = 6;
3878 break;
3879
3880 case 0x06:
3881 *rsp_type = SD_RSP_TYPE_R2;
3882 *rsp_len = 17;
3883 break;
3884
3885 case 0x07:
3886 *rsp_type = SD_RSP_TYPE_R3;
3887 *rsp_len = 6;
3888 break;
3889
3890 default:
3891 return STATUS_FAIL;
3892 }
3893
3894 return STATUS_SUCCESS;
3895}
3896
3897int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3898{
3899 struct sd_info *sd_card = &(chip->sd_card);
3900 unsigned int lun = SCSI_LUN(srb);
3901 int retval, rsp_len;
3902 u8 cmd_idx, rsp_type;
3903 u8 standby = 0, acmd = 0;
3904 u32 arg;
3905
3906 if (!sd_card->sd_pass_thru_en) {
3907 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3908 TRACE_RET(chip, TRANSPORT_FAILED);
3909 }
3910
3911 retval = sd_switch_clock(chip);
3912 if (retval != STATUS_SUCCESS) {
3913 TRACE_RET(chip, TRANSPORT_FAILED);
3914 }
3915
3916 if (sd_card->pre_cmd_err) {
3917 sd_card->pre_cmd_err = 0;
3918 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3919 TRACE_RET(chip, TRANSPORT_FAILED);
3920 }
3921
3922 cmd_idx = srb->cmnd[2] & 0x3F;
3923 if (srb->cmnd[1] & 0x02) {
3924 standby = 1;
3925 }
3926 if (srb->cmnd[1] & 0x01) {
3927 acmd = 1;
3928 }
3929
3930 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3931 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3932
3933 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3934 if (retval != STATUS_SUCCESS) {
3935 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3936 TRACE_RET(chip, TRANSPORT_FAILED);
3937 }
3938 sd_card->last_rsp_type = rsp_type;
3939
3940 retval = sd_switch_clock(chip);
3941 if (retval != STATUS_SUCCESS) {
3942 TRACE_RET(chip, TRANSPORT_FAILED);
3943 }
3944
3945#ifdef SUPPORT_SD_LOCK
3946 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3947 if (CHK_MMC_8BIT(sd_card)) {
3948 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3949 if (retval != STATUS_SUCCESS) {
3950 TRACE_RET(chip, TRANSPORT_FAILED);
3951 }
3952 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3953 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3954 if (retval != STATUS_SUCCESS) {
3955 TRACE_RET(chip, TRANSPORT_FAILED);
3956 }
3957 }
3958 }
3959#else
3960 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3961 if (retval != STATUS_SUCCESS) {
3962 TRACE_RET(chip, TRANSPORT_FAILED);
3963 }
3964#endif
3965
3966 if (standby) {
3967 retval = sd_select_card(chip, 0);
3968 if (retval != STATUS_SUCCESS) {
3969 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3970 }
3971 }
3972
3973 if (acmd) {
3974 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
3975 SD_RSP_TYPE_R1, NULL, 0, 0);
3976 if (retval != STATUS_SUCCESS) {
3977 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3978 }
3979 }
3980
3981 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3982 sd_card->rsp, rsp_len, 0);
3983 if (retval != STATUS_SUCCESS) {
3984 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3985 }
3986
3987 if (standby) {
3988 retval = sd_select_card(chip, 1);
3989 if (retval != STATUS_SUCCESS) {
3990 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3991 }
3992 }
3993
3994#ifdef SUPPORT_SD_LOCK
3995 retval = sd_update_lock_status(chip);
3996 if (retval != STATUS_SUCCESS) {
3997 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3998 }
3999#endif
4000
4001 scsi_set_resid(srb, 0);
4002 return TRANSPORT_GOOD;
4003
4004SD_Execute_Cmd_Failed:
4005 sd_card->pre_cmd_err = 1;
4006 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4007 release_sd_card(chip);
4008 do_reset_sd_card(chip);
4009 if (!(chip->card_ready & SD_CARD)) {
4010 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4011 }
4012
4013 TRACE_RET(chip, TRANSPORT_FAILED);
4014}
4015
4016int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4017{
4018 struct sd_info *sd_card = &(chip->sd_card);
4019 unsigned int lun = SCSI_LUN(srb);
4020 int retval, rsp_len, i;
4021 int cmd13_checkbit = 0, read_err = 0;
4022 u8 cmd_idx, rsp_type, bus_width;
4023 u8 send_cmd12 = 0, standby = 0, acmd = 0;
4024 u32 data_len;
4025
4026 if (!sd_card->sd_pass_thru_en) {
4027 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4028 TRACE_RET(chip, TRANSPORT_FAILED);
4029 }
4030
4031 if (sd_card->pre_cmd_err) {
4032 sd_card->pre_cmd_err = 0;
4033 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4034 TRACE_RET(chip, TRANSPORT_FAILED);
4035 }
4036
4037 retval = sd_switch_clock(chip);
4038 if (retval != STATUS_SUCCESS) {
4039 TRACE_RET(chip, TRANSPORT_FAILED);
4040 }
4041
4042 cmd_idx = srb->cmnd[2] & 0x3F;
4043 if (srb->cmnd[1] & 0x04) {
4044 send_cmd12 = 1;
4045 }
4046 if (srb->cmnd[1] & 0x02) {
4047 standby = 1;
4048 }
4049 if (srb->cmnd[1] & 0x01) {
4050 acmd = 1;
4051 }
4052
4053 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4054
4055 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4056 if (retval != STATUS_SUCCESS) {
4057 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4058 TRACE_RET(chip, TRANSPORT_FAILED);
4059 }
4060 sd_card->last_rsp_type = rsp_type;
4061
4062 retval = sd_switch_clock(chip);
4063 if (retval != STATUS_SUCCESS) {
4064 TRACE_RET(chip, TRANSPORT_FAILED);
4065 }
4066
4067#ifdef SUPPORT_SD_LOCK
4068 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4069 if (CHK_MMC_8BIT(sd_card)) {
4070 bus_width = SD_BUS_WIDTH_8;
4071 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4072 bus_width = SD_BUS_WIDTH_4;
4073 } else {
4074 bus_width = SD_BUS_WIDTH_1;
4075 }
4076 } else {
4077 bus_width = SD_BUS_WIDTH_4;
4078 }
4079 RTSX_DEBUGP("bus_width = %d\n", bus_width);
4080#else
4081 bus_width = SD_BUS_WIDTH_4;
4082#endif
4083
4084 if (data_len < 512) {
4085 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4086 SD_RSP_TYPE_R1, NULL, 0, 0);
4087 if (retval != STATUS_SUCCESS) {
4088 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4089 }
4090 }
4091
4092 if (standby) {
4093 retval = sd_select_card(chip, 0);
4094 if (retval != STATUS_SUCCESS) {
4095 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4096 }
4097 }
4098
4099 if (acmd) {
4100 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4101 SD_RSP_TYPE_R1, NULL, 0, 0);
4102 if (retval != STATUS_SUCCESS) {
4103 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4104 }
4105 }
4106
4107 if (data_len <= 512) {
4108 int min_len;
4109 u8 *buf;
4110 u16 byte_cnt, blk_cnt;
4111 u8 cmd[5];
4112
4113 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4114 blk_cnt = 1;
4115
4116 cmd[0] = 0x40 | cmd_idx;
4117 cmd[1] = srb->cmnd[3];
4118 cmd[2] = srb->cmnd[4];
4119 cmd[3] = srb->cmnd[5];
4120 cmd[4] = srb->cmnd[6];
4121
4122 buf = (u8 *)kmalloc(data_len, GFP_KERNEL);
4123 if (buf == NULL) {
4124 TRACE_RET(chip, TRANSPORT_ERROR);
4125 }
4126
4127 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4128 blk_cnt, bus_width, buf, data_len, 2000);
4129 if (retval != STATUS_SUCCESS) {
4130 read_err = 1;
4131 kfree(buf);
4132 rtsx_clear_sd_error(chip);
4133 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4134 }
4135
4136 min_len = min(data_len, scsi_bufflen(srb));
4137 rtsx_stor_set_xfer_buf(buf, min_len, srb);
4138
4139 kfree(buf);
4140 } else if (!(data_len & 0x1FF)) {
4141 rtsx_init_cmd(chip);
4142
4143 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4144
4145 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4146 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4147 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4148 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4149 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4150 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4151
4152 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
4153 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, srb->cmnd[3]);
4154 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, srb->cmnd[4]);
4155 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, srb->cmnd[5]);
4156 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, srb->cmnd[6]);
4157
4158 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4159 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4160
4161 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4162 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4163 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4164
4165 rtsx_send_cmd_no_wait(chip);
4166
4167 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4168 scsi_sg_count(srb), DMA_FROM_DEVICE, 10000);
4169 if (retval < 0) {
4170 read_err = 1;
4171 rtsx_clear_sd_error(chip);
4172 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4173 }
4174
4175 } else {
4176 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4177 }
4178
4179 retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4180 if (retval != STATUS_SUCCESS) {
4181 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4182 }
4183
4184 if (standby) {
4185 retval = sd_select_card(chip, 1);
4186 if (retval != STATUS_SUCCESS) {
4187 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4188 }
4189 }
4190
4191 if (send_cmd12) {
4192 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4193 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4194 if (retval != STATUS_SUCCESS) {
4195 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4196 }
4197 }
4198
4199 if (data_len < 512) {
4200 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4201 SD_RSP_TYPE_R1, NULL, 0, 0);
4202 if (retval != STATUS_SUCCESS) {
4203 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4204 }
4205
4206 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4207 if (retval != STATUS_SUCCESS) {
4208 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4209 }
4210 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4211 if (retval != STATUS_SUCCESS) {
4212 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4213 }
4214 }
4215
4216 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) {
4217 cmd13_checkbit = 1;
4218 }
4219
4220 for (i = 0; i < 3; i++) {
4221 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4222 SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4223 if (retval == STATUS_SUCCESS) {
4224 break;
4225 }
4226 }
4227 if (retval != STATUS_SUCCESS) {
4228 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4229 }
4230
4231 scsi_set_resid(srb, 0);
4232 return TRANSPORT_GOOD;
4233
4234SD_Execute_Read_Cmd_Failed:
4235 sd_card->pre_cmd_err = 1;
4236 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4237 if (read_err) {
4238 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4239 }
4240 release_sd_card(chip);
4241 do_reset_sd_card(chip);
4242 if (!(chip->card_ready & SD_CARD)) {
4243 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4244 }
4245
4246 TRACE_RET(chip, TRANSPORT_FAILED);
4247}
4248
4249int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4250{
4251 struct sd_info *sd_card = &(chip->sd_card);
4252 unsigned int lun = SCSI_LUN(srb);
4253 int retval, rsp_len, i;
4254 int cmd13_checkbit = 0, write_err = 0;
4255 u8 cmd_idx, rsp_type;
4256 u8 send_cmd12 = 0, standby = 0, acmd = 0;
4257 u32 data_len, arg;
4258#ifdef SUPPORT_SD_LOCK
4259 int lock_cmd_fail = 0;
4260 u8 sd_lock_state = 0;
4261 u8 lock_cmd_type = 0;
4262#endif
4263
4264 if (!sd_card->sd_pass_thru_en) {
4265 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4266 TRACE_RET(chip, TRANSPORT_FAILED);
4267 }
4268
4269 if (sd_card->pre_cmd_err) {
4270 sd_card->pre_cmd_err = 0;
4271 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4272 TRACE_RET(chip, TRANSPORT_FAILED);
4273 }
4274
4275 retval = sd_switch_clock(chip);
4276 if (retval != STATUS_SUCCESS) {
4277 TRACE_RET(chip, TRANSPORT_FAILED);
4278 }
4279
4280 cmd_idx = srb->cmnd[2] & 0x3F;
4281 if (srb->cmnd[1] & 0x04) {
4282 send_cmd12 = 1;
4283 }
4284 if (srb->cmnd[1] & 0x02) {
4285 standby = 1;
4286 }
4287 if (srb->cmnd[1] & 0x01) {
4288 acmd = 1;
4289 }
4290
4291 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4292 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4293 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4294
4295#ifdef SUPPORT_SD_LOCK
4296 if (cmd_idx == LOCK_UNLOCK) {
4297 sd_lock_state = sd_card->sd_lock_status;
4298 sd_lock_state &= SD_LOCKED;
4299 }
4300#endif
4301
4302 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4303 if (retval != STATUS_SUCCESS) {
4304 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4305 TRACE_RET(chip, TRANSPORT_FAILED);
4306 }
4307 sd_card->last_rsp_type = rsp_type;
4308
4309 retval = sd_switch_clock(chip);
4310 if (retval != STATUS_SUCCESS) {
4311 TRACE_RET(chip, TRANSPORT_FAILED);
4312 }
4313
4314#ifdef SUPPORT_SD_LOCK
4315 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4316 if (CHK_MMC_8BIT(sd_card)) {
4317 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
4318 if (retval != STATUS_SUCCESS) {
4319 TRACE_RET(chip, TRANSPORT_FAILED);
4320 }
4321 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4322 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4323 if (retval != STATUS_SUCCESS) {
4324 TRACE_RET(chip, TRANSPORT_FAILED);
4325 }
4326 }
4327 }
4328#else
4329 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4330 if (retval != STATUS_SUCCESS) {
4331 TRACE_RET(chip, TRANSPORT_FAILED);
4332 }
4333#endif
4334
4335 if (data_len < 512) {
4336 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4337 SD_RSP_TYPE_R1, NULL, 0, 0);
4338 if (retval != STATUS_SUCCESS) {
4339 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4340 }
4341 }
4342
4343 if (standby) {
4344 retval = sd_select_card(chip, 0);
4345 if (retval != STATUS_SUCCESS) {
4346 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4347 }
4348 }
4349
4350 if (acmd) {
4351 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4352 SD_RSP_TYPE_R1, NULL, 0, 0);
4353 if (retval != STATUS_SUCCESS) {
4354 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4355 }
4356 }
4357
4358 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4359 sd_card->rsp, rsp_len, 0);
4360 if (retval != STATUS_SUCCESS) {
4361 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4362 }
4363
4364 if (data_len <= 512) {
4365 u16 i;
4366 u8 *buf;
4367
4368 buf = (u8 *)kmalloc(data_len, GFP_KERNEL);
4369 if (buf == NULL) {
4370 TRACE_RET(chip, TRANSPORT_ERROR);
4371 }
4372
4373 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4374
4375#ifdef SUPPORT_SD_LOCK
4376 if (cmd_idx == LOCK_UNLOCK) {
4377 lock_cmd_type = buf[0] & 0x0F;
4378 }
4379#endif
4380
4381 if (data_len > 256) {
4382 rtsx_init_cmd(chip);
4383 for (i = 0; i < 256; i++) {
4384 rtsx_add_cmd(chip, WRITE_REG_CMD,
4385 PPBUF_BASE2 + i, 0xFF, buf[i]);
4386 }
4387 retval = rtsx_send_cmd(chip, 0, 250);
4388 if (retval != STATUS_SUCCESS) {
4389 kfree(buf);
4390 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4391 }
4392
4393 rtsx_init_cmd(chip);
4394 for (i = 256; i < data_len; i++) {
4395 rtsx_add_cmd(chip, WRITE_REG_CMD,
4396 PPBUF_BASE2 + i, 0xFF, buf[i]);
4397 }
4398 retval = rtsx_send_cmd(chip, 0, 250);
4399 if (retval != STATUS_SUCCESS) {
4400 kfree(buf);
4401 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4402 }
4403 } else {
4404 rtsx_init_cmd(chip);
4405 for (i = 0; i < data_len; i++) {
4406 rtsx_add_cmd(chip, WRITE_REG_CMD,
4407 PPBUF_BASE2 + i, 0xFF, buf[i]);
4408 }
4409 retval = rtsx_send_cmd(chip, 0, 250);
4410 if (retval != STATUS_SUCCESS) {
4411 kfree(buf);
4412 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4413 }
4414 }
4415
4416 kfree(buf);
4417
4418 rtsx_init_cmd(chip);
4419
4420 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, srb->cmnd[8] & 0x03);
4421 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, srb->cmnd[9]);
4422 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0x00);
4423 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 0x01);
4424 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
4425
4426 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4427 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4428 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4429
4430 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4431 } else if (!(data_len & 0x1FF)) {
4432 rtsx_init_cmd(chip);
4433
4434 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4435
4436 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4437 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4438 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4439 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4440 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4441 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4442
4443 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4444 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4445
4446 rtsx_send_cmd_no_wait(chip);
4447
4448 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4449 scsi_sg_count(srb), DMA_TO_DEVICE, 10000);
4450
4451 } else {
4452 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4453 }
4454
4455 if (retval < 0) {
4456 write_err = 1;
4457 rtsx_clear_sd_error(chip);
4458 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4459 }
4460
4461#ifdef SUPPORT_SD_LOCK
4462 if (cmd_idx == LOCK_UNLOCK) {
4463 if (lock_cmd_type == SD_ERASE) {
4464 sd_card->sd_erase_status = SD_UNDER_ERASING;
4465 scsi_set_resid(srb, 0);
4466 return TRANSPORT_GOOD;
4467 }
4468
4469 rtsx_init_cmd(chip);
4470 if (CHECK_PID(chip, 0x5209)) {
4471 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_BUS_STAT, SD_DAT0_STATUS, SD_DAT0_STATUS);
4472 } else {
4473 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4474 }
4475 rtsx_send_cmd(chip, SD_CARD, 250);
4476
4477 retval = sd_update_lock_status(chip);
4478 if (retval != STATUS_SUCCESS) {
4479 RTSX_DEBUGP("Lock command fail!\n");
4480 lock_cmd_fail = 1;
4481 }
4482 }
4483#endif /* SUPPORT_SD_LOCK */
4484
4485 if (standby) {
4486 retval = sd_select_card(chip, 1);
4487 if (retval != STATUS_SUCCESS) {
4488 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4489 }
4490 }
4491
4492 if (send_cmd12) {
4493 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4494 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4495 if (retval != STATUS_SUCCESS) {
4496 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4497 }
4498 }
4499
4500 if (data_len < 512) {
4501 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4502 SD_RSP_TYPE_R1, NULL, 0, 0);
4503 if (retval != STATUS_SUCCESS) {
4504 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4505 }
4506
4507 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4508 if (retval != STATUS_SUCCESS) {
4509 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4510 }
4511 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4512 if (retval != STATUS_SUCCESS) {
4513 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4514 }
4515 }
4516
4517 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) {
4518 cmd13_checkbit = 1;
4519 }
4520
4521 for (i = 0; i < 3; i++) {
4522 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4523 SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4524 if (retval == STATUS_SUCCESS) {
4525 break;
4526 }
4527 }
4528 if (retval != STATUS_SUCCESS) {
4529 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4530 }
4531
4532#ifdef SUPPORT_SD_LOCK
4533 if (cmd_idx == LOCK_UNLOCK) {
4534 if (!lock_cmd_fail) {
4535 RTSX_DEBUGP("lock_cmd_type = 0x%x\n", lock_cmd_type);
4536 if (lock_cmd_type & SD_CLR_PWD) {
4537 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4538 }
4539 if (lock_cmd_type & SD_SET_PWD) {
4540 sd_card->sd_lock_status |= SD_PWD_EXIST;
4541 }
4542 }
4543
4544 RTSX_DEBUGP("sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4545 sd_lock_state, sd_card->sd_lock_status);
4546 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4547 sd_card->sd_lock_notify = 1;
4548 if (sd_lock_state) {
4549 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4550 sd_card->sd_lock_status |= (SD_UNLOCK_POW_ON | SD_SDR_RST);
4551 if (CHK_SD(sd_card)) {
4552 retval = reset_sd(chip);
4553 if (retval != STATUS_SUCCESS) {
4554 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4555 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4556 }
4557 }
4558
4559 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4560 }
4561 }
4562 }
4563 }
4564
4565 if (lock_cmd_fail) {
4566 scsi_set_resid(srb, 0);
4567 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4568 TRACE_RET(chip, TRANSPORT_FAILED);
4569 }
4570#endif /* SUPPORT_SD_LOCK */
4571
4572 scsi_set_resid(srb, 0);
4573 return TRANSPORT_GOOD;
4574
4575SD_Execute_Write_Cmd_Failed:
4576 sd_card->pre_cmd_err = 1;
4577 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4578 if (write_err) {
4579 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4580 }
4581 release_sd_card(chip);
4582 do_reset_sd_card(chip);
4583 if (!(chip->card_ready & SD_CARD)) {
4584 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4585 }
4586
4587 TRACE_RET(chip, TRANSPORT_FAILED);
4588}
4589
4590int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4591{
4592 struct sd_info *sd_card = &(chip->sd_card);
4593 unsigned int lun = SCSI_LUN(srb);
4594 int count;
4595 u16 data_len;
4596
4597 if (!sd_card->sd_pass_thru_en) {
4598 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4599 TRACE_RET(chip, TRANSPORT_FAILED);
4600 }
4601
4602 if (sd_card->pre_cmd_err) {
4603 sd_card->pre_cmd_err = 0;
4604 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4605 TRACE_RET(chip, TRANSPORT_FAILED);
4606 }
4607
4608 data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4609
4610 if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4611 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4612 TRACE_RET(chip, TRANSPORT_FAILED);
4613 } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4614 count = (data_len < 17) ? data_len : 17;
4615 } else {
4616 count = (data_len < 6) ? data_len : 6;
4617 }
4618 rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4619
4620 RTSX_DEBUGP("Response length: %d\n", data_len);
4621 RTSX_DEBUGP("Response: 0x%x 0x%x 0x%x 0x%x\n",
4622 sd_card->rsp[0], sd_card->rsp[1], sd_card->rsp[2], sd_card->rsp[3]);
4623
4624 scsi_set_resid(srb, 0);
4625 return TRANSPORT_GOOD;
4626}
4627
4628int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4629{
4630 struct sd_info *sd_card = &(chip->sd_card);
4631 unsigned int lun = SCSI_LUN(srb);
4632 int retval;
4633
4634 if (!sd_card->sd_pass_thru_en) {
4635 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4636 TRACE_RET(chip, TRANSPORT_FAILED);
4637 }
4638
4639 if (sd_card->pre_cmd_err) {
4640 sd_card->pre_cmd_err = 0;
4641 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4642 TRACE_RET(chip, TRANSPORT_FAILED);
4643 }
4644
4645 if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
4646 (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
4647 (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
4648 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4649 TRACE_RET(chip, TRANSPORT_FAILED);
4650 }
4651
4652 switch (srb->cmnd[1] & 0x0F) {
4653 case 0:
4654#ifdef SUPPORT_SD_LOCK
4655 if (0x64 == srb->cmnd[9]) {
4656 sd_card->sd_lock_status |= SD_SDR_RST;
4657 }
4658#endif
4659 retval = reset_sd_card(chip);
4660 if (retval != STATUS_SUCCESS) {
4661#ifdef SUPPORT_SD_LOCK
4662 sd_card->sd_lock_status &= ~SD_SDR_RST;
4663#endif
4664 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4665 sd_card->pre_cmd_err = 1;
4666 TRACE_RET(chip, TRANSPORT_FAILED);
4667 }
4668#ifdef SUPPORT_SD_LOCK
4669 sd_card->sd_lock_status &= ~SD_SDR_RST;
4670#endif
4671 break;
4672
4673 case 1:
4674 retval = soft_reset_sd_card(chip);
4675 if (retval != STATUS_SUCCESS) {
4676 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4677 sd_card->pre_cmd_err = 1;
4678 TRACE_RET(chip, TRANSPORT_FAILED);
4679 }
4680 break;
4681
4682 default:
4683 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4684 TRACE_RET(chip, TRANSPORT_FAILED);
4685 }
4686
4687 scsi_set_resid(srb, 0);
4688 return TRANSPORT_GOOD;
4689}
4690#endif
4691
4692void sd_cleanup_work(struct rtsx_chip *chip)
4693{
4694 struct sd_info *sd_card = &(chip->sd_card);
4695
4696 if (sd_card->seq_mode) {
4697 RTSX_DEBUGP("SD: stop transmission\n");
4698 sd_stop_seq_mode(chip);
4699 sd_card->cleanup_counter = 0;
4700 }
4701}
4702
4703int sd_power_off_card3v3(struct rtsx_chip *chip)
4704{
4705 int retval;
4706
4707 retval = disable_card_clock(chip, SD_CARD);
4708 if (retval != STATUS_SUCCESS) {
4709 TRACE_RET(chip, STATUS_FAIL);
4710 }
4711
4712 RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0);
4713
4714 if (!chip->ft2_fast_mode) {
4715 retval = card_power_off(chip, SD_CARD);
4716 if (retval != STATUS_SUCCESS) {
4717 TRACE_RET(chip, STATUS_FAIL);
4718 }
4719
4720 wait_timeout(50);
4721 }
4722
4723 if (chip->asic_code) {
4724 retval = sd_pull_ctl_disable(chip);
4725 if (retval != STATUS_SUCCESS) {
4726 TRACE_RET(chip, STATUS_FAIL);
4727 }
4728 } else {
4729 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4730 FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT);
4731 }
4732
4733 return STATUS_SUCCESS;
4734}
4735
4736int release_sd_card(struct rtsx_chip *chip)
4737{
4738 struct sd_info *sd_card = &(chip->sd_card);
4739 int retval;
4740
4741 RTSX_DEBUGP("release_sd_card\n");
4742
4743 chip->card_ready &= ~SD_CARD;
4744 chip->card_fail &= ~SD_CARD;
4745 chip->card_wp &= ~SD_CARD;
4746
4747 chip->sd_io = 0;
4748 chip->sd_int = 0;
4749
4750#ifdef SUPPORT_SD_LOCK
4751 sd_card->sd_lock_status = 0;
4752 sd_card->sd_erase_status = 0;
4753#endif
4754
4755 memset(sd_card->raw_csd, 0, 16);
4756 memset(sd_card->raw_scr, 0, 8);
4757
4758 retval = sd_power_off_card3v3(chip);
4759 if (retval != STATUS_SUCCESS) {
4760 TRACE_RET(chip, STATUS_FAIL);
4761 }
4762
4763 if (CHECK_PID(chip, 0x5209)) {
4764 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
4765 if (retval != STATUS_SUCCESS) {
4766 TRACE_RET(chip, STATUS_FAIL);
4767 }
4768
4769 if (CHK_SD30_SPEED(sd_card)) {
4770 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3);
4771 }
4772
4773 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_400mA_ocp_thd);
4774 }
4775
4776 return STATUS_SUCCESS;
4777}
Linux kernel - Deliverables
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