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i40e: Implement ndo_features_check()
[deliverable/linux.git] / drivers / staging / slicoss / slicoss.c
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4d6f6af8
GKH		 1/**************************************************************************
2 *
3 * Copyright 2000-2006 Alacritech, Inc. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above
12 * copyright notice, this list of conditions and the following
13 * disclaimer in the documentation and/or other materials provided
14 * with the distribution.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") version 2 as published by the Free
18 * Software Foundation.
19 *
20 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * The views and conclusions contained in the software and documentation
34 * are those of the authors and should not be interpreted as representing
35 * official policies, either expressed or implied, of Alacritech, Inc.
36 *
37 **************************************************************************/
38
39/*
40 * FILENAME: slicoss.c
41 *
42 * The SLICOSS driver for Alacritech's IS-NIC products.
43 *
44 * This driver is supposed to support:
45 *
46 * Mojave cards (single port PCI Gigabit) both copper and fiber
47 * Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
48 * Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
49 *
493b67b7 50 * The driver was actually tested on Oasis and Kalahari cards.
4d6f6af8
GKH		 51 *
52 *
53 * NOTE: This is the standard, non-accelerated version of Alacritech's
54 * IS-NIC driver.
55 */
56
4d6f6af8 57
4d6f6af8
GKH		 58#define KLUDGE_FOR_4GB_BOUNDARY 1
59#define DEBUG_MICROCODE 1
4d6f6af8 60#define DBG 1
4d6f6af8 61#define SLIC_INTERRUPT_PROCESS_LIMIT 1
4d6f6af8
GKH		 62#define SLIC_OFFLOAD_IP_CHECKSUM 1
63#define STATS_TIMER_INTERVAL 2
64#define PING_TIMER_INTERVAL 1
1f6876cf 65#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4d6f6af8
GKH		 66
67#include <linux/kernel.h>
68#include <linux/string.h>
69#include <linux/errno.h>
70#include <linux/ioport.h>
71#include <linux/slab.h>
72#include <linux/interrupt.h>
73#include <linux/timer.h>
74#include <linux/pci.h>
75#include <linux/spinlock.h>
76#include <linux/init.h>
77#include <linux/bitops.h>
78#include <linux/io.h>
79#include <linux/netdevice.h>
97b3e0ed 80#include <linux/crc32.h>
4d6f6af8
GKH		 81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/delay.h>
4d6f6af8
GKH		 84#include <linux/seq_file.h>
85#include <linux/kthread.h>
86#include <linux/module.h>
4d6f6af8 87
470c5736 88#include <linux/firmware.h>
4d6f6af8 89#include <linux/types.h>
4d6f6af8 90#include <linux/dma-mapping.h>
4d6f6af8
GKH		 91#include <linux/mii.h>
92#include <linux/if_vlan.h>
4d6f6af8
GKH		 93#include <asm/unaligned.h>
94
95#include <linux/ethtool.h>
4d6f6af8 96#include <linux/uaccess.h>
77faefa3
GKH		 97#include "slichw.h"
98#include "slic.h"
99
4d6f6af8 100static uint slic_first_init = 1;
1cd0989e 101static char *slic_banner = "Alacritech SLIC Technology(tm) Server and Storage Accelerator (Non-Accelerated)";
4d6f6af8
GKH		 102
103static char *slic_proc_version = "2.0.351 2006/07/14 12:26:00";
4d6f6af8 104
e9eff9d6 105static struct base_driver slic_global = { {}, 0, 0, 0, 1, NULL, NULL };
4d6f6af8
GKH		 106static int intagg_delay = 100;
107static u32 dynamic_intagg;
4d6f6af8 108static unsigned int rcv_count;
4d6f6af8
GKH		 109
110#define DRV_NAME "slicoss"
111#define DRV_VERSION "2.0.1"
112#define DRV_AUTHOR "Alacritech, Inc. Engineering"
113#define DRV_DESCRIPTION "Alacritech SLIC Techonology(tm) "\
114 "Non-Accelerated Driver"
115#define DRV_COPYRIGHT "Copyright 2000-2006 Alacritech, Inc. "\
116 "All rights reserved."
117#define PFX DRV_NAME " "
118
119MODULE_AUTHOR(DRV_AUTHOR);
120MODULE_DESCRIPTION(DRV_DESCRIPTION);
121MODULE_LICENSE("Dual BSD/GPL");
122
123module_param(dynamic_intagg, int, 0);
124MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting");
125module_param(intagg_delay, int, 0);
126MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay");
127
41e043fc 128static const struct pci_device_id slic_pci_tbl[] = {
5d372900 129 { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_1GB_DEVICE_ID) },
130 { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_2GB_DEVICE_ID) },
131 { 0 }
4d6f6af8
GKH		 132};
133
134MODULE_DEVICE_TABLE(pci, slic_pci_tbl);
135
62f691a3 136static inline void slic_reg32_write(void __iomem *reg, u32 value, bool flush)
4d6f6af8
GKH		 137{
138 writel(value, reg);
139 if (flush)
140 mb();
141}
142
28980a3c
GKH		 143static inline void slic_reg64_write(struct adapter *adapter, void __iomem *reg,
144 u32 value, void __iomem *regh, u32 paddrh,
145 bool flush)
4d6f6af8 146{
eafe6002
DM		 147 unsigned long flags;
148
149 spin_lock_irqsave(&adapter->bit64reglock, flags);
36bf51ac 150 writel(paddrh, regh);
4d6f6af8
GKH		 151 writel(value, reg);
152 if (flush)
153 mb();
eafe6002 154 spin_unlock_irqrestore(&adapter->bit64reglock, flags);
4d6f6af8
GKH		 155}
156
4d6ea9c3
DK		 157static void slic_mcast_set_bit(struct adapter *adapter, char *address)
158{
159 unsigned char crcpoly;
4d6f6af8 160
4d6ea9c3 161 /* Get the CRC polynomial for the mac address */
97b3e0ed
PH		 162 /* we use bits 1-8 (lsb), bitwise reversed,
163 * msb (= lsb bit 0 before bitrev) is automatically discarded */
a659b3e8 164 crcpoly = ether_crc(ETH_ALEN, address)>>23;
4d6f6af8 165
4d6ea9c3
DK		 166 /* We only have space on the SLIC for 64 entries. Lop
167 * off the top two bits. (2^6 = 64)
168 */
169 crcpoly &= 0x3F;
4d6f6af8 170
4d6ea9c3
DK		 171 /* OR in the new bit into our 64 bit mask. */
172 adapter->mcastmask |= (u64) 1 << crcpoly;
173}
4d6f6af8 174
4d6ea9c3
DK		 175static void slic_mcast_set_mask(struct adapter *adapter)
176{
177 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
4d6f6af8 178
4d6ea9c3
DK		 179 if (adapter->macopts & (MAC_ALLMCAST | MAC_PROMISC)) {
180 /* Turn on all multicast addresses. We have to do this for
181 * promiscuous mode as well as ALLMCAST mode. It saves the
182 * Microcode from having to keep state about the MAC
183 * configuration.
184 */
185 slic_reg32_write(&slic_regs->slic_mcastlow, 0xFFFFFFFF, FLUSH);
186 slic_reg32_write(&slic_regs->slic_mcasthigh, 0xFFFFFFFF,
187 FLUSH);
188 } else {
189 /* Commit our multicast mast to the SLIC by writing to the
190 * multicast address mask registers
191 */
192 slic_reg32_write(&slic_regs->slic_mcastlow,
193 (u32)(adapter->mcastmask & 0xFFFFFFFF), FLUSH);
194 slic_reg32_write(&slic_regs->slic_mcasthigh,
195 (u32)((adapter->mcastmask >> 32) & 0xFFFFFFFF), FLUSH);
4d6f6af8 196 }
4d6ea9c3 197}
4d6f6af8 198
4d6ea9c3
DK		 199static void slic_timer_ping(ulong dev)
200{
201 struct adapter *adapter;
202 struct sliccard *card;
4d6f6af8 203
4d6ea9c3 204 adapter = netdev_priv((struct net_device *)dev);
4d6f6af8
GKH		 205 card = adapter->card;
206
4d6ea9c3
DK		 207 adapter->pingtimer.expires = jiffies + (PING_TIMER_INTERVAL * HZ);
208 add_timer(&adapter->pingtimer);
209}
4d6f6af8 210
4d6ea9c3
DK		 211static void slic_unmap_mmio_space(struct adapter *adapter)
212{
213 if (adapter->slic_regs)
214 iounmap(adapter->slic_regs);
215 adapter->slic_regs = NULL;
216}
4d6f6af8 217
4d6ea9c3
DK		 218/*
219 * slic_link_config
220 *
221 * Write phy control to configure link duplex/speed
222 *
223 */
224static void slic_link_config(struct adapter *adapter,
225 u32 linkspeed, u32 linkduplex)
226{
227 u32 __iomem *wphy;
228 u32 speed;
229 u32 duplex;
230 u32 phy_config;
231 u32 phy_advreg;
232 u32 phy_gctlreg;
4d6f6af8 233
4d6ea9c3
DK		 234 if (adapter->state != ADAPT_UP)
235 return;
4d6f6af8 236
4d6ea9c3
DK		 237 if (linkspeed > LINK_1000MB)
238 linkspeed = LINK_AUTOSPEED;
239 if (linkduplex > LINK_AUTOD)
240 linkduplex = LINK_AUTOD;
4d6f6af8 241
4d6ea9c3 242 wphy = &adapter->slic_regs->slic_wphy;
4d6f6af8 243
4d6ea9c3
DK		 244 if ((linkspeed == LINK_AUTOSPEED) || (linkspeed == LINK_1000MB)) {
245 if (adapter->flags & ADAPT_FLAGS_FIBERMEDIA) {
246 /* We've got a fiber gigabit interface, and register
247 * 4 is different in fiber mode than in copper mode
248 */
4d6f6af8 249
4d6ea9c3
DK		 250 /* advertise FD only @1000 Mb */
251 phy_advreg = (MIICR_REG_4 | (PAR_ADV1000XFD));
252 /* enable PAUSE frames */
253 phy_advreg |= PAR_ASYMPAUSE_FIBER;
254 slic_reg32_write(wphy, phy_advreg, FLUSH);
4d6f6af8 255
4d6ea9c3
DK		 256 if (linkspeed == LINK_AUTOSPEED) {
257 /* reset phy, enable auto-neg */
258 phy_config =
259 (MIICR_REG_PCR |
260 (PCR_RESET | PCR_AUTONEG |
261 PCR_AUTONEG_RST));
262 slic_reg32_write(wphy, phy_config, FLUSH);
263 } else { /* forced 1000 Mb FD*/
264 /* power down phy to break link
265 this may not work) */
266 phy_config = (MIICR_REG_PCR | PCR_POWERDOWN);
267 slic_reg32_write(wphy, phy_config, FLUSH);
268 /* wait, Marvell says 1 sec,
269 try to get away with 10 ms */
270 mdelay(10);
4d6f6af8 271
4d6ea9c3
DK		 272 /* disable auto-neg, set speed/duplex,
273 soft reset phy, powerup */
274 phy_config =
275 (MIICR_REG_PCR |
276 (PCR_RESET | PCR_SPEED_1000 |
277 PCR_DUPLEX_FULL));
278 slic_reg32_write(wphy, phy_config, FLUSH);
279 }
280 } else { /* copper gigabit */
4d6f6af8 281
4d6ea9c3
DK		 282 /* Auto-Negotiate or 1000 Mb must be auto negotiated
283 * We've got a copper gigabit interface, and
284 * register 4 is different in copper mode than
285 * in fiber mode
286 */
287 if (linkspeed == LINK_AUTOSPEED) {
288 /* advertise 10/100 Mb modes */
289 phy_advreg =
290 (MIICR_REG_4 |
291 (PAR_ADV100FD | PAR_ADV100HD | PAR_ADV10FD
292 | PAR_ADV10HD));
293 } else {
294 /* linkspeed == LINK_1000MB -
295 don't advertise 10/100 Mb modes */
296 phy_advreg = MIICR_REG_4;
297 }
298 /* enable PAUSE frames */
299 phy_advreg |= PAR_ASYMPAUSE;
300 /* required by the Cicada PHY */
301 phy_advreg |= PAR_802_3;
302 slic_reg32_write(wphy, phy_advreg, FLUSH);
303 /* advertise FD only @1000 Mb */
304 phy_gctlreg = (MIICR_REG_9 | (PGC_ADV1000FD));
305 slic_reg32_write(wphy, phy_gctlreg, FLUSH);
4d6f6af8 306
4d6ea9c3
DK		 307 if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
308 /* if a Marvell PHY
309 enable auto crossover */
310 phy_config =
311 (MIICR_REG_16 | (MRV_REG16_XOVERON));
312 slic_reg32_write(wphy, phy_config, FLUSH);
4d6f6af8 313
4d6ea9c3
DK		 314 /* reset phy, enable auto-neg */
315 phy_config =
316 (MIICR_REG_PCR |
317 (PCR_RESET | PCR_AUTONEG |
318 PCR_AUTONEG_RST));
319 slic_reg32_write(wphy, phy_config, FLUSH);
320 } else { /* it's a Cicada PHY */
321 /* enable and restart auto-neg (don't reset) */
322 phy_config =
323 (MIICR_REG_PCR |
324 (PCR_AUTONEG | PCR_AUTONEG_RST));
325 slic_reg32_write(wphy, phy_config, FLUSH);
326 }
4d6f6af8 327 }
4d6ea9c3
DK		 328 } else {
329 /* Forced 10/100 */
330 if (linkspeed == LINK_10MB)
331 speed = 0;
332 else
333 speed = PCR_SPEED_100;
334 if (linkduplex == LINK_HALFD)
335 duplex = 0;
336 else
337 duplex = PCR_DUPLEX_FULL;
338
339 if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
340 /* if a Marvell PHY
341 disable auto crossover */
342 phy_config = (MIICR_REG_16 | (MRV_REG16_XOVEROFF));
343 slic_reg32_write(wphy, phy_config, FLUSH);
4d6f6af8 344 }
4d6f6af8 345
4d6ea9c3
DK		 346 /* power down phy to break link (this may not work) */
347 phy_config = (MIICR_REG_PCR | (PCR_POWERDOWN | speed | duplex));
348 slic_reg32_write(wphy, phy_config, FLUSH);
4d6f6af8 349
4d6ea9c3
DK		 350 /* wait, Marvell says 1 sec, try to get away with 10 ms */
351 mdelay(10);
352
353 if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
354 /* if a Marvell PHY
355 disable auto-neg, set speed,
356 soft reset phy, powerup */
357 phy_config =
358 (MIICR_REG_PCR | (PCR_RESET | speed | duplex));
359 slic_reg32_write(wphy, phy_config, FLUSH);
360 } else { /* it's a Cicada PHY */
361 /* disable auto-neg, set speed, powerup */
362 phy_config = (MIICR_REG_PCR | (speed | duplex));
363 slic_reg32_write(wphy, phy_config, FLUSH);
364 }
365 }
4d6f6af8
GKH		 366}
367
4d6ea9c3 368static int slic_card_download_gbrcv(struct adapter *adapter)
4d6f6af8 369{
4d6ea9c3
DK		 370 const struct firmware *fw;
371 const char *file = "";
372 int ret;
373 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
374 u32 codeaddr;
375 u32 instruction;
376 int index = 0;
377 u32 rcvucodelen = 0;
4d6f6af8 378
4d6ea9c3
DK		 379 switch (adapter->devid) {
380 case SLIC_2GB_DEVICE_ID:
381 file = "slicoss/oasisrcvucode.sys";
382 break;
383 case SLIC_1GB_DEVICE_ID:
384 file = "slicoss/gbrcvucode.sys";
385 break;
386 default:
651d4bc7 387 return -ENOENT;
4d6ea9c3 388 }
4d6f6af8 389
4d6ea9c3
DK		 390 ret = request_firmware(&fw, file, &adapter->pcidev->dev);
391 if (ret) {
392 dev_err(&adapter->pcidev->dev,
811e843d 393 "Failed to load firmware %s\n", file);
4d6ea9c3 394 return ret;
786ed801 395 }
4d6ea9c3
DK		 396
397 rcvucodelen = *(u32 *)(fw->data + index);
398 index += 4;
399 switch (adapter->devid) {
400 case SLIC_2GB_DEVICE_ID:
7ee34ab2
DN		 401 if (rcvucodelen != OasisRcvUCodeLen) {
402 release_firmware(fw);
4d6ea9c3 403 return -EINVAL;
7ee34ab2 404 }
4d6ea9c3
DK		 405 break;
406 case SLIC_1GB_DEVICE_ID:
7ee34ab2
DN		 407 if (rcvucodelen != GBRcvUCodeLen) {
408 release_firmware(fw);
4d6ea9c3 409 return -EINVAL;
7ee34ab2 410 }
4d6ea9c3 411 break;
4d6f6af8 412 }
4d6ea9c3
DK		 413 /* start download */
414 slic_reg32_write(&slic_regs->slic_rcv_wcs, SLIC_RCVWCS_BEGIN, FLUSH);
415 /* download the rcv sequencer ucode */
416 for (codeaddr = 0; codeaddr < rcvucodelen; codeaddr++) {
417 /* write out instruction address */
418 slic_reg32_write(&slic_regs->slic_rcv_wcs, codeaddr, FLUSH);
419
420 instruction = *(u32 *)(fw->data + index);
421 index += 4;
422 /* write out the instruction data low addr */
423 slic_reg32_write(&slic_regs->slic_rcv_wcs, instruction, FLUSH);
424
425 instruction = *(u8 *)(fw->data + index);
426 index++;
427 /* write out the instruction data high addr */
428 slic_reg32_write(&slic_regs->slic_rcv_wcs, (u8)instruction,
429 FLUSH);
430 }
431
432 /* download finished */
433 release_firmware(fw);
434 slic_reg32_write(&slic_regs->slic_rcv_wcs, SLIC_RCVWCS_FINISH, FLUSH);
435 return 0;
4d6f6af8
GKH		 436}
437
4d6ea9c3
DK		 438MODULE_FIRMWARE("slicoss/oasisrcvucode.sys");
439MODULE_FIRMWARE("slicoss/gbrcvucode.sys");
440
441static int slic_card_download(struct adapter *adapter)
4d6f6af8 442{
4d6ea9c3
DK		 443 const struct firmware *fw;
444 const char *file = "";
445 int ret;
446 u32 section;
447 int thissectionsize;
448 int codeaddr;
e9eff9d6 449 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
4d6ea9c3
DK		 450 u32 instruction;
451 u32 baseaddress;
452 u32 i;
453 u32 numsects = 0;
454 u32 sectsize[3];
455 u32 sectstart[3];
456 int ucode_start, index = 0;
4d6f6af8 457
4d6ea9c3
DK		 458 switch (adapter->devid) {
459 case SLIC_2GB_DEVICE_ID:
460 file = "slicoss/oasisdownload.sys";
461 break;
462 case SLIC_1GB_DEVICE_ID:
463 file = "slicoss/gbdownload.sys";
464 break;
465 default:
670d145a 466 return -ENOENT;
4d6f6af8 467 }
4d6ea9c3
DK		 468 ret = request_firmware(&fw, file, &adapter->pcidev->dev);
469 if (ret) {
470 dev_err(&adapter->pcidev->dev,
811e843d 471 "Failed to load firmware %s\n", file);
4d6ea9c3
DK		 472 return ret;
473 }
474 numsects = *(u32 *)(fw->data + index);
475 index += 4;
4d6ea9c3
DK		 476 for (i = 0; i < numsects; i++) {
477 sectsize[i] = *(u32 *)(fw->data + index);
478 index += 4;
479 }
480 for (i = 0; i < numsects; i++) {
481 sectstart[i] = *(u32 *)(fw->data + index);
482 index += 4;
483 }
484 ucode_start = index;
485 instruction = *(u32 *)(fw->data + index);
486 index += 4;
487 for (section = 0; section < numsects; section++) {
488 baseaddress = sectstart[section];
489 thissectionsize = sectsize[section] >> 3;
4d6f6af8 490
4d6ea9c3
DK		 491 for (codeaddr = 0; codeaddr < thissectionsize; codeaddr++) {
492 /* Write out instruction address */
493 slic_reg32_write(&slic_regs->slic_wcs,
494 baseaddress + codeaddr, FLUSH);
495 /* Write out instruction to low addr */
17d2c643
SC		 496 slic_reg32_write(&slic_regs->slic_wcs,
497 instruction, FLUSH);
4d6ea9c3
DK		 498 instruction = *(u32 *)(fw->data + index);
499 index += 4;
500
501 /* Write out instruction to high addr */
17d2c643
SC		 502 slic_reg32_write(&slic_regs->slic_wcs,
503 instruction, FLUSH);
4d6ea9c3
DK		 504 instruction = *(u32 *)(fw->data + index);
505 index += 4;
506 }
507 }
508 index = ucode_start;
509 for (section = 0; section < numsects; section++) {
510 instruction = *(u32 *)(fw->data + index);
511 baseaddress = sectstart[section];
512 if (baseaddress < 0x8000)
513 continue;
514 thissectionsize = sectsize[section] >> 3;
515
516 for (codeaddr = 0; codeaddr < thissectionsize; codeaddr++) {
517 /* Write out instruction address */
518 slic_reg32_write(&slic_regs->slic_wcs,
519 SLIC_WCS_COMPARE | (baseaddress + codeaddr),
520 FLUSH);
521 /* Write out instruction to low addr */
522 slic_reg32_write(&slic_regs->slic_wcs, instruction,
523 FLUSH);
524 instruction = *(u32 *)(fw->data + index);
525 index += 4;
526 /* Write out instruction to high addr */
527 slic_reg32_write(&slic_regs->slic_wcs, instruction,
528 FLUSH);
529 instruction = *(u32 *)(fw->data + index);
530 index += 4;
531
532 /* Check SRAM location zero. If it is non-zero. Abort.*/
533/* failure = readl((u32 __iomem *)&slic_regs->slic_reset);
534 if (failure) {
535 release_firmware(fw);
536 return -EIO;
537 }*/
538 }
539 }
540 release_firmware(fw);
541 /* Everything OK, kick off the card */
542 mdelay(10);
543 slic_reg32_write(&slic_regs->slic_wcs, SLIC_WCS_START, FLUSH);
544
545 /* stall for 20 ms, long enough for ucode to init card
546 and reach mainloop */
547 mdelay(20);
4d6f6af8 548
d1939786 549 return 0;
4d6f6af8
GKH		 550}
551
4d6ea9c3
DK		 552MODULE_FIRMWARE("slicoss/oasisdownload.sys");
553MODULE_FIRMWARE("slicoss/gbdownload.sys");
554
555static void slic_adapter_set_hwaddr(struct adapter *adapter)
4d6f6af8 556{
4d6ea9c3 557 struct sliccard *card = adapter->card;
e52011e4 558
4d6ea9c3
DK		 559 if ((adapter->card) && (card->config_set)) {
560 memcpy(adapter->macaddr,
561 card->config.MacInfo[adapter->functionnumber].macaddrA,
562 sizeof(struct slic_config_mac));
ae7d27c0
JP		 563 if (is_zero_ether_addr(adapter->currmacaddr))
564 memcpy(adapter->currmacaddr, adapter->macaddr,
565 ETH_ALEN);
566 if (adapter->netdev)
4d6ea9c3 567 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr,
ae7d27c0 568 ETH_ALEN);
4d6ea9c3
DK		 569 }
570}
4d6f6af8 571
4d6ea9c3
DK		 572static void slic_intagg_set(struct adapter *adapter, u32 value)
573{
574 slic_reg32_write(&adapter->slic_regs->slic_intagg, value, FLUSH);
575 adapter->card->loadlevel_current = value;
576}
4d6f6af8 577
4d6ea9c3
DK		 578static void slic_soft_reset(struct adapter *adapter)
579{
580 if (adapter->card->state == CARD_UP) {
581 slic_reg32_write(&adapter->slic_regs->slic_quiesce, 0, FLUSH);
582 mdelay(1);
583 }
4d6f6af8 584
4d6ea9c3
DK		 585 slic_reg32_write(&adapter->slic_regs->slic_reset, SLIC_RESET_MAGIC,
586 FLUSH);
587 mdelay(1);
588}
e52011e4 589
4d6ea9c3
DK		 590static void slic_mac_address_config(struct adapter *adapter)
591{
592 u32 value;
593 u32 value2;
594 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
e52011e4 595
438c5826 596 value = ntohl(*(__be32 *) &adapter->currmacaddr[2]);
4d6ea9c3
DK		 597 slic_reg32_write(&slic_regs->slic_wraddral, value, FLUSH);
598 slic_reg32_write(&slic_regs->slic_wraddrbl, value, FLUSH);
e52011e4 599
4d6ea9c3
DK		 600 value2 = (u32) ((adapter->currmacaddr[0] << 8 |
601 adapter->currmacaddr[1]) & 0xFFFF);
4d6f6af8 602
4d6ea9c3
DK		 603 slic_reg32_write(&slic_regs->slic_wraddrah, value2, FLUSH);
604 slic_reg32_write(&slic_regs->slic_wraddrbh, value2, FLUSH);
e52011e4 605
4d6ea9c3
DK		 606 /* Write our multicast mask out to the card. This is done */
607 /* here in addition to the slic_mcast_addr_set routine */
608 /* because ALL_MCAST may have been enabled or disabled */
609 slic_mcast_set_mask(adapter);
610}
e52011e4 611
4d6ea9c3
DK		 612static void slic_mac_config(struct adapter *adapter)
613{
614 u32 value;
615 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
e52011e4 616
4d6ea9c3
DK		 617 /* Setup GMAC gaps */
618 if (adapter->linkspeed == LINK_1000MB) {
619 value = ((GMCR_GAPBB_1000 << GMCR_GAPBB_SHIFT) |
620 (GMCR_GAPR1_1000 << GMCR_GAPR1_SHIFT) |
621 (GMCR_GAPR2_1000 << GMCR_GAPR2_SHIFT));
622 } else {
623 value = ((GMCR_GAPBB_100 << GMCR_GAPBB_SHIFT) |
624 (GMCR_GAPR1_100 << GMCR_GAPR1_SHIFT) |
625 (GMCR_GAPR2_100 << GMCR_GAPR2_SHIFT));
626 }
e52011e4 627
4d6ea9c3
DK		 628 /* enable GMII */
629 if (adapter->linkspeed == LINK_1000MB)
630 value |= GMCR_GBIT;
631
632 /* enable fullduplex */
633 if ((adapter->linkduplex == LINK_FULLD)
634 || (adapter->macopts & MAC_LOOPBACK)) {
635 value |= GMCR_FULLD;
4d6f6af8 636 }
4d6f6af8 637
4d6ea9c3
DK		 638 /* write mac config */
639 slic_reg32_write(&slic_regs->slic_wmcfg, value, FLUSH);
4d6f6af8 640
4d6ea9c3
DK		 641 /* setup mac addresses */
642 slic_mac_address_config(adapter);
643}
644
645static void slic_config_set(struct adapter *adapter, bool linkchange)
4d6f6af8 646{
4d6ea9c3
DK		 647 u32 value;
648 u32 RcrReset;
649 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
4d6f6af8 650
4d6ea9c3
DK		 651 if (linkchange) {
652 /* Setup MAC */
653 slic_mac_config(adapter);
654 RcrReset = GRCR_RESET;
655 } else {
656 slic_mac_address_config(adapter);
657 RcrReset = 0;
658 }
4d6f6af8 659
4d6ea9c3
DK		 660 if (adapter->linkduplex == LINK_FULLD) {
661 /* setup xmtcfg */
662 value = (GXCR_RESET | /* Always reset */
663 GXCR_XMTEN | /* Enable transmit */
664 GXCR_PAUSEEN); /* Enable pause */
4d6f6af8 665
4d6ea9c3 666 slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
4d6f6af8 667
4d6ea9c3
DK		 668 /* Setup rcvcfg last */
669 value = (RcrReset | /* Reset, if linkchange */
670 GRCR_CTLEN | /* Enable CTL frames */
671 GRCR_ADDRAEN | /* Address A enable */
672 GRCR_RCVBAD | /* Rcv bad frames */
673 (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
674 } else {
675 /* setup xmtcfg */
676 value = (GXCR_RESET | /* Always reset */
677 GXCR_XMTEN); /* Enable transmit */
4d6f6af8 678
4d6ea9c3 679 slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
4d6f6af8 680
4d6ea9c3
DK		 681 /* Setup rcvcfg last */
682 value = (RcrReset | /* Reset, if linkchange */
683 GRCR_ADDRAEN | /* Address A enable */
684 GRCR_RCVBAD | /* Rcv bad frames */
685 (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
4d6f6af8
GKH		 686 }
687
4d6ea9c3
DK		 688 if (adapter->state != ADAPT_DOWN) {
689 /* Only enable receive if we are restarting or running */
690 value |= GRCR_RCVEN;
4d6f6af8 691 }
4d6f6af8 692
4d6ea9c3
DK		 693 if (adapter->macopts & MAC_PROMISC)
694 value |= GRCR_RCVALL;
4d6f6af8 695
4d6ea9c3
DK		 696 slic_reg32_write(&slic_regs->slic_wrcfg, value, FLUSH);
697}
4d6f6af8 698
4d6ea9c3
DK		 699/*
700 * Turn off RCV and XMT, power down PHY
701 */
702static void slic_config_clear(struct adapter *adapter)
4d6f6af8 703{
4d6ea9c3
DK		 704 u32 value;
705 u32 phy_config;
706 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
707
708 /* Setup xmtcfg */
709 value = (GXCR_RESET | /* Always reset */
710 GXCR_PAUSEEN); /* Enable pause */
711
712 slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
713
714 value = (GRCR_RESET | /* Always reset */
715 GRCR_CTLEN | /* Enable CTL frames */
716 GRCR_ADDRAEN | /* Address A enable */
717 (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
718
719 slic_reg32_write(&slic_regs->slic_wrcfg, value, FLUSH);
720
721 /* power down phy */
722 phy_config = (MIICR_REG_PCR | (PCR_POWERDOWN));
723 slic_reg32_write(&slic_regs->slic_wphy, phy_config, FLUSH);
4d6f6af8
GKH		 724}
725
4d6ea9c3
DK		 726static bool slic_mac_filter(struct adapter *adapter,
727 struct ether_header *ether_frame)
4d6f6af8 728{
9092de6d 729 struct net_device *netdev = adapter->netdev;
4d6ea9c3 730 u32 opts = adapter->macopts;
4d6f6af8 731
4d6ea9c3
DK		 732 if (opts & MAC_PROMISC)
733 return true;
4d6f6af8 734
ae7d27c0 735 if (is_broadcast_ether_addr(ether_frame->ether_dhost)) {
4d6ea9c3
DK		 736 if (opts & MAC_BCAST) {
737 adapter->rcv_broadcasts++;
738 return true;
4d6f6af8 739 }
351e836f
VH		 740
741 return false;
4d6ea9c3
DK		 742 }
743
ae7d27c0 744 if (is_multicast_ether_addr(ether_frame->ether_dhost)) {
4d6ea9c3
DK		 745 if (opts & MAC_ALLMCAST) {
746 adapter->rcv_multicasts++;
9092de6d 747 netdev->stats.multicast++;
4d6ea9c3 748 return true;
4d6f6af8 749 }
4d6ea9c3
DK		 750 if (opts & MAC_MCAST) {
751 struct mcast_address *mcaddr = adapter->mcastaddrs;
4d6f6af8 752
4d6ea9c3 753 while (mcaddr) {
8329419a
JP		 754 if (ether_addr_equal(mcaddr->address,
755 ether_frame->ether_dhost)) {
4d6ea9c3 756 adapter->rcv_multicasts++;
9092de6d 757 netdev->stats.multicast++;
4d6ea9c3
DK		 758 return true;
759 }
760 mcaddr = mcaddr->next;
761 }
351e836f 762
4d6ea9c3 763 return false;
4d6f6af8 764 }
351e836f
VH		 765
766 return false;
4d6f6af8 767 }
4d6ea9c3
DK		 768 if (opts & MAC_DIRECTED) {
769 adapter->rcv_unicasts++;
770 return true;
771 }
772 return false;
4d6f6af8 773
4d6ea9c3 774}
4d6f6af8 775
4d6ea9c3 776static int slic_mac_set_address(struct net_device *dev, void *ptr)
4d6f6af8 777{
4d6ea9c3
DK		 778 struct adapter *adapter = netdev_priv(dev);
779 struct sockaddr *addr = ptr;
4d6f6af8 780
4d6ea9c3
DK		 781 if (netif_running(dev))
782 return -EBUSY;
783 if (!adapter)
784 return -EBUSY;
4d6f6af8 785
4d6ea9c3
DK		 786 if (!is_valid_ether_addr(addr->sa_data))
787 return -EINVAL;
4d6f6af8 788
4d6ea9c3
DK		 789 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
790 memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
4d6f6af8 791
4d6ea9c3
DK		 792 slic_config_set(adapter, true);
793 return 0;
4d6f6af8
GKH		 794}
795
4d6ea9c3 796static void slic_timer_load_check(ulong cardaddr)
4d6f6af8 797{
4d6ea9c3
DK		 798 struct sliccard *card = (struct sliccard *)cardaddr;
799 struct adapter *adapter = card->master;
800 u32 __iomem *intagg;
801 u32 load = card->events;
802 u32 level = 0;
4d6f6af8 803
4d6ea9c3
DK		 804 if ((adapter) && (adapter->state == ADAPT_UP) &&
805 (card->state == CARD_UP) && (slic_global.dynamic_intagg)) {
81372118 806 intagg = &adapter->slic_regs->slic_intagg;
4d6ea9c3
DK		 807 if (adapter->devid == SLIC_1GB_DEVICE_ID) {
808 if (adapter->linkspeed == LINK_1000MB)
809 level = 100;
810 else {
811 if (load > SLIC_LOAD_5)
812 level = SLIC_INTAGG_5;
813 else if (load > SLIC_LOAD_4)
814 level = SLIC_INTAGG_4;
815 else if (load > SLIC_LOAD_3)
816 level = SLIC_INTAGG_3;
817 else if (load > SLIC_LOAD_2)
818 level = SLIC_INTAGG_2;
819 else if (load > SLIC_LOAD_1)
820 level = SLIC_INTAGG_1;
821 else
822 level = SLIC_INTAGG_0;
4d6f6af8 823 }
4d6ea9c3
DK		 824 if (card->loadlevel_current != level) {
825 card->loadlevel_current = level;
826 slic_reg32_write(intagg, level, FLUSH);
4d6f6af8 827 }
4d6ea9c3
DK		 828 } else {
829 if (load > SLIC_LOAD_5)
830 level = SLIC_INTAGG_5;
831 else if (load > SLIC_LOAD_4)
832 level = SLIC_INTAGG_4;
833 else if (load > SLIC_LOAD_3)
834 level = SLIC_INTAGG_3;
835 else if (load > SLIC_LOAD_2)
836 level = SLIC_INTAGG_2;
837 else if (load > SLIC_LOAD_1)
838 level = SLIC_INTAGG_1;
839 else
840 level = SLIC_INTAGG_0;
841 if (card->loadlevel_current != level) {
842 card->loadlevel_current = level;
843 slic_reg32_write(intagg, level, FLUSH);
4d6f6af8 844 }
4d6f6af8 845 }
4d6f6af8 846 }
4d6ea9c3
DK		 847 card->events = 0;
848 card->loadtimer.expires = jiffies + (SLIC_LOADTIMER_PERIOD * HZ);
849 add_timer(&card->loadtimer);
4d6f6af8
GKH		 850}
851
4d6ea9c3
DK		 852static int slic_upr_queue_request(struct adapter *adapter,
853 u32 upr_request,
854 u32 upr_data,
855 u32 upr_data_h,
856 u32 upr_buffer, u32 upr_buffer_h)
4d6f6af8 857{
4d6ea9c3
DK		 858 struct slic_upr *upr;
859 struct slic_upr *uprqueue;
4d6f6af8 860
4d6ea9c3
DK		 861 upr = kmalloc(sizeof(struct slic_upr), GFP_ATOMIC);
862 if (!upr)
863 return -ENOMEM;
4d6f6af8 864
4d6ea9c3
DK		 865 upr->adapter = adapter->port;
866 upr->upr_request = upr_request;
867 upr->upr_data = upr_data;
868 upr->upr_buffer = upr_buffer;
869 upr->upr_data_h = upr_data_h;
870 upr->upr_buffer_h = upr_buffer_h;
871 upr->next = NULL;
872 if (adapter->upr_list) {
873 uprqueue = adapter->upr_list;
a0a1cbef 874
4d6ea9c3
DK		 875 while (uprqueue->next)
876 uprqueue = uprqueue->next;
877 uprqueue->next = upr;
878 } else {
879 adapter->upr_list = upr;
4d6f6af8 880 }
4d6ea9c3 881 return 0;
4d6f6af8
GKH		 882}
883
4d6ea9c3 884static void slic_upr_start(struct adapter *adapter)
4d6f6af8 885{
4d6ea9c3
DK		 886 struct slic_upr *upr;
887 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
4d6f6af8 888/*
4d6ea9c3
DK		 889 char * ptr1;
890 char * ptr2;
891 uint cmdoffset;
892*/
893 upr = adapter->upr_list;
894 if (!upr)
895 return;
896 if (adapter->upr_busy)
897 return;
898 adapter->upr_busy = 1;
4d6f6af8 899
4d6ea9c3
DK		 900 switch (upr->upr_request) {
901 case SLIC_UPR_STATS:
902 if (upr->upr_data_h == 0) {
903 slic_reg32_write(&slic_regs->slic_stats, upr->upr_data,
904 FLUSH);
905 } else {
906 slic_reg64_write(adapter, &slic_regs->slic_stats64,
907 upr->upr_data,
908 &slic_regs->slic_addr_upper,
909 upr->upr_data_h, FLUSH);
910 }
911 break;
4d6f6af8 912
4d6ea9c3
DK		 913 case SLIC_UPR_RLSR:
914 slic_reg64_write(adapter, &slic_regs->slic_rlsr, upr->upr_data,
915 &slic_regs->slic_addr_upper, upr->upr_data_h,
916 FLUSH);
917 break;
4d6f6af8 918
4d6ea9c3
DK		 919 case SLIC_UPR_RCONFIG:
920 slic_reg64_write(adapter, &slic_regs->slic_rconfig,
921 upr->upr_data, &slic_regs->slic_addr_upper,
922 upr->upr_data_h, FLUSH);
923 break;
924 case SLIC_UPR_PING:
925 slic_reg32_write(&slic_regs->slic_ping, 1, FLUSH);
926 break;
4d6ea9c3 927 }
4d6f6af8
GKH		 928}
929
4d6ea9c3
DK		 930static int slic_upr_request(struct adapter *adapter,
931 u32 upr_request,
932 u32 upr_data,
933 u32 upr_data_h,
934 u32 upr_buffer, u32 upr_buffer_h)
4d6f6af8 935{
eafe6002 936 unsigned long flags;
4d6ea9c3 937 int rc;
4d6f6af8 938
eafe6002 939 spin_lock_irqsave(&adapter->upr_lock, flags);
4d6ea9c3
DK		 940 rc = slic_upr_queue_request(adapter,
941 upr_request,
942 upr_data,
943 upr_data_h, upr_buffer, upr_buffer_h);
944 if (rc)
945 goto err_unlock_irq;
4d6f6af8 946
4d6ea9c3
DK		 947 slic_upr_start(adapter);
948err_unlock_irq:
eafe6002 949 spin_unlock_irqrestore(&adapter->upr_lock, flags);
4d6ea9c3 950 return rc;
4d6f6af8
GKH		 951}
952
4d6ea9c3 953static void slic_link_upr_complete(struct adapter *adapter, u32 isr)
4d6f6af8 954{
4d6ea9c3
DK		 955 u32 linkstatus = adapter->pshmem->linkstatus;
956 uint linkup;
957 unsigned char linkspeed;
958 unsigned char linkduplex;
4d6f6af8 959
4d6ea9c3
DK		 960 if ((isr & ISR_UPCERR) || (isr & ISR_UPCBSY)) {
961 struct slic_shmem *pshmem;
4d6f6af8 962
01d0a9b4
JP		 963 pshmem = (struct slic_shmem *)(unsigned long)
964 adapter->phys_shmem;
1033f1f7 965#if BITS_PER_LONG == 64
4d6ea9c3
DK		 966 slic_upr_queue_request(adapter,
967 SLIC_UPR_RLSR,
968 SLIC_GET_ADDR_LOW(&pshmem->linkstatus),
969 SLIC_GET_ADDR_HIGH(&pshmem->linkstatus),
970 0, 0);
1033f1f7 971#else
4d6ea9c3
DK		 972 slic_upr_queue_request(adapter,
973 SLIC_UPR_RLSR,
974 (u32) &pshmem->linkstatus,
975 SLIC_GET_ADDR_HIGH(pshmem), 0, 0);
4d6ea9c3
DK		 976#endif
977 return;
978 }
979 if (adapter->state != ADAPT_UP)
980 return;
4d6f6af8 981
4d6ea9c3
DK		 982 linkup = linkstatus & GIG_LINKUP ? LINK_UP : LINK_DOWN;
983 if (linkstatus & GIG_SPEED_1000)
984 linkspeed = LINK_1000MB;
985 else if (linkstatus & GIG_SPEED_100)
986 linkspeed = LINK_100MB;
987 else
988 linkspeed = LINK_10MB;
4d6f6af8 989
4d6ea9c3
DK		 990 if (linkstatus & GIG_FULLDUPLEX)
991 linkduplex = LINK_FULLD;
992 else
993 linkduplex = LINK_HALFD;
4d6f6af8 994
4d6ea9c3
DK		 995 if ((adapter->linkstate == LINK_DOWN) && (linkup == LINK_DOWN))
996 return;
4d6f6af8 997
4d6ea9c3
DK		 998 /* link up event, but nothing has changed */
999 if ((adapter->linkstate == LINK_UP) &&
1000 (linkup == LINK_UP) &&
1001 (adapter->linkspeed == linkspeed) &&
1002 (adapter->linkduplex == linkduplex))
1003 return;
4d6f6af8 1004
4d6ea9c3 1005 /* link has changed at this point */
4d6f6af8 1006
4d6ea9c3
DK		 1007 /* link has gone from up to down */
1008 if (linkup == LINK_DOWN) {
1009 adapter->linkstate = LINK_DOWN;
1010 return;
4d6f6af8
GKH		 1011 }
1012
4d6ea9c3
DK		 1013 /* link has gone from down to up */
1014 adapter->linkspeed = linkspeed;
1015 adapter->linkduplex = linkduplex;
1016
1017 if (adapter->linkstate != LINK_UP) {
1018 /* setup the mac */
b574488e 1019 slic_config_set(adapter, true);
4d6ea9c3
DK		 1020 adapter->linkstate = LINK_UP;
1021 netif_start_queue(adapter->netdev);
4d6f6af8 1022 }
4d6f6af8
GKH		 1023}
1024
4d6ea9c3 1025static void slic_upr_request_complete(struct adapter *adapter, u32 isr)
4d6f6af8 1026{
4d6ea9c3
DK		 1027 struct sliccard *card = adapter->card;
1028 struct slic_upr *upr;
eafe6002 1029 unsigned long flags;
4d6f6af8 1030
eafe6002 1031 spin_lock_irqsave(&adapter->upr_lock, flags);
4d6ea9c3
DK		 1032 upr = adapter->upr_list;
1033 if (!upr) {
eafe6002 1034 spin_unlock_irqrestore(&adapter->upr_lock, flags);
4d6ea9c3 1035 return;
4d6f6af8 1036 }
4d6ea9c3
DK		 1037 adapter->upr_list = upr->next;
1038 upr->next = NULL;
1039 adapter->upr_busy = 0;
4d6ea9c3
DK		 1040 switch (upr->upr_request) {
1041 case SLIC_UPR_STATS:
1042 {
1043 struct slic_stats *slicstats =
1044 (struct slic_stats *) &adapter->pshmem->inicstats;
1045 struct slic_stats *newstats = slicstats;
1046 struct slic_stats *old = &adapter->inicstats_prev;
1047 struct slicnet_stats *stst = &adapter->slic_stats;
4d6f6af8 1048
4d6ea9c3
DK		 1049 if (isr & ISR_UPCERR) {
1050 dev_err(&adapter->netdev->dev,
1051 "SLIC_UPR_STATS command failed isr[%x]\n",
1052 isr);
4d6f6af8 1053
4d6ea9c3
DK		 1054 break;
1055 }
1056 UPDATE_STATS_GB(stst->tcp.xmit_tcp_segs,
1057 newstats->xmit_tcp_segs_gb,
1058 old->xmit_tcp_segs_gb);
4d6f6af8 1059
4d6ea9c3
DK		 1060 UPDATE_STATS_GB(stst->tcp.xmit_tcp_bytes,
1061 newstats->xmit_tcp_bytes_gb,
1062 old->xmit_tcp_bytes_gb);
4d6f6af8 1063
4d6ea9c3
DK		 1064 UPDATE_STATS_GB(stst->tcp.rcv_tcp_segs,
1065 newstats->rcv_tcp_segs_gb,
1066 old->rcv_tcp_segs_gb);
4d6f6af8 1067
4d6ea9c3
DK		 1068 UPDATE_STATS_GB(stst->tcp.rcv_tcp_bytes,
1069 newstats->rcv_tcp_bytes_gb,
1070 old->rcv_tcp_bytes_gb);
4d6f6af8 1071
4d6ea9c3
DK		 1072 UPDATE_STATS_GB(stst->iface.xmt_bytes,
1073 newstats->xmit_bytes_gb,
1074 old->xmit_bytes_gb);
4d6f6af8 1075
4d6ea9c3
DK		 1076 UPDATE_STATS_GB(stst->iface.xmt_ucast,
1077 newstats->xmit_unicasts_gb,
1078 old->xmit_unicasts_gb);
4d6f6af8 1079
4d6ea9c3
DK		 1080 UPDATE_STATS_GB(stst->iface.rcv_bytes,
1081 newstats->rcv_bytes_gb,
1082 old->rcv_bytes_gb);
4d6f6af8 1083
4d6ea9c3
DK		 1084 UPDATE_STATS_GB(stst->iface.rcv_ucast,
1085 newstats->rcv_unicasts_gb,
1086 old->rcv_unicasts_gb);
4d6f6af8 1087
4d6ea9c3
DK		 1088 UPDATE_STATS_GB(stst->iface.xmt_errors,
1089 newstats->xmit_collisions_gb,
1090 old->xmit_collisions_gb);
4d6f6af8 1091
4d6ea9c3
DK		 1092 UPDATE_STATS_GB(stst->iface.xmt_errors,
1093 newstats->xmit_excess_collisions_gb,
1094 old->xmit_excess_collisions_gb);
4d6f6af8 1095
4d6ea9c3
DK		 1096 UPDATE_STATS_GB(stst->iface.xmt_errors,
1097 newstats->xmit_other_error_gb,
1098 old->xmit_other_error_gb);
4d6f6af8 1099
4d6ea9c3
DK		 1100 UPDATE_STATS_GB(stst->iface.rcv_errors,
1101 newstats->rcv_other_error_gb,
1102 old->rcv_other_error_gb);
4d6f6af8 1103
4d6ea9c3
DK		 1104 UPDATE_STATS_GB(stst->iface.rcv_discards,
1105 newstats->rcv_drops_gb,
1106 old->rcv_drops_gb);
a0a1cbef 1107
4d6ea9c3
DK		 1108 if (newstats->rcv_drops_gb > old->rcv_drops_gb) {
1109 adapter->rcv_drops +=
1110 (newstats->rcv_drops_gb -
1111 old->rcv_drops_gb);
1112 }
1113 memcpy(old, newstats, sizeof(struct slic_stats));
1114 break;
1115 }
1116 case SLIC_UPR_RLSR:
1117 slic_link_upr_complete(adapter, isr);
1118 break;
1119 case SLIC_UPR_RCONFIG:
1120 break;
4d6ea9c3
DK		 1121 case SLIC_UPR_PING:
1122 card->pingstatus |= (isr & ISR_PINGDSMASK);
1123 break;
4d6f6af8 1124 }
4d6ea9c3
DK		 1125 kfree(upr);
1126 slic_upr_start(adapter);
eafe6002 1127 spin_unlock_irqrestore(&adapter->upr_lock, flags);
4d6f6af8
GKH		 1128}
1129
47a401a8 1130static int slic_config_get(struct adapter *adapter, u32 config, u32 config_h)
4d6f6af8 1131{
47a401a8
DM		 1132 return slic_upr_request(adapter, SLIC_UPR_RCONFIG, config, config_h,
1133 0, 0);
4d6f6af8
GKH		 1134}
1135
4d6ea9c3 1136/*
55b62cdf 1137 * Compute a checksum of the EEPROM according to RFC 1071.
4d6ea9c3 1138 */
55b62cdf 1139static u16 slic_eeprom_cksum(void *eeprom, unsigned len)
4d6f6af8 1140{
55b62cdf
DM		 1141 u16 *wp = eeprom;
1142 u32 checksum = 0;
4d6f6af8 1143
55b62cdf
DM		 1144 while (len > 1) {
1145 checksum += *(wp++);
1146 len -= 2;
1147 }
4d6f6af8 1148
55b62cdf
DM		 1149 if (len > 0)
1150 checksum += *(u8 *) wp;
4d6ea9c3 1151
4d6ea9c3 1152
55b62cdf
DM		 1153 while (checksum >> 16)
1154 checksum = (checksum & 0xFFFF) + ((checksum >> 16) & 0xFFFF);
4d6ea9c3 1155
55b62cdf 1156 return ~checksum;
4d6f6af8
GKH		 1157}
1158
4d6ea9c3 1159static void slic_rspqueue_free(struct adapter *adapter)
4d6f6af8 1160{
4d6ea9c3
DK		 1161 int i;
1162 struct slic_rspqueue *rspq = &adapter->rspqueue;
4d6f6af8 1163
4d6ea9c3
DK		 1164 for (i = 0; i < rspq->num_pages; i++) {
1165 if (rspq->vaddr[i]) {
1166 pci_free_consistent(adapter->pcidev, PAGE_SIZE,
1167 rspq->vaddr[i], rspq->paddr[i]);
1168 }
1169 rspq->vaddr[i] = NULL;
1170 rspq->paddr[i] = 0;
1171 }
1172 rspq->offset = 0;
1173 rspq->pageindex = 0;
1174 rspq->rspbuf = NULL;
4d6f6af8
GKH		 1175}
1176
4d6ea9c3 1177static int slic_rspqueue_init(struct adapter *adapter)
4d6f6af8 1178{
4d6ea9c3
DK		 1179 int i;
1180 struct slic_rspqueue *rspq = &adapter->rspqueue;
1181 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
1182 u32 paddrh = 0;
1183
4d6ea9c3
DK		 1184 memset(rspq, 0, sizeof(struct slic_rspqueue));
1185
1186 rspq->num_pages = SLIC_RSPQ_PAGES_GB;
1187
1188 for (i = 0; i < rspq->num_pages; i++) {
8b983be5
JP		 1189 rspq->vaddr[i] = pci_zalloc_consistent(adapter->pcidev,
1190 PAGE_SIZE,
1191 &rspq->paddr[i]);
4d6ea9c3
DK		 1192 if (!rspq->vaddr[i]) {
1193 dev_err(&adapter->pcidev->dev,
1194 "pci_alloc_consistent failed\n");
1195 slic_rspqueue_free(adapter);
1196 return -ENOMEM;
1197 }
4d6ea9c3
DK		 1198
1199 if (paddrh == 0) {
1200 slic_reg32_write(&slic_regs->slic_rbar,
1201 (rspq->paddr[i] | SLIC_RSPQ_BUFSINPAGE),
1202 DONT_FLUSH);
1203 } else {
1204 slic_reg64_write(adapter, &slic_regs->slic_rbar64,
1205 (rspq->paddr[i] | SLIC_RSPQ_BUFSINPAGE),
1206 &slic_regs->slic_addr_upper,
1207 paddrh, DONT_FLUSH);
1208 }
1209 }
1210 rspq->offset = 0;
1211 rspq->pageindex = 0;
1212 rspq->rspbuf = (struct slic_rspbuf *)rspq->vaddr[0];
1213 return 0;
4d6f6af8
GKH		 1214}
1215
4d6ea9c3 1216static struct slic_rspbuf *slic_rspqueue_getnext(struct adapter *adapter)
4d6f6af8 1217{
4d6ea9c3
DK		 1218 struct slic_rspqueue *rspq = &adapter->rspqueue;
1219 struct slic_rspbuf *buf;
4d6f6af8 1220
4d6ea9c3
DK		 1221 if (!(rspq->rspbuf->status))
1222 return NULL;
4d6f6af8 1223
4d6ea9c3 1224 buf = rspq->rspbuf;
4d6ea9c3
DK		 1225 if (++rspq->offset < SLIC_RSPQ_BUFSINPAGE) {
1226 rspq->rspbuf++;
4d6ea9c3 1227 } else {
4d6ea9c3
DK		 1228 slic_reg64_write(adapter, &adapter->slic_regs->slic_rbar64,
1229 (rspq->paddr[rspq->pageindex] | SLIC_RSPQ_BUFSINPAGE),
1230 &adapter->slic_regs->slic_addr_upper, 0, DONT_FLUSH);
6d1b80fd 1231 rspq->pageindex = (rspq->pageindex + 1) % rspq->num_pages;
4d6ea9c3
DK		 1232 rspq->offset = 0;
1233 rspq->rspbuf = (struct slic_rspbuf *)
1234 rspq->vaddr[rspq->pageindex];
4d6ea9c3 1235 }
40991e4f 1236
4d6ea9c3
DK		 1237 return buf;
1238}
4d6f6af8 1239
4d6ea9c3
DK		 1240static void slic_cmdqmem_free(struct adapter *adapter)
1241{
1242 struct slic_cmdqmem *cmdqmem = &adapter->cmdqmem;
1243 int i;
4d6f6af8 1244
4d6ea9c3
DK		 1245 for (i = 0; i < SLIC_CMDQ_MAXPAGES; i++) {
1246 if (cmdqmem->pages[i]) {
1247 pci_free_consistent(adapter->pcidev,
1248 PAGE_SIZE,
1249 (void *) cmdqmem->pages[i],
1250 cmdqmem->dma_pages[i]);
1251 }
1252 }
1253 memset(cmdqmem, 0, sizeof(struct slic_cmdqmem));
1254}
4d6f6af8 1255
4d6ea9c3
DK		 1256static u32 *slic_cmdqmem_addpage(struct adapter *adapter)
1257{
1258 struct slic_cmdqmem *cmdqmem = &adapter->cmdqmem;
1259 u32 *pageaddr;
4d6f6af8 1260
4d6ea9c3
DK		 1261 if (cmdqmem->pagecnt >= SLIC_CMDQ_MAXPAGES)
1262 return NULL;
1263 pageaddr = pci_alloc_consistent(adapter->pcidev,
1264 PAGE_SIZE,
1265 &cmdqmem->dma_pages[cmdqmem->pagecnt]);
1266 if (!pageaddr)
1267 return NULL;
40991e4f 1268
4d6ea9c3
DK		 1269 cmdqmem->pages[cmdqmem->pagecnt] = pageaddr;
1270 cmdqmem->pagecnt++;
1271 return pageaddr;
1272}
4d6f6af8 1273
4d6ea9c3
DK		 1274static void slic_cmdq_free(struct adapter *adapter)
1275{
1276 struct slic_hostcmd *cmd;
4d6f6af8 1277
4d6ea9c3
DK		 1278 cmd = adapter->cmdq_all.head;
1279 while (cmd) {
1280 if (cmd->busy) {
1281 struct sk_buff *tempskb;
4d6f6af8 1282
4d6ea9c3
DK		 1283 tempskb = cmd->skb;
1284 if (tempskb) {
1285 cmd->skb = NULL;
1286 dev_kfree_skb_irq(tempskb);
4d6f6af8
GKH		 1287 }
1288 }
4d6ea9c3
DK		 1289 cmd = cmd->next_all;
1290 }
1291 memset(&adapter->cmdq_all, 0, sizeof(struct slic_cmdqueue));
1292 memset(&adapter->cmdq_free, 0, sizeof(struct slic_cmdqueue));
1293 memset(&adapter->cmdq_done, 0, sizeof(struct slic_cmdqueue));
1294 slic_cmdqmem_free(adapter);
1295}
4d6f6af8 1296
4d6ea9c3
DK		 1297static void slic_cmdq_addcmdpage(struct adapter *adapter, u32 *page)
1298{
1299 struct slic_hostcmd *cmd;
1300 struct slic_hostcmd *prev;
1301 struct slic_hostcmd *tail;
1302 struct slic_cmdqueue *cmdq;
1303 int cmdcnt;
1304 void *cmdaddr;
1305 ulong phys_addr;
1306 u32 phys_addrl;
1307 u32 phys_addrh;
1308 struct slic_handle *pslic_handle;
eafe6002 1309 unsigned long flags;
4d6f6af8 1310
4d6ea9c3
DK		 1311 cmdaddr = page;
1312 cmd = (struct slic_hostcmd *)cmdaddr;
1313 cmdcnt = 0;
4d6f6af8 1314
4d6ea9c3
DK		 1315 phys_addr = virt_to_bus((void *)page);
1316 phys_addrl = SLIC_GET_ADDR_LOW(phys_addr);
1317 phys_addrh = SLIC_GET_ADDR_HIGH(phys_addr);
4d6f6af8 1318
4d6ea9c3
DK		 1319 prev = NULL;
1320 tail = cmd;
1321 while ((cmdcnt < SLIC_CMDQ_CMDSINPAGE) &&
1322 (adapter->slic_handle_ix < 256)) {
1323 /* Allocate and initialize a SLIC_HANDLE for this command */
eafe6002 1324 spin_lock_irqsave(&adapter->handle_lock, flags);
b0a0fb1e 1325 pslic_handle = adapter->pfree_slic_handles;
bcadb1dc 1326 adapter->pfree_slic_handles = pslic_handle->next;
eafe6002 1327 spin_unlock_irqrestore(&adapter->handle_lock, flags);
4d6ea9c3
DK		 1328 pslic_handle->type = SLIC_HANDLE_CMD;
1329 pslic_handle->address = (void *) cmd;
1330 pslic_handle->offset = (ushort) adapter->slic_handle_ix++;
1331 pslic_handle->other_handle = NULL;
1332 pslic_handle->next = NULL;
1333
1334 cmd->pslic_handle = pslic_handle;
1335 cmd->cmd64.hosthandle = pslic_handle->token.handle_token;
1336 cmd->busy = false;
1337 cmd->paddrl = phys_addrl;
1338 cmd->paddrh = phys_addrh;
1339 cmd->next_all = prev;
1340 cmd->next = prev;
1341 prev = cmd;
1342 phys_addrl += SLIC_HOSTCMD_SIZE;
1343 cmdaddr += SLIC_HOSTCMD_SIZE;
1344
1345 cmd = (struct slic_hostcmd *)cmdaddr;
1346 cmdcnt++;
4d6f6af8 1347 }
4d6ea9c3
DK		 1348
1349 cmdq = &adapter->cmdq_all;
1350 cmdq->count += cmdcnt; /* SLIC_CMDQ_CMDSINPAGE; mooktodo */
1351 tail->next_all = cmdq->head;
1352 cmdq->head = prev;
1353 cmdq = &adapter->cmdq_free;
eafe6002 1354 spin_lock_irqsave(&cmdq->lock, flags);
4d6ea9c3
DK		 1355 cmdq->count += cmdcnt; /* SLIC_CMDQ_CMDSINPAGE; mooktodo */
1356 tail->next = cmdq->head;
1357 cmdq->head = prev;
eafe6002 1358 spin_unlock_irqrestore(&cmdq->lock, flags);
4d6f6af8
GKH		 1359}
1360
4d6ea9c3 1361static int slic_cmdq_init(struct adapter *adapter)
4d6f6af8 1362{
4d6ea9c3
DK		 1363 int i;
1364 u32 *pageaddr;
4d6f6af8 1365
4d6ea9c3
DK		 1366 memset(&adapter->cmdq_all, 0, sizeof(struct slic_cmdqueue));
1367 memset(&adapter->cmdq_free, 0, sizeof(struct slic_cmdqueue));
1368 memset(&adapter->cmdq_done, 0, sizeof(struct slic_cmdqueue));
eafe6002
DM		 1369 spin_lock_init(&adapter->cmdq_all.lock);
1370 spin_lock_init(&adapter->cmdq_free.lock);
1371 spin_lock_init(&adapter->cmdq_done.lock);
bae5c3d1 1372 memset(&adapter->cmdqmem, 0, sizeof(struct slic_cmdqmem));
4d6ea9c3
DK		 1373 adapter->slic_handle_ix = 1;
1374 for (i = 0; i < SLIC_CMDQ_INITPAGES; i++) {
1375 pageaddr = slic_cmdqmem_addpage(adapter);
4d6ea9c3
DK		 1376 if (!pageaddr) {
1377 slic_cmdq_free(adapter);
1378 return -ENOMEM;
1379 }
1380 slic_cmdq_addcmdpage(adapter, pageaddr);
1381 }
1382 adapter->slic_handle_ix = 1;
4d6f6af8 1383
4d6ea9c3 1384 return 0;
4d6f6af8
GKH		 1385}
1386
4d6ea9c3 1387static void slic_cmdq_reset(struct adapter *adapter)
4d6f6af8 1388{
4d6ea9c3
DK		 1389 struct slic_hostcmd *hcmd;
1390 struct sk_buff *skb;
1391 u32 outstanding;
eafe6002 1392 unsigned long flags;
4d6f6af8 1393
eafe6002 1394 spin_lock_irqsave(&adapter->cmdq_free.lock, flags);
46d74c38 1395 spin_lock(&adapter->cmdq_done.lock);
4d6ea9c3
DK		 1396 outstanding = adapter->cmdq_all.count - adapter->cmdq_done.count;
1397 outstanding -= adapter->cmdq_free.count;
1398 hcmd = adapter->cmdq_all.head;
1399 while (hcmd) {
1400 if (hcmd->busy) {
1401 skb = hcmd->skb;
4d6ea9c3
DK		 1402 hcmd->busy = 0;
1403 hcmd->skb = NULL;
1404 dev_kfree_skb_irq(skb);
1405 }
1406 hcmd = hcmd->next_all;
470c5736 1407 }
4d6ea9c3
DK		 1408 adapter->cmdq_free.count = 0;
1409 adapter->cmdq_free.head = NULL;
1410 adapter->cmdq_free.tail = NULL;
1411 adapter->cmdq_done.count = 0;
1412 adapter->cmdq_done.head = NULL;
1413 adapter->cmdq_done.tail = NULL;
1414 adapter->cmdq_free.head = adapter->cmdq_all.head;
1415 hcmd = adapter->cmdq_all.head;
1416 while (hcmd) {
1417 adapter->cmdq_free.count++;
1418 hcmd->next = hcmd->next_all;
1419 hcmd = hcmd->next_all;
4d6f6af8 1420 }
4d6ea9c3
DK		 1421 if (adapter->cmdq_free.count != adapter->cmdq_all.count) {
1422 dev_err(&adapter->netdev->dev,
1423 "free_count %d != all count %d\n",
1424 adapter->cmdq_free.count, adapter->cmdq_all.count);
4d6f6af8 1425 }
46d74c38 1426 spin_unlock(&adapter->cmdq_done.lock);
eafe6002 1427 spin_unlock_irqrestore(&adapter->cmdq_free.lock, flags);
4d6f6af8
GKH		 1428}
1429
4d6ea9c3 1430static void slic_cmdq_getdone(struct adapter *adapter)
4d6f6af8 1431{
4d6ea9c3
DK		 1432 struct slic_cmdqueue *done_cmdq = &adapter->cmdq_done;
1433 struct slic_cmdqueue *free_cmdq = &adapter->cmdq_free;
eafe6002 1434 unsigned long flags;
4d6f6af8 1435
eafe6002 1436 spin_lock_irqsave(&done_cmdq->lock, flags);
4d6f6af8 1437
4d6ea9c3
DK		 1438 free_cmdq->head = done_cmdq->head;
1439 free_cmdq->count = done_cmdq->count;
1440 done_cmdq->head = NULL;
1441 done_cmdq->tail = NULL;
1442 done_cmdq->count = 0;
eafe6002 1443 spin_unlock_irqrestore(&done_cmdq->lock, flags);
4d6ea9c3 1444}
874073ea 1445
4d6ea9c3
DK		 1446static struct slic_hostcmd *slic_cmdq_getfree(struct adapter *adapter)
1447{
1448 struct slic_cmdqueue *cmdq = &adapter->cmdq_free;
1449 struct slic_hostcmd *cmd = NULL;
eafe6002 1450 unsigned long flags;
4d6f6af8 1451
4d6ea9c3 1452lock_and_retry:
eafe6002 1453 spin_lock_irqsave(&cmdq->lock, flags);
4d6ea9c3
DK		 1454retry:
1455 cmd = cmdq->head;
1456 if (cmd) {
1457 cmdq->head = cmd->next;
1458 cmdq->count--;
eafe6002 1459 spin_unlock_irqrestore(&cmdq->lock, flags);
4d6ea9c3
DK		 1460 } else {
1461 slic_cmdq_getdone(adapter);
1462 cmd = cmdq->head;
1463 if (cmd) {
1464 goto retry;
1465 } else {
1466 u32 *pageaddr;
874073ea 1467
eafe6002 1468 spin_unlock_irqrestore(&cmdq->lock, flags);
4d6ea9c3
DK		 1469 pageaddr = slic_cmdqmem_addpage(adapter);
1470 if (pageaddr) {
1471 slic_cmdq_addcmdpage(adapter, pageaddr);
1472 goto lock_and_retry;
1473 }
4d6f6af8
GKH		 1474 }
1475 }
4d6ea9c3 1476 return cmd;
4d6f6af8
GKH		 1477}
1478
4d6ea9c3
DK		 1479static void slic_cmdq_putdone_irq(struct adapter *adapter,
1480 struct slic_hostcmd *cmd)
4d6f6af8 1481{
4d6ea9c3 1482 struct slic_cmdqueue *cmdq = &adapter->cmdq_done;
4d6f6af8 1483
eafe6002 1484 spin_lock(&cmdq->lock);
4d6ea9c3
DK		 1485 cmd->busy = 0;
1486 cmd->next = cmdq->head;
1487 cmdq->head = cmd;
1488 cmdq->count++;
1489 if ((adapter->xmitq_full) && (cmdq->count > 10))
1490 netif_wake_queue(adapter->netdev);
eafe6002 1491 spin_unlock(&cmdq->lock);
4d6f6af8
GKH		 1492}
1493
4d6ea9c3 1494static int slic_rcvqueue_fill(struct adapter *adapter)
4d6f6af8 1495{
4d6ea9c3
DK		 1496 void *paddr;
1497 u32 paddrl;
1498 u32 paddrh;
1499 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
1500 int i = 0;
1501 struct device *dev = &adapter->netdev->dev;
1502
1503 while (i < SLIC_RCVQ_FILLENTRIES) {
1504 struct slic_rcvbuf *rcvbuf;
1505 struct sk_buff *skb;
1506#ifdef KLUDGE_FOR_4GB_BOUNDARY
1507retry_rcvqfill:
1508#endif
1509 skb = alloc_skb(SLIC_RCVQ_RCVBUFSIZE, GFP_ATOMIC);
1510 if (skb) {
01d0a9b4
JP		 1511 paddr = (void *)(unsigned long)
1512 pci_map_single(adapter->pcidev,
1513 skb->data,
1514 SLIC_RCVQ_RCVBUFSIZE,
1515 PCI_DMA_FROMDEVICE);
4d6ea9c3
DK		 1516 paddrl = SLIC_GET_ADDR_LOW(paddr);
1517 paddrh = SLIC_GET_ADDR_HIGH(paddr);
1518
1519 skb->len = SLIC_RCVBUF_HEADSIZE;
1520 rcvbuf = (struct slic_rcvbuf *)skb->head;
1521 rcvbuf->status = 0;
1522 skb->next = NULL;
1523#ifdef KLUDGE_FOR_4GB_BOUNDARY
1524 if (paddrl == 0) {
1525 dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
1526 __func__);
1527 dev_err(dev, "skb[%p] PROBLEM\n", skb);
17d2c643
SC		 1528 dev_err(dev, " skbdata[%p]\n",
1529 skb->data);
4d6ea9c3
DK		 1530 dev_err(dev, " skblen[%x]\n", skb->len);
1531 dev_err(dev, " paddr[%p]\n", paddr);
1532 dev_err(dev, " paddrl[%x]\n", paddrl);
1533 dev_err(dev, " paddrh[%x]\n", paddrh);
17d2c643
SC		 1534 dev_err(dev, " rcvq->head[%p]\n",
1535 rcvq->head);
1536 dev_err(dev, " rcvq->tail[%p]\n",
1537 rcvq->tail);
1538 dev_err(dev, " rcvq->count[%x]\n",
1539 rcvq->count);
4d6ea9c3
DK		 1540 dev_err(dev, "SKIP THIS SKB!!!!!!!!\n");
1541 goto retry_rcvqfill;
1542 }
1543#else
1544 if (paddrl == 0) {
1545 dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
1546 __func__);
1547 dev_err(dev, "skb[%p] PROBLEM\n", skb);
17d2c643
SC		 1548 dev_err(dev, " skbdata[%p]\n",
1549 skb->data);
4d6ea9c3
DK		 1550 dev_err(dev, " skblen[%x]\n", skb->len);
1551 dev_err(dev, " paddr[%p]\n", paddr);
1552 dev_err(dev, " paddrl[%x]\n", paddrl);
1553 dev_err(dev, " paddrh[%x]\n", paddrh);
17d2c643
SC		 1554 dev_err(dev, " rcvq->head[%p]\n",
1555 rcvq->head);
1556 dev_err(dev, " rcvq->tail[%p]\n",
1557 rcvq->tail);
1558 dev_err(dev, " rcvq->count[%x]\n",
1559 rcvq->count);
4d6ea9c3
DK		 1560 dev_err(dev, "GIVE TO CARD ANYWAY\n");
1561 }
1562#endif
1563 if (paddrh == 0) {
1564 slic_reg32_write(&adapter->slic_regs->slic_hbar,
1565 (u32)paddrl, DONT_FLUSH);
1566 } else {
1567 slic_reg64_write(adapter,
1568 &adapter->slic_regs->slic_hbar64,
1569 paddrl,
1570 &adapter->slic_regs->slic_addr_upper,
1571 paddrh, DONT_FLUSH);
1572 }
1573 if (rcvq->head)
1574 rcvq->tail->next = skb;
1575 else
1576 rcvq->head = skb;
1577 rcvq->tail = skb;
1578 rcvq->count++;
1579 i++;
1580 } else {
1581 dev_err(&adapter->netdev->dev,
1582 "slic_rcvqueue_fill could only get [%d] skbuffs\n",
1583 i);
1584 break;
1585 }
1586 }
1587 return i;
4d6f6af8
GKH		 1588}
1589
4d6ea9c3 1590static void slic_rcvqueue_free(struct adapter *adapter)
4d6f6af8 1591{
4d6ea9c3
DK		 1592 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
1593 struct sk_buff *skb;
4d6f6af8 1594
4d6ea9c3
DK		 1595 while (rcvq->head) {
1596 skb = rcvq->head;
1597 rcvq->head = rcvq->head->next;
1598 dev_kfree_skb(skb);
1599 }
1600 rcvq->tail = NULL;
1601 rcvq->head = NULL;
1602 rcvq->count = 0;
1603}
4d6f6af8 1604
4d6ea9c3
DK		 1605static int slic_rcvqueue_init(struct adapter *adapter)
1606{
1607 int i, count;
1608 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
4d6f6af8 1609
4d6ea9c3
DK		 1610 rcvq->tail = NULL;
1611 rcvq->head = NULL;
1612 rcvq->size = SLIC_RCVQ_ENTRIES;
1613 rcvq->errors = 0;
1614 rcvq->count = 0;
db9c9305 1615 i = SLIC_RCVQ_ENTRIES / SLIC_RCVQ_FILLENTRIES;
4d6ea9c3
DK		 1616 count = 0;
1617 while (i) {
1618 count += slic_rcvqueue_fill(adapter);
1619 i--;
1620 }
1621 if (rcvq->count < SLIC_RCVQ_MINENTRIES) {
1622 slic_rcvqueue_free(adapter);
1623 return -ENOMEM;
4d6f6af8 1624 }
4d6ea9c3
DK		 1625 return 0;
1626}
4d6f6af8 1627
4d6ea9c3
DK		 1628static struct sk_buff *slic_rcvqueue_getnext(struct adapter *adapter)
1629{
1630 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
1631 struct sk_buff *skb;
1632 struct slic_rcvbuf *rcvbuf;
1633 int count;
4d6f6af8 1634
4d6ea9c3
DK		 1635 if (rcvq->count) {
1636 skb = rcvq->head;
1637 rcvbuf = (struct slic_rcvbuf *)skb->head;
4d6f6af8 1638
4d6ea9c3
DK		 1639 if (rcvbuf->status & IRHDDR_SVALID) {
1640 rcvq->head = rcvq->head->next;
1641 skb->next = NULL;
1642 rcvq->count--;
4d6f6af8 1643 } else {
4d6ea9c3 1644 skb = NULL;
4d6f6af8 1645 }
4d6ea9c3
DK		 1646 } else {
1647 dev_err(&adapter->netdev->dev,
1648 "RcvQ Empty!! rcvq[%p] count[%x]\n", rcvq, rcvq->count);
1649 skb = NULL;
1650 }
1651 while (rcvq->count < SLIC_RCVQ_FILLTHRESH) {
1652 count = slic_rcvqueue_fill(adapter);
1653 if (!count)
1654 break;
1655 }
1656 if (skb)
1657 rcvq->errors = 0;
1658 return skb;
1659}
4d6f6af8 1660
4d6ea9c3
DK		 1661static u32 slic_rcvqueue_reinsert(struct adapter *adapter, struct sk_buff *skb)
1662{
1663 struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
1664 void *paddr;
1665 u32 paddrl;
1666 u32 paddrh;
1667 struct slic_rcvbuf *rcvbuf = (struct slic_rcvbuf *)skb->head;
1668 struct device *dev;
4d6f6af8 1669
01d0a9b4
JP		 1670 paddr = (void *)(unsigned long)
1671 pci_map_single(adapter->pcidev, skb->head,
1672 SLIC_RCVQ_RCVBUFSIZE, PCI_DMA_FROMDEVICE);
4d6ea9c3
DK		 1673 rcvbuf->status = 0;
1674 skb->next = NULL;
4d6f6af8 1675
4d6ea9c3
DK		 1676 paddrl = SLIC_GET_ADDR_LOW(paddr);
1677 paddrh = SLIC_GET_ADDR_HIGH(paddr);
4d6f6af8 1678
4d6ea9c3
DK		 1679 if (paddrl == 0) {
1680 dev = &adapter->netdev->dev;
1681 dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
1682 __func__);
1683 dev_err(dev, "skb[%p] PROBLEM\n", skb);
1684 dev_err(dev, " skbdata[%p]\n", skb->data);
1685 dev_err(dev, " skblen[%x]\n", skb->len);
1686 dev_err(dev, " paddr[%p]\n", paddr);
1687 dev_err(dev, " paddrl[%x]\n", paddrl);
1688 dev_err(dev, " paddrh[%x]\n", paddrh);
1689 dev_err(dev, " rcvq->head[%p]\n", rcvq->head);
1690 dev_err(dev, " rcvq->tail[%p]\n", rcvq->tail);
1691 dev_err(dev, " rcvq->count[%x]\n", rcvq->count);
4d6f6af8 1692 }
4d6ea9c3
DK		 1693 if (paddrh == 0) {
1694 slic_reg32_write(&adapter->slic_regs->slic_hbar, (u32)paddrl,
1695 DONT_FLUSH);
1696 } else {
1697 slic_reg64_write(adapter, &adapter->slic_regs->slic_hbar64,
1698 paddrl, &adapter->slic_regs->slic_addr_upper,
1699 paddrh, DONT_FLUSH);
4d6f6af8 1700 }
4d6ea9c3
DK		 1701 if (rcvq->head)
1702 rcvq->tail->next = skb;
e8bc9b7a 1703 else
4d6ea9c3
DK		 1704 rcvq->head = skb;
1705 rcvq->tail = skb;
1706 rcvq->count++;
1707 return rcvq->count;
4d6f6af8
GKH		 1708}
1709
4d6ea9c3
DK		 1710/*
1711 * slic_link_event_handler -
1712 *
1713 * Initiate a link configuration sequence. The link configuration begins
1714 * by issuing a READ_LINK_STATUS command to the Utility Processor on the
1715 * SLIC. Since the command finishes asynchronously, the slic_upr_comlete
1716 * routine will follow it up witha UP configuration write command, which
1717 * will also complete asynchronously.
1718 *
1719 */
1720static void slic_link_event_handler(struct adapter *adapter)
1721{
1722 int status;
1723 struct slic_shmem *pshmem;
4d6f6af8 1724
4d6ea9c3
DK		 1725 if (adapter->state != ADAPT_UP) {
1726 /* Adapter is not operational. Ignore. */
1727 return;
4d6f6af8
GKH		 1728 }
1729
01d0a9b4 1730 pshmem = (struct slic_shmem *)(unsigned long)adapter->phys_shmem;
4d6f6af8 1731
1033f1f7 1732#if BITS_PER_LONG == 64
4d6ea9c3
DK		 1733 status = slic_upr_request(adapter,
1734 SLIC_UPR_RLSR,
1735 SLIC_GET_ADDR_LOW(&pshmem->linkstatus),
1736 SLIC_GET_ADDR_HIGH(&pshmem->linkstatus),
1737 0, 0);
1033f1f7 1738#else
4d6ea9c3
DK		 1739 status = slic_upr_request(adapter, SLIC_UPR_RLSR,
1740 (u32) &pshmem->linkstatus, /* no 4GB wrap guaranteed */
1741 0, 0, 0);
4d6ea9c3 1742#endif
4d6f6af8
GKH		 1743}
1744
4d6ea9c3 1745static void slic_init_cleanup(struct adapter *adapter)
4d6f6af8 1746{
4d6ea9c3
DK		 1747 if (adapter->intrregistered) {
1748 adapter->intrregistered = 0;
1749 free_irq(adapter->netdev->irq, adapter->netdev);
4d6f6af8 1750
4d6f6af8 1751 }
4d6ea9c3
DK		 1752 if (adapter->pshmem) {
1753 pci_free_consistent(adapter->pcidev,
1754 sizeof(struct slic_shmem),
1755 adapter->pshmem, adapter->phys_shmem);
1756 adapter->pshmem = NULL;
01d0a9b4 1757 adapter->phys_shmem = (dma_addr_t)(unsigned long)NULL;
4d6f6af8 1758 }
4d6ea9c3
DK		 1759
1760 if (adapter->pingtimerset) {
1761 adapter->pingtimerset = 0;
1762 del_timer(&adapter->pingtimer);
4d6f6af8 1763 }
4d6f6af8 1764
4d6ea9c3
DK		 1765 slic_rspqueue_free(adapter);
1766 slic_cmdq_free(adapter);
1767 slic_rcvqueue_free(adapter);
4d6f6af8
GKH		 1768}
1769
4d6ea9c3
DK		 1770/*
1771 * Allocate a mcast_address structure to hold the multicast address.
1772 * Link it in.
1773 */
1774static int slic_mcast_add_list(struct adapter *adapter, char *address)
4d6f6af8 1775{
4d6ea9c3 1776 struct mcast_address *mcaddr, *mlist;
4d6f6af8 1777
4d6ea9c3
DK		 1778 /* Check to see if it already exists */
1779 mlist = adapter->mcastaddrs;
1780 while (mlist) {
8329419a 1781 if (ether_addr_equal(mlist->address, address))
4d6ea9c3
DK		 1782 return 0;
1783 mlist = mlist->next;
1784 }
e8bc9b7a 1785
4d6ea9c3
DK		 1786 /* Doesn't already exist. Allocate a structure to hold it */
1787 mcaddr = kmalloc(sizeof(struct mcast_address), GFP_ATOMIC);
1788 if (mcaddr == NULL)
1789 return 1;
a71b9978 1790
f999ac00 1791 ether_addr_copy(mcaddr->address, address);
4d6ea9c3
DK		 1792
1793 mcaddr->next = adapter->mcastaddrs;
1794 adapter->mcastaddrs = mcaddr;
4d6f6af8 1795
4d6f6af8
GKH		 1796 return 0;
1797}
1798
4d6ea9c3 1799static void slic_mcast_set_list(struct net_device *dev)
4d6f6af8 1800{
4d6ea9c3
DK		 1801 struct adapter *adapter = netdev_priv(dev);
1802 int status = 0;
1803 char *addresses;
1804 struct netdev_hw_addr *ha;
4d6f6af8 1805
4d6ea9c3
DK		 1806 netdev_for_each_mc_addr(ha, dev) {
1807 addresses = (char *) &ha->addr;
1808 status = slic_mcast_add_list(adapter, addresses);
1809 if (status != 0)
1810 break;
1811 slic_mcast_set_bit(adapter, addresses);
1812 }
1813
1814 if (adapter->devflags_prev != dev->flags) {
1815 adapter->macopts = MAC_DIRECTED;
1816 if (dev->flags) {
1817 if (dev->flags & IFF_BROADCAST)
1818 adapter->macopts |= MAC_BCAST;
1819 if (dev->flags & IFF_PROMISC)
1820 adapter->macopts |= MAC_PROMISC;
1821 if (dev->flags & IFF_ALLMULTI)
1822 adapter->macopts |= MAC_ALLMCAST;
1823 if (dev->flags & IFF_MULTICAST)
1824 adapter->macopts |= MAC_MCAST;
4d6f6af8 1825 }
4d6ea9c3
DK		 1826 adapter->devflags_prev = dev->flags;
1827 slic_config_set(adapter, true);
1828 } else {
1829 if (status == 0)
1830 slic_mcast_set_mask(adapter);
4d6f6af8 1831 }
4d6f6af8
GKH		 1832}
1833
4d6ea9c3
DK		 1834#define XMIT_FAIL_LINK_STATE 1
1835#define XMIT_FAIL_ZERO_LENGTH 2
1836#define XMIT_FAIL_HOSTCMD_FAIL 3
1837
1838static void slic_xmit_build_request(struct adapter *adapter,
1839 struct slic_hostcmd *hcmd, struct sk_buff *skb)
4d6f6af8 1840{
4d6ea9c3
DK		 1841 struct slic_host64_cmd *ihcmd;
1842 ulong phys_addr;
4d6f6af8 1843
4d6ea9c3
DK		 1844 ihcmd = &hcmd->cmd64;
1845
6e28c2a2 1846 ihcmd->flags = adapter->port << IHFLG_IFSHFT;
4d6ea9c3
DK		 1847 ihcmd->command = IHCMD_XMT_REQ;
1848 ihcmd->u.slic_buffers.totlen = skb->len;
1849 phys_addr = pci_map_single(adapter->pcidev, skb->data, skb->len,
1850 PCI_DMA_TODEVICE);
1851 ihcmd->u.slic_buffers.bufs[0].paddrl = SLIC_GET_ADDR_LOW(phys_addr);
1852 ihcmd->u.slic_buffers.bufs[0].paddrh = SLIC_GET_ADDR_HIGH(phys_addr);
1853 ihcmd->u.slic_buffers.bufs[0].length = skb->len;
1033f1f7 1854#if BITS_PER_LONG == 64
4d6ea9c3
DK		 1855 hcmd->cmdsize = (u32) ((((u64)&ihcmd->u.slic_buffers.bufs[1] -
1856 (u64) hcmd) + 31) >> 5);
1033f1f7 1857#else
a659b3e8
AM		 1858 hcmd->cmdsize = (((u32)&ihcmd->u.slic_buffers.bufs[1] -
1859 (u32)hcmd) + 31) >> 5;
4d6ea9c3 1860#endif
4d6f6af8
GKH		 1861}
1862
4d6ea9c3
DK		 1863static void slic_xmit_fail(struct adapter *adapter,
1864 struct sk_buff *skb,
1865 void *cmd, u32 skbtype, u32 status)
4d6f6af8 1866{
4d6ea9c3
DK		 1867 if (adapter->xmitq_full)
1868 netif_stop_queue(adapter->netdev);
1869 if ((cmd == NULL) && (status <= XMIT_FAIL_HOSTCMD_FAIL)) {
1870 switch (status) {
1871 case XMIT_FAIL_LINK_STATE:
1872 dev_err(&adapter->netdev->dev,
5d5b44b5 1873 "reject xmit skb[%p: %x] linkstate[%s] adapter[%s:%d] card[%s:%d]\n",
4d6ea9c3
DK		 1874 skb, skb->pkt_type,
1875 SLIC_LINKSTATE(adapter->linkstate),
1876 SLIC_ADAPTER_STATE(adapter->state),
1877 adapter->state,
1878 SLIC_CARD_STATE(adapter->card->state),
1879 adapter->card->state);
1880 break;
1881 case XMIT_FAIL_ZERO_LENGTH:
1882 dev_err(&adapter->netdev->dev,
1883 "xmit_start skb->len == 0 skb[%p] type[%x]\n",
1884 skb, skb->pkt_type);
1885 break;
1886 case XMIT_FAIL_HOSTCMD_FAIL:
1887 dev_err(&adapter->netdev->dev,
17d2c643
SC		 1888 "xmit_start skb[%p] type[%x] No host commands available\n",
1889 skb, skb->pkt_type);
4d6ea9c3 1890 break;
4d6ea9c3
DK		 1891 }
1892 }
1893 dev_kfree_skb(skb);
9092de6d 1894 adapter->netdev->stats.tx_dropped++;
4d6ea9c3 1895}
e8bc9b7a 1896
4d6ea9c3
DK		 1897static void slic_rcv_handle_error(struct adapter *adapter,
1898 struct slic_rcvbuf *rcvbuf)
1899{
1900 struct slic_hddr_wds *hdr = (struct slic_hddr_wds *)rcvbuf->data;
9092de6d 1901 struct net_device *netdev = adapter->netdev;
4d6f6af8 1902
4d6ea9c3
DK		 1903 if (adapter->devid != SLIC_1GB_DEVICE_ID) {
1904 if (hdr->frame_status14 & VRHSTAT_802OE)
1905 adapter->if_events.oflow802++;
1906 if (hdr->frame_status14 & VRHSTAT_TPOFLO)
1907 adapter->if_events.Tprtoflow++;
1908 if (hdr->frame_status_b14 & VRHSTATB_802UE)
1909 adapter->if_events.uflow802++;
1910 if (hdr->frame_status_b14 & VRHSTATB_RCVE) {
1911 adapter->if_events.rcvearly++;
9092de6d 1912 netdev->stats.rx_fifo_errors++;
4d6ea9c3
DK		 1913 }
1914 if (hdr->frame_status_b14 & VRHSTATB_BUFF) {
1915 adapter->if_events.Bufov++;
9092de6d 1916 netdev->stats.rx_over_errors++;
4d6ea9c3
DK		 1917 }
1918 if (hdr->frame_status_b14 & VRHSTATB_CARRE) {
1919 adapter->if_events.Carre++;
9092de6d 1920 netdev->stats.tx_carrier_errors++;
4d6ea9c3
DK		 1921 }
1922 if (hdr->frame_status_b14 & VRHSTATB_LONGE)
1923 adapter->if_events.Longe++;
1924 if (hdr->frame_status_b14 & VRHSTATB_PREA)
1925 adapter->if_events.Invp++;
1926 if (hdr->frame_status_b14 & VRHSTATB_CRC) {
1927 adapter->if_events.Crc++;
9092de6d 1928 netdev->stats.rx_crc_errors++;
4d6ea9c3
DK		 1929 }
1930 if (hdr->frame_status_b14 & VRHSTATB_DRBL)
1931 adapter->if_events.Drbl++;
1932 if (hdr->frame_status_b14 & VRHSTATB_CODE)
1933 adapter->if_events.Code++;
1934 if (hdr->frame_status_b14 & VRHSTATB_TPCSUM)
1935 adapter->if_events.TpCsum++;
1936 if (hdr->frame_status_b14 & VRHSTATB_TPHLEN)
1937 adapter->if_events.TpHlen++;
1938 if (hdr->frame_status_b14 & VRHSTATB_IPCSUM)
1939 adapter->if_events.IpCsum++;
1940 if (hdr->frame_status_b14 & VRHSTATB_IPLERR)
1941 adapter->if_events.IpLen++;
1942 if (hdr->frame_status_b14 & VRHSTATB_IPHERR)
1943 adapter->if_events.IpHlen++;
4d6f6af8 1944 } else {
4d6ea9c3
DK		 1945 if (hdr->frame_statusGB & VGBSTAT_XPERR) {
1946 u32 xerr = hdr->frame_statusGB >> VGBSTAT_XERRSHFT;
1947
1948 if (xerr == VGBSTAT_XCSERR)
1949 adapter->if_events.TpCsum++;
1950 if (xerr == VGBSTAT_XUFLOW)
1951 adapter->if_events.Tprtoflow++;
1952 if (xerr == VGBSTAT_XHLEN)
1953 adapter->if_events.TpHlen++;
1954 }
1955 if (hdr->frame_statusGB & VGBSTAT_NETERR) {
1956 u32 nerr =
1957 (hdr->
1958 frame_statusGB >> VGBSTAT_NERRSHFT) &
1959 VGBSTAT_NERRMSK;
1960 if (nerr == VGBSTAT_NCSERR)
1961 adapter->if_events.IpCsum++;
1962 if (nerr == VGBSTAT_NUFLOW)
1963 adapter->if_events.IpLen++;
1964 if (nerr == VGBSTAT_NHLEN)
1965 adapter->if_events.IpHlen++;
1966 }
1967 if (hdr->frame_statusGB & VGBSTAT_LNKERR) {
1968 u32 lerr = hdr->frame_statusGB & VGBSTAT_LERRMSK;
1969
1970 if (lerr == VGBSTAT_LDEARLY)
1971 adapter->if_events.rcvearly++;
1972 if (lerr == VGBSTAT_LBOFLO)
1973 adapter->if_events.Bufov++;
1974 if (lerr == VGBSTAT_LCODERR)
1975 adapter->if_events.Code++;
1976 if (lerr == VGBSTAT_LDBLNBL)
1977 adapter->if_events.Drbl++;
1978 if (lerr == VGBSTAT_LCRCERR)
1979 adapter->if_events.Crc++;
1980 if (lerr == VGBSTAT_LOFLO)
1981 adapter->if_events.oflow802++;
1982 if (lerr == VGBSTAT_LUFLO)
1983 adapter->if_events.uflow802++;
1984 }
4d6f6af8 1985 }
4d6f6af8
GKH		 1986}
1987
4d6ea9c3
DK		 1988#define TCP_OFFLOAD_FRAME_PUSHFLAG 0x10000000
1989#define M_FAST_PATH 0x0040
4d6f6af8 1990
4d6ea9c3 1991static void slic_rcv_handler(struct adapter *adapter)
4d6f6af8 1992{
9092de6d 1993 struct net_device *netdev = adapter->netdev;
4d6ea9c3
DK		 1994 struct sk_buff *skb;
1995 struct slic_rcvbuf *rcvbuf;
1996 u32 frames = 0;
4d6f6af8 1997
4d6ea9c3
DK		 1998 while ((skb = slic_rcvqueue_getnext(adapter))) {
1999 u32 rx_bytes;
4d6f6af8 2000
4d6ea9c3
DK		 2001 rcvbuf = (struct slic_rcvbuf *)skb->head;
2002 adapter->card->events++;
2003 if (rcvbuf->status & IRHDDR_ERR) {
2004 adapter->rx_errors++;
2005 slic_rcv_handle_error(adapter, rcvbuf);
2006 slic_rcvqueue_reinsert(adapter, skb);
2007 continue;
2008 }
4d6f6af8 2009
4d6ea9c3
DK		 2010 if (!slic_mac_filter(adapter, (struct ether_header *)
2011 rcvbuf->data)) {
2012 slic_rcvqueue_reinsert(adapter, skb);
2013 continue;
2014 }
2015 skb_pull(skb, SLIC_RCVBUF_HEADSIZE);
2016 rx_bytes = (rcvbuf->length & IRHDDR_FLEN_MSK);
2017 skb_put(skb, rx_bytes);
9092de6d
DK		 2018 netdev->stats.rx_packets++;
2019 netdev->stats.rx_bytes += rx_bytes;
4d6ea9c3
DK		 2020#if SLIC_OFFLOAD_IP_CHECKSUM
2021 skb->ip_summed = CHECKSUM_UNNECESSARY;
2022#endif
4d6f6af8 2023
4d6ea9c3
DK		 2024 skb->dev = adapter->netdev;
2025 skb->protocol = eth_type_trans(skb, skb->dev);
2026 netif_rx(skb);
4d6f6af8 2027
4d6ea9c3
DK		 2028 ++frames;
2029#if SLIC_INTERRUPT_PROCESS_LIMIT
2030 if (frames >= SLIC_RCVQ_MAX_PROCESS_ISR) {
2031 adapter->rcv_interrupt_yields++;
4d6f6af8
GKH		 2032 break;
2033 }
4d6ea9c3 2034#endif
4d6f6af8 2035 }
4d6ea9c3 2036 adapter->max_isr_rcvs = max(adapter->max_isr_rcvs, frames);
4d6f6af8
GKH		 2037}
2038
4d6ea9c3 2039static void slic_xmit_complete(struct adapter *adapter)
4d6f6af8 2040{
4d6ea9c3
DK		 2041 struct slic_hostcmd *hcmd;
2042 struct slic_rspbuf *rspbuf;
2043 u32 frames = 0;
2044 struct slic_handle_word slic_handle_word;
4d6f6af8 2045
4d6ea9c3
DK		 2046 do {
2047 rspbuf = slic_rspqueue_getnext(adapter);
2048 if (!rspbuf)
2049 break;
2050 adapter->xmit_completes++;
2051 adapter->card->events++;
2052 /*
2053 Get the complete host command buffer
2054 */
2055 slic_handle_word.handle_token = rspbuf->hosthandle;
4d6ea9c3
DK		 2056 hcmd =
2057 (struct slic_hostcmd *)
2058 adapter->slic_handles[slic_handle_word.handle_index].
2059 address;
2060/* hcmd = (struct slic_hostcmd *) rspbuf->hosthandle; */
4d6ea9c3
DK		 2061 if (hcmd->type == SLIC_CMD_DUMB) {
2062 if (hcmd->skb)
2063 dev_kfree_skb_irq(hcmd->skb);
2064 slic_cmdq_putdone_irq(adapter, hcmd);
4d6f6af8 2065 }
4d6ea9c3
DK		 2066 rspbuf->status = 0;
2067 rspbuf->hosthandle = 0;
2068 frames++;
2069 } while (1);
2070 adapter->max_isr_xmits = max(adapter->max_isr_xmits, frames);
4d6f6af8
GKH		 2071}
2072
f66626e4
RK		 2073static void slic_interrupt_card_up(u32 isr, struct adapter *adapter,
2074 struct net_device *dev)
2075{
2076 if (isr & ~ISR_IO) {
2077 if (isr & ISR_ERR) {
2078 adapter->error_interrupts++;
2079 if (isr & ISR_RMISS) {
2080 int count;
2081 int pre_count;
2082 int errors;
2083
2084 struct slic_rcvqueue *rcvq =
2085 &adapter->rcvqueue;
2086
2087 adapter->error_rmiss_interrupts++;
2088
2089 if (!rcvq->errors)
2090 rcv_count = rcvq->count;
2091 pre_count = rcvq->count;
2092 errors = rcvq->errors;
2093
2094 while (rcvq->count < SLIC_RCVQ_FILLTHRESH) {
2095 count = slic_rcvqueue_fill(adapter);
2096 if (!count)
2097 break;
2098 }
2099 } else if (isr & ISR_XDROP) {
2100 dev_err(&dev->dev,
17d2c643
SC		 2101 "isr & ISR_ERR [%x] ISR_XDROP\n",
2102 isr);
f66626e4
RK		 2103 } else {
2104 dev_err(&dev->dev,
2105 "isr & ISR_ERR [%x]\n",
2106 isr);
2107 }
2108 }
2109
2110 if (isr & ISR_LEVENT) {
2111 adapter->linkevent_interrupts++;
2112 slic_link_event_handler(adapter);
2113 }
2114
2115 if ((isr & ISR_UPC) || (isr & ISR_UPCERR) ||
2116 (isr & ISR_UPCBSY)) {
2117 adapter->upr_interrupts++;
2118 slic_upr_request_complete(adapter, isr);
2119 }
2120 }
2121
2122 if (isr & ISR_RCV) {
2123 adapter->rcv_interrupts++;
2124 slic_rcv_handler(adapter);
2125 }
2126
2127 if (isr & ISR_CMD) {
2128 adapter->xmit_interrupts++;
2129 slic_xmit_complete(adapter);
2130 }
2131}
2132
2133
4d6ea9c3 2134static irqreturn_t slic_interrupt(int irq, void *dev_id)
4d6f6af8 2135{
4d6ea9c3
DK		 2136 struct net_device *dev = (struct net_device *)dev_id;
2137 struct adapter *adapter = netdev_priv(dev);
2138 u32 isr;
4d6f6af8 2139
4d6ea9c3
DK		 2140 if ((adapter->pshmem) && (adapter->pshmem->isr)) {
2141 slic_reg32_write(&adapter->slic_regs->slic_icr,
2142 ICR_INT_MASK, FLUSH);
2143 isr = adapter->isrcopy = adapter->pshmem->isr;
2144 adapter->pshmem->isr = 0;
2145 adapter->num_isrs++;
2146 switch (adapter->card->state) {
2147 case CARD_UP:
f66626e4 2148 slic_interrupt_card_up(isr, adapter, dev);
4d6ea9c3 2149 break;
4d6f6af8 2150
4d6ea9c3
DK		 2151 case CARD_DOWN:
2152 if ((isr & ISR_UPC) ||
2153 (isr & ISR_UPCERR) || (isr & ISR_UPCBSY)) {
2154 adapter->upr_interrupts++;
2155 slic_upr_request_complete(adapter, isr);
2156 }
2157 break;
4d6ea9c3 2158 }
4d6f6af8 2159
4d6ea9c3
DK		 2160 adapter->isrcopy = 0;
2161 adapter->all_reg_writes += 2;
2162 adapter->isr_reg_writes++;
2163 slic_reg32_write(&adapter->slic_regs->slic_isr, 0, FLUSH);
2164 } else {
2165 adapter->false_interrupts++;
4d6f6af8 2166 }
4d6ea9c3 2167 return IRQ_HANDLED;
4d6f6af8
GKH		 2168}
2169
4d6ea9c3 2170#define NORMAL_ETHFRAME 0
4d6f6af8 2171
4d6ea9c3
DK		 2172static netdev_tx_t slic_xmit_start(struct sk_buff *skb, struct net_device *dev)
2173{
2174 struct sliccard *card;
2175 struct adapter *adapter = netdev_priv(dev);
2176 struct slic_hostcmd *hcmd = NULL;
2177 u32 status = 0;
4d6ea9c3 2178 void *offloadcmd = NULL;
4d6f6af8 2179
4d6ea9c3 2180 card = adapter->card;
4d6ea9c3
DK		 2181 if ((adapter->linkstate != LINK_UP) ||
2182 (adapter->state != ADAPT_UP) || (card->state != CARD_UP)) {
2183 status = XMIT_FAIL_LINK_STATE;
2184 goto xmit_fail;
4d6f6af8 2185
4d6ea9c3
DK		 2186 } else if (skb->len == 0) {
2187 status = XMIT_FAIL_ZERO_LENGTH;
2188 goto xmit_fail;
4d6f6af8
GKH		 2189 }
2190
cbb0920b
PH		 2191 hcmd = slic_cmdq_getfree(adapter);
2192 if (!hcmd) {
2193 adapter->xmitq_full = 1;
2194 status = XMIT_FAIL_HOSTCMD_FAIL;
2195 goto xmit_fail;
4d6ea9c3 2196 }
cbb0920b
PH		 2197 hcmd->skb = skb;
2198 hcmd->busy = 1;
2199 hcmd->type = SLIC_CMD_DUMB;
2200 slic_xmit_build_request(adapter, hcmd, skb);
9092de6d
DK		 2201 dev->stats.tx_packets++;
2202 dev->stats.tx_bytes += skb->len;
4d6f6af8 2203
4d6ea9c3
DK		 2204#ifdef DEBUG_DUMP
2205 if (adapter->kill_card) {
2206 struct slic_host64_cmd ihcmd;
4d6f6af8 2207
4d6ea9c3
DK		 2208 ihcmd = &hcmd->cmd64;
2209
2210 ihcmd->flags |= 0x40;
2211 adapter->kill_card = 0; /* only do this once */
4d6f6af8 2212 }
4d6ea9c3
DK		 2213#endif
2214 if (hcmd->paddrh == 0) {
2215 slic_reg32_write(&adapter->slic_regs->slic_cbar,
2216 (hcmd->paddrl | hcmd->cmdsize), DONT_FLUSH);
2217 } else {
2218 slic_reg64_write(adapter, &adapter->slic_regs->slic_cbar64,
2219 (hcmd->paddrl | hcmd->cmdsize),
2220 &adapter->slic_regs->slic_addr_upper,
2221 hcmd->paddrh, DONT_FLUSH);
2222 }
2223xmit_done:
2224 return NETDEV_TX_OK;
2225xmit_fail:
cbb0920b 2226 slic_xmit_fail(adapter, skb, offloadcmd, NORMAL_ETHFRAME, status);
4d6ea9c3 2227 goto xmit_done;
4d6f6af8
GKH		 2228}
2229
4d6ea9c3
DK		 2230
2231static void slic_adapter_freeresources(struct adapter *adapter)
4d6f6af8 2232{
4d6ea9c3 2233 slic_init_cleanup(adapter);
4d6ea9c3
DK		 2234 adapter->error_interrupts = 0;
2235 adapter->rcv_interrupts = 0;
2236 adapter->xmit_interrupts = 0;
2237 adapter->linkevent_interrupts = 0;
2238 adapter->upr_interrupts = 0;
2239 adapter->num_isrs = 0;
2240 adapter->xmit_completes = 0;
2241 adapter->rcv_broadcasts = 0;
2242 adapter->rcv_multicasts = 0;
2243 adapter->rcv_unicasts = 0;
2244}
4d6f6af8 2245
eafe6002
DM		 2246static int slic_adapter_allocresources(struct adapter *adapter,
2247 unsigned long *flags)
4d6ea9c3
DK		 2248{
2249 if (!adapter->intrregistered) {
2250 int retval;
4d6f6af8 2251
eafe6002 2252 spin_unlock_irqrestore(&slic_global.driver_lock, *flags);
4d6f6af8 2253
4d6ea9c3
DK		 2254 retval = request_irq(adapter->netdev->irq,
2255 &slic_interrupt,
2256 IRQF_SHARED,
2257 adapter->netdev->name, adapter->netdev);
4d6f6af8 2258
eafe6002 2259 spin_lock_irqsave(&slic_global.driver_lock, *flags);
4d6ea9c3
DK		 2260
2261 if (retval) {
2262 dev_err(&adapter->netdev->dev,
2263 "request_irq (%s) FAILED [%x]\n",
2264 adapter->netdev->name, retval);
2265 return retval;
4d6f6af8 2266 }
4d6ea9c3 2267 adapter->intrregistered = 1;
4d6f6af8 2268 }
d1939786 2269 return 0;
4d6f6af8
GKH		 2270}
2271
4d6ea9c3
DK		 2272/*
2273 * slic_if_init
2274 *
2275 * Perform initialization of our slic interface.
2276 *
2277 */
eafe6002 2278static int slic_if_init(struct adapter *adapter, unsigned long *flags)
4d6f6af8 2279{
4d6ea9c3
DK		 2280 struct sliccard *card = adapter->card;
2281 struct net_device *dev = adapter->netdev;
2282 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
2283 struct slic_shmem *pshmem;
2284 int rc;
4d6f6af8 2285
4d6ea9c3
DK		 2286 /* adapter should be down at this point */
2287 if (adapter->state != ADAPT_DOWN) {
2288 dev_err(&dev->dev, "%s: adapter->state != ADAPT_DOWN\n",
2289 __func__);
2290 rc = -EIO;
2291 goto err;
4d6f6af8 2292 }
4d6f6af8 2293
4d6ea9c3
DK		 2294 adapter->devflags_prev = dev->flags;
2295 adapter->macopts = MAC_DIRECTED;
2296 if (dev->flags) {
2297 if (dev->flags & IFF_BROADCAST)
2298 adapter->macopts |= MAC_BCAST;
2299 if (dev->flags & IFF_PROMISC)
2300 adapter->macopts |= MAC_PROMISC;
2301 if (dev->flags & IFF_ALLMULTI)
2302 adapter->macopts |= MAC_ALLMCAST;
2303 if (dev->flags & IFF_MULTICAST)
2304 adapter->macopts |= MAC_MCAST;
2305 }
eafe6002 2306 rc = slic_adapter_allocresources(adapter, flags);
4d6ea9c3 2307 if (rc) {
eb856202
HM		 2308 dev_err(&dev->dev, "slic_adapter_allocresources FAILED %x\n",
2309 rc);
4d6ea9c3
DK		 2310 slic_adapter_freeresources(adapter);
2311 goto err;
2312 }
4d6f6af8 2313
4d6ea9c3 2314 if (!adapter->queues_initialized) {
83682cd2
CJB		 2315 rc = slic_rspqueue_init(adapter);
2316 if (rc)
4d6ea9c3 2317 goto err;
83682cd2
CJB		 2318 rc = slic_cmdq_init(adapter);
2319 if (rc)
4d6ea9c3 2320 goto err;
83682cd2
CJB		 2321 rc = slic_rcvqueue_init(adapter);
2322 if (rc)
4d6ea9c3
DK		 2323 goto err;
2324 adapter->queues_initialized = 1;
2325 }
4d6f6af8 2326
4d6ea9c3
DK		 2327 slic_reg32_write(&slic_regs->slic_icr, ICR_INT_OFF, FLUSH);
2328 mdelay(1);
2329
2330 if (!adapter->isp_initialized) {
eafe6002 2331 unsigned long flags;
01d0a9b4
JP		 2332 pshmem = (struct slic_shmem *)(unsigned long)
2333 adapter->phys_shmem;
4d6ea9c3 2334
eafe6002 2335 spin_lock_irqsave(&adapter->bit64reglock, flags);
4d6ea9c3 2336
1033f1f7 2337#if BITS_PER_LONG == 64
4d6ea9c3
DK		 2338 slic_reg32_write(&slic_regs->slic_addr_upper,
2339 SLIC_GET_ADDR_HIGH(&pshmem->isr), DONT_FLUSH);
2340 slic_reg32_write(&slic_regs->slic_isp,
2341 SLIC_GET_ADDR_LOW(&pshmem->isr), FLUSH);
1033f1f7 2342#else
4d6ea9c3 2343 slic_reg32_write(&slic_regs->slic_addr_upper, 0, DONT_FLUSH);
17d2c643
SC		 2344 slic_reg32_write(&slic_regs->slic_isp, (u32)&pshmem->isr,
2345 FLUSH);
4d6f6af8 2346#endif
eafe6002 2347 spin_unlock_irqrestore(&adapter->bit64reglock, flags);
4d6ea9c3 2348 adapter->isp_initialized = 1;
4d6f6af8 2349 }
4d6f6af8 2350
4d6ea9c3
DK		 2351 adapter->state = ADAPT_UP;
2352 if (!card->loadtimerset) {
7d2b3cf7
AM		 2353 setup_timer(&card->loadtimer, &slic_timer_load_check,
2354 (ulong)card);
4d6ea9c3
DK		 2355 card->loadtimer.expires =
2356 jiffies + (SLIC_LOADTIMER_PERIOD * HZ);
4d6ea9c3
DK		 2357 add_timer(&card->loadtimer);
2358
2359 card->loadtimerset = 1;
2360 }
2361
2362 if (!adapter->pingtimerset) {
7d2b3cf7 2363 setup_timer(&adapter->pingtimer, &slic_timer_ping, (ulong)dev);
4d6ea9c3
DK		 2364 adapter->pingtimer.expires =
2365 jiffies + (PING_TIMER_INTERVAL * HZ);
4d6ea9c3
DK		 2366 add_timer(&adapter->pingtimer);
2367 adapter->pingtimerset = 1;
2368 adapter->card->pingstatus = ISR_PINGMASK;
2369 }
2370
2371 /*
2372 * clear any pending events, then enable interrupts
2373 */
2374 adapter->isrcopy = 0;
2375 adapter->pshmem->isr = 0;
2376 slic_reg32_write(&slic_regs->slic_isr, 0, FLUSH);
2377 slic_reg32_write(&slic_regs->slic_icr, ICR_INT_ON, FLUSH);
2378
2379 slic_link_config(adapter, LINK_AUTOSPEED, LINK_AUTOD);
2380 slic_link_event_handler(adapter);
4d6f6af8 2381
4d6ea9c3
DK		 2382err:
2383 return rc;
4d6f6af8
GKH		 2384}
2385
4d6ea9c3 2386static int slic_entry_open(struct net_device *dev)
4d6f6af8 2387{
4d6ea9c3
DK		 2388 struct adapter *adapter = netdev_priv(dev);
2389 struct sliccard *card = adapter->card;
eafe6002 2390 unsigned long flags;
4d6ea9c3 2391 int status;
4d6f6af8 2392
4d6ea9c3 2393 netif_stop_queue(adapter->netdev);
4d6f6af8 2394
eafe6002 2395 spin_lock_irqsave(&slic_global.driver_lock, flags);
4d6ea9c3
DK		 2396 if (!adapter->activated) {
2397 card->adapters_activated++;
2398 slic_global.num_slic_ports_active++;
2399 adapter->activated = 1;
2400 }
eafe6002 2401 status = slic_if_init(adapter, &flags);
4d6f6af8 2402
4d6ea9c3
DK		 2403 if (status != 0) {
2404 if (adapter->activated) {
2405 card->adapters_activated--;
2406 slic_global.num_slic_ports_active--;
2407 adapter->activated = 0;
4d6f6af8 2408 }
71329965 2409 goto spin_unlock;
4d6ea9c3
DK		 2410 }
2411 if (!card->master)
2412 card->master = adapter;
2413
71329965 2414spin_unlock:
eafe6002 2415 spin_unlock_irqrestore(&slic_global.driver_lock, flags);
71329965 2416 return status;
4d6f6af8
GKH		 2417}
2418
4d6ea9c3 2419static void slic_card_cleanup(struct sliccard *card)
4d6f6af8 2420{
4d6ea9c3
DK		 2421 if (card->loadtimerset) {
2422 card->loadtimerset = 0;
161737a6 2423 del_timer_sync(&card->loadtimer);
4d6ea9c3 2424 }
4d6f6af8 2425
4d6ea9c3 2426 kfree(card);
4d6f6af8
GKH		 2427}
2428
ecb4f387 2429static void slic_entry_remove(struct pci_dev *pcidev)
4d6f6af8 2430{
4d6ea9c3 2431 struct net_device *dev = pci_get_drvdata(pcidev);
4d6ea9c3
DK		 2432 struct adapter *adapter = netdev_priv(dev);
2433 struct sliccard *card;
2434 struct mcast_address *mcaddr, *mlist;
4d6f6af8 2435
dedabbbc
DM		 2436 unregister_netdev(dev);
2437
4d6ea9c3
DK		 2438 slic_adapter_freeresources(adapter);
2439 slic_unmap_mmio_space(adapter);
4d6ea9c3 2440
4d6ea9c3
DK		 2441 /* free multicast addresses */
2442 mlist = adapter->mcastaddrs;
2443 while (mlist) {
2444 mcaddr = mlist;
2445 mlist = mlist->next;
2446 kfree(mcaddr);
4d6f6af8 2447 }
4d6ea9c3 2448 card = adapter->card;
4d6ea9c3
DK		 2449 card->adapters_allocated--;
2450 adapter->allocated = 0;
2451 if (!card->adapters_allocated) {
2452 struct sliccard *curr_card = slic_global.slic_card;
0d0e9d9e 2453
4d6ea9c3
DK		 2454 if (curr_card == card) {
2455 slic_global.slic_card = card->next;
2456 } else {
2457 while (curr_card->next != card)
2458 curr_card = curr_card->next;
4d6ea9c3
DK		 2459 curr_card->next = card->next;
2460 }
4d6ea9c3
DK		 2461 slic_global.num_slic_cards--;
2462 slic_card_cleanup(card);
4d6f6af8 2463 }
20caa14c 2464 free_netdev(dev);
4d6ea9c3 2465 pci_release_regions(pcidev);
d99b5ac6 2466 pci_disable_device(pcidev);
4d6f6af8
GKH		 2467}
2468
4d6ea9c3 2469static int slic_entry_halt(struct net_device *dev)
4d6f6af8 2470{
4d6ea9c3
DK		 2471 struct adapter *adapter = netdev_priv(dev);
2472 struct sliccard *card = adapter->card;
2473 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
eafe6002 2474 unsigned long flags;
4d6f6af8 2475
eafe6002 2476 spin_lock_irqsave(&slic_global.driver_lock, flags);
4d6ea9c3
DK		 2477 netif_stop_queue(adapter->netdev);
2478 adapter->state = ADAPT_DOWN;
2479 adapter->linkstate = LINK_DOWN;
2480 adapter->upr_list = NULL;
2481 adapter->upr_busy = 0;
2482 adapter->devflags_prev = 0;
4d6ea9c3
DK		 2483 slic_reg32_write(&slic_regs->slic_icr, ICR_INT_OFF, FLUSH);
2484 adapter->all_reg_writes++;
2485 adapter->icr_reg_writes++;
2486 slic_config_clear(adapter);
2487 if (adapter->activated) {
2488 card->adapters_activated--;
2489 slic_global.num_slic_ports_active--;
2490 adapter->activated = 0;
2491 }
2492#ifdef AUTOMATIC_RESET
2493 slic_reg32_write(&slic_regs->slic_reset_iface, 0, FLUSH);
2494#endif
2495 /*
2496 * Reset the adapter's cmd queues
2497 */
2498 slic_cmdq_reset(adapter);
4d6f6af8 2499
4d6ea9c3
DK		 2500#ifdef AUTOMATIC_RESET
2501 if (!card->adapters_activated)
2502 slic_card_init(card, adapter);
2503#endif
4d6f6af8 2504
eafe6002 2505 spin_unlock_irqrestore(&slic_global.driver_lock, flags);
4d6ea9c3
DK		 2506 return 0;
2507}
4d6f6af8 2508
4d6ea9c3
DK		 2509static struct net_device_stats *slic_get_stats(struct net_device *dev)
2510{
2511 struct adapter *adapter = netdev_priv(dev);
4d6f6af8 2512
4d6ea9c3
DK		 2513 dev->stats.collisions = adapter->slic_stats.iface.xmit_collisions;
2514 dev->stats.rx_errors = adapter->slic_stats.iface.rcv_errors;
2515 dev->stats.tx_errors = adapter->slic_stats.iface.xmt_errors;
2516 dev->stats.rx_missed_errors = adapter->slic_stats.iface.rcv_discards;
2517 dev->stats.tx_heartbeat_errors = 0;
2518 dev->stats.tx_aborted_errors = 0;
2519 dev->stats.tx_window_errors = 0;
2520 dev->stats.tx_fifo_errors = 0;
2521 dev->stats.rx_frame_errors = 0;
2522 dev->stats.rx_length_errors = 0;
2523
2524 return &dev->stats;
4d6f6af8
GKH		 2525}
2526
4d6ea9c3 2527static int slic_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4d6f6af8 2528{
4d6ea9c3
DK		 2529 struct adapter *adapter = netdev_priv(dev);
2530 struct ethtool_cmd edata;
2531 struct ethtool_cmd ecmd;
2532 u32 data[7];
2533 u32 intagg;
4d6f6af8 2534
4d6ea9c3
DK		 2535 switch (cmd) {
2536 case SIOCSLICSETINTAGG:
2537 if (copy_from_user(data, rq->ifr_data, 28))
2538 return -EFAULT;
2539 intagg = data[0];
eb856202
HM		 2540 dev_err(&dev->dev, "set interrupt aggregation to %d\n",
2541 intagg);
4d6ea9c3
DK		 2542 slic_intagg_set(adapter, intagg);
2543 return 0;
4d6f6af8 2544
4d6ea9c3 2545 case SIOCETHTOOL:
4d6ea9c3
DK		 2546 if (copy_from_user(&ecmd, rq->ifr_data, sizeof(ecmd)))
2547 return -EFAULT;
4d6f6af8 2548
4d6ea9c3 2549 if (ecmd.cmd == ETHTOOL_GSET) {
986d7584 2550 memset(&edata, 0, sizeof(edata));
4d6ea9c3
DK		 2551 edata.supported = (SUPPORTED_10baseT_Half |
2552 SUPPORTED_10baseT_Full |
2553 SUPPORTED_100baseT_Half |
2554 SUPPORTED_100baseT_Full |
2555 SUPPORTED_Autoneg | SUPPORTED_MII);
2556 edata.port = PORT_MII;
2557 edata.transceiver = XCVR_INTERNAL;
2558 edata.phy_address = 0;
2559 if (adapter->linkspeed == LINK_100MB)
2560 edata.speed = SPEED_100;
2561 else if (adapter->linkspeed == LINK_10MB)
2562 edata.speed = SPEED_10;
2563 else
2564 edata.speed = 0;
4d6f6af8 2565
4d6ea9c3
DK		 2566 if (adapter->linkduplex == LINK_FULLD)
2567 edata.duplex = DUPLEX_FULL;
2568 else
2569 edata.duplex = DUPLEX_HALF;
4d6f6af8 2570
4d6ea9c3
DK		 2571 edata.autoneg = AUTONEG_ENABLE;
2572 edata.maxtxpkt = 1;
2573 edata.maxrxpkt = 1;
2574 if (copy_to_user(rq->ifr_data, &edata, sizeof(edata)))
2575 return -EFAULT;
4d6f6af8 2576
4d6ea9c3
DK		 2577 } else if (ecmd.cmd == ETHTOOL_SSET) {
2578 if (!capable(CAP_NET_ADMIN))
2579 return -EPERM;
4d6f6af8 2580
4d6ea9c3
DK		 2581 if (adapter->linkspeed == LINK_100MB)
2582 edata.speed = SPEED_100;
2583 else if (adapter->linkspeed == LINK_10MB)
2584 edata.speed = SPEED_10;
2585 else
2586 edata.speed = 0;
2587
2588 if (adapter->linkduplex == LINK_FULLD)
2589 edata.duplex = DUPLEX_FULL;
2590 else
2591 edata.duplex = DUPLEX_HALF;
2592
2593 edata.autoneg = AUTONEG_ENABLE;
2594 edata.maxtxpkt = 1;
2595 edata.maxrxpkt = 1;
2596 if ((ecmd.speed != edata.speed) ||
2597 (ecmd.duplex != edata.duplex)) {
2598 u32 speed;
2599 u32 duplex;
2600
2601 if (ecmd.speed == SPEED_10)
2602 speed = 0;
2603 else
2604 speed = PCR_SPEED_100;
2605 if (ecmd.duplex == DUPLEX_FULL)
2606 duplex = PCR_DUPLEX_FULL;
2607 else
2608 duplex = 0;
2609 slic_link_config(adapter, speed, duplex);
2610 slic_link_event_handler(adapter);
2611 }
2612 }
2613 return 0;
2614 default:
2615 return -EOPNOTSUPP;
2616 }
4d6f6af8
GKH		 2617}
2618
4d6ea9c3 2619static void slic_config_pci(struct pci_dev *pcidev)
4d6f6af8 2620{
4d6ea9c3
DK		 2621 u16 pci_command;
2622 u16 new_command;
4d6f6af8 2623
4d6ea9c3
DK		 2624 pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
2625
2626 new_command = pci_command | PCI_COMMAND_MASTER
2627 | PCI_COMMAND_MEMORY
2628 | PCI_COMMAND_INVALIDATE
2629 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
2630 if (pci_command != new_command)
2631 pci_write_config_word(pcidev, PCI_COMMAND, new_command);
4d6f6af8
GKH		 2632}
2633
4d6ea9c3 2634static int slic_card_init(struct sliccard *card, struct adapter *adapter)
4d6f6af8 2635{
4d6ea9c3
DK		 2636 __iomem struct slic_regs *slic_regs = adapter->slic_regs;
2637 struct slic_eeprom *peeprom;
2638 struct oslic_eeprom *pOeeprom;
2639 dma_addr_t phys_config;
2640 u32 phys_configh;
2641 u32 phys_configl;
2642 u32 i = 0;
2643 struct slic_shmem *pshmem;
2644 int status;
2645 uint macaddrs = card->card_size;
2646 ushort eecodesize;
2647 ushort dramsize;
2648 ushort ee_chksum;
2649 ushort calc_chksum;
2650 struct slic_config_mac *pmac;
2651 unsigned char fruformat;
2652 unsigned char oemfruformat;
2653 struct atk_fru *patkfru;
2654 union oemfru *poemfru;
eafe6002 2655 unsigned long flags;
4d6f6af8 2656
4d6ea9c3
DK		 2657 /* Reset everything except PCI configuration space */
2658 slic_soft_reset(adapter);
2659
2660 /* Download the microcode */
2661 status = slic_card_download(adapter);
811e843d 2662 if (status)
4d6ea9c3 2663 return status;
4d6f6af8 2664
4d6ea9c3
DK		 2665 if (!card->config_set) {
2666 peeprom = pci_alloc_consistent(adapter->pcidev,
2667 sizeof(struct slic_eeprom),
2668 &phys_config);
4d6f6af8 2669
4d6ea9c3
DK		 2670 phys_configl = SLIC_GET_ADDR_LOW(phys_config);
2671 phys_configh = SLIC_GET_ADDR_HIGH(phys_config);
4d6f6af8 2672
4d6ea9c3
DK		 2673 if (!peeprom) {
2674 dev_err(&adapter->pcidev->dev,
811e843d 2675 "Failed to allocate DMA memory for EEPROM.\n");
4d6ea9c3 2676 return -ENOMEM;
4d6f6af8 2677 }
351e836f
VH		 2678
2679 memset(peeprom, 0, sizeof(struct slic_eeprom));
2680
4d6ea9c3
DK		 2681 slic_reg32_write(&slic_regs->slic_icr, ICR_INT_OFF, FLUSH);
2682 mdelay(1);
01d0a9b4
JP		 2683 pshmem = (struct slic_shmem *)(unsigned long)
2684 adapter->phys_shmem;
4d6f6af8 2685
eafe6002 2686 spin_lock_irqsave(&adapter->bit64reglock, flags);
0783c636
DM		 2687 slic_reg32_write(&slic_regs->slic_addr_upper,
2688 SLIC_GET_ADDR_HIGH(&pshmem->isr), DONT_FLUSH);
4d6ea9c3
DK		 2689 slic_reg32_write(&slic_regs->slic_isp,
2690 SLIC_GET_ADDR_LOW(&pshmem->isr), FLUSH);
eafe6002 2691 spin_unlock_irqrestore(&adapter->bit64reglock, flags);
4d6f6af8 2692
47a401a8
DM		 2693 status = slic_config_get(adapter, phys_configl, phys_configh);
2694 if (status) {
2695 dev_err(&adapter->pcidev->dev,
2696 "Failed to fetch config data from device.\n");
2697 goto card_init_err;
2698 }
4d6f6af8 2699
4d6ea9c3
DK		 2700 for (;;) {
2701 if (adapter->pshmem->isr) {
2702 if (adapter->pshmem->isr & ISR_UPC) {
2703 adapter->pshmem->isr = 0;
2704 slic_reg64_write(adapter,
2705 &slic_regs->slic_isp, 0,
2706 &slic_regs->slic_addr_upper,
2707 0, FLUSH);
2708 slic_reg32_write(&slic_regs->slic_isr,
2709 0, FLUSH);
2710
2711 slic_upr_request_complete(adapter, 0);
2712 break;
4d6ea9c3 2713 }
351e836f
VH		 2714
2715 adapter->pshmem->isr = 0;
2716 slic_reg32_write(&slic_regs->slic_isr,
2717 0, FLUSH);
4d6f6af8 2718 } else {
4d6ea9c3
DK		 2719 mdelay(1);
2720 i++;
2721 if (i > 5000) {
2722 dev_err(&adapter->pcidev->dev,
811e843d 2723 "Fetch of config data timed out.\n");
4d6ea9c3
DK		 2724 slic_reg64_write(adapter,
2725 &slic_regs->slic_isp, 0,
2726 &slic_regs->slic_addr_upper,
2727 0, FLUSH);
47a401a8
DM		 2728 status = -EINVAL;
2729 goto card_init_err;
4d6ea9c3 2730 }
4d6f6af8 2731 }
4d6ea9c3
DK		 2732 }
2733
2734 switch (adapter->devid) {
2735 /* Oasis card */
2736 case SLIC_2GB_DEVICE_ID:
2737 /* extract EEPROM data and pointers to EEPROM data */
2738 pOeeprom = (struct oslic_eeprom *) peeprom;
2739 eecodesize = pOeeprom->EecodeSize;
2740 dramsize = pOeeprom->DramSize;
2741 pmac = pOeeprom->MacInfo;
2742 fruformat = pOeeprom->FruFormat;
2743 patkfru = &pOeeprom->AtkFru;
2744 oemfruformat = pOeeprom->OemFruFormat;
2745 poemfru = &pOeeprom->OemFru;
2746 macaddrs = 2;
2747 /* Minor kludge for Oasis card
2748 get 2 MAC addresses from the
2749 EEPROM to ensure that function 1
2750 gets the Port 1 MAC address */
2751 break;
2752 default:
2753 /* extract EEPROM data and pointers to EEPROM data */
2754 eecodesize = peeprom->EecodeSize;
2755 dramsize = peeprom->DramSize;
2756 pmac = peeprom->u2.mac.MacInfo;
2757 fruformat = peeprom->FruFormat;
2758 patkfru = &peeprom->AtkFru;
2759 oemfruformat = peeprom->OemFruFormat;
2760 poemfru = &peeprom->OemFru;
4d6f6af8
GKH		 2761 break;
2762 }
4d6f6af8 2763
4d6ea9c3
DK		 2764 card->config.EepromValid = false;
2765
2766 /* see if the EEPROM is valid by checking it's checksum */
2767 if ((eecodesize <= MAX_EECODE_SIZE) &&
2768 (eecodesize >= MIN_EECODE_SIZE)) {
2769
2770 ee_chksum =
2771 *(u16 *) ((char *) peeprom + (eecodesize - 2));
2772 /*
2773 calculate the EEPROM checksum
2774 */
55b62cdf
DM		 2775 calc_chksum = slic_eeprom_cksum(peeprom,
2776 eecodesize - 2);
4d6ea9c3
DK		 2777 /*
2778 if the ucdoe chksum flag bit worked,
7864a0ac 2779 we wouldn't need this
4d6ea9c3
DK		 2780 */
2781 if (ee_chksum == calc_chksum)
2782 card->config.EepromValid = true;
2783 }
2784 /* copy in the DRAM size */
2785 card->config.DramSize = dramsize;
2786
2787 /* copy in the MAC address(es) */
2788 for (i = 0; i < macaddrs; i++) {
2789 memcpy(&card->config.MacInfo[i],
2790 &pmac[i], sizeof(struct slic_config_mac));
2791 }
4d6f6af8 2792
4d6ea9c3
DK		 2793 /* copy the Alacritech FRU information */
2794 card->config.FruFormat = fruformat;
2795 memcpy(&card->config.AtkFru, patkfru,
2796 sizeof(struct atk_fru));
e9eff9d6 2797
4d6ea9c3
DK		 2798 pci_free_consistent(adapter->pcidev,
2799 sizeof(struct slic_eeprom),
2800 peeprom, phys_config);
4d6f6af8 2801
28277a55 2802 if (!card->config.EepromValid) {
4d6ea9c3
DK		 2803 slic_reg64_write(adapter, &slic_regs->slic_isp, 0,
2804 &slic_regs->slic_addr_upper,
2805 0, FLUSH);
811e843d 2806 dev_err(&adapter->pcidev->dev, "EEPROM invalid.\n");
4d6ea9c3
DK		 2807 return -EINVAL;
2808 }
4d6f6af8 2809
4d6ea9c3 2810 card->config_set = 1;
4d6f6af8 2811 }
4d6ea9c3 2812
811e843d
DM		 2813 status = slic_card_download_gbrcv(adapter);
2814 if (status)
2815 return status;
4d6ea9c3
DK		 2816
2817 if (slic_global.dynamic_intagg)
2818 slic_intagg_set(adapter, 0);
4d6f6af8 2819 else
4d6ea9c3 2820 slic_intagg_set(adapter, intagg_delay);
4d6f6af8 2821
4d6ea9c3
DK		 2822 /*
2823 * Initialize ping status to "ok"
2824 */
2825 card->pingstatus = ISR_PINGMASK;
4d6f6af8 2826
4d6ea9c3
DK		 2827 /*
2828 * Lastly, mark our card state as up and return success
2829 */
2830 card->state = CARD_UP;
2831 card->reset_in_progress = 0;
4d6f6af8 2832
4d6ea9c3 2833 return 0;
47a401a8
DM		 2834
2835card_init_err:
2836 pci_free_consistent(adapter->pcidev, sizeof(struct slic_eeprom),
2837 peeprom, phys_config);
2838 return status;
4d6ea9c3
DK		 2839}
2840
2841static void slic_init_driver(void)
2842{
2843 if (slic_first_init) {
2844 slic_first_init = 0;
eafe6002 2845 spin_lock_init(&slic_global.driver_lock);
4d6f6af8 2846 }
4d6ea9c3 2847}
4d6f6af8 2848
4d6ea9c3
DK		 2849static void slic_init_adapter(struct net_device *netdev,
2850 struct pci_dev *pcidev,
2851 const struct pci_device_id *pci_tbl_entry,
2852 void __iomem *memaddr, int chip_idx)
2853{
2854 ushort index;
2855 struct slic_handle *pslic_handle;
2856 struct adapter *adapter = netdev_priv(netdev);
4d6f6af8 2857
4d6ea9c3
DK		 2858/* adapter->pcidev = pcidev;*/
2859 adapter->vendid = pci_tbl_entry->vendor;
2860 adapter->devid = pci_tbl_entry->device;
2861 adapter->subsysid = pci_tbl_entry->subdevice;
2862 adapter->busnumber = pcidev->bus->number;
2863 adapter->slotnumber = ((pcidev->devfn >> 3) & 0x1F);
2864 adapter->functionnumber = (pcidev->devfn & 0x7);
4d6ea9c3
DK		 2865 adapter->slic_regs = (__iomem struct slic_regs *)memaddr;
2866 adapter->irq = pcidev->irq;
2867/* adapter->netdev = netdev;*/
4d6ea9c3
DK		 2868 adapter->chipid = chip_idx;
2869 adapter->port = 0; /*adapter->functionnumber;*/
2870 adapter->cardindex = adapter->port;
eafe6002
DM		 2871 spin_lock_init(&adapter->upr_lock);
2872 spin_lock_init(&adapter->bit64reglock);
2873 spin_lock_init(&adapter->adapter_lock);
2874 spin_lock_init(&adapter->reset_lock);
2875 spin_lock_init(&adapter->handle_lock);
4d6f6af8 2876
4d6ea9c3
DK		 2877 adapter->card_size = 1;
2878 /*
2879 Initialize slic_handle array
2880 */
4d6ea9c3
DK		 2881 /*
2882 Start with 1. 0 is an invalid host handle.
2883 */
2884 for (index = 1, pslic_handle = &adapter->slic_handles[1];
2885 index < SLIC_CMDQ_MAXCMDS; index++, pslic_handle++) {
2886
2887 pslic_handle->token.handle_index = index;
2888 pslic_handle->type = SLIC_HANDLE_FREE;
2889 pslic_handle->next = adapter->pfree_slic_handles;
2890 adapter->pfree_slic_handles = pslic_handle;
4d6f6af8 2891 }
4d6ea9c3
DK		 2892 adapter->pshmem = (struct slic_shmem *)
2893 pci_alloc_consistent(adapter->pcidev,
2894 sizeof(struct slic_shmem),
2895 &adapter->
2896 phys_shmem);
b8131fc0
DN		 2897 if (adapter->pshmem)
2898 memset(adapter->pshmem, 0, sizeof(struct slic_shmem));
4d6ea9c3 2899}
4d6f6af8 2900
4d6ea9c3
DK		 2901static const struct net_device_ops slic_netdev_ops = {
2902 .ndo_open = slic_entry_open,
2903 .ndo_stop = slic_entry_halt,
2904 .ndo_start_xmit = slic_xmit_start,
2905 .ndo_do_ioctl = slic_ioctl,
2906 .ndo_set_mac_address = slic_mac_set_address,
2907 .ndo_get_stats = slic_get_stats,
afc4b13d 2908 .ndo_set_rx_mode = slic_mcast_set_list,
4d6ea9c3
DK		 2909 .ndo_validate_addr = eth_validate_addr,
2910 .ndo_change_mtu = eth_change_mtu,
2911};
4d6f6af8 2912
4d6ea9c3
DK		 2913static u32 slic_card_locate(struct adapter *adapter)
2914{
2915 struct sliccard *card = slic_global.slic_card;
2916 struct physcard *physcard = slic_global.phys_card;
2917 ushort card_hostid;
2918 u16 __iomem *hostid_reg;
2919 uint i;
2920 uint rdhostid_offset = 0;
4d6f6af8 2921
4d6ea9c3
DK		 2922 switch (adapter->devid) {
2923 case SLIC_2GB_DEVICE_ID:
2924 rdhostid_offset = SLIC_RDHOSTID_2GB;
2925 break;
2926 case SLIC_1GB_DEVICE_ID:
2927 rdhostid_offset = SLIC_RDHOSTID_1GB;
2928 break;
4d6f6af8 2929 default:
0ab19005 2930 return -ENODEV;
4d6f6af8 2931 }
4d6f6af8 2932
4d6ea9c3
DK		 2933 hostid_reg =
2934 (u16 __iomem *) (((u8 __iomem *) (adapter->slic_regs)) +
2935 rdhostid_offset);
4d6f6af8 2936
4d6ea9c3
DK		 2937 /* read the 16 bit hostid from SRAM */
2938 card_hostid = (ushort) readw(hostid_reg);
4d6f6af8 2939
4d6ea9c3
DK		 2940 /* Initialize a new card structure if need be */
2941 if (card_hostid == SLIC_HOSTID_DEFAULT) {
2942 card = kzalloc(sizeof(struct sliccard), GFP_KERNEL);
2943 if (card == NULL)
2944 return -ENOMEM;
2945
2946 card->next = slic_global.slic_card;
2947 slic_global.slic_card = card;
2948 card->busnumber = adapter->busnumber;
2949 card->slotnumber = adapter->slotnumber;
2950
2951 /* Find an available cardnum */
2952 for (i = 0; i < SLIC_MAX_CARDS; i++) {
2953 if (slic_global.cardnuminuse[i] == 0) {
2954 slic_global.cardnuminuse[i] = 1;
2955 card->cardnum = i;
2956 break;
2957 }
2958 }
2959 slic_global.num_slic_cards++;
4d6ea9c3
DK		 2960 } else {
2961 /* Card exists, find the card this adapter belongs to */
2962 while (card) {
2963 if (card->cardnum == card_hostid)
2964 break;
2965 card = card->next;
2966 }
2967 }
2968
4d6ea9c3
DK		 2969 if (!card)
2970 return -ENXIO;
2971 /* Put the adapter in the card's adapter list */
4d6ea9c3
DK		 2972 if (!card->adapter[adapter->port]) {
2973 card->adapter[adapter->port] = adapter;
2974 adapter->card = card;
2975 }
2976
2977 card->card_size = 1; /* one port per *logical* card */
2978
2979 while (physcard) {
2980 for (i = 0; i < SLIC_MAX_PORTS; i++) {
20d403e8 2981 if (physcard->adapter[i])
4d6ea9c3
DK		 2982 break;
2983 }
20d403e8
PH		 2984 if (i == SLIC_MAX_PORTS)
2985 break;
2986
4d6ea9c3
DK		 2987 if (physcard->adapter[i]->slotnumber == adapter->slotnumber)
2988 break;
2989 physcard = physcard->next;
2990 }
2991 if (!physcard) {
2992 /* no structure allocated for this physical card yet */
2993 physcard = kzalloc(sizeof(struct physcard), GFP_ATOMIC);
34ec83f4
DN		 2994 if (!physcard) {
2995 if (card_hostid == SLIC_HOSTID_DEFAULT)
2996 kfree(card);
0608882d 2997 return -ENOMEM;
34ec83f4 2998 }
4d6ea9c3
DK		 2999
3000 physcard->next = slic_global.phys_card;
3001 slic_global.phys_card = physcard;
3002 physcard->adapters_allocd = 1;
3003 } else {
3004 physcard->adapters_allocd++;
3005 }
3006 /* Note - this is ZERO relative */
3007 adapter->physport = physcard->adapters_allocd - 1;
3008
4d6ea9c3
DK		 3009 physcard->adapter[adapter->physport] = adapter;
3010 adapter->physcard = physcard;
4d6f6af8
GKH		 3011
3012 return 0;
3013}
4d6f6af8 3014
a0c2feb1 3015static int slic_entry_probe(struct pci_dev *pcidev,
4d6ea9c3 3016 const struct pci_device_id *pci_tbl_entry)
4d6f6af8 3017{
4d6ea9c3
DK		 3018 static int cards_found;
3019 static int did_version;
3020 int err = -ENODEV;
3021 struct net_device *netdev;
3022 struct adapter *adapter;
3023 void __iomem *memmapped_ioaddr = NULL;
4d6ea9c3
DK		 3024 ulong mmio_start = 0;
3025 ulong mmio_len = 0;
3026 struct sliccard *card = NULL;
3027 int pci_using_dac = 0;
4d6f6af8 3028
4d6ea9c3 3029 slic_global.dynamic_intagg = dynamic_intagg;
4d6f6af8 3030
4d6ea9c3 3031 err = pci_enable_device(pcidev);
4d6f6af8 3032
4d6ea9c3
DK		 3033 if (err)
3034 return err;
4d6f6af8 3035
04cc3c8a
DM		 3036 if (did_version++ == 0) {
3037 dev_info(&pcidev->dev, "%s\n", slic_banner);
3038 dev_info(&pcidev->dev, "%s\n", slic_proc_version);
4d6ea9c3 3039 }
4d6f6af8 3040
4d6ea9c3
DK		 3041 if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
3042 pci_using_dac = 1;
1154eb51
WY		 3043 err = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
3044 if (err) {
79b0ae8d 3045 dev_err(&pcidev->dev, "unable to obtain 64-bit DMA for consistent allocations\n");
4d6ea9c3
DK		 3046 goto err_out_disable_pci;
3047 }
1154eb51
WY		 3048 } else {
3049 err = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
3050 if (err) {
3051 dev_err(&pcidev->dev, "no usable DMA configuration\n");
3052 goto err_out_disable_pci;
3053 }
4d6ea9c3
DK		 3054 pci_using_dac = 0;
3055 pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
4d6ea9c3 3056 }
4d6f6af8 3057
4d6ea9c3
DK		 3058 err = pci_request_regions(pcidev, DRV_NAME);
3059 if (err) {
3060 dev_err(&pcidev->dev, "can't obtain PCI resources\n");
3061 goto err_out_disable_pci;
3062 }
4d6f6af8 3063
4d6ea9c3 3064 pci_set_master(pcidev);
4d6f6af8 3065
4d6ea9c3
DK		 3066 netdev = alloc_etherdev(sizeof(struct adapter));
3067 if (!netdev) {
3068 err = -ENOMEM;
3069 goto err_out_exit_slic_probe;
4d6f6af8 3070 }
4d6f6af8 3071
4d6ea9c3 3072 SET_NETDEV_DEV(netdev, &pcidev->dev);
4d6f6af8 3073
4d6ea9c3
DK		 3074 pci_set_drvdata(pcidev, netdev);
3075 adapter = netdev_priv(netdev);
3076 adapter->netdev = netdev;
3077 adapter->pcidev = pcidev;
3078 if (pci_using_dac)
3079 netdev->features |= NETIF_F_HIGHDMA;
4d6f6af8 3080
4d6ea9c3
DK		 3081 mmio_start = pci_resource_start(pcidev, 0);
3082 mmio_len = pci_resource_len(pcidev, 0);
3083
3084
3085/* memmapped_ioaddr = (u32)ioremap_nocache(mmio_start, mmio_len);*/
3086 memmapped_ioaddr = ioremap(mmio_start, mmio_len);
3087 if (!memmapped_ioaddr) {
3088 dev_err(&pcidev->dev, "cannot remap MMIO region %lx @ %lx\n",
3089 mmio_len, mmio_start);
1154eb51 3090 err = -ENOMEM;
4d6ea9c3 3091 goto err_out_free_netdev;
4d6f6af8 3092 }
4d6ea9c3
DK		 3093
3094 slic_config_pci(pcidev);
3095
3096 slic_init_driver();
3097
3098 slic_init_adapter(netdev,
3099 pcidev, pci_tbl_entry, memmapped_ioaddr, cards_found);
3100
1154eb51
WY		 3101 err = slic_card_locate(adapter);
3102 if (err) {
4d6ea9c3 3103 dev_err(&pcidev->dev, "cannot locate card\n");
eea7c703 3104 goto err_out_unmap;
4d6f6af8 3105 }
4d6ea9c3
DK		 3106
3107 card = adapter->card;
3108
3109 if (!adapter->allocated) {
3110 card->adapters_allocated++;
3111 adapter->allocated = 1;
4d6f6af8 3112 }
4d6f6af8 3113
65bc0aaa
DM		 3114 err = slic_card_init(card, adapter);
3115 if (err)
3116 goto err_out_unmap;
4d6f6af8 3117
65bc0aaa 3118 slic_adapter_set_hwaddr(adapter);
4d6f6af8 3119
563dce37 3120 netdev->base_addr = (unsigned long) memmapped_ioaddr;
4d6ea9c3
DK		 3121 netdev->irq = adapter->irq;
3122 netdev->netdev_ops = &slic_netdev_ops;
4d6f6af8 3123
4d6ea9c3
DK		 3124 strcpy(netdev->name, "eth%d");
3125 err = register_netdev(netdev);
3126 if (err) {
3127 dev_err(&pcidev->dev, "Cannot register net device, aborting.\n");
3128 goto err_out_unmap;
4d6f6af8 3129 }
4d6f6af8 3130
4d6ea9c3
DK		 3131 cards_found++;
3132
65bc0aaa 3133 return 0;
4d6ea9c3
DK		 3134
3135err_out_unmap:
3136 iounmap(memmapped_ioaddr);
4d6ea9c3
DK		 3137err_out_free_netdev:
3138 free_netdev(netdev);
3139err_out_exit_slic_probe:
3140 pci_release_regions(pcidev);
3141err_out_disable_pci:
3142 pci_disable_device(pcidev);
3143 return err;
3144}
4d6f6af8
GKH		 3145
3146static struct pci_driver slic_driver = {
3147 .name = DRV_NAME,
3148 .id_table = slic_pci_tbl,
3149 .probe = slic_entry_probe,
2e0d79c5 3150 .remove = slic_entry_remove,
4d6f6af8
GKH		 3151};
3152
3153static int __init slic_module_init(void)
3154{
4d6f6af8
GKH		 3155 slic_init_driver();
3156
e8bc9b7a 3157 return pci_register_driver(&slic_driver);
4d6f6af8
GKH		 3158}
3159
3160static void __exit slic_module_cleanup(void)
3161{
4d6f6af8 3162 pci_unregister_driver(&slic_driver);
4d6f6af8
GKH		 3163}
3164
3165module_init(slic_module_init);
3166module_exit(slic_module_cleanup);
Linux kernel - Deliverables
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