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5449c685 FB |
1 | /* |
2 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | * | |
612822f5 | 19 | * |
5449c685 FB |
20 | * File: mac.c |
21 | * | |
22 | * Purpose: MAC routines | |
23 | * | |
24 | * Author: Tevin Chen | |
25 | * | |
26 | * Date: May 21, 1996 | |
27 | * | |
28 | * Functions: | |
5449c685 FB |
29 | * MACbIsRegBitsOn - Test if All test Bits On |
30 | * MACbIsRegBitsOff - Test if All test Bits Off | |
31 | * MACbIsIntDisable - Test if MAC interrupt disable | |
5449c685 | 32 | * MACvSetShortRetryLimit - Set 802.11 Short Retry limit |
5449c685 | 33 | * MACvSetLongRetryLimit - Set 802.11 Long Retry limit |
5449c685 | 34 | * MACvSetLoopbackMode - Set MAC Loopback Mode |
5449c685 FB |
35 | * MACvSaveContext - Save Context of MAC Registers |
36 | * MACvRestoreContext - Restore Context of MAC Registers | |
5449c685 FB |
37 | * MACbSoftwareReset - Software Reset MAC |
38 | * MACbSafeRxOff - Turn Off MAC Rx | |
39 | * MACbSafeTxOff - Turn Off MAC Tx | |
40 | * MACbSafeStop - Stop MAC function | |
41 | * MACbShutdown - Shut down MAC | |
42 | * MACvInitialize - Initialize MAC | |
789d1aef JM |
43 | * MACvSetCurrRxDescAddr - Set Rx Descriptors Address |
44 | * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address | |
45 | * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address | |
5449c685 FB |
46 | * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC |
47 | * | |
48 | * Revision History: | |
49 | * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53 | |
50 | * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()& MACvEnableBusSusEn() | |
51 | * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry | |
52 | * | |
53 | */ | |
54 | ||
5449c685 | 55 | #include "tmacro.h" |
5449c685 | 56 | #include "mac.h" |
5449c685 | 57 | |
5449c685 FB |
58 | /* |
59 | * Description: | |
60 | * Test if all test bits on | |
61 | * | |
62 | * Parameters: | |
63 | * In: | |
c2d845de | 64 | * io_base - Base Address for MAC |
5449c685 FB |
65 | * byRegOfs - Offset of MAC Register |
66 | * byTestBits - Test bits | |
67 | * Out: | |
68 | * none | |
69 | * | |
5a5a2a6a | 70 | * Return Value: true if all test bits On; otherwise false |
5449c685 FB |
71 | * |
72 | */ | |
f9f853af | 73 | bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs, |
d4855fe1 | 74 | unsigned char byTestBits) |
5449c685 | 75 | { |
c2d845de | 76 | void __iomem *io_base = priv->PortOffset; |
5449c685 | 77 | |
f205e8d1 | 78 | return (ioread8(io_base + byRegOfs) & byTestBits) == byTestBits; |
5449c685 FB |
79 | } |
80 | ||
81 | /* | |
82 | * Description: | |
83 | * Test if all test bits off | |
84 | * | |
85 | * Parameters: | |
86 | * In: | |
c2d845de | 87 | * io_base - Base Address for MAC |
5449c685 FB |
88 | * byRegOfs - Offset of MAC Register |
89 | * byTestBits - Test bits | |
90 | * Out: | |
91 | * none | |
92 | * | |
5a5a2a6a | 93 | * Return Value: true if all test bits Off; otherwise false |
5449c685 FB |
94 | * |
95 | */ | |
f9f853af | 96 | bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs, |
d4855fe1 | 97 | unsigned char byTestBits) |
5449c685 | 98 | { |
c2d845de | 99 | void __iomem *io_base = priv->PortOffset; |
5449c685 | 100 | |
f205e8d1 | 101 | return !(ioread8(io_base + byRegOfs) & byTestBits); |
5449c685 FB |
102 | } |
103 | ||
104 | /* | |
105 | * Description: | |
106 | * Test if MAC interrupt disable | |
107 | * | |
108 | * Parameters: | |
109 | * In: | |
c2d845de | 110 | * io_base - Base Address for MAC |
5449c685 FB |
111 | * Out: |
112 | * none | |
113 | * | |
5a5a2a6a | 114 | * Return Value: true if interrupt is disable; otherwise false |
5449c685 FB |
115 | * |
116 | */ | |
f9f853af | 117 | bool MACbIsIntDisable(struct vnt_private *priv) |
5449c685 | 118 | { |
c2d845de | 119 | void __iomem *io_base = priv->PortOffset; |
5449c685 | 120 | |
e52ab0ec | 121 | if (ioread32(io_base + MAC_REG_IMR)) |
c3504bfd | 122 | return false; |
5449c685 | 123 | |
c3504bfd | 124 | return true; |
5449c685 FB |
125 | } |
126 | ||
5449c685 FB |
127 | /* |
128 | * Description: | |
129 | * Set 802.11 Short Retry Limit | |
130 | * | |
131 | * Parameters: | |
132 | * In: | |
c2d845de | 133 | * io_base - Base Address for MAC |
5449c685 FB |
134 | * byRetryLimit- Retry Limit |
135 | * Out: | |
136 | * none | |
137 | * | |
138 | * Return Value: none | |
139 | * | |
140 | */ | |
f9f853af | 141 | void MACvSetShortRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit) |
5449c685 | 142 | { |
c2d845de | 143 | void __iomem *io_base = priv->PortOffset; |
9ab81fb7 | 144 | /* set SRT */ |
3b8eb64c | 145 | iowrite8(byRetryLimit, io_base + MAC_REG_SRT); |
5449c685 FB |
146 | } |
147 | ||
5449c685 FB |
148 | |
149 | /* | |
150 | * Description: | |
151 | * Set 802.11 Long Retry Limit | |
152 | * | |
153 | * Parameters: | |
154 | * In: | |
c2d845de | 155 | * io_base - Base Address for MAC |
5449c685 FB |
156 | * byRetryLimit- Retry Limit |
157 | * Out: | |
158 | * none | |
159 | * | |
160 | * Return Value: none | |
161 | * | |
162 | */ | |
f9f853af | 163 | void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit) |
5449c685 | 164 | { |
c2d845de | 165 | void __iomem *io_base = priv->PortOffset; |
9ab81fb7 | 166 | /* set LRT */ |
3b8eb64c | 167 | iowrite8(byRetryLimit, io_base + MAC_REG_LRT); |
5449c685 FB |
168 | } |
169 | ||
5449c685 FB |
170 | /* |
171 | * Description: | |
172 | * Set MAC Loopback mode | |
173 | * | |
174 | * Parameters: | |
175 | * In: | |
c2d845de | 176 | * io_base - Base Address for MAC |
5449c685 FB |
177 | * byLoopbackMode - Loopback Mode |
178 | * Out: | |
179 | * none | |
180 | * | |
181 | * Return Value: none | |
182 | * | |
183 | */ | |
f9f853af | 184 | void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode) |
5449c685 | 185 | { |
c2d845de | 186 | void __iomem *io_base = priv->PortOffset; |
c3504bfd | 187 | |
c3504bfd | 188 | byLoopbackMode <<= 6; |
9ab81fb7 | 189 | /* set TCR */ |
58fe2702 MP |
190 | iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode, |
191 | io_base + MAC_REG_TEST); | |
5449c685 FB |
192 | } |
193 | ||
5449c685 FB |
194 | /* |
195 | * Description: | |
196 | * Save MAC registers to context buffer | |
197 | * | |
198 | * Parameters: | |
199 | * In: | |
c2d845de | 200 | * io_base - Base Address for MAC |
5449c685 | 201 | * Out: |
70715017 | 202 | * cxt_buf - Context buffer |
5449c685 FB |
203 | * |
204 | * Return Value: none | |
205 | * | |
206 | */ | |
70715017 | 207 | void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf) |
5449c685 | 208 | { |
c2d845de | 209 | void __iomem *io_base = priv->PortOffset; |
5449c685 | 210 | |
9ab81fb7 | 211 | /* read page0 register */ |
70715017 | 212 | memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0); |
5449c685 | 213 | |
c2d845de | 214 | MACvSelectPage1(io_base); |
5449c685 | 215 | |
9ab81fb7 | 216 | /* read page1 register */ |
70715017 | 217 | memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base, |
7e5120e9 | 218 | MAC_MAX_CONTEXT_SIZE_PAGE1); |
5449c685 | 219 | |
c2d845de | 220 | MACvSelectPage0(io_base); |
5449c685 FB |
221 | } |
222 | ||
223 | /* | |
224 | * Description: | |
225 | * Restore MAC registers from context buffer | |
226 | * | |
227 | * Parameters: | |
228 | * In: | |
c2d845de | 229 | * io_base - Base Address for MAC |
70715017 | 230 | * cxt_buf - Context buffer |
5449c685 FB |
231 | * Out: |
232 | * none | |
233 | * | |
234 | * Return Value: none | |
235 | * | |
236 | */ | |
70715017 | 237 | void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf) |
5449c685 | 238 | { |
c2d845de | 239 | void __iomem *io_base = priv->PortOffset; |
5449c685 | 240 | |
c2d845de | 241 | MACvSelectPage1(io_base); |
9ab81fb7 | 242 | /* restore page1 */ |
46331952 MP |
243 | memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, |
244 | MAC_MAX_CONTEXT_SIZE_PAGE1); | |
bc5cf656 | 245 | |
c2d845de | 246 | MACvSelectPage0(io_base); |
5449c685 | 247 | |
9ab81fb7 | 248 | /* restore RCR,TCR,IMR... */ |
46331952 MP |
249 | memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR, |
250 | MAC_REG_ISR - MAC_REG_RCR); | |
bc5cf656 | 251 | |
9ab81fb7 | 252 | /* restore MAC Config. */ |
46331952 MP |
253 | memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT, |
254 | MAC_REG_PAGE1SEL - MAC_REG_LRT); | |
bc5cf656 | 255 | |
3b8eb64c | 256 | iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG); |
5449c685 | 257 | |
9ab81fb7 | 258 | /* restore PS Config. */ |
46331952 MP |
259 | memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG, |
260 | MAC_REG_BBREGCTL - MAC_REG_PSCFG); | |
5449c685 | 261 | |
9ab81fb7 | 262 | /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */ |
e2ad8e23 MP |
263 | iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0), |
264 | io_base + MAC_REG_TXDMAPTR0); | |
265 | iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR), | |
266 | io_base + MAC_REG_AC0DMAPTR); | |
267 | iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR), | |
268 | io_base + MAC_REG_BCNDMAPTR); | |
269 | iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0), | |
270 | io_base + MAC_REG_RXDMAPTR0); | |
271 | iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1), | |
272 | io_base + MAC_REG_RXDMAPTR1); | |
5449c685 FB |
273 | } |
274 | ||
5449c685 FB |
275 | /* |
276 | * Description: | |
277 | * Software Reset MAC | |
278 | * | |
279 | * Parameters: | |
280 | * In: | |
c2d845de | 281 | * io_base - Base Address for MAC |
5449c685 FB |
282 | * Out: |
283 | * none | |
284 | * | |
5a5a2a6a | 285 | * Return Value: true if Reset Success; otherwise false |
5449c685 FB |
286 | * |
287 | */ | |
f9f853af | 288 | bool MACbSoftwareReset(struct vnt_private *priv) |
5449c685 | 289 | { |
c2d845de | 290 | void __iomem *io_base = priv->PortOffset; |
c3504bfd JP |
291 | unsigned short ww; |
292 | ||
9ab81fb7 | 293 | /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */ |
3b8eb64c | 294 | iowrite8(0x01, io_base + MAC_REG_HOSTCR); |
c3504bfd JP |
295 | |
296 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { | |
f205e8d1 | 297 | if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST)) |
c3504bfd JP |
298 | break; |
299 | } | |
300 | if (ww == W_MAX_TIMEOUT) | |
301 | return false; | |
302 | return true; | |
5449c685 FB |
303 | } |
304 | ||
305 | /* | |
306 | * Description: | |
307 | * save some important register's value, then do reset, then restore register's value | |
308 | * | |
309 | * Parameters: | |
310 | * In: | |
c2d845de | 311 | * io_base - Base Address for MAC |
5449c685 FB |
312 | * Out: |
313 | * none | |
314 | * | |
5a5a2a6a | 315 | * Return Value: true if success; otherwise false |
5449c685 FB |
316 | * |
317 | */ | |
f9f853af | 318 | bool MACbSafeSoftwareReset(struct vnt_private *priv) |
5449c685 | 319 | { |
c3504bfd JP |
320 | unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0+MAC_MAX_CONTEXT_SIZE_PAGE1]; |
321 | bool bRetVal; | |
322 | ||
9ab81fb7 MS |
323 | /* PATCH.... |
324 | * save some important register's value, then do | |
325 | * reset, then restore register's value | |
326 | */ | |
327 | /* save MAC context */ | |
f9f853af | 328 | MACvSaveContext(priv, abyTmpRegData); |
9ab81fb7 | 329 | /* do reset */ |
f9f853af | 330 | bRetVal = MACbSoftwareReset(priv); |
9ab81fb7 | 331 | /* restore MAC context, except CR0 */ |
f9f853af | 332 | MACvRestoreContext(priv, abyTmpRegData); |
c3504bfd JP |
333 | |
334 | return bRetVal; | |
5449c685 FB |
335 | } |
336 | ||
337 | /* | |
338 | * Description: | |
b1797dfd | 339 | * Turn Off MAC Rx |
5449c685 FB |
340 | * |
341 | * Parameters: | |
342 | * In: | |
c2d845de | 343 | * io_base - Base Address for MAC |
5449c685 FB |
344 | * Out: |
345 | * none | |
346 | * | |
5a5a2a6a | 347 | * Return Value: true if success; otherwise false |
5449c685 FB |
348 | * |
349 | */ | |
f9f853af | 350 | bool MACbSafeRxOff(struct vnt_private *priv) |
5449c685 | 351 | { |
c2d845de | 352 | void __iomem *io_base = priv->PortOffset; |
c3504bfd | 353 | unsigned short ww; |
c3504bfd | 354 | |
9ab81fb7 | 355 | /* turn off wow temp for turn off Rx safely */ |
c3504bfd | 356 | |
9ab81fb7 | 357 | /* Clear RX DMA0,1 */ |
e2ad8e23 MP |
358 | iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0); |
359 | iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1); | |
c3504bfd | 360 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
e52ab0ec | 361 | if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN)) |
c3504bfd JP |
362 | break; |
363 | } | |
364 | if (ww == W_MAX_TIMEOUT) { | |
48caf5a0 | 365 | pr_debug(" DBG_PORT80(0x10)\n"); |
a4ef27ad | 366 | return false; |
c3504bfd JP |
367 | } |
368 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { | |
e52ab0ec | 369 | if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN)) |
c3504bfd JP |
370 | break; |
371 | } | |
372 | if (ww == W_MAX_TIMEOUT) { | |
48caf5a0 | 373 | pr_debug(" DBG_PORT80(0x11)\n"); |
a4ef27ad | 374 | return false; |
c3504bfd JP |
375 | } |
376 | ||
9ab81fb7 | 377 | /* try to safe shutdown RX */ |
c2d845de | 378 | MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON); |
9ab81fb7 | 379 | /* W_MAX_TIMEOUT is the timeout period */ |
c3504bfd | 380 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
f205e8d1 | 381 | if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST)) |
c3504bfd JP |
382 | break; |
383 | } | |
384 | if (ww == W_MAX_TIMEOUT) { | |
48caf5a0 | 385 | pr_debug(" DBG_PORT80(0x12)\n"); |
a4ef27ad | 386 | return false; |
c3504bfd JP |
387 | } |
388 | return true; | |
5449c685 FB |
389 | } |
390 | ||
391 | /* | |
392 | * Description: | |
b1797dfd | 393 | * Turn Off MAC Tx |
5449c685 FB |
394 | * |
395 | * Parameters: | |
396 | * In: | |
c2d845de | 397 | * io_base - Base Address for MAC |
5449c685 FB |
398 | * Out: |
399 | * none | |
400 | * | |
5a5a2a6a | 401 | * Return Value: true if success; otherwise false |
5449c685 FB |
402 | * |
403 | */ | |
f9f853af | 404 | bool MACbSafeTxOff(struct vnt_private *priv) |
5449c685 | 405 | { |
c2d845de | 406 | void __iomem *io_base = priv->PortOffset; |
c3504bfd | 407 | unsigned short ww; |
c3504bfd | 408 | |
9ab81fb7 MS |
409 | /* Clear TX DMA */ |
410 | /* Tx0 */ | |
e2ad8e23 | 411 | iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0); |
9ab81fb7 | 412 | /* AC0 */ |
e2ad8e23 | 413 | iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL); |
c3504bfd | 414 | |
c3504bfd | 415 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
e52ab0ec | 416 | if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN)) |
c3504bfd JP |
417 | break; |
418 | } | |
419 | if (ww == W_MAX_TIMEOUT) { | |
48caf5a0 | 420 | pr_debug(" DBG_PORT80(0x20)\n"); |
a4ef27ad | 421 | return false; |
c3504bfd JP |
422 | } |
423 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { | |
e52ab0ec | 424 | if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN)) |
c3504bfd JP |
425 | break; |
426 | } | |
427 | if (ww == W_MAX_TIMEOUT) { | |
48caf5a0 | 428 | pr_debug(" DBG_PORT80(0x21)\n"); |
a4ef27ad | 429 | return false; |
c3504bfd JP |
430 | } |
431 | ||
9ab81fb7 | 432 | /* try to safe shutdown TX */ |
c2d845de | 433 | MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON); |
c3504bfd | 434 | |
9ab81fb7 | 435 | /* W_MAX_TIMEOUT is the timeout period */ |
c3504bfd | 436 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
f205e8d1 | 437 | if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST)) |
c3504bfd JP |
438 | break; |
439 | } | |
440 | if (ww == W_MAX_TIMEOUT) { | |
48caf5a0 | 441 | pr_debug(" DBG_PORT80(0x24)\n"); |
a4ef27ad | 442 | return false; |
c3504bfd JP |
443 | } |
444 | return true; | |
5449c685 FB |
445 | } |
446 | ||
447 | /* | |
448 | * Description: | |
449 | * Stop MAC function | |
450 | * | |
451 | * Parameters: | |
452 | * In: | |
c2d845de | 453 | * io_base - Base Address for MAC |
5449c685 FB |
454 | * Out: |
455 | * none | |
456 | * | |
5a5a2a6a | 457 | * Return Value: true if success; otherwise false |
5449c685 FB |
458 | * |
459 | */ | |
f9f853af | 460 | bool MACbSafeStop(struct vnt_private *priv) |
5449c685 | 461 | { |
c2d845de | 462 | void __iomem *io_base = priv->PortOffset; |
e1c484db | 463 | |
c2d845de | 464 | MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX); |
c3504bfd | 465 | |
f9f853af | 466 | if (!MACbSafeRxOff(priv)) { |
48caf5a0 | 467 | pr_debug(" MACbSafeRxOff == false)\n"); |
f9f853af | 468 | MACbSafeSoftwareReset(priv); |
c3504bfd JP |
469 | return false; |
470 | } | |
f9f853af | 471 | if (!MACbSafeTxOff(priv)) { |
48caf5a0 | 472 | pr_debug(" MACbSafeTxOff == false)\n"); |
f9f853af | 473 | MACbSafeSoftwareReset(priv); |
c3504bfd JP |
474 | return false; |
475 | } | |
476 | ||
c2d845de | 477 | MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN); |
c3504bfd JP |
478 | |
479 | return true; | |
5449c685 FB |
480 | } |
481 | ||
482 | /* | |
483 | * Description: | |
484 | * Shut Down MAC | |
485 | * | |
486 | * Parameters: | |
487 | * In: | |
c2d845de | 488 | * io_base - Base Address for MAC |
5449c685 FB |
489 | * Out: |
490 | * none | |
491 | * | |
5a5a2a6a | 492 | * Return Value: true if success; otherwise false |
5449c685 FB |
493 | * |
494 | */ | |
f9f853af | 495 | bool MACbShutdown(struct vnt_private *priv) |
5449c685 | 496 | { |
c2d845de | 497 | void __iomem *io_base = priv->PortOffset; |
9ab81fb7 | 498 | /* disable MAC IMR */ |
c2d845de | 499 | MACvIntDisable(io_base); |
f9f853af | 500 | MACvSetLoopbackMode(priv, MAC_LB_INTERNAL); |
9ab81fb7 | 501 | /* stop the adapter */ |
f9f853af MP |
502 | if (!MACbSafeStop(priv)) { |
503 | MACvSetLoopbackMode(priv, MAC_LB_NONE); | |
c3504bfd JP |
504 | return false; |
505 | } | |
f9f853af | 506 | MACvSetLoopbackMode(priv, MAC_LB_NONE); |
c3504bfd | 507 | return true; |
5449c685 FB |
508 | } |
509 | ||
510 | /* | |
511 | * Description: | |
512 | * Initialize MAC | |
513 | * | |
514 | * Parameters: | |
515 | * In: | |
c2d845de | 516 | * io_base - Base Address for MAC |
5449c685 FB |
517 | * Out: |
518 | * none | |
519 | * | |
520 | * Return Value: none | |
521 | * | |
522 | */ | |
f9f853af | 523 | void MACvInitialize(struct vnt_private *priv) |
5449c685 | 524 | { |
c2d845de | 525 | void __iomem *io_base = priv->PortOffset; |
9ab81fb7 | 526 | /* clear sticky bits */ |
c2d845de | 527 | MACvClearStckDS(io_base); |
9ab81fb7 | 528 | /* disable force PME-enable */ |
3b8eb64c | 529 | iowrite8(PME_OVR, io_base + MAC_REG_PMC1); |
9ab81fb7 | 530 | /* only 3253 A */ |
c3504bfd | 531 | |
9ab81fb7 | 532 | /* do reset */ |
f9f853af | 533 | MACbSoftwareReset(priv); |
c3504bfd | 534 | |
9ab81fb7 | 535 | /* reset TSF counter */ |
3b8eb64c | 536 | iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL); |
9ab81fb7 | 537 | /* enable TSF counter */ |
3b8eb64c | 538 | iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL); |
5449c685 FB |
539 | } |
540 | ||
541 | /* | |
542 | * Description: | |
543 | * Set the chip with current rx descriptor address | |
544 | * | |
545 | * Parameters: | |
546 | * In: | |
c2d845de | 547 | * io_base - Base Address for MAC |
28029472 | 548 | * curr_desc_addr - Descriptor Address |
5449c685 FB |
549 | * Out: |
550 | * none | |
551 | * | |
552 | * Return Value: none | |
553 | * | |
554 | */ | |
28029472 | 555 | void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr) |
5449c685 | 556 | { |
c2d845de | 557 | void __iomem *io_base = priv->PortOffset; |
c3504bfd | 558 | unsigned short ww; |
ebc9bd83 | 559 | unsigned char org_dma_ctl; |
c3504bfd | 560 | |
ebc9bd83 MP |
561 | org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0); |
562 | if (org_dma_ctl & DMACTL_RUN) | |
3b8eb64c | 563 | iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2); |
bc5cf656 | 564 | |
c3504bfd | 565 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
f205e8d1 | 566 | if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN)) |
c3504bfd JP |
567 | break; |
568 | } | |
bc5cf656 | 569 | |
28029472 | 570 | iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0); |
ebc9bd83 | 571 | if (org_dma_ctl & DMACTL_RUN) |
3b8eb64c | 572 | iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0); |
5449c685 FB |
573 | } |
574 | ||
575 | /* | |
576 | * Description: | |
577 | * Set the chip with current rx descriptor address | |
578 | * | |
579 | * Parameters: | |
580 | * In: | |
c2d845de | 581 | * io_base - Base Address for MAC |
28029472 | 582 | * curr_desc_addr - Descriptor Address |
5449c685 FB |
583 | * Out: |
584 | * none | |
585 | * | |
586 | * Return Value: none | |
587 | * | |
588 | */ | |
28029472 | 589 | void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr) |
5449c685 | 590 | { |
c2d845de | 591 | void __iomem *io_base = priv->PortOffset; |
c3504bfd | 592 | unsigned short ww; |
ebc9bd83 | 593 | unsigned char org_dma_ctl; |
c3504bfd | 594 | |
ebc9bd83 MP |
595 | org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1); |
596 | if (org_dma_ctl & DMACTL_RUN) | |
3b8eb64c | 597 | iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2); |
bc5cf656 | 598 | |
c3504bfd | 599 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
f205e8d1 | 600 | if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN)) |
c3504bfd JP |
601 | break; |
602 | } | |
bc5cf656 | 603 | |
28029472 | 604 | iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1); |
ebc9bd83 | 605 | if (org_dma_ctl & DMACTL_RUN) |
3b8eb64c | 606 | iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1); |
bc5cf656 | 607 | |
5449c685 FB |
608 | } |
609 | ||
610 | /* | |
611 | * Description: | |
612 | * Set the chip with current tx0 descriptor address | |
613 | * | |
614 | * Parameters: | |
615 | * In: | |
c2d845de | 616 | * io_base - Base Address for MAC |
28029472 | 617 | * curr_desc_addr - Descriptor Address |
5449c685 FB |
618 | * Out: |
619 | * none | |
620 | * | |
621 | * Return Value: none | |
622 | * | |
623 | */ | |
f9f853af | 624 | void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv, |
28029472 | 625 | u32 curr_desc_addr) |
5449c685 | 626 | { |
c2d845de | 627 | void __iomem *io_base = priv->PortOffset; |
c3504bfd | 628 | unsigned short ww; |
ebc9bd83 | 629 | unsigned char org_dma_ctl; |
c3504bfd | 630 | |
ebc9bd83 MP |
631 | org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0); |
632 | if (org_dma_ctl & DMACTL_RUN) | |
3b8eb64c | 633 | iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2); |
bc5cf656 | 634 | |
c3504bfd | 635 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
f205e8d1 | 636 | if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN)) |
c3504bfd JP |
637 | break; |
638 | } | |
bc5cf656 | 639 | |
28029472 | 640 | iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0); |
ebc9bd83 | 641 | if (org_dma_ctl & DMACTL_RUN) |
3b8eb64c | 642 | iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0); |
5449c685 FB |
643 | } |
644 | ||
645 | /* | |
646 | * Description: | |
647 | * Set the chip with current AC0 descriptor address | |
648 | * | |
649 | * Parameters: | |
650 | * In: | |
c2d845de | 651 | * io_base - Base Address for MAC |
28029472 | 652 | * curr_desc_addr - Descriptor Address |
5449c685 FB |
653 | * Out: |
654 | * none | |
655 | * | |
656 | * Return Value: none | |
657 | * | |
658 | */ | |
9ab81fb7 | 659 | /* TxDMA1 = AC0DMA */ |
f9f853af | 660 | void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv, |
28029472 | 661 | u32 curr_desc_addr) |
5449c685 | 662 | { |
c2d845de | 663 | void __iomem *io_base = priv->PortOffset; |
c3504bfd | 664 | unsigned short ww; |
ebc9bd83 | 665 | unsigned char org_dma_ctl; |
c3504bfd | 666 | |
ebc9bd83 MP |
667 | org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL); |
668 | if (org_dma_ctl & DMACTL_RUN) | |
3b8eb64c | 669 | iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2); |
bc5cf656 | 670 | |
c3504bfd | 671 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
f205e8d1 | 672 | if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN)) |
c3504bfd JP |
673 | break; |
674 | } | |
4188e586 | 675 | if (ww == W_MAX_TIMEOUT) |
48caf5a0 | 676 | pr_debug(" DBG_PORT80(0x26)\n"); |
28029472 | 677 | iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR); |
ebc9bd83 | 678 | if (org_dma_ctl & DMACTL_RUN) |
3b8eb64c | 679 | iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL); |
5449c685 FB |
680 | } |
681 | ||
f9f853af | 682 | void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv, |
28029472 | 683 | u32 curr_desc_addr) |
5449c685 | 684 | { |
bc5cf656 | 685 | if (iTxType == TYPE_AC0DMA) |
28029472 | 686 | MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr); |
bc5cf656 | 687 | else if (iTxType == TYPE_TXDMA0) |
28029472 | 688 | MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr); |
5449c685 FB |
689 | } |
690 | ||
691 | /* | |
692 | * Description: | |
693 | * Micro Second Delay via MAC | |
694 | * | |
695 | * Parameters: | |
696 | * In: | |
c2d845de | 697 | * io_base - Base Address for MAC |
5449c685 FB |
698 | * uDelay - Delay time (timer resolution is 4 us) |
699 | * Out: | |
700 | * none | |
701 | * | |
702 | * Return Value: none | |
703 | * | |
704 | */ | |
f9f853af | 705 | void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay) |
5449c685 | 706 | { |
c2d845de | 707 | void __iomem *io_base = priv->PortOffset; |
c3504bfd JP |
708 | unsigned char byValue; |
709 | unsigned int uu, ii; | |
710 | ||
3b8eb64c | 711 | iowrite8(0, io_base + MAC_REG_TMCTL0); |
e2ad8e23 | 712 | iowrite32(uDelay, io_base + MAC_REG_TMDATA0); |
3b8eb64c | 713 | iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0); |
9ab81fb7 | 714 | for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */ |
c3504bfd | 715 | for (uu = 0; uu < uDelay; uu++) { |
17c4c51e | 716 | byValue = ioread8(io_base + MAC_REG_TMCTL0); |
c3504bfd JP |
717 | if ((byValue == 0) || |
718 | (byValue & TMCTL_TSUSP)) { | |
3b8eb64c | 719 | iowrite8(0, io_base + MAC_REG_TMCTL0); |
c3504bfd JP |
720 | return; |
721 | } | |
722 | } | |
723 | } | |
3b8eb64c | 724 | iowrite8(0, io_base + MAC_REG_TMCTL0); |
5449c685 FB |
725 | } |
726 | ||
5449c685 FB |
727 | /* |
728 | * Description: | |
729 | * Micro Second One shot timer via MAC | |
730 | * | |
731 | * Parameters: | |
732 | * In: | |
c2d845de | 733 | * io_base - Base Address for MAC |
5449c685 FB |
734 | * uDelay - Delay time |
735 | * Out: | |
736 | * none | |
737 | * | |
738 | * Return Value: none | |
739 | * | |
740 | */ | |
f9f853af | 741 | void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime) |
5449c685 | 742 | { |
c2d845de | 743 | void __iomem *io_base = priv->PortOffset; |
f9f853af | 744 | |
3b8eb64c | 745 | iowrite8(0, io_base + MAC_REG_TMCTL1); |
e2ad8e23 | 746 | iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1); |
3b8eb64c | 747 | iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1); |
5449c685 FB |
748 | } |
749 | ||
0e7997c1 | 750 | void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset, |
e984c758 | 751 | u32 dwData) |
5449c685 | 752 | { |
c2d845de | 753 | void __iomem *io_base = priv->PortOffset; |
f9f853af | 754 | |
0e7997c1 | 755 | if (offset > 273) |
c3504bfd | 756 | return; |
0e7997c1 | 757 | iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); |
e2ad8e23 | 758 | iowrite32(dwData, io_base + MAC_REG_MISCFFDATA); |
54a14e62 | 759 | iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); |
5449c685 FB |
760 | } |
761 | ||
f9f853af | 762 | bool MACbPSWakeup(struct vnt_private *priv) |
5449c685 | 763 | { |
c2d845de | 764 | void __iomem *io_base = priv->PortOffset; |
c3504bfd | 765 | unsigned int ww; |
9ab81fb7 | 766 | /* Read PSCTL */ |
f9f853af | 767 | if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS)) |
c3504bfd | 768 | return true; |
bc5cf656 | 769 | |
9ab81fb7 | 770 | /* Disable PS */ |
c2d845de | 771 | MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN); |
c3504bfd | 772 | |
9ab81fb7 | 773 | /* Check if SyncFlushOK */ |
c3504bfd | 774 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
e206939f | 775 | if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE) |
c3504bfd JP |
776 | break; |
777 | } | |
778 | if (ww == W_MAX_TIMEOUT) { | |
48caf5a0 | 779 | pr_debug(" DBG_PORT80(0x33)\n"); |
c3504bfd JP |
780 | return false; |
781 | } | |
782 | return true; | |
5449c685 FB |
783 | } |
784 | ||
785 | /* | |
786 | * Description: | |
787 | * Set the Key by MISCFIFO | |
788 | * | |
789 | * Parameters: | |
790 | * In: | |
c2d845de | 791 | * io_base - Base Address for MAC |
5449c685 FB |
792 | * |
793 | * Out: | |
794 | * none | |
795 | * | |
796 | * Return Value: none | |
797 | * | |
798 | */ | |
799 | ||
f9f853af | 800 | void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl, |
d4855fe1 GB |
801 | unsigned int uEntryIdx, unsigned int uKeyIdx, |
802 | unsigned char *pbyAddr, u32 *pdwKey, | |
803 | unsigned char byLocalID) | |
5449c685 | 804 | { |
c2d845de | 805 | void __iomem *io_base = priv->PortOffset; |
0e7997c1 | 806 | unsigned short offset; |
4dbc77c0 | 807 | u32 dwData; |
c3504bfd JP |
808 | int ii; |
809 | ||
810 | if (byLocalID <= 1) | |
811 | return; | |
812 | ||
48caf5a0 | 813 | pr_debug("MACvSetKeyEntry\n"); |
0e7997c1 MP |
814 | offset = MISCFIFO_KEYETRY0; |
815 | offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE); | |
c3504bfd JP |
816 | |
817 | dwData = 0; | |
818 | dwData |= wKeyCtl; | |
819 | dwData <<= 16; | |
820 | dwData |= MAKEWORD(*(pbyAddr+4), *(pbyAddr+5)); | |
0e7997c1 MP |
821 | pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n", |
822 | offset, dwData, wKeyCtl); | |
c3504bfd | 823 | |
0e7997c1 | 824 | iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); |
e2ad8e23 | 825 | iowrite32(dwData, io_base + MAC_REG_MISCFFDATA); |
54a14e62 | 826 | iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); |
0e7997c1 | 827 | offset++; |
c3504bfd JP |
828 | |
829 | dwData = 0; | |
830 | dwData |= *(pbyAddr+3); | |
831 | dwData <<= 8; | |
832 | dwData |= *(pbyAddr+2); | |
833 | dwData <<= 8; | |
834 | dwData |= *(pbyAddr+1); | |
835 | dwData <<= 8; | |
836 | dwData |= *(pbyAddr+0); | |
0e7997c1 | 837 | pr_debug("2. offset: %d, Data: %X\n", offset, dwData); |
c3504bfd | 838 | |
0e7997c1 | 839 | iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); |
e2ad8e23 | 840 | iowrite32(dwData, io_base + MAC_REG_MISCFFDATA); |
54a14e62 | 841 | iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); |
0e7997c1 | 842 | offset++; |
c3504bfd | 843 | |
0e7997c1 | 844 | offset += (uKeyIdx * 4); |
c3504bfd | 845 | for (ii = 0; ii < 4; ii++) { |
9ab81fb7 | 846 | /* always push 128 bits */ |
0e7997c1 MP |
847 | pr_debug("3.(%d) offset: %d, Data: %X\n", |
848 | ii, offset + ii, *pdwKey); | |
849 | iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX); | |
e2ad8e23 | 850 | iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA); |
54a14e62 | 851 | iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); |
c3504bfd | 852 | } |
5449c685 FB |
853 | } |
854 | ||
5449c685 FB |
855 | /* |
856 | * Description: | |
857 | * Disable the Key Entry by MISCFIFO | |
858 | * | |
859 | * Parameters: | |
860 | * In: | |
c2d845de | 861 | * io_base - Base Address for MAC |
5449c685 FB |
862 | * |
863 | * Out: | |
864 | * none | |
865 | * | |
866 | * Return Value: none | |
867 | * | |
868 | */ | |
f9f853af | 869 | void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx) |
5449c685 | 870 | { |
c2d845de | 871 | void __iomem *io_base = priv->PortOffset; |
0e7997c1 | 872 | unsigned short offset; |
5449c685 | 873 | |
0e7997c1 MP |
874 | offset = MISCFIFO_KEYETRY0; |
875 | offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE); | |
5449c685 | 876 | |
0e7997c1 | 877 | iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); |
e2ad8e23 | 878 | iowrite32(0, io_base + MAC_REG_MISCFFDATA); |
54a14e62 | 879 | iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); |
5449c685 | 880 | } |