Staging: vt6655: rxtx: Remove extra parentheses
[deliverable/linux.git] / drivers / staging / vt6655 / mac.c
CommitLineData
5449c685
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1/*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
612822f5 19 *
5449c685
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20 * File: mac.c
21 *
22 * Purpose: MAC routines
23 *
24 * Author: Tevin Chen
25 *
26 * Date: May 21, 1996
27 *
28 * Functions:
5449c685
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29 * MACbIsRegBitsOn - Test if All test Bits On
30 * MACbIsRegBitsOff - Test if All test Bits Off
31 * MACbIsIntDisable - Test if MAC interrupt disable
5449c685 32 * MACvSetShortRetryLimit - Set 802.11 Short Retry limit
5449c685 33 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit
5449c685 34 * MACvSetLoopbackMode - Set MAC Loopback Mode
5449c685
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35 * MACvSaveContext - Save Context of MAC Registers
36 * MACvRestoreContext - Restore Context of MAC Registers
5449c685
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37 * MACbSoftwareReset - Software Reset MAC
38 * MACbSafeRxOff - Turn Off MAC Rx
39 * MACbSafeTxOff - Turn Off MAC Tx
40 * MACbSafeStop - Stop MAC function
41 * MACbShutdown - Shut down MAC
42 * MACvInitialize - Initialize MAC
789d1aef
JM
43 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address
44 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
45 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
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46 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
47 *
48 * Revision History:
49 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53
50 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()& MACvEnableBusSusEn()
51 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry
52 *
53 */
54
5449c685 55#include "tmacro.h"
5449c685 56#include "mac.h"
5449c685 57
5449c685
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58/*
59 * Description:
60 * Test if all test bits on
61 *
62 * Parameters:
63 * In:
64 * dwIoBase - Base Address for MAC
65 * byRegOfs - Offset of MAC Register
66 * byTestBits - Test bits
67 * Out:
68 * none
69 *
5a5a2a6a 70 * Return Value: true if all test bits On; otherwise false
5449c685
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71 *
72 */
d4855fe1
GB
73bool MACbIsRegBitsOn(void __iomem *dwIoBase, unsigned char byRegOfs,
74 unsigned char byTestBits)
5449c685 75{
c3504bfd 76 unsigned char byData;
5449c685 77
c3504bfd
JP
78 VNSvInPortB(dwIoBase + byRegOfs, &byData);
79 return (byData & byTestBits) == byTestBits;
5449c685
FB
80}
81
82/*
83 * Description:
84 * Test if all test bits off
85 *
86 * Parameters:
87 * In:
88 * dwIoBase - Base Address for MAC
89 * byRegOfs - Offset of MAC Register
90 * byTestBits - Test bits
91 * Out:
92 * none
93 *
5a5a2a6a 94 * Return Value: true if all test bits Off; otherwise false
5449c685
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95 *
96 */
d4855fe1
GB
97bool MACbIsRegBitsOff(void __iomem *dwIoBase, unsigned char byRegOfs,
98 unsigned char byTestBits)
5449c685 99{
c3504bfd 100 unsigned char byData;
5449c685 101
c3504bfd
JP
102 VNSvInPortB(dwIoBase + byRegOfs, &byData);
103 return !(byData & byTestBits);
5449c685
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104}
105
106/*
107 * Description:
108 * Test if MAC interrupt disable
109 *
110 * Parameters:
111 * In:
112 * dwIoBase - Base Address for MAC
113 * Out:
114 * none
115 *
5a5a2a6a 116 * Return Value: true if interrupt is disable; otherwise false
5449c685
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117 *
118 */
16834405 119bool MACbIsIntDisable(void __iomem *dwIoBase)
5449c685 120{
c3504bfd 121 unsigned long dwData;
5449c685 122
c3504bfd
JP
123 VNSvInPortD(dwIoBase + MAC_REG_IMR, &dwData);
124 if (dwData != 0)
125 return false;
5449c685 126
c3504bfd 127 return true;
5449c685
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128}
129
5449c685
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130/*
131 * Description:
132 * Set 802.11 Short Retry Limit
133 *
134 * Parameters:
135 * In:
136 * dwIoBase - Base Address for MAC
137 * byRetryLimit- Retry Limit
138 * Out:
139 * none
140 *
141 * Return Value: none
142 *
143 */
16834405 144void MACvSetShortRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit)
5449c685 145{
9ab81fb7 146 /* set SRT */
c3504bfd 147 VNSvOutPortB(dwIoBase + MAC_REG_SRT, byRetryLimit);
5449c685
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148}
149
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150
151/*
152 * Description:
153 * Set 802.11 Long Retry Limit
154 *
155 * Parameters:
156 * In:
157 * dwIoBase - Base Address for MAC
158 * byRetryLimit- Retry Limit
159 * Out:
160 * none
161 *
162 * Return Value: none
163 *
164 */
16834405 165void MACvSetLongRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit)
5449c685 166{
9ab81fb7 167 /* set LRT */
c3504bfd 168 VNSvOutPortB(dwIoBase + MAC_REG_LRT, byRetryLimit);
5449c685
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169}
170
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171/*
172 * Description:
173 * Set MAC Loopback mode
174 *
175 * Parameters:
176 * In:
177 * dwIoBase - Base Address for MAC
178 * byLoopbackMode - Loopback Mode
179 * Out:
180 * none
181 *
182 * Return Value: none
183 *
184 */
16834405 185void MACvSetLoopbackMode(void __iomem *dwIoBase, unsigned char byLoopbackMode)
5449c685 186{
c3504bfd
JP
187 unsigned char byOrgValue;
188
c3504bfd 189 byLoopbackMode <<= 6;
9ab81fb7 190 /* set TCR */
c3504bfd
JP
191 VNSvInPortB(dwIoBase + MAC_REG_TEST, &byOrgValue);
192 byOrgValue = byOrgValue & 0x3F;
193 byOrgValue = byOrgValue | byLoopbackMode;
194 VNSvOutPortB(dwIoBase + MAC_REG_TEST, byOrgValue);
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195}
196
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197/*
198 * Description:
199 * Save MAC registers to context buffer
200 *
201 * Parameters:
202 * In:
203 * dwIoBase - Base Address for MAC
204 * Out:
205 * pbyCxtBuf - Context buffer
206 *
207 * Return Value: none
208 *
209 */
16834405 210void MACvSaveContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf)
5449c685 211{
c3504bfd 212 int ii;
5449c685 213
9ab81fb7 214 /* read page0 register */
bc5cf656 215 for (ii = 0; ii < MAC_MAX_CONTEXT_SIZE_PAGE0; ii++)
c3504bfd 216 VNSvInPortB((dwIoBase + ii), (pbyCxtBuf + ii));
5449c685 217
c3504bfd 218 MACvSelectPage1(dwIoBase);
5449c685 219
9ab81fb7 220 /* read page1 register */
bc5cf656 221 for (ii = 0; ii < MAC_MAX_CONTEXT_SIZE_PAGE1; ii++)
d4855fe1
GB
222 VNSvInPortB((dwIoBase + ii),
223 (pbyCxtBuf + MAC_MAX_CONTEXT_SIZE_PAGE0 + ii));
5449c685 224
c3504bfd 225 MACvSelectPage0(dwIoBase);
5449c685
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226}
227
228/*
229 * Description:
230 * Restore MAC registers from context buffer
231 *
232 * Parameters:
233 * In:
234 * dwIoBase - Base Address for MAC
235 * pbyCxtBuf - Context buffer
236 * Out:
237 * none
238 *
239 * Return Value: none
240 *
241 */
16834405 242void MACvRestoreContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf)
5449c685 243{
c3504bfd 244 int ii;
5449c685 245
c3504bfd 246 MACvSelectPage1(dwIoBase);
9ab81fb7 247 /* restore page1 */
bc5cf656 248 for (ii = 0; ii < MAC_MAX_CONTEXT_SIZE_PAGE1; ii++)
d4855fe1
GB
249 VNSvOutPortB((dwIoBase + ii),
250 *(pbyCxtBuf + MAC_MAX_CONTEXT_SIZE_PAGE0 + ii));
bc5cf656 251
c3504bfd 252 MACvSelectPage0(dwIoBase);
5449c685 253
9ab81fb7 254 /* restore RCR,TCR,IMR... */
bc5cf656 255 for (ii = MAC_REG_RCR; ii < MAC_REG_ISR; ii++)
c3504bfd 256 VNSvOutPortB(dwIoBase + ii, *(pbyCxtBuf + ii));
bc5cf656 257
9ab81fb7 258 /* restore MAC Config. */
bc5cf656 259 for (ii = MAC_REG_LRT; ii < MAC_REG_PAGE1SEL; ii++)
c3504bfd 260 VNSvOutPortB(dwIoBase + ii, *(pbyCxtBuf + ii));
bc5cf656 261
c3504bfd 262 VNSvOutPortB(dwIoBase + MAC_REG_CFG, *(pbyCxtBuf + MAC_REG_CFG));
5449c685 263
9ab81fb7 264 /* restore PS Config. */
bc5cf656 265 for (ii = MAC_REG_PSCFG; ii < MAC_REG_BBREGCTL; ii++)
c3504bfd 266 VNSvOutPortB(dwIoBase + ii, *(pbyCxtBuf + ii));
5449c685 267
9ab81fb7 268 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
d4855fe1
GB
269 VNSvOutPortD(dwIoBase + MAC_REG_TXDMAPTR0,
270 *(unsigned long *)(pbyCxtBuf + MAC_REG_TXDMAPTR0));
271 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMAPTR,
272 *(unsigned long *)(pbyCxtBuf + MAC_REG_AC0DMAPTR));
273 VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR,
274 *(unsigned long *)(pbyCxtBuf + MAC_REG_BCNDMAPTR));
275
276 VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR0,
277 *(unsigned long *)(pbyCxtBuf + MAC_REG_RXDMAPTR0));
278
279 VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR1,
280 *(unsigned long *)(pbyCxtBuf + MAC_REG_RXDMAPTR1));
5449c685
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281}
282
5449c685
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283/*
284 * Description:
285 * Software Reset MAC
286 *
287 * Parameters:
288 * In:
289 * dwIoBase - Base Address for MAC
290 * Out:
291 * none
292 *
5a5a2a6a 293 * Return Value: true if Reset Success; otherwise false
5449c685
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294 *
295 */
16834405 296bool MACbSoftwareReset(void __iomem *dwIoBase)
5449c685 297{
c3504bfd
JP
298 unsigned char byData;
299 unsigned short ww;
300
9ab81fb7 301 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
c3504bfd
JP
302 VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, 0x01);
303
304 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
305 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
306 if (!(byData & HOSTCR_SOFTRST))
307 break;
308 }
309 if (ww == W_MAX_TIMEOUT)
310 return false;
311 return true;
5449c685
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312}
313
314/*
315 * Description:
316 * save some important register's value, then do reset, then restore register's value
317 *
318 * Parameters:
319 * In:
320 * dwIoBase - Base Address for MAC
321 * Out:
322 * none
323 *
5a5a2a6a 324 * Return Value: true if success; otherwise false
5449c685
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325 *
326 */
16834405 327bool MACbSafeSoftwareReset(void __iomem *dwIoBase)
5449c685 328{
c3504bfd
JP
329 unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0+MAC_MAX_CONTEXT_SIZE_PAGE1];
330 bool bRetVal;
331
9ab81fb7
MS
332 /* PATCH....
333 * save some important register's value, then do
334 * reset, then restore register's value
335 */
336 /* save MAC context */
c3504bfd 337 MACvSaveContext(dwIoBase, abyTmpRegData);
9ab81fb7 338 /* do reset */
c3504bfd 339 bRetVal = MACbSoftwareReset(dwIoBase);
9ab81fb7 340 /* restore MAC context, except CR0 */
c3504bfd
JP
341 MACvRestoreContext(dwIoBase, abyTmpRegData);
342
343 return bRetVal;
5449c685
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344}
345
346/*
347 * Description:
b1797dfd 348 * Turn Off MAC Rx
5449c685
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349 *
350 * Parameters:
351 * In:
352 * dwIoBase - Base Address for MAC
353 * Out:
354 * none
355 *
5a5a2a6a 356 * Return Value: true if success; otherwise false
5449c685
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357 *
358 */
16834405 359bool MACbSafeRxOff(void __iomem *dwIoBase)
5449c685 360{
c3504bfd
JP
361 unsigned short ww;
362 unsigned long dwData;
363 unsigned char byData;
364
9ab81fb7 365 /* turn off wow temp for turn off Rx safely */
c3504bfd 366
9ab81fb7 367 /* Clear RX DMA0,1 */
c3504bfd
JP
368 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_CLRRUN);
369 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_CLRRUN);
370 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
371 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData);
372 if (!(dwData & DMACTL_RUN))
373 break;
374 }
375 if (ww == W_MAX_TIMEOUT) {
48caf5a0 376 pr_debug(" DBG_PORT80(0x10)\n");
a4ef27ad 377 return false;
c3504bfd
JP
378 }
379 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
380 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData);
381 if (!(dwData & DMACTL_RUN))
382 break;
383 }
384 if (ww == W_MAX_TIMEOUT) {
48caf5a0 385 pr_debug(" DBG_PORT80(0x11)\n");
a4ef27ad 386 return false;
c3504bfd
JP
387 }
388
9ab81fb7 389 /* try to safe shutdown RX */
c3504bfd 390 MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON);
9ab81fb7 391 /* W_MAX_TIMEOUT is the timeout period */
c3504bfd
JP
392 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
393 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
394 if (!(byData & HOSTCR_RXONST))
395 break;
396 }
397 if (ww == W_MAX_TIMEOUT) {
48caf5a0 398 pr_debug(" DBG_PORT80(0x12)\n");
a4ef27ad 399 return false;
c3504bfd
JP
400 }
401 return true;
5449c685
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402}
403
404/*
405 * Description:
b1797dfd 406 * Turn Off MAC Tx
5449c685
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407 *
408 * Parameters:
409 * In:
410 * dwIoBase - Base Address for MAC
411 * Out:
412 * none
413 *
5a5a2a6a 414 * Return Value: true if success; otherwise false
5449c685
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415 *
416 */
16834405 417bool MACbSafeTxOff(void __iomem *dwIoBase)
5449c685 418{
c3504bfd
JP
419 unsigned short ww;
420 unsigned long dwData;
421 unsigned char byData;
422
9ab81fb7
MS
423 /* Clear TX DMA */
424 /* Tx0 */
c3504bfd 425 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_CLRRUN);
9ab81fb7 426 /* AC0 */
c3504bfd
JP
427 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_CLRRUN);
428
c3504bfd
JP
429 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
430 VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData);
431 if (!(dwData & DMACTL_RUN))
432 break;
433 }
434 if (ww == W_MAX_TIMEOUT) {
48caf5a0 435 pr_debug(" DBG_PORT80(0x20)\n");
a4ef27ad 436 return false;
c3504bfd
JP
437 }
438 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
439 VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData);
440 if (!(dwData & DMACTL_RUN))
441 break;
442 }
443 if (ww == W_MAX_TIMEOUT) {
48caf5a0 444 pr_debug(" DBG_PORT80(0x21)\n");
a4ef27ad 445 return false;
c3504bfd
JP
446 }
447
9ab81fb7 448 /* try to safe shutdown TX */
c3504bfd
JP
449 MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON);
450
9ab81fb7 451 /* W_MAX_TIMEOUT is the timeout period */
c3504bfd
JP
452 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
453 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
454 if (!(byData & HOSTCR_TXONST))
455 break;
456 }
457 if (ww == W_MAX_TIMEOUT) {
48caf5a0 458 pr_debug(" DBG_PORT80(0x24)\n");
a4ef27ad 459 return false;
c3504bfd
JP
460 }
461 return true;
5449c685
FB
462}
463
464/*
465 * Description:
466 * Stop MAC function
467 *
468 * Parameters:
469 * In:
470 * dwIoBase - Base Address for MAC
471 * Out:
472 * none
473 *
5a5a2a6a 474 * Return Value: true if success; otherwise false
5449c685
FB
475 *
476 */
16834405 477bool MACbSafeStop(void __iomem *dwIoBase)
5449c685 478{
c3504bfd
JP
479 MACvRegBitsOff(dwIoBase, MAC_REG_TCR, TCR_AUTOBCNTX);
480
1208f14a 481 if (!MACbSafeRxOff(dwIoBase)) {
48caf5a0 482 pr_debug(" MACbSafeRxOff == false)\n");
c3504bfd
JP
483 MACbSafeSoftwareReset(dwIoBase);
484 return false;
485 }
1208f14a 486 if (!MACbSafeTxOff(dwIoBase)) {
48caf5a0 487 pr_debug(" MACbSafeTxOff == false)\n");
c3504bfd
JP
488 MACbSafeSoftwareReset(dwIoBase);
489 return false;
490 }
491
492 MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_MACEN);
493
494 return true;
5449c685
FB
495}
496
497/*
498 * Description:
499 * Shut Down MAC
500 *
501 * Parameters:
502 * In:
503 * dwIoBase - Base Address for MAC
504 * Out:
505 * none
506 *
5a5a2a6a 507 * Return Value: true if success; otherwise false
5449c685
FB
508 *
509 */
16834405 510bool MACbShutdown(void __iomem *dwIoBase)
5449c685 511{
9ab81fb7 512 /* disable MAC IMR */
c3504bfd
JP
513 MACvIntDisable(dwIoBase);
514 MACvSetLoopbackMode(dwIoBase, MAC_LB_INTERNAL);
9ab81fb7 515 /* stop the adapter */
c3504bfd
JP
516 if (!MACbSafeStop(dwIoBase)) {
517 MACvSetLoopbackMode(dwIoBase, MAC_LB_NONE);
518 return false;
519 }
520 MACvSetLoopbackMode(dwIoBase, MAC_LB_NONE);
521 return true;
5449c685
FB
522}
523
524/*
525 * Description:
526 * Initialize MAC
527 *
528 * Parameters:
529 * In:
530 * dwIoBase - Base Address for MAC
531 * Out:
532 * none
533 *
534 * Return Value: none
535 *
536 */
16834405 537void MACvInitialize(void __iomem *dwIoBase)
5449c685 538{
9ab81fb7 539 /* clear sticky bits */
c3504bfd 540 MACvClearStckDS(dwIoBase);
9ab81fb7 541 /* disable force PME-enable */
c3504bfd 542 VNSvOutPortB(dwIoBase + MAC_REG_PMC1, PME_OVR);
9ab81fb7 543 /* only 3253 A */
c3504bfd 544
9ab81fb7 545 /* do reset */
c3504bfd
JP
546 MACbSoftwareReset(dwIoBase);
547
9ab81fb7 548 /* reset TSF counter */
c3504bfd 549 VNSvOutPortB(dwIoBase + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST);
9ab81fb7 550 /* enable TSF counter */
c3504bfd 551 VNSvOutPortB(dwIoBase + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN);
5449c685
FB
552}
553
554/*
555 * Description:
556 * Set the chip with current rx descriptor address
557 *
558 * Parameters:
559 * In:
560 * dwIoBase - Base Address for MAC
561 * dwCurrDescAddr - Descriptor Address
562 * Out:
563 * none
564 *
565 * Return Value: none
566 *
567 */
16834405 568void MACvSetCurrRx0DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr)
5449c685 569{
c3504bfd
JP
570 unsigned short ww;
571 unsigned char byData;
572 unsigned char byOrgDMACtl;
573
574 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL0, &byOrgDMACtl);
bc5cf656 575 if (byOrgDMACtl & DMACTL_RUN)
c3504bfd 576 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL0+2, DMACTL_RUN);
bc5cf656 577
c3504bfd
JP
578 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
579 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL0, &byData);
580 if (!(byData & DMACTL_RUN))
581 break;
582 }
bc5cf656 583
c3504bfd 584 VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR0, dwCurrDescAddr);
bc5cf656 585 if (byOrgDMACtl & DMACTL_RUN)
c3504bfd 586 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN);
5449c685
FB
587}
588
589/*
590 * Description:
591 * Set the chip with current rx descriptor address
592 *
593 * Parameters:
594 * In:
595 * dwIoBase - Base Address for MAC
596 * dwCurrDescAddr - Descriptor Address
597 * Out:
598 * none
599 *
600 * Return Value: none
601 *
602 */
16834405 603void MACvSetCurrRx1DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr)
5449c685 604{
c3504bfd
JP
605 unsigned short ww;
606 unsigned char byData;
607 unsigned char byOrgDMACtl;
608
609 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL1, &byOrgDMACtl);
bc5cf656 610 if (byOrgDMACtl & DMACTL_RUN)
c3504bfd 611 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL1+2, DMACTL_RUN);
bc5cf656 612
c3504bfd
JP
613 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
614 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL1, &byData);
615 if (!(byData & DMACTL_RUN))
616 break;
617 }
bc5cf656 618
c3504bfd 619 VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR1, dwCurrDescAddr);
bc5cf656 620 if (byOrgDMACtl & DMACTL_RUN)
c3504bfd 621 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN);
bc5cf656 622
5449c685
FB
623}
624
625/*
626 * Description:
627 * Set the chip with current tx0 descriptor address
628 *
629 * Parameters:
630 * In:
631 * dwIoBase - Base Address for MAC
632 * dwCurrDescAddr - Descriptor Address
633 * Out:
634 * none
635 *
636 * Return Value: none
637 *
638 */
d4855fe1
GB
639void MACvSetCurrTx0DescAddrEx(void __iomem *dwIoBase,
640 unsigned long dwCurrDescAddr)
5449c685 641{
c3504bfd
JP
642 unsigned short ww;
643 unsigned char byData;
644 unsigned char byOrgDMACtl;
645
646 VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byOrgDMACtl);
bc5cf656 647 if (byOrgDMACtl & DMACTL_RUN)
c3504bfd 648 VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0+2, DMACTL_RUN);
bc5cf656 649
c3504bfd
JP
650 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
651 VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byData);
652 if (!(byData & DMACTL_RUN))
653 break;
654 }
bc5cf656 655
c3504bfd 656 VNSvOutPortD(dwIoBase + MAC_REG_TXDMAPTR0, dwCurrDescAddr);
bc5cf656 657 if (byOrgDMACtl & DMACTL_RUN)
c3504bfd 658 VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN);
5449c685
FB
659}
660
661/*
662 * Description:
663 * Set the chip with current AC0 descriptor address
664 *
665 * Parameters:
666 * In:
667 * dwIoBase - Base Address for MAC
668 * dwCurrDescAddr - Descriptor Address
669 * Out:
670 * none
671 *
672 * Return Value: none
673 *
674 */
9ab81fb7 675/* TxDMA1 = AC0DMA */
d4855fe1
GB
676void MACvSetCurrAC0DescAddrEx(void __iomem *dwIoBase,
677 unsigned long dwCurrDescAddr)
5449c685 678{
c3504bfd
JP
679 unsigned short ww;
680 unsigned char byData;
681 unsigned char byOrgDMACtl;
682
683 VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byOrgDMACtl);
bc5cf656 684 if (byOrgDMACtl & DMACTL_RUN)
c3504bfd 685 VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL+2, DMACTL_RUN);
bc5cf656 686
c3504bfd
JP
687 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
688 VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byData);
689 if (!(byData & DMACTL_RUN))
690 break;
691 }
692 if (ww == W_MAX_TIMEOUT) {
48caf5a0 693 pr_debug(" DBG_PORT80(0x26)\n");
c3504bfd
JP
694 }
695 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMAPTR, dwCurrDescAddr);
bc5cf656 696 if (byOrgDMACtl & DMACTL_RUN)
c3504bfd 697 VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN);
5449c685
FB
698}
699
d4855fe1
GB
700void MACvSetCurrTXDescAddr(int iTxType, void __iomem *dwIoBase,
701 unsigned long dwCurrDescAddr)
5449c685 702{
bc5cf656 703 if (iTxType == TYPE_AC0DMA)
c3504bfd 704 MACvSetCurrAC0DescAddrEx(dwIoBase, dwCurrDescAddr);
bc5cf656 705 else if (iTxType == TYPE_TXDMA0)
c3504bfd 706 MACvSetCurrTx0DescAddrEx(dwIoBase, dwCurrDescAddr);
5449c685
FB
707}
708
709/*
710 * Description:
711 * Micro Second Delay via MAC
712 *
713 * Parameters:
714 * In:
715 * dwIoBase - Base Address for MAC
716 * uDelay - Delay time (timer resolution is 4 us)
717 * Out:
718 * none
719 *
720 * Return Value: none
721 *
722 */
16834405 723void MACvTimer0MicroSDelay(void __iomem *dwIoBase, unsigned int uDelay)
5449c685 724{
c3504bfd
JP
725 unsigned char byValue;
726 unsigned int uu, ii;
727
728 VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0);
729 VNSvOutPortD(dwIoBase + MAC_REG_TMDATA0, uDelay);
730 VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, (TMCTL_TMD | TMCTL_TE));
9ab81fb7 731 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
c3504bfd
JP
732 for (uu = 0; uu < uDelay; uu++) {
733 VNSvInPortB(dwIoBase + MAC_REG_TMCTL0, &byValue);
734 if ((byValue == 0) ||
735 (byValue & TMCTL_TSUSP)) {
736 VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0);
737 return;
738 }
739 }
740 }
741 VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0);
5449c685
FB
742}
743
5449c685
FB
744/*
745 * Description:
746 * Micro Second One shot timer via MAC
747 *
748 * Parameters:
749 * In:
750 * dwIoBase - Base Address for MAC
751 * uDelay - Delay time
752 * Out:
753 * none
754 *
755 * Return Value: none
756 *
757 */
16834405 758void MACvOneShotTimer1MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime)
5449c685 759{
c3504bfd
JP
760 VNSvOutPortB(dwIoBase + MAC_REG_TMCTL1, 0);
761 VNSvOutPortD(dwIoBase + MAC_REG_TMDATA1, uDelayTime);
762 VNSvOutPortB(dwIoBase + MAC_REG_TMCTL1, (TMCTL_TMD | TMCTL_TE));
5449c685
FB
763}
764
d4855fe1
GB
765void MACvSetMISCFifo(void __iomem *dwIoBase, unsigned short wOffset,
766 unsigned long dwData)
5449c685 767{
c3504bfd
JP
768 if (wOffset > 273)
769 return;
770 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset);
771 VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData);
772 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
5449c685
FB
773}
774
16834405 775bool MACbPSWakeup(void __iomem *dwIoBase)
5449c685 776{
c3504bfd
JP
777 unsigned char byOrgValue;
778 unsigned int ww;
9ab81fb7 779 /* Read PSCTL */
bc5cf656 780 if (MACbIsRegBitsOff(dwIoBase, MAC_REG_PSCTL, PSCTL_PS))
c3504bfd 781 return true;
bc5cf656 782
9ab81fb7 783 /* Disable PS */
c3504bfd
JP
784 MACvRegBitsOff(dwIoBase, MAC_REG_PSCTL, PSCTL_PSEN);
785
9ab81fb7 786 /* Check if SyncFlushOK */
c3504bfd 787 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
75b4d52b 788 VNSvInPortB(dwIoBase + MAC_REG_PSCTL, &byOrgValue);
c3504bfd
JP
789 if (byOrgValue & PSCTL_WAKEDONE)
790 break;
791 }
792 if (ww == W_MAX_TIMEOUT) {
48caf5a0 793 pr_debug(" DBG_PORT80(0x33)\n");
c3504bfd
JP
794 return false;
795 }
796 return true;
5449c685
FB
797}
798
799/*
800 * Description:
801 * Set the Key by MISCFIFO
802 *
803 * Parameters:
804 * In:
805 * dwIoBase - Base Address for MAC
806 *
807 * Out:
808 * none
809 *
810 * Return Value: none
811 *
812 */
813
d4855fe1
GB
814void MACvSetKeyEntry(void __iomem *dwIoBase, unsigned short wKeyCtl,
815 unsigned int uEntryIdx, unsigned int uKeyIdx,
816 unsigned char *pbyAddr, u32 *pdwKey,
817 unsigned char byLocalID)
5449c685 818{
c3504bfd 819 unsigned short wOffset;
4dbc77c0 820 u32 dwData;
c3504bfd
JP
821 int ii;
822
823 if (byLocalID <= 1)
824 return;
825
48caf5a0 826 pr_debug("MACvSetKeyEntry\n");
c3504bfd
JP
827 wOffset = MISCFIFO_KEYETRY0;
828 wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
829
830 dwData = 0;
831 dwData |= wKeyCtl;
832 dwData <<= 16;
833 dwData |= MAKEWORD(*(pbyAddr+4), *(pbyAddr+5));
48caf5a0
JP
834 pr_debug("1. wOffset: %d, Data: %X, KeyCtl:%X\n",
835 wOffset, dwData, wKeyCtl);
c3504bfd
JP
836
837 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset);
838 VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData);
839 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
840 wOffset++;
841
842 dwData = 0;
843 dwData |= *(pbyAddr+3);
844 dwData <<= 8;
845 dwData |= *(pbyAddr+2);
846 dwData <<= 8;
847 dwData |= *(pbyAddr+1);
848 dwData <<= 8;
849 dwData |= *(pbyAddr+0);
48caf5a0 850 pr_debug("2. wOffset: %d, Data: %X\n", wOffset, dwData);
c3504bfd
JP
851
852 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset);
853 VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData);
854 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
855 wOffset++;
856
857 wOffset += (uKeyIdx * 4);
858 for (ii = 0; ii < 4; ii++) {
9ab81fb7 859 /* always push 128 bits */
48caf5a0
JP
860 pr_debug("3.(%d) wOffset: %d, Data: %X\n",
861 ii, wOffset+ii, *pdwKey);
c3504bfd
JP
862 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset+ii);
863 VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, *pdwKey++);
864 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
865 }
5449c685
FB
866}
867
5449c685
FB
868/*
869 * Description:
870 * Disable the Key Entry by MISCFIFO
871 *
872 * Parameters:
873 * In:
874 * dwIoBase - Base Address for MAC
875 *
876 * Out:
877 * none
878 *
879 * Return Value: none
880 *
881 */
16834405 882void MACvDisableKeyEntry(void __iomem *dwIoBase, unsigned int uEntryIdx)
5449c685 883{
c3504bfd 884 unsigned short wOffset;
5449c685 885
c3504bfd
JP
886 wOffset = MISCFIFO_KEYETRY0;
887 wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
5449c685 888
c3504bfd
JP
889 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset);
890 VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, 0);
891 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
5449c685 892}
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