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staging: wilc1000: remove dead codes
[deliverable/linux.git] / drivers / staging / wilc1000 / wilc_wlan.c
CommitLineData
c5c77ba1
JK		 1/* ////////////////////////////////////////////////////////////////////////// */
2/* */
3/* Copyright (c) Atmel Corporation. All rights reserved. */
4/* */
5/* Module Name: wilc_wlan.c */
6/* */
7/* */
8/* //////////////////////////////////////////////////////////////////////////// */
9
10#include "wilc_wlan_if.h"
11#include "wilc_wlan.h"
12#define INLINE static __inline
13
14/********************************************
15 *
16 * Global
17 *
18 ********************************************/
c5c77ba1
JK		 19extern wilc_hif_func_t hif_sdio;
20extern wilc_hif_func_t hif_spi;
21extern wilc_cfg_func_t mac_cfg;
22#if defined(PLAT_RK3026_TCHIP)
63d03e47 23extern u8 g_wilc_initialized; /* AMR : 0422 RK3026 Crash issue */
c5c77ba1
JK		 24#endif
25extern void WILC_WFI_mgmt_rx(uint8_t *buff, uint32_t size);
c5c77ba1 26uint32_t wilc_get_chipid(uint8_t update);
72ed4dc7 27u16 Set_machw_change_vir_if(bool bValue);
c5c77ba1 28
c5c77ba1
JK		 29
30
31typedef struct {
32 int quit;
33
34 /**
35 * input interface functions
36 **/
37 wilc_wlan_os_func_t os_func;
38 wilc_wlan_io_func_t io_func;
39 wilc_wlan_net_func_t net_func;
40 wilc_wlan_indicate_func_t indicate_func;
41
42 /**
43 * host interface functions
44 **/
45 wilc_hif_func_t hif_func;
5e150b52 46 struct mutex *hif_lock;
c5c77ba1
JK		 47
48 /**
49 * configuration interface functions
50 **/
51 wilc_cfg_func_t cif_func;
52 int cfg_frame_in_use;
53 wilc_cfg_frame_t cfg_frame;
54 uint32_t cfg_frame_offset;
55 int cfg_seq_no;
56 void *cfg_wait;
57
58 /**
59 * RX buffer
60 **/
61 #ifdef MEMORY_STATIC
62 uint32_t rx_buffer_size;
63 uint8_t *rx_buffer;
64 uint32_t rx_buffer_offset;
65 #endif
66 /**
67 * TX buffer
68 **/
69 uint32_t tx_buffer_size;
70 uint8_t *tx_buffer;
71 uint32_t tx_buffer_offset;
72
73 /**
74 * TX queue
75 **/
76 void *txq_lock;
77
78 /*Added by Amr - BugID_4720*/
8990d856 79 struct semaphore *txq_add_to_head_lock;
c5c77ba1
JK		 80 void *txq_spinlock;
81 unsigned long txq_spinlock_flags;
82
83 struct txq_entry_t *txq_head;
84 struct txq_entry_t *txq_tail;
85 int txq_entries;
86 void *txq_wait;
87 int txq_exit;
88
89 /**
90 * RX queue
91 **/
5e150b52 92 struct mutex *rxq_lock;
c5c77ba1
JK		 93 struct rxq_entry_t *rxq_head;
94 struct rxq_entry_t *rxq_tail;
95 int rxq_entries;
96 void *rxq_wait;
97 int rxq_exit;
98
99
100} wilc_wlan_dev_t;
101
102static wilc_wlan_dev_t g_wlan;
103
104INLINE void chip_allow_sleep(void);
105INLINE void chip_wakeup(void);
106/********************************************
107 *
108 * Debug
109 *
110 ********************************************/
111
112static uint32_t dbgflag = N_INIT | N_ERR | N_INTR | N_TXQ | N_RXQ;
113
114static void wilc_debug(uint32_t flag, char *fmt, ...)
115{
116 char buf[256];
117 va_list args;
c5c77ba1
JK		 118
119 if (flag & dbgflag) {
120 va_start(args, fmt);
81053222 121 vsprintf(buf, fmt, args);
c5c77ba1
JK		 122 va_end(args);
123
124 if (g_wlan.os_func.os_debug)
125 g_wlan.os_func.os_debug(buf);
126 }
c5c77ba1
JK		 127}
128
129static CHIP_PS_STATE_T genuChipPSstate = CHIP_WAKEDUP;
130
131/*BugID_5213*/
132/*acquire_bus() and release_bus() are made INLINE functions*/
133/*as a temporary workaround to fix a problem of receiving*/
134/*unknown interrupt from FW*/
135INLINE void acquire_bus(BUS_ACQUIRE_T acquire)
136{
137
5e150b52 138 mutex_lock(g_wlan.hif_lock);
c5c77ba1
JK		 139 #ifndef WILC_OPTIMIZE_SLEEP_INT
140 if (genuChipPSstate != CHIP_WAKEDUP)
141 #endif
142 {
143 if (acquire == ACQUIRE_AND_WAKEUP)
144 chip_wakeup();
145 }
146
147}
148INLINE void release_bus(BUS_RELEASE_T release)
149{
150 #ifdef WILC_OPTIMIZE_SLEEP_INT
151 if (release == RELEASE_ALLOW_SLEEP)
152 chip_allow_sleep();
153 #endif
5e150b52 154 mutex_unlock(g_wlan.hif_lock);
c5c77ba1
JK		 155}
156/********************************************
157 *
158 * Queue
159 *
160 ********************************************/
161
162static void wilc_wlan_txq_remove(struct txq_entry_t *tqe)
163{
164
165 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
166 /* unsigned long flags; */
c5c77ba1
JK		 167 if (tqe == p->txq_head) {
168
169 p->txq_head = tqe->next;
170 if (p->txq_head)
171 p->txq_head->prev = NULL;
172
173
174 } else if (tqe == p->txq_tail) {
175 p->txq_tail = (tqe->prev);
176 if (p->txq_tail)
177 p->txq_tail->next = NULL;
178 } else {
179 tqe->prev->next = tqe->next;
180 tqe->next->prev = tqe->prev;
181 }
182 p->txq_entries -= 1;
c5c77ba1
JK		 183
184}
185
186static struct txq_entry_t *wilc_wlan_txq_remove_from_head(void)
187{
188 struct txq_entry_t *tqe;
189 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
190 unsigned long flags;
8dfaafd6 191
17c4d5d5 192 spin_lock_irqsave(p->txq_spinlock, flags);
c5c77ba1 193 if (p->txq_head) {
c5c77ba1
JK		 194 tqe = p->txq_head;
195 p->txq_head = tqe->next;
196 if (p->txq_head) {
197 p->txq_head->prev = NULL;
198 }
199 p->txq_entries -= 1;
200
201 /*Added by Amr - BugID_4720*/
202
203
c5c77ba1
JK		 204
205 } else {
206 tqe = NULL;
207 }
17c4d5d5 208 spin_unlock_irqrestore(p->txq_spinlock, flags);
c5c77ba1
JK		 209 return tqe;
210}
211
212static void wilc_wlan_txq_add_to_tail(struct txq_entry_t *tqe)
213{
214 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
215 unsigned long flags;
216 /*Added by Amr - BugID_4720*/
17c4d5d5 217 spin_lock_irqsave(p->txq_spinlock, flags);
c5c77ba1 218
c5c77ba1
JK		 219 if (p->txq_head == NULL) {
220 tqe->next = NULL;
221 tqe->prev = NULL;
222 p->txq_head = tqe;
223 p->txq_tail = tqe;
c5c77ba1
JK		 224 } else {
225 tqe->next = NULL;
226 tqe->prev = p->txq_tail;
227 p->txq_tail->next = tqe;
228 p->txq_tail = tqe;
229 }
230 p->txq_entries += 1;
231 PRINT_D(TX_DBG, "Number of entries in TxQ = %d\n", p->txq_entries);
c5c77ba1
JK		 232
233 /*Added by Amr - BugID_4720*/
17c4d5d5 234 spin_unlock_irqrestore(p->txq_spinlock, flags);
c5c77ba1
JK		 235
236 /**
237 * wake up TX queue
238 **/
239 PRINT_D(TX_DBG, "Wake the txq_handling\n");
240
8990d856 241 up(p->txq_wait);
c5c77ba1
JK		 242}
243
244static int wilc_wlan_txq_add_to_head(struct txq_entry_t *tqe)
245{
246 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
247 unsigned long flags;
248 /*Added by Amr - BugID_4720*/
249 if (p->os_func.os_wait(p->txq_add_to_head_lock, CFG_PKTS_TIMEOUT))
250 return -1;
251
17c4d5d5 252 spin_lock_irqsave(p->txq_spinlock, flags);
c5c77ba1 253
c5c77ba1
JK		 254 if (p->txq_head == NULL) {
255 tqe->next = NULL;
256 tqe->prev = NULL;
257 p->txq_head = tqe;
258 p->txq_tail = tqe;
259 } else {
260 tqe->next = p->txq_head;
261 tqe->prev = NULL;
262 p->txq_head->prev = tqe;
263 p->txq_head = tqe;
264 }
265 p->txq_entries += 1;
266 PRINT_D(TX_DBG, "Number of entries in TxQ = %d\n", p->txq_entries);
c5c77ba1
JK		 267
268 /*Added by Amr - BugID_4720*/
17c4d5d5 269 spin_unlock_irqrestore(p->txq_spinlock, flags);
8990d856 270 up(p->txq_add_to_head_lock);
c5c77ba1
JK		 271
272
273 /**
274 * wake up TX queue
275 **/
8990d856 276 up(p->txq_wait);
c5c77ba1 277 PRINT_D(TX_DBG, "Wake up the txq_handler\n");
c5c77ba1
JK		 278
279 /*Added by Amr - BugID_4720*/
280 return 0;
281
282}
283
284uint32_t Statisitcs_totalAcks = 0, Statisitcs_DroppedAcks = 0;
285
286#ifdef TCP_ACK_FILTER
287struct Ack_session_info;
eeb1c062 288struct Ack_session_info {
c5c77ba1
JK		 289 uint32_t Ack_seq_num;
290 uint32_t Bigger_Ack_num;
291 uint16_t src_port;
292 uint16_t dst_port;
293 uint16_t status;
eeb1c062 294};
c5c77ba1
JK		 295
296typedef struct {
297 uint32_t ack_num;
c5c77ba1
JK		 298 uint32_t Session_index;
299 struct txq_entry_t *txqe;
c5c77ba1
JK		 300} Pending_Acks_info_t /*Ack_info_t*/;
301
302
303
304
305struct Ack_session_info *Free_head;
306struct Ack_session_info *Alloc_head;
307
308#define TCP_FIN_MASK (1 << 0)
309#define TCP_SYN_MASK (1 << 1)
310#define TCP_Ack_MASK (1 << 4)
311#define NOT_TCP_ACK (-1)
312
313#define MAX_TCP_SESSION 25
314#define MAX_PENDING_ACKS 256
eeb1c062 315struct Ack_session_info Acks_keep_track_info[2 * MAX_TCP_SESSION];
c5c77ba1
JK		 316Pending_Acks_info_t Pending_Acks_info[MAX_PENDING_ACKS];
317
318uint32_t PendingAcks_arrBase;
319uint32_t Opened_TCP_session;
320uint32_t Pending_Acks;
321
322
323
324static __inline int Init_TCP_tracking(void)
325{
326
c5c77ba1
JK		 327 return 0;
328
329}
330static __inline int add_TCP_track_session(uint32_t src_prt, uint32_t dst_prt, uint32_t seq)
331{
332 Acks_keep_track_info[Opened_TCP_session].Ack_seq_num = seq;
333 Acks_keep_track_info[Opened_TCP_session].Bigger_Ack_num = 0;
334 Acks_keep_track_info[Opened_TCP_session].src_port = src_prt;
335 Acks_keep_track_info[Opened_TCP_session].dst_port = dst_prt;
336 Opened_TCP_session++;
337
338 PRINT_D(TCP_ENH, "TCP Session %d to Ack %d\n", Opened_TCP_session, seq);
339 return 0;
340}
341
342static __inline int Update_TCP_track_session(uint32_t index, uint32_t Ack)
343{
344
345 if (Ack > Acks_keep_track_info[index].Bigger_Ack_num) {
346 Acks_keep_track_info[index].Bigger_Ack_num = Ack;
347 }
348 return 0;
349
350}
351static __inline int add_TCP_Pending_Ack(uint32_t Ack, uint32_t Session_index, struct txq_entry_t *txqe)
352{
353 Statisitcs_totalAcks++;
354 if (Pending_Acks < MAX_PENDING_ACKS) {
355 Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].ack_num = Ack;
356 Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].txqe = txqe;
357 Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].Session_index = Session_index;
358 txqe->tcp_PendingAck_index = PendingAcks_arrBase + Pending_Acks;
359 Pending_Acks++;
360
361 } else {
362
363 }
364 return 0;
365}
366static __inline int remove_TCP_related(void)
367{
368 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
369 unsigned long flags;
8dfaafd6 370
17c4d5d5 371 spin_lock_irqsave(p->txq_spinlock, flags);
c5c77ba1 372
17c4d5d5 373 spin_unlock_irqrestore(p->txq_spinlock, flags);
c5c77ba1
JK		 374 return 0;
375}
376
377static __inline int tcp_process(struct txq_entry_t *tqe)
378{
379 int ret;
380 uint8_t *eth_hdr_ptr;
381 uint8_t *buffer = tqe->buffer;
382 unsigned short h_proto;
383 int i;
384 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
385 unsigned long flags;
8dfaafd6 386
17c4d5d5 387 spin_lock_irqsave(p->txq_spinlock, flags);
c5c77ba1
JK		 388
389 eth_hdr_ptr = &buffer[0];
390 h_proto = ntohs(*((unsigned short *)&eth_hdr_ptr[12]));
391 if (h_proto == 0x0800) { /* IP */
392 uint8_t *ip_hdr_ptr;
393 uint8_t protocol;
394
395 ip_hdr_ptr = &buffer[ETHERNET_HDR_LEN];
396 protocol = ip_hdr_ptr[9];
397
398
399 if (protocol == 0x06) {
400 uint8_t *tcp_hdr_ptr;
401 uint32_t IHL, Total_Length, Data_offset;
8dfaafd6 402
c5c77ba1
JK		 403 tcp_hdr_ptr = &ip_hdr_ptr[IP_HDR_LEN];
404 IHL = (ip_hdr_ptr[0] & 0xf) << 2;
405 Total_Length = (((uint32_t)ip_hdr_ptr[2]) << 8) + ((uint32_t)ip_hdr_ptr[3]);
406 Data_offset = (((uint32_t)tcp_hdr_ptr[12] & 0xf0) >> 2);
407 if (Total_Length == (IHL + Data_offset)) { /*we want to recognize the clear Acks(packet only carry Ack infos not with data) so data size must be equal zero*/
408 uint32_t seq_no, Ack_no;
8dfaafd6 409
c5c77ba1
JK		 410 seq_no = (((uint32_t)tcp_hdr_ptr[4]) << 24) + (((uint32_t)tcp_hdr_ptr[5]) << 16) + (((uint32_t)tcp_hdr_ptr[6]) << 8) + ((uint32_t)tcp_hdr_ptr[7]);
411
412 Ack_no = (((uint32_t)tcp_hdr_ptr[8]) << 24) + (((uint32_t)tcp_hdr_ptr[9]) << 16) + (((uint32_t)tcp_hdr_ptr[10]) << 8) + ((uint32_t)tcp_hdr_ptr[11]);
413
414
415 for (i = 0; i < Opened_TCP_session; i++) {
416 if (Acks_keep_track_info[i].Ack_seq_num == seq_no) {
417 Update_TCP_track_session(i, Ack_no);
418 break;
419 }
420 }
421 if (i == Opened_TCP_session) {
422 add_TCP_track_session(0, 0, seq_no);
423 }
424 add_TCP_Pending_Ack(Ack_no, i, tqe);
425
426
427 }
428
429 } else {
430 ret = 0;
431 }
432 } else {
433 ret = 0;
434 }
17c4d5d5 435 spin_unlock_irqrestore(p->txq_spinlock, flags);
c5c77ba1
JK		 436 return ret;
437}
438
439
440static int wilc_wlan_txq_filter_dup_tcp_ack(void)
441{
442
443 uint32_t i = 0;
444 uint32_t Dropped = 0;
445 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
446
17c4d5d5 447 spin_lock_irqsave(p->txq_spinlock, p->txq_spinlock_flags);
c5c77ba1
JK		 448 for (i = PendingAcks_arrBase; i < (PendingAcks_arrBase + Pending_Acks); i++) {
449 if (Pending_Acks_info[i].ack_num < Acks_keep_track_info[Pending_Acks_info[i].Session_index].Bigger_Ack_num) {
450 struct txq_entry_t *tqe;
8dfaafd6 451
17aacd43 452 PRINT_D(TCP_ENH, "DROP ACK: %u\n", Pending_Acks_info[i].ack_num);
c5c77ba1
JK		 453 tqe = Pending_Acks_info[i].txqe;
454 if (tqe) {
455 wilc_wlan_txq_remove(tqe);
456 Statisitcs_DroppedAcks++;
457 tqe->status = 1; /* mark the packet send */
458 if (tqe->tx_complete_func)
459 tqe->tx_complete_func(tqe->priv, tqe->status);
a18dd630 460 kfree(tqe);
c5c77ba1 461 Dropped++;
c5c77ba1
JK		 462 }
463 }
464 }
465 Pending_Acks = 0;
466 Opened_TCP_session = 0;
467
78174ada 468 if (PendingAcks_arrBase == 0)
c5c77ba1 469 PendingAcks_arrBase = MAX_TCP_SESSION;
78174ada 470 else
c5c77ba1 471 PendingAcks_arrBase = 0;
c5c77ba1
JK		 472
473
17c4d5d5 474 spin_unlock_irqrestore(p->txq_spinlock, p->txq_spinlock_flags);
c5c77ba1
JK		 475
476 while (Dropped > 0) {
477 /*consume the semaphore count of the removed packet*/
478 p->os_func.os_wait(p->txq_wait, 1);
479 Dropped--;
480 }
481
482 return 1;
483}
484#endif
485
486#ifdef TCP_ENHANCEMENTS
72ed4dc7 487bool EnableTCPAckFilter = false;
c5c77ba1 488
72ed4dc7 489void Enable_TCP_ACK_Filter(bool value)
c5c77ba1
JK		 490{
491 EnableTCPAckFilter = value;
492}
493
72ed4dc7 494bool is_TCP_ACK_Filter_Enabled(void)
c5c77ba1
JK		 495{
496 return EnableTCPAckFilter;
497}
498#endif
499
500static int wilc_wlan_txq_add_cfg_pkt(uint8_t *buffer, uint32_t buffer_size)
501{
502 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
503 struct txq_entry_t *tqe;
504
505 PRINT_D(TX_DBG, "Adding config packet ...\n");
506 if (p->quit) {
507 PRINT_D(TX_DBG, "Return due to clear function\n");
8990d856 508 up(p->cfg_wait);
c5c77ba1
JK		 509 return 0;
510 }
511
47c632d8 512 tqe = kmalloc(sizeof(struct txq_entry_t), GFP_ATOMIC);
c5c77ba1
JK		 513 if (tqe == NULL) {
514 PRINT_ER("Failed to allocate memory\n");
515 return 0;
516 }
517
518 tqe->type = WILC_CFG_PKT;
519 tqe->buffer = buffer;
520 tqe->buffer_size = buffer_size;
521 tqe->tx_complete_func = NULL;
522 tqe->priv = NULL;
523#ifdef TCP_ACK_FILTER
524 tqe->tcp_PendingAck_index = NOT_TCP_ACK;
525#endif
526 /**
527 * Configuration packet always at the front
528 **/
529 PRINT_D(TX_DBG, "Adding the config packet at the Queue tail\n");
530
531 /*Edited by Amr - BugID_4720*/
532 if (wilc_wlan_txq_add_to_head(tqe))
533 return 0;
c5c77ba1
JK		 534 return 1;
535}
536
537static int wilc_wlan_txq_add_net_pkt(void *priv, uint8_t *buffer, uint32_t buffer_size, wilc_tx_complete_func_t func)
538{
539 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
540 struct txq_entry_t *tqe;
541
542 if (p->quit)
543 return 0;
544
47c632d8 545 tqe = kmalloc(sizeof(struct txq_entry_t), GFP_ATOMIC);
c5c77ba1
JK		 546
547 if (tqe == NULL)
548 return 0;
549 tqe->type = WILC_NET_PKT;
550 tqe->buffer = buffer;
551 tqe->buffer_size = buffer_size;
552 tqe->tx_complete_func = func;
553 tqe->priv = priv;
554
555 PRINT_D(TX_DBG, "Adding mgmt packet at the Queue tail\n");
556#ifdef TCP_ACK_FILTER
557 tqe->tcp_PendingAck_index = NOT_TCP_ACK;
558#ifdef TCP_ENHANCEMENTS
5a66bf20 559 if (is_TCP_ACK_Filter_Enabled())
c5c77ba1
JK		 560#endif
561 tcp_process(tqe);
562#endif
563 wilc_wlan_txq_add_to_tail(tqe);
564 /*return number of itemes in the queue*/
565 return p->txq_entries;
566}
567/*Bug3959: transmitting mgmt frames received from host*/
568#if defined(WILC_AP_EXTERNAL_MLME) || defined(WILC_P2P)
569int wilc_wlan_txq_add_mgmt_pkt(void *priv, uint8_t *buffer, uint32_t buffer_size, wilc_tx_complete_func_t func)
570{
571
572 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
573 struct txq_entry_t *tqe;
574
575 if (p->quit)
576 return 0;
577
47c632d8 578 tqe = kmalloc(sizeof(struct txq_entry_t), GFP_KERNEL);
c5c77ba1
JK		 579
580 if (tqe == NULL)
581 return 0;
582 tqe->type = WILC_MGMT_PKT;
583 tqe->buffer = buffer;
584 tqe->buffer_size = buffer_size;
585 tqe->tx_complete_func = func;
586 tqe->priv = priv;
587#ifdef TCP_ACK_FILTER
588 tqe->tcp_PendingAck_index = NOT_TCP_ACK;
589#endif
590 PRINT_D(TX_DBG, "Adding Network packet at the Queue tail\n");
591 wilc_wlan_txq_add_to_tail(tqe);
592 return 1;
593}
c5c77ba1
JK		 594#endif /*WILC_AP_EXTERNAL_MLME*/
595static struct txq_entry_t *wilc_wlan_txq_get_first(void)
596{
597 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
598 struct txq_entry_t *tqe;
599 unsigned long flags;
600
601 /*Added by Amr - BugID_4720*/
17c4d5d5 602 spin_lock_irqsave(p->txq_spinlock, flags);
c5c77ba1 603
c5c77ba1
JK		 604 tqe = p->txq_head;
605
606 /*Added by Amr - BugID_4720*/
17c4d5d5 607 spin_unlock_irqrestore(p->txq_spinlock, flags);
c5c77ba1 608
c5c77ba1
JK		 609
610 return tqe;
611}
612
613static struct txq_entry_t *wilc_wlan_txq_get_next(struct txq_entry_t *tqe)
614{
615 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
616 unsigned long flags;
617 /*Added by Amr - BugID_4720*/
17c4d5d5 618 spin_lock_irqsave(p->txq_spinlock, flags);
c5c77ba1 619
c5c77ba1 620 tqe = tqe->next;
c5c77ba1 621 /*Added by Amr - BugID_4720*/
17c4d5d5 622 spin_unlock_irqrestore(p->txq_spinlock, flags);
c5c77ba1 623
c5c77ba1
JK		 624
625 return tqe;
626}
627
628static int wilc_wlan_rxq_add(struct rxq_entry_t *rqe)
629{
630 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
631
632 if (p->quit)
633 return 0;
634
5e150b52 635 mutex_lock(p->rxq_lock);
c5c77ba1
JK		 636 if (p->rxq_head == NULL) {
637 PRINT_D(RX_DBG, "Add to Queue head\n");
638 rqe->next = NULL;
639 p->rxq_head = rqe;
640 p->rxq_tail = rqe;
641 } else {
642 PRINT_D(RX_DBG, "Add to Queue tail\n");
643 p->rxq_tail->next = rqe;
644 rqe->next = NULL;
645 p->rxq_tail = rqe;
646 }
647 p->rxq_entries += 1;
648 PRINT_D(RX_DBG, "Number of queue entries: %d\n", p->rxq_entries);
5e150b52 649 mutex_unlock(p->rxq_lock);
c5c77ba1
JK		 650 return p->rxq_entries;
651}
652
653static struct rxq_entry_t *wilc_wlan_rxq_remove(void)
654{
655 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
656
657 PRINT_D(RX_DBG, "Getting rxQ element\n");
658 if (p->rxq_head) {
659 struct rxq_entry_t *rqe;
660
5e150b52 661 mutex_lock(p->rxq_lock);
c5c77ba1
JK		 662 rqe = p->rxq_head;
663 p->rxq_head = p->rxq_head->next;
664 p->rxq_entries -= 1;
665 PRINT_D(RX_DBG, "RXQ entries decreased\n");
5e150b52 666 mutex_unlock(p->rxq_lock);
c5c77ba1
JK		 667 return rqe;
668 }
669 PRINT_D(RX_DBG, "Nothing to get from Q\n");
670 return NULL;
671}
672
673
674/********************************************
675 *
676 * Power Save handle functions
677 *
678 ********************************************/
679
680
681
682#ifdef WILC_OPTIMIZE_SLEEP_INT
683
684INLINE void chip_allow_sleep(void)
685{
686 uint32_t reg = 0;
687
688 /* Clear bit 1 */
689 g_wlan.hif_func.hif_read_reg(0xf0, &reg);
690
691 g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0));
692}
693
694INLINE void chip_wakeup(void)
695{
696 uint32_t reg, clk_status_reg, trials = 0;
697 uint32_t sleep_time;
698
699 if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) {
700 do {
701 g_wlan.hif_func.hif_read_reg(1, &reg);
702 /* Set bit 1 */
703 g_wlan.hif_func.hif_write_reg(1, reg | (1 << 1));
704
705 /* Clear bit 1*/
706 g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1));
707
708 do {
709 /* Wait for the chip to stabilize*/
80e29c7a 710 usleep_range(2 * 1000, 2 * 1000);
c5c77ba1
JK		 711 /* Make sure chip is awake. This is an extra step that can be removed */
712 /* later to avoid the bus access overhead */
72ed4dc7 713 if ((wilc_get_chipid(true) == 0)) {
c5c77ba1
JK		 714 wilc_debug(N_ERR, "Couldn't read chip id. Wake up failed\n");
715 }
72ed4dc7 716 } while ((wilc_get_chipid(true) == 0) && ((++trials % 3) == 0));
c5c77ba1 717
72ed4dc7 718 } while (wilc_get_chipid(true) == 0);
c5c77ba1
JK		 719 } else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO) {
720 g_wlan.hif_func.hif_read_reg(0xf0, &reg);
721 do {
722 /* Set bit 1 */
723 g_wlan.hif_func.hif_write_reg(0xf0, reg | (1 << 0));
724
725 /* Check the clock status */
726 g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg);
727
728 /* in case of clocks off, wait 2ms, and check it again. */
729 /* if still off, wait for another 2ms, for a total wait of 6ms. */
730 /* If still off, redo the wake up sequence */
731 while (((clk_status_reg & 0x1) == 0) && (((++trials) % 3) == 0)) {
732 /* Wait for the chip to stabilize*/
80e29c7a 733 usleep_range(2 * 1000, 2 * 1000);
c5c77ba1
JK		 734
735 /* Make sure chip is awake. This is an extra step that can be removed */
736 /* later to avoid the bus access overhead */
737 g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg);
738
739 if ((clk_status_reg & 0x1) == 0) {
740 wilc_debug(N_ERR, "clocks still OFF. Wake up failed\n");
741 }
742 }
743 /* in case of failure, Reset the wakeup bit to introduce a new edge on the next loop */
744 if ((clk_status_reg & 0x1) == 0) {
745 /* Reset bit 0 */
746 g_wlan.hif_func.hif_write_reg(0xf0, reg & (~(1 << 0)));
747 }
748 } while ((clk_status_reg & 0x1) == 0);
749 }
750
751
752 if (genuChipPSstate == CHIP_SLEEPING_MANUAL) {
753 g_wlan.hif_func.hif_read_reg(0x1C0C, &reg);
754 reg &= ~(1 << 0);
755 g_wlan.hif_func.hif_write_reg(0x1C0C, reg);
756
72ed4dc7 757 if (wilc_get_chipid(false) >= 0x1002b0) {
c5c77ba1
JK		 758 /* Enable PALDO back right after wakeup */
759 uint32_t val32;
8dfaafd6 760
c5c77ba1
JK		 761 g_wlan.hif_func.hif_read_reg(0x1e1c, &val32);
762 val32 |= (1 << 6);
763 g_wlan.hif_func.hif_write_reg(0x1e1c, val32);
764
765 g_wlan.hif_func.hif_read_reg(0x1e9c, &val32);
766 val32 |= (1 << 6);
767 g_wlan.hif_func.hif_write_reg(0x1e9c, val32);
768 }
769 }
770 genuChipPSstate = CHIP_WAKEDUP;
771}
772#else
773INLINE void chip_wakeup(void)
774{
775 uint32_t reg, trials = 0;
8dfaafd6 776
c5c77ba1
JK		 777 do {
778 if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) {
779 g_wlan.hif_func.hif_read_reg(1, &reg);
780 /* Make sure bit 1 is 0 before we start. */
781 g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1));
782 /* Set bit 1 */
783 g_wlan.hif_func.hif_write_reg(1, reg | (1 << 1));
784 /* Clear bit 1*/
785 g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1));
786 } else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO) {
787 /* Make sure bit 0 is 0 before we start. */
788 g_wlan.hif_func.hif_read_reg(0xf0, &reg);
789 g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0));
790 /* Set bit 1 */
791 g_wlan.hif_func.hif_write_reg(0xf0, reg | (1 << 0));
792 /* Clear bit 1 */
793 g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0));
794 }
795
796 do {
797 /* Wait for the chip to stabilize*/
c5c77ba1
JK		 798 mdelay(3);
799
800 /* Make sure chip is awake. This is an extra step that can be removed */
801 /* later to avoid the bus access overhead */
72ed4dc7 802 if ((wilc_get_chipid(true) == 0)) {
c5c77ba1
JK		 803 wilc_debug(N_ERR, "Couldn't read chip id. Wake up failed\n");
804 }
72ed4dc7 805 } while ((wilc_get_chipid(true) == 0) && ((++trials % 3) == 0));
c5c77ba1 806
72ed4dc7 807 } while (wilc_get_chipid(true) == 0);
c5c77ba1
JK		 808
809 if (genuChipPSstate == CHIP_SLEEPING_MANUAL) {
810 g_wlan.hif_func.hif_read_reg(0x1C0C, &reg);
811 reg &= ~(1 << 0);
812 g_wlan.hif_func.hif_write_reg(0x1C0C, reg);
813
72ed4dc7 814 if (wilc_get_chipid(false) >= 0x1002b0) {
c5c77ba1
JK		 815 /* Enable PALDO back right after wakeup */
816 uint32_t val32;
8dfaafd6 817
c5c77ba1
JK		 818 g_wlan.hif_func.hif_read_reg(0x1e1c, &val32);
819 val32 |= (1 << 6);
820 g_wlan.hif_func.hif_write_reg(0x1e1c, val32);
821
822 g_wlan.hif_func.hif_read_reg(0x1e9c, &val32);
823 val32 |= (1 << 6);
824 g_wlan.hif_func.hif_write_reg(0x1e9c, val32);
825 }
826 }
827 genuChipPSstate = CHIP_WAKEDUP;
828}
829#endif
4e4467fd 830void chip_sleep_manually(u32 u32SleepTime)
c5c77ba1 831{
c5c77ba1
JK		 832 if (genuChipPSstate != CHIP_WAKEDUP) {
833 /* chip is already sleeping. Do nothing */
834 return;
835 }
836 acquire_bus(ACQUIRE_ONLY);
837
838#ifdef WILC_OPTIMIZE_SLEEP_INT
839 chip_allow_sleep();
840#endif
841
842 /* Trigger the manual sleep interrupt */
843 g_wlan.hif_func.hif_write_reg(0x10a8, 1);
844
845 genuChipPSstate = CHIP_SLEEPING_MANUAL;
846 release_bus(RELEASE_ONLY);
847
848}
849
850
851/********************************************
852 *
853 * Tx, Rx queue handle functions
854 *
855 ********************************************/
856static int wilc_wlan_handle_txq(uint32_t *pu32TxqCount)
857{
858 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
859 int i, entries = 0;
860 uint32_t sum;
861 uint32_t reg;
862 uint8_t *txb = p->tx_buffer;
863 uint32_t offset = 0;
864 int vmm_sz = 0;
865 struct txq_entry_t *tqe;
866 int ret = 0;
867 int counter;
868 int timeout;
869 uint32_t vmm_table[WILC_VMM_TBL_SIZE];
8dfaafd6 870
c5c77ba1
JK		 871 p->txq_exit = 0;
872 do {
873 if (p->quit)
874 break;
875
876 /*Added by Amr - BugID_4720*/
877 p->os_func.os_wait(p->txq_add_to_head_lock, CFG_PKTS_TIMEOUT);
878#ifdef TCP_ACK_FILTER
879 wilc_wlan_txq_filter_dup_tcp_ack();
880#endif
881 /**
882 * build the vmm list
883 **/
884 PRINT_D(TX_DBG, "Getting the head of the TxQ\n");
885 tqe = wilc_wlan_txq_get_first();
886 i = 0;
887 sum = 0;
888 do {
889 /* if ((tqe != NULL) && (i < (8)) && */
890 /* if ((tqe != NULL) && (i < (WILC_VMM_TBL_SIZE-1)) && */
891 if ((tqe != NULL) && (i < (WILC_VMM_TBL_SIZE - 1)) /* reserve last entry to 0 */) {
892
893 if (tqe->type == WILC_CFG_PKT) {
894 vmm_sz = ETH_CONFIG_PKT_HDR_OFFSET;
895 }
896 /*Bug3959: transmitting mgmt frames received from host*/
897 /*vmm_sz will only be equal to tqe->buffer_size + 4 bytes (HOST_HDR_OFFSET)*/
898 /* in other cases WILC_MGMT_PKT and WILC_DATA_PKT_MAC_HDR*/
899 else if (tqe->type == WILC_NET_PKT) {
900 vmm_sz = ETH_ETHERNET_HDR_OFFSET;
901 }
c5c77ba1
JK		 902#ifdef WILC_AP_EXTERNAL_MLME
903 else {
904 vmm_sz = HOST_HDR_OFFSET;
905 }
906#endif
907 vmm_sz += tqe->buffer_size;
908 PRINT_D(TX_DBG, "VMM Size before alignment = %d\n", vmm_sz);
909 if (vmm_sz & 0x3) { /* has to be word aligned */
910 vmm_sz = (vmm_sz + 4) & ~0x3;
911 }
912 if ((sum + vmm_sz) > p->tx_buffer_size) {
913 break;
914 }
915 PRINT_D(TX_DBG, "VMM Size AFTER alignment = %d\n", vmm_sz);
916 vmm_table[i] = vmm_sz / 4; /* table take the word size */
917 PRINT_D(TX_DBG, "VMMTable entry size = %d\n", vmm_table[i]);
918
919 if (tqe->type == WILC_CFG_PKT) {
920 vmm_table[i] |= (1 << 10);
921 PRINT_D(TX_DBG, "VMMTable entry changed for CFG packet = %d\n", vmm_table[i]);
922 }
923#ifdef BIG_ENDIAN
924 vmm_table[i] = BYTE_SWAP(vmm_table[i]);
925#endif
c5c77ba1 926
c5c77ba1
JK		 927 i++;
928 sum += vmm_sz;
929 PRINT_D(TX_DBG, "sum = %d\n", sum);
930 tqe = wilc_wlan_txq_get_next(tqe);
931 } else {
932 break;
933 }
934 } while (1);
935
936 if (i == 0) { /* nothing in the queue */
937 PRINT_D(TX_DBG, "Nothing in TX-Q\n");
938 break;
939 } else {
940 PRINT_D(TX_DBG, "Mark the last entry in VMM table - number of previous entries = %d\n", i);
941 vmm_table[i] = 0x0; /* mark the last element to 0 */
942 }
943 acquire_bus(ACQUIRE_AND_WAKEUP);
944 counter = 0;
945 do {
946
947 ret = p->hif_func.hif_read_reg(WILC_HOST_TX_CTRL, &reg);
948 if (!ret) {
949 wilc_debug(N_ERR, "[wilc txq]: fail can't read reg vmm_tbl_entry..\n");
950 break;
951 }
952
953 if ((reg & 0x1) == 0) {
954 /**
955 * write to vmm table
956 **/
957 PRINT_D(TX_DBG, "Writing VMM table ... with Size = %d\n", ((i + 1) * 4));
958 break;
959 } else {
960 counter++;
961 if (counter > 200) {
962 counter = 0;
963 PRINT_D(TX_DBG, "Looping in tx ctrl , forcce quit\n");
964 ret = p->hif_func.hif_write_reg(WILC_HOST_TX_CTRL, 0);
965 break;
966 }
967 /**
968 * wait for vmm table is ready
969 **/
17aacd43 970 PRINT_WRN(GENERIC_DBG, "[wilc txq]: warn, vmm table not clear yet, wait...\n");
c5c77ba1 971 release_bus(RELEASE_ALLOW_SLEEP);
2b922cbe 972 usleep_range(3000, 3000);
c5c77ba1
JK		 973 acquire_bus(ACQUIRE_AND_WAKEUP);
974 }
975 } while (!p->quit);
976
977 if (!ret) {
978 goto _end_;
979 }
980
981 timeout = 200;
982 do {
983
984 /**
985 * write to vmm table
986 **/
987 ret = p->hif_func.hif_block_tx(WILC_VMM_TBL_RX_SHADOW_BASE, (uint8_t *)vmm_table, ((i + 1) * 4)); /* Bug 4477 fix */
988 if (!ret) {
989 wilc_debug(N_ERR, "ERR block TX of VMM table.\n");
990 break;
991 }
992
993
994 /**
995 * interrupt firmware
996 **/
997 ret = p->hif_func.hif_write_reg(WILC_HOST_VMM_CTL, 0x2);
998 if (!ret) {
999 wilc_debug(N_ERR, "[wilc txq]: fail can't write reg host_vmm_ctl..\n");
1000 break;
1001 }
1002
1003 /**
1004 * wait for confirm...
1005 **/
1006
1007 do {
1008 ret = p->hif_func.hif_read_reg(WILC_HOST_VMM_CTL, &reg);
1009 if (!ret) {
1010 wilc_debug(N_ERR, "[wilc txq]: fail can't read reg host_vmm_ctl..\n");
1011 break;
1012 }
1013 if ((reg >> 2) & 0x1) {
1014 /**
1015 * Get the entries
1016 **/
1017 entries = ((reg >> 3) & 0x3f);
1018 /* entries = ((reg>>3)&0x2f); */
1019 break;
1020 } else {
1021 release_bus(RELEASE_ALLOW_SLEEP);
2b922cbe 1022 usleep_range(3000, 3000);
c5c77ba1
JK		 1023 acquire_bus(ACQUIRE_AND_WAKEUP);
1024 PRINT_WRN(GENERIC_DBG, "Can't get VMM entery - reg = %2x\n", reg);
1025 }
1026 } while (--timeout);
1027 if (timeout <= 0) {
1028 ret = p->hif_func.hif_write_reg(WILC_HOST_VMM_CTL, 0x0);
1029 break;
1030 }
1031
1032 if (!ret) {
1033 break;
1034 }
1035
1036 if (entries == 0) {
17aacd43 1037 PRINT_WRN(GENERIC_DBG, "[wilc txq]: no more buffer in the chip (reg: %08x), retry later [[ %d, %x ]]\n", reg, i, vmm_table[i - 1]);
c5c77ba1
JK		 1038
1039 /* undo the transaction. */
1040 ret = p->hif_func.hif_read_reg(WILC_HOST_TX_CTRL, &reg);
1041 if (!ret) {
1042 wilc_debug(N_ERR, "[wilc txq]: fail can't read reg WILC_HOST_TX_CTRL..\n");
1043 break;
1044 }
1045 reg &= ~(1ul << 0);
1046 ret = p->hif_func.hif_write_reg(WILC_HOST_TX_CTRL, reg);
1047 if (!ret) {
1048 wilc_debug(N_ERR, "[wilc txq]: fail can't write reg WILC_HOST_TX_CTRL..\n");
1049 break;
1050 }
1051 break;
1052 } else {
1053 break;
1054 }
1055 } while (1);
1056
1057 if (!ret) {
1058 goto _end_;
1059 }
1060 if (entries == 0) {
1061 ret = WILC_TX_ERR_NO_BUF;
1062 goto _end_;
1063 }
1064
1065 /* since copying data into txb takes some time, then
1066 * allow the bus lock to be released let the RX task go. */
1067 release_bus(RELEASE_ALLOW_SLEEP);
1068
1069 /**
1070 * Copy data to the TX buffer
1071 **/
1072 offset = 0;
1073 i = 0;
1074 do {
1075 tqe = wilc_wlan_txq_remove_from_head();
1076 if (tqe != NULL && (vmm_table[i] != 0)) {
1077 uint32_t header, buffer_offset;
1078
1079#ifdef BIG_ENDIAN
1080 vmm_table[i] = BYTE_SWAP(vmm_table[i]);
1081#endif
1082 vmm_sz = (vmm_table[i] & 0x3ff); /* in word unit */
1083 vmm_sz *= 4;
1084 header = (tqe->type << 31) | (tqe->buffer_size << 15) | vmm_sz;
1085 /*Bug3959: transmitting mgmt frames received from host*/
1086 /*setting bit 30 in the host header to indicate mgmt frame*/
1087#ifdef WILC_AP_EXTERNAL_MLME
78174ada 1088 if (tqe->type == WILC_MGMT_PKT)
c5c77ba1 1089 header |= (1 << 30);
78174ada 1090 else
c5c77ba1 1091 header &= ~(1 << 30);
c5c77ba1 1092#endif
c5c77ba1
JK		 1093
1094#ifdef BIG_ENDIAN
1095 header = BYTE_SWAP(header);
1096#endif
1097 memcpy(&txb[offset], &header, 4);
1098 if (tqe->type == WILC_CFG_PKT) {
1099 buffer_offset = ETH_CONFIG_PKT_HDR_OFFSET;
1100 }
1101 /*Bug3959: transmitting mgmt frames received from host*/
1102 /*buffer offset = HOST_HDR_OFFSET in other cases: WILC_MGMT_PKT*/
1103 /* and WILC_DATA_PKT_MAC_HDR*/
1104 else if (tqe->type == WILC_NET_PKT) {
1105 char *pBSSID = ((struct tx_complete_data *)(tqe->priv))->pBssid;
8dfaafd6 1106
c5c77ba1
JK		 1107 buffer_offset = ETH_ETHERNET_HDR_OFFSET;
1108 /* copy the bssid at the sart of the buffer */
1109 memcpy(&txb[offset + 4], pBSSID, 6);
1110 }
c5c77ba1
JK		 1111 else {
1112 buffer_offset = HOST_HDR_OFFSET;
1113 }
1114
1115 memcpy(&txb[offset + buffer_offset], tqe->buffer, tqe->buffer_size);
1116 offset += vmm_sz;
1117 i++;
1118 tqe->status = 1; /* mark the packet send */
1119 if (tqe->tx_complete_func)
1120 tqe->tx_complete_func(tqe->priv, tqe->status);
1121 #ifdef TCP_ACK_FILTER
1122 if (tqe->tcp_PendingAck_index != NOT_TCP_ACK) {
1123 Pending_Acks_info[tqe->tcp_PendingAck_index].txqe = NULL;
1124 }
1125 #endif
a18dd630 1126 kfree(tqe);
c5c77ba1
JK		 1127 } else {
1128 break;
1129 }
1130 } while (--entries);
1131
1132 /**
1133 * lock the bus
1134 **/
1135 acquire_bus(ACQUIRE_AND_WAKEUP);
1136
1137 ret = p->hif_func.hif_clear_int_ext(ENABLE_TX_VMM);
1138 if (!ret) {
1139 wilc_debug(N_ERR, "[wilc txq]: fail can't start tx VMM ...\n");
1140 goto _end_;
1141 }
1142
1143 /**
1144 * transfer
1145 **/
1146 ret = p->hif_func.hif_block_tx_ext(0, txb, offset);
1147 if (!ret) {
1148 wilc_debug(N_ERR, "[wilc txq]: fail can't block tx ext...\n");
1149 goto _end_;
1150 }
1151
1152_end_:
1153
1154 release_bus(RELEASE_ALLOW_SLEEP);
1155 if (ret != 1)
1156 break;
1157 } while (0);
c5c77ba1 1158 /*Added by Amr - BugID_4720*/
8990d856 1159 up(p->txq_add_to_head_lock);
c5c77ba1
JK		 1160
1161 p->txq_exit = 1;
1162 PRINT_D(TX_DBG, "THREAD: Exiting txq\n");
1163 /* return tx[]q count */
1164 *pu32TxqCount = p->txq_entries;
1165 return ret;
1166}
1167
1168static void wilc_wlan_handle_rxq(void)
1169{
1170 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1171 int offset = 0, size, has_packet = 0;
1172 uint8_t *buffer;
1173 struct rxq_entry_t *rqe;
1174
1175 p->rxq_exit = 0;
1176
1177
1178
1179
1180 do {
1181 if (p->quit) {
17aacd43 1182 PRINT_D(RX_DBG, "exit 1st do-while due to Clean_UP function\n");
8990d856 1183 up(p->cfg_wait);
c5c77ba1
JK		 1184 break;
1185 }
1186 rqe = wilc_wlan_rxq_remove();
1187 if (rqe == NULL) {
1188 PRINT_D(RX_DBG, "nothing in the queue - exit 1st do-while\n");
1189 break;
1190 }
1191 buffer = rqe->buffer;
1192 size = rqe->buffer_size;
1193 PRINT_D(RX_DBG, "rxQ entery Size = %d - Address = %p\n", size, buffer);
1194 offset = 0;
1195
1196
1197
1198 do {
1199 uint32_t header;
1200 uint32_t pkt_len, pkt_offset, tp_len;
1201 int is_cfg_packet;
8dfaafd6 1202
c5c77ba1
JK		 1203 PRINT_D(RX_DBG, "In the 2nd do-while\n");
1204 memcpy(&header, &buffer[offset], 4);
1205#ifdef BIG_ENDIAN
1206 header = BYTE_SWAP(header);
1207#endif
1208 PRINT_D(RX_DBG, "Header = %04x - Offset = %d\n", header, offset);
1209
1210
1211
1212 is_cfg_packet = (header >> 31) & 0x1;
1213 pkt_offset = (header >> 22) & 0x1ff;
1214 tp_len = (header >> 11) & 0x7ff;
1215 pkt_len = header & 0x7ff;
1216
1217 if (pkt_len == 0 || tp_len == 0) {
1218 wilc_debug(N_RXQ, "[wilc rxq]: data corrupt, packet len or tp_len is 0 [%d][%d]\n", pkt_len, tp_len);
1219 break;
1220 }
1221
1222/*bug 3887: [AP] Allow Management frames to be passed to the host*/
1223 #if defined(WILC_AP_EXTERNAL_MLME) || defined(WILC_P2P)
1224 #define IS_MANAGMEMENT 0x100
1225 #define IS_MANAGMEMENT_CALLBACK 0x080
1226 #define IS_MGMT_STATUS_SUCCES 0x040
1227
1228
1229 if (pkt_offset & IS_MANAGMEMENT) {
1230 /* reset mgmt indicator bit, to use pkt_offeset in furthur calculations */
1231 pkt_offset &= ~(IS_MANAGMEMENT | IS_MANAGMEMENT_CALLBACK | IS_MGMT_STATUS_SUCCES);
1232
1233#ifdef USE_WIRELESS
1234 WILC_WFI_mgmt_rx(&buffer[offset + HOST_HDR_OFFSET], pkt_len);
1235
1236#endif
1237
1238 }
1239 /* BUG4530 fix */
1240 else
1241 #endif
1242 {
c5c77ba1
JK		 1243
1244 if (!is_cfg_packet) {
1245
1246 if (p->net_func.rx_indicate) {
1247 if (pkt_len > 0) {
1248 p->net_func.rx_indicate(&buffer[offset], pkt_len, pkt_offset);
1249 has_packet = 1;
1250 }
1251 }
1252 } else {
1253 wilc_cfg_rsp_t rsp;
1254
1255
1256
1257 p->cif_func.rx_indicate(&buffer[pkt_offset + offset], pkt_len, &rsp);
1258 if (rsp.type == WILC_CFG_RSP) {
1259 /**
1260 * wake up the waiting task...
1261 **/
1262 PRINT_D(RX_DBG, "p->cfg_seq_no = %d - rsp.seq_no = %d\n", p->cfg_seq_no, rsp.seq_no);
1263 if (p->cfg_seq_no == rsp.seq_no) {
8990d856 1264 up(p->cfg_wait);
c5c77ba1 1265 }
c5c77ba1
JK		 1266 } else if (rsp.type == WILC_CFG_RSP_STATUS) {
1267 /**
1268 * Call back to indicate status...
1269 **/
1270 if (p->indicate_func.mac_indicate) {
1271 p->indicate_func.mac_indicate(WILC_MAC_INDICATE_STATUS);
1272 }
1273
1274 } else if (rsp.type == WILC_CFG_RSP_SCAN) {
1275 if (p->indicate_func.mac_indicate)
1276 p->indicate_func.mac_indicate(WILC_MAC_INDICATE_SCAN);
1277 }
1278 }
1279 }
1280 offset += tp_len;
1281 if (offset >= size)
1282 break;
1283 } while (1);
1284
1285
1286#ifndef MEMORY_STATIC
a18dd630 1287 kfree(buffer);
c5c77ba1 1288#endif
a18dd630 1289 kfree(rqe);
c5c77ba1
JK		 1290
1291 if (has_packet) {
1292 if (p->net_func.rx_complete)
1293 p->net_func.rx_complete();
1294 }
1295 } while (1);
1296
1297 p->rxq_exit = 1;
17aacd43 1298 PRINT_D(RX_DBG, "THREAD: Exiting RX thread\n");
c5c77ba1
JK		 1299}
1300
1301/********************************************
1302 *
1303 * Fast DMA Isr
1304 *
1305 ********************************************/
1306static void wilc_unknown_isr_ext(void)
1307{
1308 g_wlan.hif_func.hif_clear_int_ext(0);
1309}
1310static void wilc_pllupdate_isr_ext(uint32_t int_stats)
1311{
1312
1313 int trials = 10;
1314
1315 g_wlan.hif_func.hif_clear_int_ext(PLL_INT_CLR);
1316
1317 /* Waiting for PLL */
c2e4c0f1 1318 mdelay(WILC_PLL_TO);
c5c77ba1
JK		 1319
1320 /* poll till read a valid data */
72ed4dc7 1321 while (!(ISWILC1000(wilc_get_chipid(true)) && --trials)) {
c5c77ba1 1322 PRINT_D(TX_DBG, "PLL update retrying\n");
c2e4c0f1 1323 mdelay(1);
c5c77ba1
JK		 1324 }
1325}
1326
1327static void wilc_sleeptimer_isr_ext(uint32_t int_stats1)
1328{
1329 g_wlan.hif_func.hif_clear_int_ext(SLEEP_INT_CLR);
1330#ifndef WILC_OPTIMIZE_SLEEP_INT
1331 genuChipPSstate = CHIP_SLEEPING_AUTO;
1332#endif
1333}
1334
1335static void wilc_wlan_handle_isr_ext(uint32_t int_status)
1336{
1337 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1338#ifdef MEMORY_STATIC
1339 uint32_t offset = p->rx_buffer_offset;
1340#endif
1341 uint8_t *buffer = NULL;
1342 uint32_t size;
1343 uint32_t retries = 0;
1344 int ret = 0;
1345 struct rxq_entry_t *rqe;
1346
1347
1348 /**
1349 * Get the rx size
1350 **/
1351
1352 size = ((int_status & 0x7fff) << 2);
1353
1354 while (!size && retries < 10) {
1355 uint32_t time = 0;
1356 /*looping more secure*/
1357 /*zero size make a crashe because the dma will not happen and that will block the firmware*/
1358 wilc_debug(N_ERR, "RX Size equal zero ... Trying to read it again for %d time\n", time++);
1359 p->hif_func.hif_read_size(&size);
1360 size = ((size & 0x7fff) << 2);
1361 retries++;
1362
1363 }
1364
1365 if (size > 0) {
1366#ifdef MEMORY_STATIC
1367 if (p->rx_buffer_size - offset < size)
1368 offset = 0;
1369
1370 if (p->rx_buffer)
1371 buffer = &p->rx_buffer[offset];
1372 else {
1373 wilc_debug(N_ERR, "[wilc isr]: fail Rx Buffer is NULL...drop the packets (%d)\n", size);
1374 goto _end_;
1375 }
1376
1377#else
f019b9d9 1378 buffer = kmalloc(size, GFP_KERNEL);
c5c77ba1
JK		 1379 if (buffer == NULL) {
1380 wilc_debug(N_ERR, "[wilc isr]: fail alloc host memory...drop the packets (%d)\n", size);
80e29c7a 1381 usleep_range(100 * 1000, 100 * 1000);
c5c77ba1
JK		 1382 goto _end_;
1383 }
1384#endif
1385
1386 /**
1387 * clear the chip's interrupt after getting size some register getting corrupted after clear the interrupt
1388 **/
1389 p->hif_func.hif_clear_int_ext(DATA_INT_CLR | ENABLE_RX_VMM);
1390
1391
1392 /**
1393 * start transfer
1394 **/
1395 ret = p->hif_func.hif_block_rx_ext(0, buffer, size);
1396
1397 if (!ret) {
1398 wilc_debug(N_ERR, "[wilc isr]: fail block rx...\n");
1399 goto _end_;
1400 }
1401_end_:
1402
1403
1404 if (ret) {
1405#ifdef MEMORY_STATIC
1406 offset += size;
1407 p->rx_buffer_offset = offset;
1408#endif
1409 /**
1410 * add to rx queue
1411 **/
f019b9d9 1412 rqe = kmalloc(sizeof(struct rxq_entry_t), GFP_KERNEL);
c5c77ba1
JK		 1413 if (rqe != NULL) {
1414 rqe->buffer = buffer;
1415 rqe->buffer_size = size;
1416 PRINT_D(RX_DBG, "rxq entery Size= %d - Address = %p\n", rqe->buffer_size, rqe->buffer);
1417 wilc_wlan_rxq_add(rqe);
8990d856 1418 up(p->rxq_wait);
c5c77ba1
JK		 1419 }
1420 } else {
1421#ifndef MEMORY_STATIC
a18dd630 1422 kfree(buffer);
c5c77ba1
JK		 1423#endif
1424 }
1425 }
1426#ifdef TCP_ENHANCEMENTS
1427 wilc_wlan_handle_rxq();
1428#endif
1429}
1430
1431void wilc_handle_isr(void)
1432{
1433 uint32_t int_status;
1434
1435 acquire_bus(ACQUIRE_AND_WAKEUP);
1436 g_wlan.hif_func.hif_read_int(&int_status);
1437
1438 if (int_status & PLL_INT_EXT) {
1439 wilc_pllupdate_isr_ext(int_status);
1440 }
1441 if (int_status & DATA_INT_EXT) {
1442 wilc_wlan_handle_isr_ext(int_status);
1443 #ifndef WILC_OPTIMIZE_SLEEP_INT
1444 /* Chip is up and talking*/
1445 genuChipPSstate = CHIP_WAKEDUP;
1446 #endif
1447 }
1448 if (int_status & SLEEP_INT_EXT) {
1449 wilc_sleeptimer_isr_ext(int_status);
1450 }
1451
1452 if (!(int_status & (ALL_INT_EXT))) {
1453#ifdef WILC_SDIO
1454 PRINT_D(TX_DBG, ">> UNKNOWN_INTERRUPT - 0x%08x\n", int_status);
1455#endif
1456 wilc_unknown_isr_ext();
1457 }
1458#if ((!defined WILC_SDIO) || (defined WILC_SDIO_IRQ_GPIO))
1459 linux_wlan_enable_irq();
1460#endif
1461 release_bus(RELEASE_ALLOW_SLEEP);
1462}
1463
1464/********************************************
1465 *
1466 * Firmware download
1467 *
1468 ********************************************/
1469static int wilc_wlan_firmware_download(const uint8_t *buffer, uint32_t buffer_size)
1470{
1471 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1472 uint32_t offset;
1473 uint32_t addr, size, size2, blksz;
1474 uint8_t *dma_buffer;
1475 int ret = 0;
1476
1477 blksz = (1ul << 12); /* Bug 4703: 4KB Good enough size for most platforms = PAGE_SIZE. */
1478 /* Allocate a DMA coherent buffer. */
1479
f019b9d9 1480 dma_buffer = kmalloc(blksz, GFP_KERNEL);
c5c77ba1
JK		 1481 if (dma_buffer == NULL) {
1482 /*EIO 5*/
1483 ret = -5;
1484 PRINT_ER("Can't allocate buffer for firmware download IO error\n ");
1485 goto _fail_1;
1486 }
1487
1488 PRINT_D(INIT_DBG, "Downloading firmware size = %d ...\n", buffer_size);
1489 /**
1490 * load the firmware
1491 **/
1492 offset = 0;
1493 do {
1494 memcpy(&addr, &buffer[offset], 4);
1495 memcpy(&size, &buffer[offset + 4], 4);
1496#ifdef BIG_ENDIAN
1497 addr = BYTE_SWAP(addr);
1498 size = BYTE_SWAP(size);
1499#endif
1500 acquire_bus(ACQUIRE_ONLY);
1501 offset += 8;
1502 while (((int)size) && (offset < buffer_size)) {
78174ada 1503 if (size <= blksz)
c5c77ba1 1504 size2 = size;
78174ada 1505 else
c5c77ba1 1506 size2 = blksz;
c5c77ba1
JK		 1507 /* Copy firmware into a DMA coherent buffer */
1508 memcpy(dma_buffer, &buffer[offset], size2);
1509 ret = p->hif_func.hif_block_tx(addr, dma_buffer, size2);
1510 if (!ret)
1511 break;
1512
1513 addr += size2;
1514 offset += size2;
1515 size -= size2;
1516 }
1517 release_bus(RELEASE_ONLY);
1518
1519 if (!ret) {
1520 /*EIO 5*/
1521 ret = -5;
1522 PRINT_ER("Can't download firmware IO error\n ");
1523 goto _fail_;
1524 }
1525 PRINT_D(INIT_DBG, "Offset = %d\n", offset);
1526 } while (offset < buffer_size);
1527
1528_fail_:
1529
a18dd630 1530 kfree(dma_buffer);
c5c77ba1
JK		 1531
1532_fail_1:
1533
1534 return (ret < 0) ? ret : 0;
1535}
1536
1537/********************************************
1538 *
1539 * Common
1540 *
1541 ********************************************/
1542static int wilc_wlan_start(void)
1543{
1544 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1545 uint32_t reg = 0;
1546 int ret;
1547 uint32_t chipid;
1548
1549 /**
1550 * Set the host interface
1551 **/
1552#ifdef OLD_FPGA_BITFILE
1553 acquire_bus(ACQUIRE_ONLY);
1554 ret = p->hif_func.hif_read_reg(WILC_VMM_CORE_CTL, &reg);
1555 if (!ret) {
1556 wilc_debug(N_ERR, "[wilc start]: fail read reg vmm_core_ctl...\n");
1557 release_bus(RELEASE_ALLOW_SLEEP);
1558 return ret;
1559 }
1560 reg |= (p->io_func.io_type << 2);
1561 ret = p->hif_func.hif_write_reg(WILC_VMM_CORE_CTL, reg);
1562 if (!ret) {
1563 wilc_debug(N_ERR, "[wilc start]: fail write reg vmm_core_ctl...\n");
1564 release_bus(RELEASE_ONLY);
1565 return ret;
1566 }
1567#else
1568 if (p->io_func.io_type == HIF_SDIO) {
1569 reg = 0;
1570 reg |= (1 << 3); /* bug 4456 and 4557 */
1571 } else if (p->io_func.io_type == HIF_SPI) {
1572 reg = 1;
1573 }
1574 acquire_bus(ACQUIRE_ONLY);
1575 ret = p->hif_func.hif_write_reg(WILC_VMM_CORE_CFG, reg);
1576 if (!ret) {
1577 wilc_debug(N_ERR, "[wilc start]: fail write reg vmm_core_cfg...\n");
1578 release_bus(RELEASE_ONLY);
1579 /* EIO 5*/
1580 ret = -5;
1581 return ret;
1582 }
1583 reg = 0;
1584#ifdef WILC_SDIO_IRQ_GPIO
1585 reg |= WILC_HAVE_SDIO_IRQ_GPIO;
1586#endif
1587
1588#ifdef WILC_DISABLE_PMU
1589#else
1590 reg |= WILC_HAVE_USE_PMU;
1591#endif
1592
1593#ifdef WILC_SLEEP_CLK_SRC_XO
1594 reg |= WILC_HAVE_SLEEP_CLK_SRC_XO;
1595#elif defined WILC_SLEEP_CLK_SRC_RTC
1596 reg |= WILC_HAVE_SLEEP_CLK_SRC_RTC;
1597#endif
1598
1599#ifdef WILC_EXT_PA_INV_TX_RX
1600 reg |= WILC_HAVE_EXT_PA_INV_TX_RX;
1601#endif
1602
1603 reg |= WILC_HAVE_LEGACY_RF_SETTINGS;
1604
1605
1606/*BugID_5257*/
1607/*Set oscillator frequency*/
1608#ifdef XTAL_24
1609 reg |= WILC_HAVE_XTAL_24;
1610#endif
1611
1612/*BugID_5271*/
1613/*Enable/Disable GPIO configuration for FW logs*/
1614#ifdef DISABLE_WILC_UART
1615 reg |= WILC_HAVE_DISABLE_WILC_UART;
1616#endif
1617
1618 ret = p->hif_func.hif_write_reg(WILC_GP_REG_1, reg);
1619 if (!ret) {
1620 wilc_debug(N_ERR, "[wilc start]: fail write WILC_GP_REG_1 ...\n");
1621 release_bus(RELEASE_ONLY);
1622 /* EIO 5*/
1623 ret = -5;
1624 return ret;
1625 }
1626#endif
1627
1628
1629 /**
1630 * Bus related
1631 **/
1632 p->hif_func.hif_sync_ext(NUM_INT_EXT);
1633
1634 ret = p->hif_func.hif_read_reg(0x1000, &chipid);
1635 if (!ret) {
1636 wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1000 ...\n");
1637 release_bus(RELEASE_ONLY);
1638 /* EIO 5*/
1639 ret = -5;
1640 return ret;
1641 }
1642
1643 /**
1644 * Go...
1645 **/
1646
c5c77ba1
JK		 1647
1648 p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1649 if ((reg & (1ul << 10)) == (1ul << 10)) {
1650 reg &= ~(1ul << 10);
1651 p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1652 p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1653 }
1654
1655 reg |= (1ul << 10);
1656 ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1657 p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1658 release_bus(RELEASE_ONLY);
1659
1660 return (ret < 0) ? ret : 0;
1661}
1662
1663void wilc_wlan_global_reset(void)
1664{
1665
1666 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
8dfaafd6 1667
c5c77ba1
JK		 1668 acquire_bus(ACQUIRE_AND_WAKEUP);
1669 p->hif_func.hif_write_reg(WILC_GLB_RESET_0, 0x0);
1670 release_bus(RELEASE_ONLY);
1671}
1672static int wilc_wlan_stop(void)
1673{
1674 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1675 uint32_t reg = 0;
1676 int ret;
1677 uint8_t timeout = 10;
1678 /**
1679 * TODO: stop the firmware, need a re-download
1680 **/
1681 acquire_bus(ACQUIRE_AND_WAKEUP);
1682
1683 ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1684 if (!ret) {
1685 PRINT_ER("Error while reading reg\n");
1686 release_bus(RELEASE_ALLOW_SLEEP);
1687 return ret;
1688 }
1689
1690 reg &= ~(1 << 10);
1691
1692
1693 ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1694 if (!ret) {
1695 PRINT_ER("Error while writing reg\n");
1696 release_bus(RELEASE_ALLOW_SLEEP);
1697 return ret;
1698 }
1699
1700
1701
1702 do {
1703 ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1704 if (!ret) {
1705 PRINT_ER("Error while reading reg\n");
1706 release_bus(RELEASE_ALLOW_SLEEP);
1707 return ret;
1708 }
1709 PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg, timeout);
1710 /*Workaround to ensure that the chip is actually reset*/
1711 if ((reg & (1 << 10))) {
1712 PRINT_D(GENERIC_DBG, "Bit 10 not reset : Retry %d\n", timeout);
1713 reg &= ~(1 << 10);
1714 ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
1715 timeout--;
1716 } else {
1717 PRINT_D(GENERIC_DBG, "Bit 10 reset after : Retry %d\n", timeout);
1718 ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, &reg);
1719 if (!ret) {
1720 PRINT_ER("Error while reading reg\n");
1721 release_bus(RELEASE_ALLOW_SLEEP);
1722 return ret;
1723 }
1724 PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg, timeout);
1725 break;
1726 }
1727
1728 } while (timeout);
1729#if 1
1730/******************************************************************************/
1731/* This was add at Bug 4595 to reset the chip while maintaining the bus state */
1732/******************************************************************************/
1733 reg = ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 8) | (1 << 9) | (1 << 26) | (1 << 29) | (1 << 30) | (1 << 31)); /**/
1734 /**/
369f190a 1735 p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); /**/
c5c77ba1
JK		 1736 reg = ~(1 << 10); /**/
1737 /**/
1738 ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); /**/
1739/******************************************************************************/
1740#endif
1741
1742 release_bus(RELEASE_ALLOW_SLEEP);
1743
1744 return ret;
1745}
1746
1747static void wilc_wlan_cleanup(void)
1748{
1749 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1750 struct txq_entry_t *tqe;
1751 struct rxq_entry_t *rqe;
1752 uint32_t reg = 0;
1753 int ret;
1754
1755 p->quit = 1;
c5c77ba1
JK		 1756 do {
1757 tqe = wilc_wlan_txq_remove_from_head();
1758 if (tqe == NULL)
1759 break;
1760 if (tqe->tx_complete_func)
1761 tqe->tx_complete_func(tqe->priv, 0);
a18dd630 1762 kfree(tqe);
c5c77ba1
JK		 1763 } while (1);
1764
1765 do {
1766 rqe = wilc_wlan_rxq_remove();
1767 if (rqe == NULL)
1768 break;
1769#ifdef MEMORY_DYNAMIC
a18dd630 1770 kfree(tqe->buffer);
c5c77ba1 1771#endif
a18dd630 1772 kfree(rqe);
c5c77ba1
JK		 1773 } while (1);
1774
1775 /**
1776 * clean up buffer
1777 **/
1778
c5c77ba1 1779 #ifdef MEMORY_STATIC
a18dd630
GKH		 1780 kfree(p->rx_buffer);
1781 p->rx_buffer = NULL;
c5c77ba1 1782 #endif
a18dd630 1783 kfree(p->tx_buffer);
c5c77ba1
JK		 1784
1785 acquire_bus(ACQUIRE_AND_WAKEUP);
1786
1787
1788 ret = p->hif_func.hif_read_reg(WILC_GP_REG_0, &reg);
1789 if (!ret) {
1790 PRINT_ER("Error while reading reg\n");
1791 release_bus(RELEASE_ALLOW_SLEEP);
1792 }
1793 PRINT_ER("Writing ABORT reg\n");
1794 ret = p->hif_func.hif_write_reg(WILC_GP_REG_0, (reg | ABORT_INT));
1795 if (!ret) {
1796 PRINT_ER("Error while writing reg\n");
1797 release_bus(RELEASE_ALLOW_SLEEP);
1798 }
1799 release_bus(RELEASE_ALLOW_SLEEP);
1800 /**
1801 * io clean up
1802 **/
1803 p->hif_func.hif_deinit(NULL);
1804
1805}
1806
1807static int wilc_wlan_cfg_commit(int type, uint32_t drvHandler)
1808{
1809 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1810 wilc_cfg_frame_t *cfg = &p->cfg_frame;
1811 int total_len = p->cfg_frame_offset + 4 + DRIVER_HANDLER_SIZE;
1812 int seq_no = p->cfg_seq_no % 256;
4e4467fd 1813 int driver_handler = (u32)drvHandler;
c5c77ba1
JK		 1814
1815
1816 /**
1817 * Set up header
1818 **/
1819 if (type == WILC_CFG_SET) { /* Set */
1820 cfg->wid_header[0] = 'W';
1821 } else { /* Query */
1822 cfg->wid_header[0] = 'Q';
1823 }
1824 cfg->wid_header[1] = seq_no; /* sequence number */
1825 cfg->wid_header[2] = (uint8_t)total_len;
1826 cfg->wid_header[3] = (uint8_t)(total_len >> 8);
1827 cfg->wid_header[4] = (uint8_t)driver_handler;
1828 cfg->wid_header[5] = (uint8_t)(driver_handler >> 8);
1829 cfg->wid_header[6] = (uint8_t)(driver_handler >> 16);
1830 cfg->wid_header[7] = (uint8_t)(driver_handler >> 24);
1831 p->cfg_seq_no = seq_no;
1832
1833 /**
1834 * Add to TX queue
1835 **/
1836
1837 /*Edited by Amr - BugID_4720*/
1838 if (!wilc_wlan_txq_add_cfg_pkt(&cfg->wid_header[0], total_len))
1839 return -1;
1840
1841 return 0;
1842}
1843
1844static int wilc_wlan_cfg_set(int start, uint32_t wid, uint8_t *buffer, uint32_t buffer_size, int commit, uint32_t drvHandler)
1845{
1846 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1847 uint32_t offset;
1848 int ret_size;
1849
1850
1851 if (p->cfg_frame_in_use)
1852 return 0;
1853
1854 if (start)
1855 p->cfg_frame_offset = 0;
1856
1857 offset = p->cfg_frame_offset;
1858 ret_size = p->cif_func.cfg_wid_set(p->cfg_frame.frame, offset, (uint16_t)wid, buffer, buffer_size);
1859 offset += ret_size;
1860 p->cfg_frame_offset = offset;
1861
1862 if (commit) {
1863 PRINT_D(TX_DBG, "[WILC]PACKET Commit with sequence number %d\n", p->cfg_seq_no);
1864 PRINT_D(RX_DBG, "Processing cfg_set()\n");
1865 p->cfg_frame_in_use = 1;
1866
1867 /*Edited by Amr - BugID_4720*/
1868 if (wilc_wlan_cfg_commit(WILC_CFG_SET, drvHandler))
1869 ret_size = 0; /* BugID_5213 */
1870
1871 if (p->os_func.os_wait(p->cfg_wait, CFG_PKTS_TIMEOUT)) {
1872 PRINT_D(TX_DBG, "Set Timed Out\n");
1873 ret_size = 0;
1874 }
1875 p->cfg_frame_in_use = 0;
1876 p->cfg_frame_offset = 0;
1877 p->cfg_seq_no += 1;
1878
1879 }
1880
1881 return ret_size;
1882}
1883static int wilc_wlan_cfg_get(int start, uint32_t wid, int commit, uint32_t drvHandler)
1884{
1885 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1886 uint32_t offset;
1887 int ret_size;
1888
1889
1890 if (p->cfg_frame_in_use)
1891 return 0;
1892
1893 if (start)
1894 p->cfg_frame_offset = 0;
1895
1896 offset = p->cfg_frame_offset;
1897 ret_size = p->cif_func.cfg_wid_get(p->cfg_frame.frame, offset, (uint16_t)wid);
1898 offset += ret_size;
1899 p->cfg_frame_offset = offset;
1900
1901 if (commit) {
1902 p->cfg_frame_in_use = 1;
1903
1904 /*Edited by Amr - BugID_4720*/
1905 if (wilc_wlan_cfg_commit(WILC_CFG_QUERY, drvHandler))
1906 ret_size = 0; /* BugID_5213 */
1907
1908
1909 if (p->os_func.os_wait(p->cfg_wait, CFG_PKTS_TIMEOUT)) {
1910 PRINT_D(TX_DBG, "Get Timed Out\n");
1911 ret_size = 0;
1912 }
1913 PRINT_D(GENERIC_DBG, "[WILC]Get Response received\n");
1914 p->cfg_frame_in_use = 0;
1915 p->cfg_frame_offset = 0;
1916 p->cfg_seq_no += 1;
1917 }
1918
1919 return ret_size;
1920}
1921
1922static int wilc_wlan_cfg_get_val(uint32_t wid, uint8_t *buffer, uint32_t buffer_size)
1923{
1924 wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan;
1925 int ret;
1926
1927 ret = p->cif_func.cfg_wid_get_val((uint16_t)wid, buffer, buffer_size);
1928
1929 return ret;
1930}
1931
1932void wilc_bus_set_max_speed(void)
1933{
1934
1935 /* Increase bus speed to max possible. */
1936 g_wlan.hif_func.hif_set_max_bus_speed();
1937}
1938
1939void wilc_bus_set_default_speed(void)
1940{
1941
1942 /* Restore bus speed to default. */
1943 g_wlan.hif_func.hif_set_default_bus_speed();
1944}
1945uint32_t init_chip(void)
1946{
1947 uint32_t chipid;
1948 uint32_t reg, ret = 0;
1949
1950#if defined(PLAT_RK3026_TCHIP)
1951 acquire_bus(ACQUIRE_AND_WAKEUP); /* AMR : 0422 RK3026 Crash issue */
1952#else
1953 acquire_bus(ACQUIRE_ONLY);
1954#endif
1955
72ed4dc7 1956 chipid = wilc_get_chipid(true);
c5c77ba1
JK		 1957
1958
1959
1960 if ((chipid & 0xfff) != 0xa0) {
1961 /**
1962 * Avoid booting from boot ROM. Make sure that Drive IRQN [SDIO platform]
1963 * or SD_DAT3 [SPI platform] to ?1?
1964 **/
1965 /* Set cortus reset register to register control. */
1966 ret = g_wlan.hif_func.hif_read_reg(0x1118, &reg);
1967 if (!ret) {
1968 wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1118 ...\n");
1969 return ret;
1970 }
1971 reg |= (1 << 0);
1972 ret = g_wlan.hif_func.hif_write_reg(0x1118, reg);
1973 if (!ret) {
1974 wilc_debug(N_ERR, "[wilc start]: fail write reg 0x1118 ...\n");
1975 return ret;
1976 }
1977 /**
1978 * Write branch intruction to IRAM (0x71 trap) at location 0xFFFF0000
1979 * (Cortus map) or C0000 (AHB map).
1980 **/
1981 ret = g_wlan.hif_func.hif_write_reg(0xc0000, 0x71);
1982 if (!ret) {
1983 wilc_debug(N_ERR, "[wilc start]: fail write reg 0xc0000 ...\n");
1984 return ret;
1985 }
1986 }
1987
c5c77ba1
JK		 1988 release_bus(RELEASE_ONLY);
1989
1990 return ret;
1991
1992}
1993
1994uint32_t wilc_get_chipid(uint8_t update)
1995{
1996 static uint32_t chipid;
1997 /* SDIO can't read into global variables */
1998 /* Use this variable as a temp, then copy to the global */
1999 uint32_t tempchipid = 0;
2000 uint32_t rfrevid;
2001
2002 if (chipid == 0 || update != 0) {
2003 g_wlan.hif_func.hif_read_reg(0x1000, &tempchipid);
2004 g_wlan.hif_func.hif_read_reg(0x13f4, &rfrevid);
2005 if (!ISWILC1000(tempchipid)) {
2006 chipid = 0;
2007 goto _fail_;
2008 }
2009 if (tempchipid == 0x1002a0) {
2010 if (rfrevid == 0x1) { /* 1002A0 */
2011 } else { /* if (rfrevid == 0x2) */ /* 1002A1 */
2012 tempchipid = 0x1002a1;
2013 }
2014 } else if (tempchipid == 0x1002b0) {
2015 if (rfrevid == 3) { /* 1002B0 */
2016 } else if (rfrevid == 4) { /* 1002B1 */
2017 tempchipid = 0x1002b1;
2018 } else { /* if(rfrevid == 5) */ /* 1002B2 */
2019 tempchipid = 0x1002b2;
2020 }
2021 } else {
2022 }
2023
2024 chipid = tempchipid;
2025 }
2026_fail_:
2027 return chipid;
2028}
2029
2030#ifdef COMPLEMENT_BOOT
2031uint8_t core_11b_ready(void)
2032{
2033 uint32_t reg_val;
2034
2035 acquire_bus(ACQUIRE_ONLY);
2036 g_wlan.hif_func.hif_write_reg(0x16082c, 1);
2037 g_wlan.hif_func.hif_write_reg(0x161600, 0x90);
2038 g_wlan.hif_func.hif_read_reg(0x161600, &reg_val);
2039 release_bus(RELEASE_ONLY);
2040
2041 if (reg_val == 0x90)
2042 return 0;
2043 else
2044 return 1;
2045}
2046#endif
2047
2048int wilc_wlan_init(wilc_wlan_inp_t *inp, wilc_wlan_oup_t *oup)
2049{
2050
2051 int ret = 0;
2052
2053 PRINT_D(INIT_DBG, "Initializing WILC_Wlan ...\n");
2054
2055 memset((void *)&g_wlan, 0, sizeof(wilc_wlan_dev_t));
2056
2057 /**
2058 * store the input
2059 **/
2060 memcpy((void *)&g_wlan.os_func, (void *)&inp->os_func, sizeof(wilc_wlan_os_func_t));
2061 memcpy((void *)&g_wlan.io_func, (void *)&inp->io_func, sizeof(wilc_wlan_io_func_t));
2062 memcpy((void *)&g_wlan.net_func, (void *)&inp->net_func, sizeof(wilc_wlan_net_func_t));
2063 memcpy((void *)&g_wlan.indicate_func, (void *)&inp->indicate_func, sizeof(wilc_wlan_net_func_t));
2064 g_wlan.hif_lock = inp->os_context.hif_critical_section;
2065 g_wlan.txq_lock = inp->os_context.txq_critical_section;
2066
2067 /*Added by Amr - BugID_4720*/
2068 g_wlan.txq_add_to_head_lock = inp->os_context.txq_add_to_head_critical_section;
2069
2070 /*Added by Amr - BugID_4720*/
2071 g_wlan.txq_spinlock = inp->os_context.txq_spin_lock;
2072
2073 g_wlan.rxq_lock = inp->os_context.rxq_critical_section;
2074 g_wlan.txq_wait = inp->os_context.txq_wait_event;
2075 g_wlan.rxq_wait = inp->os_context.rxq_wait_event;
2076 g_wlan.cfg_wait = inp->os_context.cfg_wait_event;
2077 g_wlan.tx_buffer_size = inp->os_context.tx_buffer_size;
2078#if defined (MEMORY_STATIC)
2079 g_wlan.rx_buffer_size = inp->os_context.rx_buffer_size;
2080#endif
c5c77ba1
JK		 2081 /***
2082 * host interface init
2083 **/
2084#if defined(PLAT_RK3026_TCHIP) /* AMR : 0422 RK3026 Crash issue */
2085 if (!g_wilc_initialized) {
2086 custom_lock_bus(g_mac_open);
2087 custom_wakeup(g_mac_open);
2088 }
2089#endif
2090
2091 if ((inp->io_func.io_type & 0x1) == HIF_SDIO) {
2092 if (!hif_sdio.hif_init(inp, wilc_debug)) {
2093 /* EIO 5 */
2094 ret = -5;
2095 goto _fail_;
2096 }
2097 memcpy((void *)&g_wlan.hif_func, &hif_sdio, sizeof(wilc_hif_func_t));
2098 } else {
2099 if ((inp->io_func.io_type & 0x1) == HIF_SPI) {
2100 /**
2101 * TODO:
2102 **/
2103 if (!hif_spi.hif_init(inp, wilc_debug)) {
2104 /* EIO 5 */
2105 ret = -5;
2106 goto _fail_;
2107 }
2108 memcpy((void *)&g_wlan.hif_func, &hif_spi, sizeof(wilc_hif_func_t));
2109 } else {
2110 /* EIO 5 */
2111 ret = -5;
2112 goto _fail_;
2113 }
2114 }
2115
2116 /***
2117 * mac interface init
2118 **/
2119 if (!mac_cfg.cfg_init(wilc_debug)) {
2120 /* ENOBUFS 105 */
2121 ret = -105;
2122 goto _fail_;
2123 }
2124 memcpy((void *)&g_wlan.cif_func, &mac_cfg, sizeof(wilc_cfg_func_t));
2125
2126
2127 /**
2128 * alloc tx, rx buffer
2129 **/
b1413b60 2130 if (g_wlan.tx_buffer == NULL)
f019b9d9 2131 g_wlan.tx_buffer = kmalloc(g_wlan.tx_buffer_size, GFP_KERNEL);
7a8fd841 2132 PRINT_D(TX_DBG, "g_wlan.tx_buffer = %p\n", g_wlan.tx_buffer);
c5c77ba1 2133
b1413b60 2134 if (g_wlan.tx_buffer == NULL) {
c5c77ba1
JK		 2135 /* ENOBUFS 105 */
2136 ret = -105;
2137 PRINT_ER("Can't allocate Tx Buffer");
2138 goto _fail_;
2139 }
2140
2141/* rx_buffer is not used unless we activate USE_MEM STATIC which is not applicable, allocating such memory is useless*/
2142#if defined (MEMORY_STATIC)
b1413b60 2143 if (g_wlan.rx_buffer == NULL)
f019b9d9 2144 g_wlan.rx_buffer = kmalloc(g_wlan.rx_buffer_size, GFP_KERNEL);
7a8fd841 2145 PRINT_D(TX_DBG, "g_wlan.rx_buffer =%p\n", g_wlan.rx_buffer);
b1413b60 2146 if (g_wlan.rx_buffer == NULL) {
c5c77ba1
JK		 2147 /* ENOBUFS 105 */
2148 ret = -105;
2149 PRINT_ER("Can't allocate Rx Buffer");
2150 goto _fail_;
2151 }
2152#endif
2153
2154 /**
2155 * export functions
2156 **/
2157 oup->wlan_firmware_download = wilc_wlan_firmware_download;
2158 oup->wlan_start = wilc_wlan_start;
2159 oup->wlan_stop = wilc_wlan_stop;
2160 oup->wlan_add_to_tx_que = wilc_wlan_txq_add_net_pkt;
2161 oup->wlan_handle_tx_que = wilc_wlan_handle_txq;
2162 oup->wlan_handle_rx_que = wilc_wlan_handle_rxq;
c5c77ba1
JK		 2163 oup->wlan_handle_rx_isr = wilc_handle_isr;
2164 oup->wlan_cleanup = wilc_wlan_cleanup;
2165 oup->wlan_cfg_set = wilc_wlan_cfg_set;
2166 oup->wlan_cfg_get = wilc_wlan_cfg_get;
2167 oup->wlan_cfg_get_value = wilc_wlan_cfg_get_val;
2168
2169 /*Bug3959: transmitting mgmt frames received from host*/
2170 #if defined(WILC_AP_EXTERNAL_MLME) || defined(WILC_P2P)
2171 oup->wlan_add_mgmt_to_tx_que = wilc_wlan_txq_add_mgmt_pkt;
c5c77ba1
JK		 2172 #endif
2173
2174 if (!init_chip()) {
2175 /* EIO 5 */
2176 ret = -5;
2177 goto _fail_;
2178 }
2179#ifdef TCP_ACK_FILTER
2180 Init_TCP_tracking();
2181#endif
2182
2183#if defined(PLAT_RK3026_TCHIP) /* AMR : 0422 RK3026 Crash issue */
2184 if (!g_wilc_initialized)
2185 custom_unlock_bus(g_mac_open);
2186#endif
2187
2188 return 1;
2189
2190_fail_:
2191
c5c77ba1 2192 #ifdef MEMORY_STATIC
a18dd630
GKH		 2193 kfree(g_wlan.rx_buffer);
2194 g_wlan.rx_buffer = NULL;
c5c77ba1 2195 #endif
a18dd630
GKH		 2196 kfree(g_wlan.tx_buffer);
2197 g_wlan.tx_buffer = NULL;
c5c77ba1
JK		 2198
2199#if defined(PLAT_RK3026_TCHIP) /* AMR : 0422 RK3026 Crash issue */
2200 if (!g_wilc_initialized)
2201 custom_unlock_bus(g_mac_open);
2202#endif
2203
2204 return ret;
2205
2206}
2207
2208#define BIT31 (1 << 31)
72ed4dc7 2209u16 Set_machw_change_vir_if(bool bValue)
c5c77ba1 2210{
d85f5326 2211 u16 ret;
4e4467fd 2212 u32 reg;
c5c77ba1
JK		 2213
2214 /*Reset WILC_CHANGING_VIR_IF register to allow adding futrue keys to CE H/W*/
5e150b52 2215 mutex_lock((&g_wlan)->hif_lock);
c5c77ba1
JK		 2216 ret = (&g_wlan)->hif_func.hif_read_reg(WILC_CHANGING_VIR_IF, &reg);
2217 if (!ret) {
2218 PRINT_ER("Error while Reading reg WILC_CHANGING_VIR_IF\n");
2219 }
2220
78174ada 2221 if (bValue)
c5c77ba1 2222 reg |= (BIT31);
78174ada 2223 else
c5c77ba1 2224 reg &= ~(BIT31);
c5c77ba1
JK		 2225
2226 ret = (&g_wlan)->hif_func.hif_write_reg(WILC_CHANGING_VIR_IF, reg);
2227
2228 if (!ret) {
2229 PRINT_ER("Error while writing reg WILC_CHANGING_VIR_IF\n");
2230 }
5e150b52 2231 mutex_unlock((&g_wlan)->hif_lock);
c5c77ba1
JK		 2232
2233 return ret;
2234}
Linux kernel - Deliverables
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