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c5c77ba1 JK |
1 | /* ////////////////////////////////////////////////////////////////////////// */ |
2 | /* */ | |
3 | /* Copyright (c) Atmel Corporation. All rights reserved. */ | |
4 | /* */ | |
5 | /* Module Name: wilc_wlan.c */ | |
6 | /* */ | |
7 | /* */ | |
8 | /* //////////////////////////////////////////////////////////////////////////// */ | |
9 | ||
10 | #include "wilc_wlan_if.h" | |
11 | #include "wilc_wlan.h" | |
12 | #define INLINE static __inline | |
13 | ||
14 | /******************************************** | |
15 | * | |
16 | * Global | |
17 | * | |
18 | ********************************************/ | |
c5c77ba1 JK |
19 | extern wilc_hif_func_t hif_sdio; |
20 | extern wilc_hif_func_t hif_spi; | |
21 | extern wilc_cfg_func_t mac_cfg; | |
fbc2fe16 CL |
22 | extern void WILC_WFI_mgmt_rx(u8 *buff, u32 size); |
23 | u32 wilc_get_chipid(u8 update); | |
72ed4dc7 | 24 | u16 Set_machw_change_vir_if(bool bValue); |
c5c77ba1 | 25 | |
c5c77ba1 JK |
26 | |
27 | ||
28 | typedef struct { | |
29 | int quit; | |
30 | ||
31 | /** | |
32 | * input interface functions | |
33 | **/ | |
34 | wilc_wlan_os_func_t os_func; | |
35 | wilc_wlan_io_func_t io_func; | |
36 | wilc_wlan_net_func_t net_func; | |
37 | wilc_wlan_indicate_func_t indicate_func; | |
38 | ||
39 | /** | |
40 | * host interface functions | |
41 | **/ | |
42 | wilc_hif_func_t hif_func; | |
5e150b52 | 43 | struct mutex *hif_lock; |
c5c77ba1 JK |
44 | |
45 | /** | |
46 | * configuration interface functions | |
47 | **/ | |
48 | wilc_cfg_func_t cif_func; | |
49 | int cfg_frame_in_use; | |
50 | wilc_cfg_frame_t cfg_frame; | |
fbc2fe16 | 51 | u32 cfg_frame_offset; |
c5c77ba1 JK |
52 | int cfg_seq_no; |
53 | void *cfg_wait; | |
54 | ||
55 | /** | |
56 | * RX buffer | |
57 | **/ | |
58 | #ifdef MEMORY_STATIC | |
fbc2fe16 | 59 | u32 rx_buffer_size; |
51e825f7 | 60 | u8 *rx_buffer; |
fbc2fe16 | 61 | u32 rx_buffer_offset; |
c5c77ba1 JK |
62 | #endif |
63 | /** | |
64 | * TX buffer | |
65 | **/ | |
fbc2fe16 | 66 | u32 tx_buffer_size; |
51e825f7 | 67 | u8 *tx_buffer; |
fbc2fe16 | 68 | u32 tx_buffer_offset; |
c5c77ba1 JK |
69 | |
70 | /** | |
71 | * TX queue | |
72 | **/ | |
73 | void *txq_lock; | |
74 | ||
75 | /*Added by Amr - BugID_4720*/ | |
8990d856 | 76 | struct semaphore *txq_add_to_head_lock; |
c5c77ba1 JK |
77 | void *txq_spinlock; |
78 | unsigned long txq_spinlock_flags; | |
79 | ||
80 | struct txq_entry_t *txq_head; | |
81 | struct txq_entry_t *txq_tail; | |
82 | int txq_entries; | |
83 | void *txq_wait; | |
84 | int txq_exit; | |
85 | ||
86 | /** | |
87 | * RX queue | |
88 | **/ | |
5e150b52 | 89 | struct mutex *rxq_lock; |
c5c77ba1 JK |
90 | struct rxq_entry_t *rxq_head; |
91 | struct rxq_entry_t *rxq_tail; | |
92 | int rxq_entries; | |
93 | void *rxq_wait; | |
94 | int rxq_exit; | |
95 | ||
96 | ||
97 | } wilc_wlan_dev_t; | |
98 | ||
99 | static wilc_wlan_dev_t g_wlan; | |
100 | ||
101 | INLINE void chip_allow_sleep(void); | |
102 | INLINE void chip_wakeup(void); | |
103 | /******************************************** | |
104 | * | |
105 | * Debug | |
106 | * | |
107 | ********************************************/ | |
108 | ||
fbc2fe16 | 109 | static u32 dbgflag = N_INIT | N_ERR | N_INTR | N_TXQ | N_RXQ; |
c5c77ba1 | 110 | |
fbc2fe16 | 111 | static void wilc_debug(u32 flag, char *fmt, ...) |
c5c77ba1 JK |
112 | { |
113 | char buf[256]; | |
114 | va_list args; | |
c5c77ba1 JK |
115 | |
116 | if (flag & dbgflag) { | |
117 | va_start(args, fmt); | |
81053222 | 118 | vsprintf(buf, fmt, args); |
c5c77ba1 JK |
119 | va_end(args); |
120 | ||
121 | if (g_wlan.os_func.os_debug) | |
122 | g_wlan.os_func.os_debug(buf); | |
123 | } | |
c5c77ba1 JK |
124 | } |
125 | ||
126 | static CHIP_PS_STATE_T genuChipPSstate = CHIP_WAKEDUP; | |
127 | ||
128 | /*BugID_5213*/ | |
129 | /*acquire_bus() and release_bus() are made INLINE functions*/ | |
130 | /*as a temporary workaround to fix a problem of receiving*/ | |
131 | /*unknown interrupt from FW*/ | |
132 | INLINE void acquire_bus(BUS_ACQUIRE_T acquire) | |
133 | { | |
134 | ||
5e150b52 | 135 | mutex_lock(g_wlan.hif_lock); |
c5c77ba1 JK |
136 | #ifndef WILC_OPTIMIZE_SLEEP_INT |
137 | if (genuChipPSstate != CHIP_WAKEDUP) | |
138 | #endif | |
139 | { | |
140 | if (acquire == ACQUIRE_AND_WAKEUP) | |
141 | chip_wakeup(); | |
142 | } | |
143 | ||
144 | } | |
145 | INLINE void release_bus(BUS_RELEASE_T release) | |
146 | { | |
147 | #ifdef WILC_OPTIMIZE_SLEEP_INT | |
148 | if (release == RELEASE_ALLOW_SLEEP) | |
149 | chip_allow_sleep(); | |
150 | #endif | |
5e150b52 | 151 | mutex_unlock(g_wlan.hif_lock); |
c5c77ba1 JK |
152 | } |
153 | /******************************************** | |
154 | * | |
155 | * Queue | |
156 | * | |
157 | ********************************************/ | |
158 | ||
159 | static void wilc_wlan_txq_remove(struct txq_entry_t *tqe) | |
160 | { | |
161 | ||
162 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
163 | /* unsigned long flags; */ | |
c5c77ba1 JK |
164 | if (tqe == p->txq_head) { |
165 | ||
166 | p->txq_head = tqe->next; | |
167 | if (p->txq_head) | |
168 | p->txq_head->prev = NULL; | |
169 | ||
170 | ||
171 | } else if (tqe == p->txq_tail) { | |
172 | p->txq_tail = (tqe->prev); | |
173 | if (p->txq_tail) | |
174 | p->txq_tail->next = NULL; | |
175 | } else { | |
176 | tqe->prev->next = tqe->next; | |
177 | tqe->next->prev = tqe->prev; | |
178 | } | |
179 | p->txq_entries -= 1; | |
c5c77ba1 JK |
180 | |
181 | } | |
182 | ||
183 | static struct txq_entry_t *wilc_wlan_txq_remove_from_head(void) | |
184 | { | |
185 | struct txq_entry_t *tqe; | |
186 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
187 | unsigned long flags; | |
8dfaafd6 | 188 | |
17c4d5d5 | 189 | spin_lock_irqsave(p->txq_spinlock, flags); |
c5c77ba1 | 190 | if (p->txq_head) { |
c5c77ba1 JK |
191 | tqe = p->txq_head; |
192 | p->txq_head = tqe->next; | |
193 | if (p->txq_head) { | |
194 | p->txq_head->prev = NULL; | |
195 | } | |
196 | p->txq_entries -= 1; | |
197 | ||
198 | /*Added by Amr - BugID_4720*/ | |
199 | ||
200 | ||
c5c77ba1 JK |
201 | |
202 | } else { | |
203 | tqe = NULL; | |
204 | } | |
17c4d5d5 | 205 | spin_unlock_irqrestore(p->txq_spinlock, flags); |
c5c77ba1 JK |
206 | return tqe; |
207 | } | |
208 | ||
209 | static void wilc_wlan_txq_add_to_tail(struct txq_entry_t *tqe) | |
210 | { | |
211 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
212 | unsigned long flags; | |
213 | /*Added by Amr - BugID_4720*/ | |
17c4d5d5 | 214 | spin_lock_irqsave(p->txq_spinlock, flags); |
c5c77ba1 | 215 | |
c5c77ba1 JK |
216 | if (p->txq_head == NULL) { |
217 | tqe->next = NULL; | |
218 | tqe->prev = NULL; | |
219 | p->txq_head = tqe; | |
220 | p->txq_tail = tqe; | |
c5c77ba1 JK |
221 | } else { |
222 | tqe->next = NULL; | |
223 | tqe->prev = p->txq_tail; | |
224 | p->txq_tail->next = tqe; | |
225 | p->txq_tail = tqe; | |
226 | } | |
227 | p->txq_entries += 1; | |
228 | PRINT_D(TX_DBG, "Number of entries in TxQ = %d\n", p->txq_entries); | |
c5c77ba1 JK |
229 | |
230 | /*Added by Amr - BugID_4720*/ | |
17c4d5d5 | 231 | spin_unlock_irqrestore(p->txq_spinlock, flags); |
c5c77ba1 JK |
232 | |
233 | /** | |
234 | * wake up TX queue | |
235 | **/ | |
236 | PRINT_D(TX_DBG, "Wake the txq_handling\n"); | |
237 | ||
8990d856 | 238 | up(p->txq_wait); |
c5c77ba1 JK |
239 | } |
240 | ||
241 | static int wilc_wlan_txq_add_to_head(struct txq_entry_t *tqe) | |
242 | { | |
243 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
244 | unsigned long flags; | |
245 | /*Added by Amr - BugID_4720*/ | |
246 | if (p->os_func.os_wait(p->txq_add_to_head_lock, CFG_PKTS_TIMEOUT)) | |
247 | return -1; | |
248 | ||
17c4d5d5 | 249 | spin_lock_irqsave(p->txq_spinlock, flags); |
c5c77ba1 | 250 | |
c5c77ba1 JK |
251 | if (p->txq_head == NULL) { |
252 | tqe->next = NULL; | |
253 | tqe->prev = NULL; | |
254 | p->txq_head = tqe; | |
255 | p->txq_tail = tqe; | |
256 | } else { | |
257 | tqe->next = p->txq_head; | |
258 | tqe->prev = NULL; | |
259 | p->txq_head->prev = tqe; | |
260 | p->txq_head = tqe; | |
261 | } | |
262 | p->txq_entries += 1; | |
263 | PRINT_D(TX_DBG, "Number of entries in TxQ = %d\n", p->txq_entries); | |
c5c77ba1 JK |
264 | |
265 | /*Added by Amr - BugID_4720*/ | |
17c4d5d5 | 266 | spin_unlock_irqrestore(p->txq_spinlock, flags); |
8990d856 | 267 | up(p->txq_add_to_head_lock); |
c5c77ba1 JK |
268 | |
269 | ||
270 | /** | |
271 | * wake up TX queue | |
272 | **/ | |
8990d856 | 273 | up(p->txq_wait); |
c5c77ba1 | 274 | PRINT_D(TX_DBG, "Wake up the txq_handler\n"); |
c5c77ba1 JK |
275 | |
276 | /*Added by Amr - BugID_4720*/ | |
277 | return 0; | |
278 | ||
279 | } | |
280 | ||
fbc2fe16 | 281 | u32 Statisitcs_totalAcks = 0, Statisitcs_DroppedAcks = 0; |
c5c77ba1 JK |
282 | |
283 | #ifdef TCP_ACK_FILTER | |
284 | struct Ack_session_info; | |
eeb1c062 | 285 | struct Ack_session_info { |
fbc2fe16 CL |
286 | u32 Ack_seq_num; |
287 | u32 Bigger_Ack_num; | |
ec53adfe CL |
288 | u16 src_port; |
289 | u16 dst_port; | |
290 | u16 status; | |
eeb1c062 | 291 | }; |
c5c77ba1 JK |
292 | |
293 | typedef struct { | |
fbc2fe16 CL |
294 | u32 ack_num; |
295 | u32 Session_index; | |
c5c77ba1 | 296 | struct txq_entry_t *txqe; |
c5c77ba1 JK |
297 | } Pending_Acks_info_t /*Ack_info_t*/; |
298 | ||
299 | ||
300 | ||
301 | ||
302 | struct Ack_session_info *Free_head; | |
303 | struct Ack_session_info *Alloc_head; | |
304 | ||
305 | #define TCP_FIN_MASK (1 << 0) | |
306 | #define TCP_SYN_MASK (1 << 1) | |
307 | #define TCP_Ack_MASK (1 << 4) | |
308 | #define NOT_TCP_ACK (-1) | |
309 | ||
310 | #define MAX_TCP_SESSION 25 | |
311 | #define MAX_PENDING_ACKS 256 | |
eeb1c062 | 312 | struct Ack_session_info Acks_keep_track_info[2 * MAX_TCP_SESSION]; |
c5c77ba1 JK |
313 | Pending_Acks_info_t Pending_Acks_info[MAX_PENDING_ACKS]; |
314 | ||
fbc2fe16 CL |
315 | u32 PendingAcks_arrBase; |
316 | u32 Opened_TCP_session; | |
317 | u32 Pending_Acks; | |
c5c77ba1 JK |
318 | |
319 | ||
320 | ||
321 | static __inline int Init_TCP_tracking(void) | |
322 | { | |
323 | ||
c5c77ba1 JK |
324 | return 0; |
325 | ||
326 | } | |
fbc2fe16 | 327 | static __inline int add_TCP_track_session(u32 src_prt, u32 dst_prt, u32 seq) |
c5c77ba1 JK |
328 | { |
329 | Acks_keep_track_info[Opened_TCP_session].Ack_seq_num = seq; | |
330 | Acks_keep_track_info[Opened_TCP_session].Bigger_Ack_num = 0; | |
331 | Acks_keep_track_info[Opened_TCP_session].src_port = src_prt; | |
332 | Acks_keep_track_info[Opened_TCP_session].dst_port = dst_prt; | |
333 | Opened_TCP_session++; | |
334 | ||
335 | PRINT_D(TCP_ENH, "TCP Session %d to Ack %d\n", Opened_TCP_session, seq); | |
336 | return 0; | |
337 | } | |
338 | ||
fbc2fe16 | 339 | static __inline int Update_TCP_track_session(u32 index, u32 Ack) |
c5c77ba1 JK |
340 | { |
341 | ||
342 | if (Ack > Acks_keep_track_info[index].Bigger_Ack_num) { | |
343 | Acks_keep_track_info[index].Bigger_Ack_num = Ack; | |
344 | } | |
345 | return 0; | |
346 | ||
347 | } | |
fbc2fe16 | 348 | static __inline int add_TCP_Pending_Ack(u32 Ack, u32 Session_index, struct txq_entry_t *txqe) |
c5c77ba1 JK |
349 | { |
350 | Statisitcs_totalAcks++; | |
351 | if (Pending_Acks < MAX_PENDING_ACKS) { | |
352 | Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].ack_num = Ack; | |
353 | Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].txqe = txqe; | |
354 | Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].Session_index = Session_index; | |
355 | txqe->tcp_PendingAck_index = PendingAcks_arrBase + Pending_Acks; | |
356 | Pending_Acks++; | |
357 | ||
358 | } else { | |
359 | ||
360 | } | |
361 | return 0; | |
362 | } | |
363 | static __inline int remove_TCP_related(void) | |
364 | { | |
365 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
366 | unsigned long flags; | |
8dfaafd6 | 367 | |
17c4d5d5 | 368 | spin_lock_irqsave(p->txq_spinlock, flags); |
c5c77ba1 | 369 | |
17c4d5d5 | 370 | spin_unlock_irqrestore(p->txq_spinlock, flags); |
c5c77ba1 JK |
371 | return 0; |
372 | } | |
373 | ||
374 | static __inline int tcp_process(struct txq_entry_t *tqe) | |
375 | { | |
376 | int ret; | |
51e825f7 CL |
377 | u8 *eth_hdr_ptr; |
378 | u8 *buffer = tqe->buffer; | |
c5c77ba1 JK |
379 | unsigned short h_proto; |
380 | int i; | |
381 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
382 | unsigned long flags; | |
8dfaafd6 | 383 | |
17c4d5d5 | 384 | spin_lock_irqsave(p->txq_spinlock, flags); |
c5c77ba1 JK |
385 | |
386 | eth_hdr_ptr = &buffer[0]; | |
387 | h_proto = ntohs(*((unsigned short *)ð_hdr_ptr[12])); | |
388 | if (h_proto == 0x0800) { /* IP */ | |
51e825f7 CL |
389 | u8 *ip_hdr_ptr; |
390 | u8 protocol; | |
c5c77ba1 JK |
391 | |
392 | ip_hdr_ptr = &buffer[ETHERNET_HDR_LEN]; | |
393 | protocol = ip_hdr_ptr[9]; | |
394 | ||
395 | ||
396 | if (protocol == 0x06) { | |
51e825f7 | 397 | u8 *tcp_hdr_ptr; |
fbc2fe16 | 398 | u32 IHL, Total_Length, Data_offset; |
8dfaafd6 | 399 | |
c5c77ba1 JK |
400 | tcp_hdr_ptr = &ip_hdr_ptr[IP_HDR_LEN]; |
401 | IHL = (ip_hdr_ptr[0] & 0xf) << 2; | |
fbc2fe16 CL |
402 | Total_Length = (((u32)ip_hdr_ptr[2]) << 8) + ((u32)ip_hdr_ptr[3]); |
403 | Data_offset = (((u32)tcp_hdr_ptr[12] & 0xf0) >> 2); | |
c5c77ba1 | 404 | if (Total_Length == (IHL + Data_offset)) { /*we want to recognize the clear Acks(packet only carry Ack infos not with data) so data size must be equal zero*/ |
fbc2fe16 | 405 | u32 seq_no, Ack_no; |
8dfaafd6 | 406 | |
fbc2fe16 | 407 | seq_no = (((u32)tcp_hdr_ptr[4]) << 24) + (((u32)tcp_hdr_ptr[5]) << 16) + (((u32)tcp_hdr_ptr[6]) << 8) + ((u32)tcp_hdr_ptr[7]); |
c5c77ba1 | 408 | |
fbc2fe16 | 409 | Ack_no = (((u32)tcp_hdr_ptr[8]) << 24) + (((u32)tcp_hdr_ptr[9]) << 16) + (((u32)tcp_hdr_ptr[10]) << 8) + ((u32)tcp_hdr_ptr[11]); |
c5c77ba1 JK |
410 | |
411 | ||
412 | for (i = 0; i < Opened_TCP_session; i++) { | |
413 | if (Acks_keep_track_info[i].Ack_seq_num == seq_no) { | |
414 | Update_TCP_track_session(i, Ack_no); | |
415 | break; | |
416 | } | |
417 | } | |
418 | if (i == Opened_TCP_session) { | |
419 | add_TCP_track_session(0, 0, seq_no); | |
420 | } | |
421 | add_TCP_Pending_Ack(Ack_no, i, tqe); | |
422 | ||
423 | ||
424 | } | |
425 | ||
426 | } else { | |
427 | ret = 0; | |
428 | } | |
429 | } else { | |
430 | ret = 0; | |
431 | } | |
17c4d5d5 | 432 | spin_unlock_irqrestore(p->txq_spinlock, flags); |
c5c77ba1 JK |
433 | return ret; |
434 | } | |
435 | ||
436 | ||
437 | static int wilc_wlan_txq_filter_dup_tcp_ack(void) | |
438 | { | |
439 | ||
fbc2fe16 CL |
440 | u32 i = 0; |
441 | u32 Dropped = 0; | |
c5c77ba1 JK |
442 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; |
443 | ||
17c4d5d5 | 444 | spin_lock_irqsave(p->txq_spinlock, p->txq_spinlock_flags); |
c5c77ba1 JK |
445 | for (i = PendingAcks_arrBase; i < (PendingAcks_arrBase + Pending_Acks); i++) { |
446 | if (Pending_Acks_info[i].ack_num < Acks_keep_track_info[Pending_Acks_info[i].Session_index].Bigger_Ack_num) { | |
447 | struct txq_entry_t *tqe; | |
8dfaafd6 | 448 | |
17aacd43 | 449 | PRINT_D(TCP_ENH, "DROP ACK: %u\n", Pending_Acks_info[i].ack_num); |
c5c77ba1 JK |
450 | tqe = Pending_Acks_info[i].txqe; |
451 | if (tqe) { | |
452 | wilc_wlan_txq_remove(tqe); | |
453 | Statisitcs_DroppedAcks++; | |
454 | tqe->status = 1; /* mark the packet send */ | |
455 | if (tqe->tx_complete_func) | |
456 | tqe->tx_complete_func(tqe->priv, tqe->status); | |
a18dd630 | 457 | kfree(tqe); |
c5c77ba1 | 458 | Dropped++; |
c5c77ba1 JK |
459 | } |
460 | } | |
461 | } | |
462 | Pending_Acks = 0; | |
463 | Opened_TCP_session = 0; | |
464 | ||
78174ada | 465 | if (PendingAcks_arrBase == 0) |
c5c77ba1 | 466 | PendingAcks_arrBase = MAX_TCP_SESSION; |
78174ada | 467 | else |
c5c77ba1 | 468 | PendingAcks_arrBase = 0; |
c5c77ba1 JK |
469 | |
470 | ||
17c4d5d5 | 471 | spin_unlock_irqrestore(p->txq_spinlock, p->txq_spinlock_flags); |
c5c77ba1 JK |
472 | |
473 | while (Dropped > 0) { | |
474 | /*consume the semaphore count of the removed packet*/ | |
475 | p->os_func.os_wait(p->txq_wait, 1); | |
476 | Dropped--; | |
477 | } | |
478 | ||
479 | return 1; | |
480 | } | |
481 | #endif | |
482 | ||
483 | #ifdef TCP_ENHANCEMENTS | |
72ed4dc7 | 484 | bool EnableTCPAckFilter = false; |
c5c77ba1 | 485 | |
72ed4dc7 | 486 | void Enable_TCP_ACK_Filter(bool value) |
c5c77ba1 JK |
487 | { |
488 | EnableTCPAckFilter = value; | |
489 | } | |
490 | ||
72ed4dc7 | 491 | bool is_TCP_ACK_Filter_Enabled(void) |
c5c77ba1 JK |
492 | { |
493 | return EnableTCPAckFilter; | |
494 | } | |
495 | #endif | |
496 | ||
fbc2fe16 | 497 | static int wilc_wlan_txq_add_cfg_pkt(u8 *buffer, u32 buffer_size) |
c5c77ba1 JK |
498 | { |
499 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
500 | struct txq_entry_t *tqe; | |
501 | ||
502 | PRINT_D(TX_DBG, "Adding config packet ...\n"); | |
503 | if (p->quit) { | |
504 | PRINT_D(TX_DBG, "Return due to clear function\n"); | |
8990d856 | 505 | up(p->cfg_wait); |
c5c77ba1 JK |
506 | return 0; |
507 | } | |
508 | ||
47c632d8 | 509 | tqe = kmalloc(sizeof(struct txq_entry_t), GFP_ATOMIC); |
c5c77ba1 JK |
510 | if (tqe == NULL) { |
511 | PRINT_ER("Failed to allocate memory\n"); | |
512 | return 0; | |
513 | } | |
514 | ||
515 | tqe->type = WILC_CFG_PKT; | |
516 | tqe->buffer = buffer; | |
517 | tqe->buffer_size = buffer_size; | |
518 | tqe->tx_complete_func = NULL; | |
519 | tqe->priv = NULL; | |
520 | #ifdef TCP_ACK_FILTER | |
521 | tqe->tcp_PendingAck_index = NOT_TCP_ACK; | |
522 | #endif | |
523 | /** | |
524 | * Configuration packet always at the front | |
525 | **/ | |
526 | PRINT_D(TX_DBG, "Adding the config packet at the Queue tail\n"); | |
527 | ||
528 | /*Edited by Amr - BugID_4720*/ | |
529 | if (wilc_wlan_txq_add_to_head(tqe)) | |
530 | return 0; | |
c5c77ba1 JK |
531 | return 1; |
532 | } | |
533 | ||
fbc2fe16 | 534 | static int wilc_wlan_txq_add_net_pkt(void *priv, u8 *buffer, u32 buffer_size, wilc_tx_complete_func_t func) |
c5c77ba1 JK |
535 | { |
536 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
537 | struct txq_entry_t *tqe; | |
538 | ||
539 | if (p->quit) | |
540 | return 0; | |
541 | ||
47c632d8 | 542 | tqe = kmalloc(sizeof(struct txq_entry_t), GFP_ATOMIC); |
c5c77ba1 JK |
543 | |
544 | if (tqe == NULL) | |
545 | return 0; | |
546 | tqe->type = WILC_NET_PKT; | |
547 | tqe->buffer = buffer; | |
548 | tqe->buffer_size = buffer_size; | |
549 | tqe->tx_complete_func = func; | |
550 | tqe->priv = priv; | |
551 | ||
552 | PRINT_D(TX_DBG, "Adding mgmt packet at the Queue tail\n"); | |
553 | #ifdef TCP_ACK_FILTER | |
554 | tqe->tcp_PendingAck_index = NOT_TCP_ACK; | |
555 | #ifdef TCP_ENHANCEMENTS | |
5a66bf20 | 556 | if (is_TCP_ACK_Filter_Enabled()) |
c5c77ba1 JK |
557 | #endif |
558 | tcp_process(tqe); | |
559 | #endif | |
560 | wilc_wlan_txq_add_to_tail(tqe); | |
561 | /*return number of itemes in the queue*/ | |
562 | return p->txq_entries; | |
563 | } | |
564 | /*Bug3959: transmitting mgmt frames received from host*/ | |
565 | #if defined(WILC_AP_EXTERNAL_MLME) || defined(WILC_P2P) | |
fbc2fe16 | 566 | int wilc_wlan_txq_add_mgmt_pkt(void *priv, u8 *buffer, u32 buffer_size, wilc_tx_complete_func_t func) |
c5c77ba1 JK |
567 | { |
568 | ||
569 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
570 | struct txq_entry_t *tqe; | |
571 | ||
572 | if (p->quit) | |
573 | return 0; | |
574 | ||
47c632d8 | 575 | tqe = kmalloc(sizeof(struct txq_entry_t), GFP_KERNEL); |
c5c77ba1 JK |
576 | |
577 | if (tqe == NULL) | |
578 | return 0; | |
579 | tqe->type = WILC_MGMT_PKT; | |
580 | tqe->buffer = buffer; | |
581 | tqe->buffer_size = buffer_size; | |
582 | tqe->tx_complete_func = func; | |
583 | tqe->priv = priv; | |
584 | #ifdef TCP_ACK_FILTER | |
585 | tqe->tcp_PendingAck_index = NOT_TCP_ACK; | |
586 | #endif | |
587 | PRINT_D(TX_DBG, "Adding Network packet at the Queue tail\n"); | |
588 | wilc_wlan_txq_add_to_tail(tqe); | |
589 | return 1; | |
590 | } | |
c5c77ba1 JK |
591 | #endif /*WILC_AP_EXTERNAL_MLME*/ |
592 | static struct txq_entry_t *wilc_wlan_txq_get_first(void) | |
593 | { | |
594 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
595 | struct txq_entry_t *tqe; | |
596 | unsigned long flags; | |
597 | ||
598 | /*Added by Amr - BugID_4720*/ | |
17c4d5d5 | 599 | spin_lock_irqsave(p->txq_spinlock, flags); |
c5c77ba1 | 600 | |
c5c77ba1 JK |
601 | tqe = p->txq_head; |
602 | ||
603 | /*Added by Amr - BugID_4720*/ | |
17c4d5d5 | 604 | spin_unlock_irqrestore(p->txq_spinlock, flags); |
c5c77ba1 | 605 | |
c5c77ba1 JK |
606 | |
607 | return tqe; | |
608 | } | |
609 | ||
610 | static struct txq_entry_t *wilc_wlan_txq_get_next(struct txq_entry_t *tqe) | |
611 | { | |
612 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
613 | unsigned long flags; | |
614 | /*Added by Amr - BugID_4720*/ | |
17c4d5d5 | 615 | spin_lock_irqsave(p->txq_spinlock, flags); |
c5c77ba1 | 616 | |
c5c77ba1 | 617 | tqe = tqe->next; |
c5c77ba1 | 618 | /*Added by Amr - BugID_4720*/ |
17c4d5d5 | 619 | spin_unlock_irqrestore(p->txq_spinlock, flags); |
c5c77ba1 | 620 | |
c5c77ba1 JK |
621 | |
622 | return tqe; | |
623 | } | |
624 | ||
625 | static int wilc_wlan_rxq_add(struct rxq_entry_t *rqe) | |
626 | { | |
627 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
628 | ||
629 | if (p->quit) | |
630 | return 0; | |
631 | ||
5e150b52 | 632 | mutex_lock(p->rxq_lock); |
c5c77ba1 JK |
633 | if (p->rxq_head == NULL) { |
634 | PRINT_D(RX_DBG, "Add to Queue head\n"); | |
635 | rqe->next = NULL; | |
636 | p->rxq_head = rqe; | |
637 | p->rxq_tail = rqe; | |
638 | } else { | |
639 | PRINT_D(RX_DBG, "Add to Queue tail\n"); | |
640 | p->rxq_tail->next = rqe; | |
641 | rqe->next = NULL; | |
642 | p->rxq_tail = rqe; | |
643 | } | |
644 | p->rxq_entries += 1; | |
645 | PRINT_D(RX_DBG, "Number of queue entries: %d\n", p->rxq_entries); | |
5e150b52 | 646 | mutex_unlock(p->rxq_lock); |
c5c77ba1 JK |
647 | return p->rxq_entries; |
648 | } | |
649 | ||
650 | static struct rxq_entry_t *wilc_wlan_rxq_remove(void) | |
651 | { | |
652 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
653 | ||
654 | PRINT_D(RX_DBG, "Getting rxQ element\n"); | |
655 | if (p->rxq_head) { | |
656 | struct rxq_entry_t *rqe; | |
657 | ||
5e150b52 | 658 | mutex_lock(p->rxq_lock); |
c5c77ba1 JK |
659 | rqe = p->rxq_head; |
660 | p->rxq_head = p->rxq_head->next; | |
661 | p->rxq_entries -= 1; | |
662 | PRINT_D(RX_DBG, "RXQ entries decreased\n"); | |
5e150b52 | 663 | mutex_unlock(p->rxq_lock); |
c5c77ba1 JK |
664 | return rqe; |
665 | } | |
666 | PRINT_D(RX_DBG, "Nothing to get from Q\n"); | |
667 | return NULL; | |
668 | } | |
669 | ||
670 | ||
671 | /******************************************** | |
672 | * | |
673 | * Power Save handle functions | |
674 | * | |
675 | ********************************************/ | |
676 | ||
677 | ||
678 | ||
679 | #ifdef WILC_OPTIMIZE_SLEEP_INT | |
680 | ||
681 | INLINE void chip_allow_sleep(void) | |
682 | { | |
fbc2fe16 | 683 | u32 reg = 0; |
c5c77ba1 JK |
684 | |
685 | /* Clear bit 1 */ | |
686 | g_wlan.hif_func.hif_read_reg(0xf0, ®); | |
687 | ||
688 | g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0)); | |
689 | } | |
690 | ||
691 | INLINE void chip_wakeup(void) | |
692 | { | |
fbc2fe16 CL |
693 | u32 reg, clk_status_reg, trials = 0; |
694 | u32 sleep_time; | |
c5c77ba1 JK |
695 | |
696 | if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) { | |
697 | do { | |
698 | g_wlan.hif_func.hif_read_reg(1, ®); | |
699 | /* Set bit 1 */ | |
700 | g_wlan.hif_func.hif_write_reg(1, reg | (1 << 1)); | |
701 | ||
702 | /* Clear bit 1*/ | |
703 | g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1)); | |
704 | ||
705 | do { | |
706 | /* Wait for the chip to stabilize*/ | |
80e29c7a | 707 | usleep_range(2 * 1000, 2 * 1000); |
c5c77ba1 JK |
708 | /* Make sure chip is awake. This is an extra step that can be removed */ |
709 | /* later to avoid the bus access overhead */ | |
72ed4dc7 | 710 | if ((wilc_get_chipid(true) == 0)) { |
c5c77ba1 JK |
711 | wilc_debug(N_ERR, "Couldn't read chip id. Wake up failed\n"); |
712 | } | |
72ed4dc7 | 713 | } while ((wilc_get_chipid(true) == 0) && ((++trials % 3) == 0)); |
c5c77ba1 | 714 | |
72ed4dc7 | 715 | } while (wilc_get_chipid(true) == 0); |
c5c77ba1 JK |
716 | } else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO) { |
717 | g_wlan.hif_func.hif_read_reg(0xf0, ®); | |
718 | do { | |
719 | /* Set bit 1 */ | |
720 | g_wlan.hif_func.hif_write_reg(0xf0, reg | (1 << 0)); | |
721 | ||
722 | /* Check the clock status */ | |
723 | g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg); | |
724 | ||
725 | /* in case of clocks off, wait 2ms, and check it again. */ | |
726 | /* if still off, wait for another 2ms, for a total wait of 6ms. */ | |
727 | /* If still off, redo the wake up sequence */ | |
728 | while (((clk_status_reg & 0x1) == 0) && (((++trials) % 3) == 0)) { | |
729 | /* Wait for the chip to stabilize*/ | |
80e29c7a | 730 | usleep_range(2 * 1000, 2 * 1000); |
c5c77ba1 JK |
731 | |
732 | /* Make sure chip is awake. This is an extra step that can be removed */ | |
733 | /* later to avoid the bus access overhead */ | |
734 | g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg); | |
735 | ||
736 | if ((clk_status_reg & 0x1) == 0) { | |
737 | wilc_debug(N_ERR, "clocks still OFF. Wake up failed\n"); | |
738 | } | |
739 | } | |
740 | /* in case of failure, Reset the wakeup bit to introduce a new edge on the next loop */ | |
741 | if ((clk_status_reg & 0x1) == 0) { | |
742 | /* Reset bit 0 */ | |
743 | g_wlan.hif_func.hif_write_reg(0xf0, reg & (~(1 << 0))); | |
744 | } | |
745 | } while ((clk_status_reg & 0x1) == 0); | |
746 | } | |
747 | ||
748 | ||
749 | if (genuChipPSstate == CHIP_SLEEPING_MANUAL) { | |
750 | g_wlan.hif_func.hif_read_reg(0x1C0C, ®); | |
751 | reg &= ~(1 << 0); | |
752 | g_wlan.hif_func.hif_write_reg(0x1C0C, reg); | |
753 | ||
72ed4dc7 | 754 | if (wilc_get_chipid(false) >= 0x1002b0) { |
c5c77ba1 | 755 | /* Enable PALDO back right after wakeup */ |
fbc2fe16 | 756 | u32 val32; |
8dfaafd6 | 757 | |
c5c77ba1 JK |
758 | g_wlan.hif_func.hif_read_reg(0x1e1c, &val32); |
759 | val32 |= (1 << 6); | |
760 | g_wlan.hif_func.hif_write_reg(0x1e1c, val32); | |
761 | ||
762 | g_wlan.hif_func.hif_read_reg(0x1e9c, &val32); | |
763 | val32 |= (1 << 6); | |
764 | g_wlan.hif_func.hif_write_reg(0x1e9c, val32); | |
765 | } | |
766 | } | |
767 | genuChipPSstate = CHIP_WAKEDUP; | |
768 | } | |
769 | #else | |
770 | INLINE void chip_wakeup(void) | |
771 | { | |
fbc2fe16 | 772 | u32 reg, trials = 0; |
8dfaafd6 | 773 | |
c5c77ba1 JK |
774 | do { |
775 | if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) { | |
776 | g_wlan.hif_func.hif_read_reg(1, ®); | |
777 | /* Make sure bit 1 is 0 before we start. */ | |
778 | g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1)); | |
779 | /* Set bit 1 */ | |
780 | g_wlan.hif_func.hif_write_reg(1, reg | (1 << 1)); | |
781 | /* Clear bit 1*/ | |
782 | g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1)); | |
783 | } else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO) { | |
784 | /* Make sure bit 0 is 0 before we start. */ | |
785 | g_wlan.hif_func.hif_read_reg(0xf0, ®); | |
786 | g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0)); | |
787 | /* Set bit 1 */ | |
788 | g_wlan.hif_func.hif_write_reg(0xf0, reg | (1 << 0)); | |
789 | /* Clear bit 1 */ | |
790 | g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0)); | |
791 | } | |
792 | ||
793 | do { | |
794 | /* Wait for the chip to stabilize*/ | |
c5c77ba1 JK |
795 | mdelay(3); |
796 | ||
797 | /* Make sure chip is awake. This is an extra step that can be removed */ | |
798 | /* later to avoid the bus access overhead */ | |
72ed4dc7 | 799 | if ((wilc_get_chipid(true) == 0)) { |
c5c77ba1 JK |
800 | wilc_debug(N_ERR, "Couldn't read chip id. Wake up failed\n"); |
801 | } | |
72ed4dc7 | 802 | } while ((wilc_get_chipid(true) == 0) && ((++trials % 3) == 0)); |
c5c77ba1 | 803 | |
72ed4dc7 | 804 | } while (wilc_get_chipid(true) == 0); |
c5c77ba1 JK |
805 | |
806 | if (genuChipPSstate == CHIP_SLEEPING_MANUAL) { | |
807 | g_wlan.hif_func.hif_read_reg(0x1C0C, ®); | |
808 | reg &= ~(1 << 0); | |
809 | g_wlan.hif_func.hif_write_reg(0x1C0C, reg); | |
810 | ||
72ed4dc7 | 811 | if (wilc_get_chipid(false) >= 0x1002b0) { |
c5c77ba1 | 812 | /* Enable PALDO back right after wakeup */ |
fbc2fe16 | 813 | u32 val32; |
8dfaafd6 | 814 | |
c5c77ba1 JK |
815 | g_wlan.hif_func.hif_read_reg(0x1e1c, &val32); |
816 | val32 |= (1 << 6); | |
817 | g_wlan.hif_func.hif_write_reg(0x1e1c, val32); | |
818 | ||
819 | g_wlan.hif_func.hif_read_reg(0x1e9c, &val32); | |
820 | val32 |= (1 << 6); | |
821 | g_wlan.hif_func.hif_write_reg(0x1e9c, val32); | |
822 | } | |
823 | } | |
824 | genuChipPSstate = CHIP_WAKEDUP; | |
825 | } | |
826 | #endif | |
4e4467fd | 827 | void chip_sleep_manually(u32 u32SleepTime) |
c5c77ba1 | 828 | { |
c5c77ba1 JK |
829 | if (genuChipPSstate != CHIP_WAKEDUP) { |
830 | /* chip is already sleeping. Do nothing */ | |
831 | return; | |
832 | } | |
833 | acquire_bus(ACQUIRE_ONLY); | |
834 | ||
835 | #ifdef WILC_OPTIMIZE_SLEEP_INT | |
836 | chip_allow_sleep(); | |
837 | #endif | |
838 | ||
839 | /* Trigger the manual sleep interrupt */ | |
840 | g_wlan.hif_func.hif_write_reg(0x10a8, 1); | |
841 | ||
842 | genuChipPSstate = CHIP_SLEEPING_MANUAL; | |
843 | release_bus(RELEASE_ONLY); | |
844 | ||
845 | } | |
846 | ||
847 | ||
848 | /******************************************** | |
849 | * | |
850 | * Tx, Rx queue handle functions | |
851 | * | |
852 | ********************************************/ | |
fbc2fe16 | 853 | static int wilc_wlan_handle_txq(u32 *pu32TxqCount) |
c5c77ba1 JK |
854 | { |
855 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
856 | int i, entries = 0; | |
fbc2fe16 CL |
857 | u32 sum; |
858 | u32 reg; | |
51e825f7 | 859 | u8 *txb = p->tx_buffer; |
fbc2fe16 | 860 | u32 offset = 0; |
c5c77ba1 JK |
861 | int vmm_sz = 0; |
862 | struct txq_entry_t *tqe; | |
863 | int ret = 0; | |
864 | int counter; | |
865 | int timeout; | |
fbc2fe16 | 866 | u32 vmm_table[WILC_VMM_TBL_SIZE]; |
8dfaafd6 | 867 | |
c5c77ba1 JK |
868 | p->txq_exit = 0; |
869 | do { | |
870 | if (p->quit) | |
871 | break; | |
872 | ||
873 | /*Added by Amr - BugID_4720*/ | |
874 | p->os_func.os_wait(p->txq_add_to_head_lock, CFG_PKTS_TIMEOUT); | |
875 | #ifdef TCP_ACK_FILTER | |
876 | wilc_wlan_txq_filter_dup_tcp_ack(); | |
877 | #endif | |
878 | /** | |
879 | * build the vmm list | |
880 | **/ | |
881 | PRINT_D(TX_DBG, "Getting the head of the TxQ\n"); | |
882 | tqe = wilc_wlan_txq_get_first(); | |
883 | i = 0; | |
884 | sum = 0; | |
885 | do { | |
886 | /* if ((tqe != NULL) && (i < (8)) && */ | |
887 | /* if ((tqe != NULL) && (i < (WILC_VMM_TBL_SIZE-1)) && */ | |
888 | if ((tqe != NULL) && (i < (WILC_VMM_TBL_SIZE - 1)) /* reserve last entry to 0 */) { | |
889 | ||
890 | if (tqe->type == WILC_CFG_PKT) { | |
891 | vmm_sz = ETH_CONFIG_PKT_HDR_OFFSET; | |
892 | } | |
893 | /*Bug3959: transmitting mgmt frames received from host*/ | |
894 | /*vmm_sz will only be equal to tqe->buffer_size + 4 bytes (HOST_HDR_OFFSET)*/ | |
895 | /* in other cases WILC_MGMT_PKT and WILC_DATA_PKT_MAC_HDR*/ | |
896 | else if (tqe->type == WILC_NET_PKT) { | |
897 | vmm_sz = ETH_ETHERNET_HDR_OFFSET; | |
898 | } | |
c5c77ba1 JK |
899 | #ifdef WILC_AP_EXTERNAL_MLME |
900 | else { | |
901 | vmm_sz = HOST_HDR_OFFSET; | |
902 | } | |
903 | #endif | |
904 | vmm_sz += tqe->buffer_size; | |
905 | PRINT_D(TX_DBG, "VMM Size before alignment = %d\n", vmm_sz); | |
906 | if (vmm_sz & 0x3) { /* has to be word aligned */ | |
907 | vmm_sz = (vmm_sz + 4) & ~0x3; | |
908 | } | |
909 | if ((sum + vmm_sz) > p->tx_buffer_size) { | |
910 | break; | |
911 | } | |
912 | PRINT_D(TX_DBG, "VMM Size AFTER alignment = %d\n", vmm_sz); | |
913 | vmm_table[i] = vmm_sz / 4; /* table take the word size */ | |
914 | PRINT_D(TX_DBG, "VMMTable entry size = %d\n", vmm_table[i]); | |
915 | ||
916 | if (tqe->type == WILC_CFG_PKT) { | |
917 | vmm_table[i] |= (1 << 10); | |
918 | PRINT_D(TX_DBG, "VMMTable entry changed for CFG packet = %d\n", vmm_table[i]); | |
919 | } | |
920 | #ifdef BIG_ENDIAN | |
921 | vmm_table[i] = BYTE_SWAP(vmm_table[i]); | |
922 | #endif | |
c5c77ba1 | 923 | |
c5c77ba1 JK |
924 | i++; |
925 | sum += vmm_sz; | |
926 | PRINT_D(TX_DBG, "sum = %d\n", sum); | |
927 | tqe = wilc_wlan_txq_get_next(tqe); | |
928 | } else { | |
929 | break; | |
930 | } | |
931 | } while (1); | |
932 | ||
933 | if (i == 0) { /* nothing in the queue */ | |
934 | PRINT_D(TX_DBG, "Nothing in TX-Q\n"); | |
935 | break; | |
936 | } else { | |
937 | PRINT_D(TX_DBG, "Mark the last entry in VMM table - number of previous entries = %d\n", i); | |
938 | vmm_table[i] = 0x0; /* mark the last element to 0 */ | |
939 | } | |
940 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
941 | counter = 0; | |
942 | do { | |
943 | ||
944 | ret = p->hif_func.hif_read_reg(WILC_HOST_TX_CTRL, ®); | |
945 | if (!ret) { | |
946 | wilc_debug(N_ERR, "[wilc txq]: fail can't read reg vmm_tbl_entry..\n"); | |
947 | break; | |
948 | } | |
949 | ||
950 | if ((reg & 0x1) == 0) { | |
951 | /** | |
952 | * write to vmm table | |
953 | **/ | |
954 | PRINT_D(TX_DBG, "Writing VMM table ... with Size = %d\n", ((i + 1) * 4)); | |
955 | break; | |
956 | } else { | |
957 | counter++; | |
958 | if (counter > 200) { | |
959 | counter = 0; | |
960 | PRINT_D(TX_DBG, "Looping in tx ctrl , forcce quit\n"); | |
961 | ret = p->hif_func.hif_write_reg(WILC_HOST_TX_CTRL, 0); | |
962 | break; | |
963 | } | |
964 | /** | |
965 | * wait for vmm table is ready | |
966 | **/ | |
17aacd43 | 967 | PRINT_WRN(GENERIC_DBG, "[wilc txq]: warn, vmm table not clear yet, wait...\n"); |
c5c77ba1 | 968 | release_bus(RELEASE_ALLOW_SLEEP); |
2b922cbe | 969 | usleep_range(3000, 3000); |
c5c77ba1 JK |
970 | acquire_bus(ACQUIRE_AND_WAKEUP); |
971 | } | |
972 | } while (!p->quit); | |
973 | ||
974 | if (!ret) { | |
975 | goto _end_; | |
976 | } | |
977 | ||
978 | timeout = 200; | |
979 | do { | |
980 | ||
981 | /** | |
982 | * write to vmm table | |
983 | **/ | |
51e825f7 | 984 | ret = p->hif_func.hif_block_tx(WILC_VMM_TBL_RX_SHADOW_BASE, (u8 *)vmm_table, ((i + 1) * 4)); /* Bug 4477 fix */ |
c5c77ba1 JK |
985 | if (!ret) { |
986 | wilc_debug(N_ERR, "ERR block TX of VMM table.\n"); | |
987 | break; | |
988 | } | |
989 | ||
990 | ||
991 | /** | |
992 | * interrupt firmware | |
993 | **/ | |
994 | ret = p->hif_func.hif_write_reg(WILC_HOST_VMM_CTL, 0x2); | |
995 | if (!ret) { | |
996 | wilc_debug(N_ERR, "[wilc txq]: fail can't write reg host_vmm_ctl..\n"); | |
997 | break; | |
998 | } | |
999 | ||
1000 | /** | |
1001 | * wait for confirm... | |
1002 | **/ | |
1003 | ||
1004 | do { | |
1005 | ret = p->hif_func.hif_read_reg(WILC_HOST_VMM_CTL, ®); | |
1006 | if (!ret) { | |
1007 | wilc_debug(N_ERR, "[wilc txq]: fail can't read reg host_vmm_ctl..\n"); | |
1008 | break; | |
1009 | } | |
1010 | if ((reg >> 2) & 0x1) { | |
1011 | /** | |
1012 | * Get the entries | |
1013 | **/ | |
1014 | entries = ((reg >> 3) & 0x3f); | |
1015 | /* entries = ((reg>>3)&0x2f); */ | |
1016 | break; | |
1017 | } else { | |
1018 | release_bus(RELEASE_ALLOW_SLEEP); | |
2b922cbe | 1019 | usleep_range(3000, 3000); |
c5c77ba1 JK |
1020 | acquire_bus(ACQUIRE_AND_WAKEUP); |
1021 | PRINT_WRN(GENERIC_DBG, "Can't get VMM entery - reg = %2x\n", reg); | |
1022 | } | |
1023 | } while (--timeout); | |
1024 | if (timeout <= 0) { | |
1025 | ret = p->hif_func.hif_write_reg(WILC_HOST_VMM_CTL, 0x0); | |
1026 | break; | |
1027 | } | |
1028 | ||
1029 | if (!ret) { | |
1030 | break; | |
1031 | } | |
1032 | ||
1033 | if (entries == 0) { | |
17aacd43 | 1034 | PRINT_WRN(GENERIC_DBG, "[wilc txq]: no more buffer in the chip (reg: %08x), retry later [[ %d, %x ]]\n", reg, i, vmm_table[i - 1]); |
c5c77ba1 JK |
1035 | |
1036 | /* undo the transaction. */ | |
1037 | ret = p->hif_func.hif_read_reg(WILC_HOST_TX_CTRL, ®); | |
1038 | if (!ret) { | |
1039 | wilc_debug(N_ERR, "[wilc txq]: fail can't read reg WILC_HOST_TX_CTRL..\n"); | |
1040 | break; | |
1041 | } | |
1042 | reg &= ~(1ul << 0); | |
1043 | ret = p->hif_func.hif_write_reg(WILC_HOST_TX_CTRL, reg); | |
1044 | if (!ret) { | |
1045 | wilc_debug(N_ERR, "[wilc txq]: fail can't write reg WILC_HOST_TX_CTRL..\n"); | |
1046 | break; | |
1047 | } | |
1048 | break; | |
1049 | } else { | |
1050 | break; | |
1051 | } | |
1052 | } while (1); | |
1053 | ||
1054 | if (!ret) { | |
1055 | goto _end_; | |
1056 | } | |
1057 | if (entries == 0) { | |
1058 | ret = WILC_TX_ERR_NO_BUF; | |
1059 | goto _end_; | |
1060 | } | |
1061 | ||
1062 | /* since copying data into txb takes some time, then | |
1063 | * allow the bus lock to be released let the RX task go. */ | |
1064 | release_bus(RELEASE_ALLOW_SLEEP); | |
1065 | ||
1066 | /** | |
1067 | * Copy data to the TX buffer | |
1068 | **/ | |
1069 | offset = 0; | |
1070 | i = 0; | |
1071 | do { | |
1072 | tqe = wilc_wlan_txq_remove_from_head(); | |
1073 | if (tqe != NULL && (vmm_table[i] != 0)) { | |
fbc2fe16 | 1074 | u32 header, buffer_offset; |
c5c77ba1 JK |
1075 | |
1076 | #ifdef BIG_ENDIAN | |
1077 | vmm_table[i] = BYTE_SWAP(vmm_table[i]); | |
1078 | #endif | |
1079 | vmm_sz = (vmm_table[i] & 0x3ff); /* in word unit */ | |
1080 | vmm_sz *= 4; | |
1081 | header = (tqe->type << 31) | (tqe->buffer_size << 15) | vmm_sz; | |
1082 | /*Bug3959: transmitting mgmt frames received from host*/ | |
1083 | /*setting bit 30 in the host header to indicate mgmt frame*/ | |
1084 | #ifdef WILC_AP_EXTERNAL_MLME | |
78174ada | 1085 | if (tqe->type == WILC_MGMT_PKT) |
c5c77ba1 | 1086 | header |= (1 << 30); |
78174ada | 1087 | else |
c5c77ba1 | 1088 | header &= ~(1 << 30); |
c5c77ba1 | 1089 | #endif |
c5c77ba1 JK |
1090 | |
1091 | #ifdef BIG_ENDIAN | |
1092 | header = BYTE_SWAP(header); | |
1093 | #endif | |
1094 | memcpy(&txb[offset], &header, 4); | |
1095 | if (tqe->type == WILC_CFG_PKT) { | |
1096 | buffer_offset = ETH_CONFIG_PKT_HDR_OFFSET; | |
1097 | } | |
1098 | /*Bug3959: transmitting mgmt frames received from host*/ | |
1099 | /*buffer offset = HOST_HDR_OFFSET in other cases: WILC_MGMT_PKT*/ | |
1100 | /* and WILC_DATA_PKT_MAC_HDR*/ | |
1101 | else if (tqe->type == WILC_NET_PKT) { | |
1102 | char *pBSSID = ((struct tx_complete_data *)(tqe->priv))->pBssid; | |
8dfaafd6 | 1103 | |
c5c77ba1 JK |
1104 | buffer_offset = ETH_ETHERNET_HDR_OFFSET; |
1105 | /* copy the bssid at the sart of the buffer */ | |
1106 | memcpy(&txb[offset + 4], pBSSID, 6); | |
1107 | } | |
c5c77ba1 JK |
1108 | else { |
1109 | buffer_offset = HOST_HDR_OFFSET; | |
1110 | } | |
1111 | ||
1112 | memcpy(&txb[offset + buffer_offset], tqe->buffer, tqe->buffer_size); | |
1113 | offset += vmm_sz; | |
1114 | i++; | |
1115 | tqe->status = 1; /* mark the packet send */ | |
1116 | if (tqe->tx_complete_func) | |
1117 | tqe->tx_complete_func(tqe->priv, tqe->status); | |
1118 | #ifdef TCP_ACK_FILTER | |
1119 | if (tqe->tcp_PendingAck_index != NOT_TCP_ACK) { | |
1120 | Pending_Acks_info[tqe->tcp_PendingAck_index].txqe = NULL; | |
1121 | } | |
1122 | #endif | |
a18dd630 | 1123 | kfree(tqe); |
c5c77ba1 JK |
1124 | } else { |
1125 | break; | |
1126 | } | |
1127 | } while (--entries); | |
1128 | ||
1129 | /** | |
1130 | * lock the bus | |
1131 | **/ | |
1132 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
1133 | ||
1134 | ret = p->hif_func.hif_clear_int_ext(ENABLE_TX_VMM); | |
1135 | if (!ret) { | |
1136 | wilc_debug(N_ERR, "[wilc txq]: fail can't start tx VMM ...\n"); | |
1137 | goto _end_; | |
1138 | } | |
1139 | ||
1140 | /** | |
1141 | * transfer | |
1142 | **/ | |
1143 | ret = p->hif_func.hif_block_tx_ext(0, txb, offset); | |
1144 | if (!ret) { | |
1145 | wilc_debug(N_ERR, "[wilc txq]: fail can't block tx ext...\n"); | |
1146 | goto _end_; | |
1147 | } | |
1148 | ||
1149 | _end_: | |
1150 | ||
1151 | release_bus(RELEASE_ALLOW_SLEEP); | |
1152 | if (ret != 1) | |
1153 | break; | |
1154 | } while (0); | |
c5c77ba1 | 1155 | /*Added by Amr - BugID_4720*/ |
8990d856 | 1156 | up(p->txq_add_to_head_lock); |
c5c77ba1 JK |
1157 | |
1158 | p->txq_exit = 1; | |
1159 | PRINT_D(TX_DBG, "THREAD: Exiting txq\n"); | |
1160 | /* return tx[]q count */ | |
1161 | *pu32TxqCount = p->txq_entries; | |
1162 | return ret; | |
1163 | } | |
1164 | ||
1165 | static void wilc_wlan_handle_rxq(void) | |
1166 | { | |
1167 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
1168 | int offset = 0, size, has_packet = 0; | |
51e825f7 | 1169 | u8 *buffer; |
c5c77ba1 JK |
1170 | struct rxq_entry_t *rqe; |
1171 | ||
1172 | p->rxq_exit = 0; | |
1173 | ||
1174 | ||
1175 | ||
1176 | ||
1177 | do { | |
1178 | if (p->quit) { | |
17aacd43 | 1179 | PRINT_D(RX_DBG, "exit 1st do-while due to Clean_UP function\n"); |
8990d856 | 1180 | up(p->cfg_wait); |
c5c77ba1 JK |
1181 | break; |
1182 | } | |
1183 | rqe = wilc_wlan_rxq_remove(); | |
1184 | if (rqe == NULL) { | |
1185 | PRINT_D(RX_DBG, "nothing in the queue - exit 1st do-while\n"); | |
1186 | break; | |
1187 | } | |
1188 | buffer = rqe->buffer; | |
1189 | size = rqe->buffer_size; | |
1190 | PRINT_D(RX_DBG, "rxQ entery Size = %d - Address = %p\n", size, buffer); | |
1191 | offset = 0; | |
1192 | ||
1193 | ||
1194 | ||
1195 | do { | |
fbc2fe16 CL |
1196 | u32 header; |
1197 | u32 pkt_len, pkt_offset, tp_len; | |
c5c77ba1 | 1198 | int is_cfg_packet; |
8dfaafd6 | 1199 | |
c5c77ba1 JK |
1200 | PRINT_D(RX_DBG, "In the 2nd do-while\n"); |
1201 | memcpy(&header, &buffer[offset], 4); | |
1202 | #ifdef BIG_ENDIAN | |
1203 | header = BYTE_SWAP(header); | |
1204 | #endif | |
1205 | PRINT_D(RX_DBG, "Header = %04x - Offset = %d\n", header, offset); | |
1206 | ||
1207 | ||
1208 | ||
1209 | is_cfg_packet = (header >> 31) & 0x1; | |
1210 | pkt_offset = (header >> 22) & 0x1ff; | |
1211 | tp_len = (header >> 11) & 0x7ff; | |
1212 | pkt_len = header & 0x7ff; | |
1213 | ||
1214 | if (pkt_len == 0 || tp_len == 0) { | |
1215 | wilc_debug(N_RXQ, "[wilc rxq]: data corrupt, packet len or tp_len is 0 [%d][%d]\n", pkt_len, tp_len); | |
1216 | break; | |
1217 | } | |
1218 | ||
1219 | /*bug 3887: [AP] Allow Management frames to be passed to the host*/ | |
1220 | #if defined(WILC_AP_EXTERNAL_MLME) || defined(WILC_P2P) | |
1221 | #define IS_MANAGMEMENT 0x100 | |
1222 | #define IS_MANAGMEMENT_CALLBACK 0x080 | |
1223 | #define IS_MGMT_STATUS_SUCCES 0x040 | |
1224 | ||
1225 | ||
1226 | if (pkt_offset & IS_MANAGMEMENT) { | |
1227 | /* reset mgmt indicator bit, to use pkt_offeset in furthur calculations */ | |
1228 | pkt_offset &= ~(IS_MANAGMEMENT | IS_MANAGMEMENT_CALLBACK | IS_MGMT_STATUS_SUCCES); | |
1229 | ||
c5c77ba1 | 1230 | WILC_WFI_mgmt_rx(&buffer[offset + HOST_HDR_OFFSET], pkt_len); |
c5c77ba1 JK |
1231 | } |
1232 | /* BUG4530 fix */ | |
1233 | else | |
1234 | #endif | |
1235 | { | |
c5c77ba1 JK |
1236 | |
1237 | if (!is_cfg_packet) { | |
1238 | ||
1239 | if (p->net_func.rx_indicate) { | |
1240 | if (pkt_len > 0) { | |
1241 | p->net_func.rx_indicate(&buffer[offset], pkt_len, pkt_offset); | |
1242 | has_packet = 1; | |
1243 | } | |
1244 | } | |
1245 | } else { | |
1246 | wilc_cfg_rsp_t rsp; | |
1247 | ||
1248 | ||
1249 | ||
1250 | p->cif_func.rx_indicate(&buffer[pkt_offset + offset], pkt_len, &rsp); | |
1251 | if (rsp.type == WILC_CFG_RSP) { | |
1252 | /** | |
1253 | * wake up the waiting task... | |
1254 | **/ | |
1255 | PRINT_D(RX_DBG, "p->cfg_seq_no = %d - rsp.seq_no = %d\n", p->cfg_seq_no, rsp.seq_no); | |
1256 | if (p->cfg_seq_no == rsp.seq_no) { | |
8990d856 | 1257 | up(p->cfg_wait); |
c5c77ba1 | 1258 | } |
c5c77ba1 JK |
1259 | } else if (rsp.type == WILC_CFG_RSP_STATUS) { |
1260 | /** | |
1261 | * Call back to indicate status... | |
1262 | **/ | |
1263 | if (p->indicate_func.mac_indicate) { | |
1264 | p->indicate_func.mac_indicate(WILC_MAC_INDICATE_STATUS); | |
1265 | } | |
1266 | ||
1267 | } else if (rsp.type == WILC_CFG_RSP_SCAN) { | |
1268 | if (p->indicate_func.mac_indicate) | |
1269 | p->indicate_func.mac_indicate(WILC_MAC_INDICATE_SCAN); | |
1270 | } | |
1271 | } | |
1272 | } | |
1273 | offset += tp_len; | |
1274 | if (offset >= size) | |
1275 | break; | |
1276 | } while (1); | |
1277 | ||
1278 | ||
1279 | #ifndef MEMORY_STATIC | |
a18dd630 | 1280 | kfree(buffer); |
c5c77ba1 | 1281 | #endif |
a18dd630 | 1282 | kfree(rqe); |
c5c77ba1 JK |
1283 | |
1284 | if (has_packet) { | |
1285 | if (p->net_func.rx_complete) | |
1286 | p->net_func.rx_complete(); | |
1287 | } | |
1288 | } while (1); | |
1289 | ||
1290 | p->rxq_exit = 1; | |
17aacd43 | 1291 | PRINT_D(RX_DBG, "THREAD: Exiting RX thread\n"); |
c5c77ba1 JK |
1292 | } |
1293 | ||
1294 | /******************************************** | |
1295 | * | |
1296 | * Fast DMA Isr | |
1297 | * | |
1298 | ********************************************/ | |
1299 | static void wilc_unknown_isr_ext(void) | |
1300 | { | |
1301 | g_wlan.hif_func.hif_clear_int_ext(0); | |
1302 | } | |
fbc2fe16 | 1303 | static void wilc_pllupdate_isr_ext(u32 int_stats) |
c5c77ba1 JK |
1304 | { |
1305 | ||
1306 | int trials = 10; | |
1307 | ||
1308 | g_wlan.hif_func.hif_clear_int_ext(PLL_INT_CLR); | |
1309 | ||
1310 | /* Waiting for PLL */ | |
c2e4c0f1 | 1311 | mdelay(WILC_PLL_TO); |
c5c77ba1 JK |
1312 | |
1313 | /* poll till read a valid data */ | |
72ed4dc7 | 1314 | while (!(ISWILC1000(wilc_get_chipid(true)) && --trials)) { |
c5c77ba1 | 1315 | PRINT_D(TX_DBG, "PLL update retrying\n"); |
c2e4c0f1 | 1316 | mdelay(1); |
c5c77ba1 JK |
1317 | } |
1318 | } | |
1319 | ||
fbc2fe16 | 1320 | static void wilc_sleeptimer_isr_ext(u32 int_stats1) |
c5c77ba1 JK |
1321 | { |
1322 | g_wlan.hif_func.hif_clear_int_ext(SLEEP_INT_CLR); | |
1323 | #ifndef WILC_OPTIMIZE_SLEEP_INT | |
1324 | genuChipPSstate = CHIP_SLEEPING_AUTO; | |
1325 | #endif | |
1326 | } | |
1327 | ||
fbc2fe16 | 1328 | static void wilc_wlan_handle_isr_ext(u32 int_status) |
c5c77ba1 JK |
1329 | { |
1330 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
1331 | #ifdef MEMORY_STATIC | |
fbc2fe16 | 1332 | u32 offset = p->rx_buffer_offset; |
c5c77ba1 | 1333 | #endif |
51e825f7 | 1334 | u8 *buffer = NULL; |
fbc2fe16 CL |
1335 | u32 size; |
1336 | u32 retries = 0; | |
c5c77ba1 JK |
1337 | int ret = 0; |
1338 | struct rxq_entry_t *rqe; | |
1339 | ||
1340 | ||
1341 | /** | |
1342 | * Get the rx size | |
1343 | **/ | |
1344 | ||
1345 | size = ((int_status & 0x7fff) << 2); | |
1346 | ||
1347 | while (!size && retries < 10) { | |
fbc2fe16 | 1348 | u32 time = 0; |
c5c77ba1 JK |
1349 | /*looping more secure*/ |
1350 | /*zero size make a crashe because the dma will not happen and that will block the firmware*/ | |
1351 | wilc_debug(N_ERR, "RX Size equal zero ... Trying to read it again for %d time\n", time++); | |
1352 | p->hif_func.hif_read_size(&size); | |
1353 | size = ((size & 0x7fff) << 2); | |
1354 | retries++; | |
1355 | ||
1356 | } | |
1357 | ||
1358 | if (size > 0) { | |
1359 | #ifdef MEMORY_STATIC | |
1360 | if (p->rx_buffer_size - offset < size) | |
1361 | offset = 0; | |
1362 | ||
1363 | if (p->rx_buffer) | |
1364 | buffer = &p->rx_buffer[offset]; | |
1365 | else { | |
1366 | wilc_debug(N_ERR, "[wilc isr]: fail Rx Buffer is NULL...drop the packets (%d)\n", size); | |
1367 | goto _end_; | |
1368 | } | |
1369 | ||
1370 | #else | |
f019b9d9 | 1371 | buffer = kmalloc(size, GFP_KERNEL); |
c5c77ba1 JK |
1372 | if (buffer == NULL) { |
1373 | wilc_debug(N_ERR, "[wilc isr]: fail alloc host memory...drop the packets (%d)\n", size); | |
80e29c7a | 1374 | usleep_range(100 * 1000, 100 * 1000); |
c5c77ba1 JK |
1375 | goto _end_; |
1376 | } | |
1377 | #endif | |
1378 | ||
1379 | /** | |
1380 | * clear the chip's interrupt after getting size some register getting corrupted after clear the interrupt | |
1381 | **/ | |
1382 | p->hif_func.hif_clear_int_ext(DATA_INT_CLR | ENABLE_RX_VMM); | |
1383 | ||
1384 | ||
1385 | /** | |
1386 | * start transfer | |
1387 | **/ | |
1388 | ret = p->hif_func.hif_block_rx_ext(0, buffer, size); | |
1389 | ||
1390 | if (!ret) { | |
1391 | wilc_debug(N_ERR, "[wilc isr]: fail block rx...\n"); | |
1392 | goto _end_; | |
1393 | } | |
1394 | _end_: | |
1395 | ||
1396 | ||
1397 | if (ret) { | |
1398 | #ifdef MEMORY_STATIC | |
1399 | offset += size; | |
1400 | p->rx_buffer_offset = offset; | |
1401 | #endif | |
1402 | /** | |
1403 | * add to rx queue | |
1404 | **/ | |
f019b9d9 | 1405 | rqe = kmalloc(sizeof(struct rxq_entry_t), GFP_KERNEL); |
c5c77ba1 JK |
1406 | if (rqe != NULL) { |
1407 | rqe->buffer = buffer; | |
1408 | rqe->buffer_size = size; | |
1409 | PRINT_D(RX_DBG, "rxq entery Size= %d - Address = %p\n", rqe->buffer_size, rqe->buffer); | |
1410 | wilc_wlan_rxq_add(rqe); | |
8990d856 | 1411 | up(p->rxq_wait); |
c5c77ba1 JK |
1412 | } |
1413 | } else { | |
1414 | #ifndef MEMORY_STATIC | |
a18dd630 | 1415 | kfree(buffer); |
c5c77ba1 JK |
1416 | #endif |
1417 | } | |
1418 | } | |
1419 | #ifdef TCP_ENHANCEMENTS | |
1420 | wilc_wlan_handle_rxq(); | |
1421 | #endif | |
1422 | } | |
1423 | ||
1424 | void wilc_handle_isr(void) | |
1425 | { | |
fbc2fe16 | 1426 | u32 int_status; |
c5c77ba1 JK |
1427 | |
1428 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
1429 | g_wlan.hif_func.hif_read_int(&int_status); | |
1430 | ||
1431 | if (int_status & PLL_INT_EXT) { | |
1432 | wilc_pllupdate_isr_ext(int_status); | |
1433 | } | |
1434 | if (int_status & DATA_INT_EXT) { | |
1435 | wilc_wlan_handle_isr_ext(int_status); | |
1436 | #ifndef WILC_OPTIMIZE_SLEEP_INT | |
1437 | /* Chip is up and talking*/ | |
1438 | genuChipPSstate = CHIP_WAKEDUP; | |
1439 | #endif | |
1440 | } | |
1441 | if (int_status & SLEEP_INT_EXT) { | |
1442 | wilc_sleeptimer_isr_ext(int_status); | |
1443 | } | |
1444 | ||
1445 | if (!(int_status & (ALL_INT_EXT))) { | |
1446 | #ifdef WILC_SDIO | |
1447 | PRINT_D(TX_DBG, ">> UNKNOWN_INTERRUPT - 0x%08x\n", int_status); | |
1448 | #endif | |
1449 | wilc_unknown_isr_ext(); | |
1450 | } | |
1451 | #if ((!defined WILC_SDIO) || (defined WILC_SDIO_IRQ_GPIO)) | |
1452 | linux_wlan_enable_irq(); | |
1453 | #endif | |
1454 | release_bus(RELEASE_ALLOW_SLEEP); | |
1455 | } | |
1456 | ||
1457 | /******************************************** | |
1458 | * | |
1459 | * Firmware download | |
1460 | * | |
1461 | ********************************************/ | |
fbc2fe16 | 1462 | static int wilc_wlan_firmware_download(const u8 *buffer, u32 buffer_size) |
c5c77ba1 JK |
1463 | { |
1464 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
fbc2fe16 CL |
1465 | u32 offset; |
1466 | u32 addr, size, size2, blksz; | |
51e825f7 | 1467 | u8 *dma_buffer; |
c5c77ba1 JK |
1468 | int ret = 0; |
1469 | ||
1470 | blksz = (1ul << 12); /* Bug 4703: 4KB Good enough size for most platforms = PAGE_SIZE. */ | |
1471 | /* Allocate a DMA coherent buffer. */ | |
1472 | ||
f019b9d9 | 1473 | dma_buffer = kmalloc(blksz, GFP_KERNEL); |
c5c77ba1 JK |
1474 | if (dma_buffer == NULL) { |
1475 | /*EIO 5*/ | |
1476 | ret = -5; | |
1477 | PRINT_ER("Can't allocate buffer for firmware download IO error\n "); | |
1478 | goto _fail_1; | |
1479 | } | |
1480 | ||
1481 | PRINT_D(INIT_DBG, "Downloading firmware size = %d ...\n", buffer_size); | |
1482 | /** | |
1483 | * load the firmware | |
1484 | **/ | |
1485 | offset = 0; | |
1486 | do { | |
1487 | memcpy(&addr, &buffer[offset], 4); | |
1488 | memcpy(&size, &buffer[offset + 4], 4); | |
1489 | #ifdef BIG_ENDIAN | |
1490 | addr = BYTE_SWAP(addr); | |
1491 | size = BYTE_SWAP(size); | |
1492 | #endif | |
1493 | acquire_bus(ACQUIRE_ONLY); | |
1494 | offset += 8; | |
1495 | while (((int)size) && (offset < buffer_size)) { | |
78174ada | 1496 | if (size <= blksz) |
c5c77ba1 | 1497 | size2 = size; |
78174ada | 1498 | else |
c5c77ba1 | 1499 | size2 = blksz; |
c5c77ba1 JK |
1500 | /* Copy firmware into a DMA coherent buffer */ |
1501 | memcpy(dma_buffer, &buffer[offset], size2); | |
1502 | ret = p->hif_func.hif_block_tx(addr, dma_buffer, size2); | |
1503 | if (!ret) | |
1504 | break; | |
1505 | ||
1506 | addr += size2; | |
1507 | offset += size2; | |
1508 | size -= size2; | |
1509 | } | |
1510 | release_bus(RELEASE_ONLY); | |
1511 | ||
1512 | if (!ret) { | |
1513 | /*EIO 5*/ | |
1514 | ret = -5; | |
1515 | PRINT_ER("Can't download firmware IO error\n "); | |
1516 | goto _fail_; | |
1517 | } | |
1518 | PRINT_D(INIT_DBG, "Offset = %d\n", offset); | |
1519 | } while (offset < buffer_size); | |
1520 | ||
1521 | _fail_: | |
1522 | ||
a18dd630 | 1523 | kfree(dma_buffer); |
c5c77ba1 JK |
1524 | |
1525 | _fail_1: | |
1526 | ||
1527 | return (ret < 0) ? ret : 0; | |
1528 | } | |
1529 | ||
1530 | /******************************************** | |
1531 | * | |
1532 | * Common | |
1533 | * | |
1534 | ********************************************/ | |
1535 | static int wilc_wlan_start(void) | |
1536 | { | |
1537 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
fbc2fe16 | 1538 | u32 reg = 0; |
c5c77ba1 | 1539 | int ret; |
fbc2fe16 | 1540 | u32 chipid; |
c5c77ba1 JK |
1541 | |
1542 | /** | |
1543 | * Set the host interface | |
1544 | **/ | |
1545 | #ifdef OLD_FPGA_BITFILE | |
1546 | acquire_bus(ACQUIRE_ONLY); | |
1547 | ret = p->hif_func.hif_read_reg(WILC_VMM_CORE_CTL, ®); | |
1548 | if (!ret) { | |
1549 | wilc_debug(N_ERR, "[wilc start]: fail read reg vmm_core_ctl...\n"); | |
1550 | release_bus(RELEASE_ALLOW_SLEEP); | |
1551 | return ret; | |
1552 | } | |
1553 | reg |= (p->io_func.io_type << 2); | |
1554 | ret = p->hif_func.hif_write_reg(WILC_VMM_CORE_CTL, reg); | |
1555 | if (!ret) { | |
1556 | wilc_debug(N_ERR, "[wilc start]: fail write reg vmm_core_ctl...\n"); | |
1557 | release_bus(RELEASE_ONLY); | |
1558 | return ret; | |
1559 | } | |
1560 | #else | |
1561 | if (p->io_func.io_type == HIF_SDIO) { | |
1562 | reg = 0; | |
1563 | reg |= (1 << 3); /* bug 4456 and 4557 */ | |
1564 | } else if (p->io_func.io_type == HIF_SPI) { | |
1565 | reg = 1; | |
1566 | } | |
1567 | acquire_bus(ACQUIRE_ONLY); | |
1568 | ret = p->hif_func.hif_write_reg(WILC_VMM_CORE_CFG, reg); | |
1569 | if (!ret) { | |
1570 | wilc_debug(N_ERR, "[wilc start]: fail write reg vmm_core_cfg...\n"); | |
1571 | release_bus(RELEASE_ONLY); | |
1572 | /* EIO 5*/ | |
1573 | ret = -5; | |
1574 | return ret; | |
1575 | } | |
1576 | reg = 0; | |
1577 | #ifdef WILC_SDIO_IRQ_GPIO | |
1578 | reg |= WILC_HAVE_SDIO_IRQ_GPIO; | |
1579 | #endif | |
1580 | ||
1581 | #ifdef WILC_DISABLE_PMU | |
1582 | #else | |
1583 | reg |= WILC_HAVE_USE_PMU; | |
1584 | #endif | |
1585 | ||
1586 | #ifdef WILC_SLEEP_CLK_SRC_XO | |
1587 | reg |= WILC_HAVE_SLEEP_CLK_SRC_XO; | |
1588 | #elif defined WILC_SLEEP_CLK_SRC_RTC | |
1589 | reg |= WILC_HAVE_SLEEP_CLK_SRC_RTC; | |
1590 | #endif | |
1591 | ||
1592 | #ifdef WILC_EXT_PA_INV_TX_RX | |
1593 | reg |= WILC_HAVE_EXT_PA_INV_TX_RX; | |
1594 | #endif | |
1595 | ||
1596 | reg |= WILC_HAVE_LEGACY_RF_SETTINGS; | |
1597 | ||
1598 | ||
1599 | /*BugID_5257*/ | |
1600 | /*Set oscillator frequency*/ | |
1601 | #ifdef XTAL_24 | |
1602 | reg |= WILC_HAVE_XTAL_24; | |
1603 | #endif | |
1604 | ||
1605 | /*BugID_5271*/ | |
1606 | /*Enable/Disable GPIO configuration for FW logs*/ | |
1607 | #ifdef DISABLE_WILC_UART | |
1608 | reg |= WILC_HAVE_DISABLE_WILC_UART; | |
1609 | #endif | |
1610 | ||
1611 | ret = p->hif_func.hif_write_reg(WILC_GP_REG_1, reg); | |
1612 | if (!ret) { | |
1613 | wilc_debug(N_ERR, "[wilc start]: fail write WILC_GP_REG_1 ...\n"); | |
1614 | release_bus(RELEASE_ONLY); | |
1615 | /* EIO 5*/ | |
1616 | ret = -5; | |
1617 | return ret; | |
1618 | } | |
1619 | #endif | |
1620 | ||
1621 | ||
1622 | /** | |
1623 | * Bus related | |
1624 | **/ | |
1625 | p->hif_func.hif_sync_ext(NUM_INT_EXT); | |
1626 | ||
1627 | ret = p->hif_func.hif_read_reg(0x1000, &chipid); | |
1628 | if (!ret) { | |
1629 | wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1000 ...\n"); | |
1630 | release_bus(RELEASE_ONLY); | |
1631 | /* EIO 5*/ | |
1632 | ret = -5; | |
1633 | return ret; | |
1634 | } | |
1635 | ||
1636 | /** | |
1637 | * Go... | |
1638 | **/ | |
1639 | ||
c5c77ba1 JK |
1640 | |
1641 | p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1642 | if ((reg & (1ul << 10)) == (1ul << 10)) { | |
1643 | reg &= ~(1ul << 10); | |
1644 | p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); | |
1645 | p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1646 | } | |
1647 | ||
1648 | reg |= (1ul << 10); | |
1649 | ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); | |
1650 | p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1651 | release_bus(RELEASE_ONLY); | |
1652 | ||
1653 | return (ret < 0) ? ret : 0; | |
1654 | } | |
1655 | ||
1656 | void wilc_wlan_global_reset(void) | |
1657 | { | |
1658 | ||
1659 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
8dfaafd6 | 1660 | |
c5c77ba1 JK |
1661 | acquire_bus(ACQUIRE_AND_WAKEUP); |
1662 | p->hif_func.hif_write_reg(WILC_GLB_RESET_0, 0x0); | |
1663 | release_bus(RELEASE_ONLY); | |
1664 | } | |
1665 | static int wilc_wlan_stop(void) | |
1666 | { | |
1667 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
fbc2fe16 | 1668 | u32 reg = 0; |
c5c77ba1 | 1669 | int ret; |
51e825f7 | 1670 | u8 timeout = 10; |
c5c77ba1 JK |
1671 | /** |
1672 | * TODO: stop the firmware, need a re-download | |
1673 | **/ | |
1674 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
1675 | ||
1676 | ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1677 | if (!ret) { | |
1678 | PRINT_ER("Error while reading reg\n"); | |
1679 | release_bus(RELEASE_ALLOW_SLEEP); | |
1680 | return ret; | |
1681 | } | |
1682 | ||
1683 | reg &= ~(1 << 10); | |
1684 | ||
1685 | ||
1686 | ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); | |
1687 | if (!ret) { | |
1688 | PRINT_ER("Error while writing reg\n"); | |
1689 | release_bus(RELEASE_ALLOW_SLEEP); | |
1690 | return ret; | |
1691 | } | |
1692 | ||
1693 | ||
1694 | ||
1695 | do { | |
1696 | ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1697 | if (!ret) { | |
1698 | PRINT_ER("Error while reading reg\n"); | |
1699 | release_bus(RELEASE_ALLOW_SLEEP); | |
1700 | return ret; | |
1701 | } | |
1702 | PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg, timeout); | |
1703 | /*Workaround to ensure that the chip is actually reset*/ | |
1704 | if ((reg & (1 << 10))) { | |
1705 | PRINT_D(GENERIC_DBG, "Bit 10 not reset : Retry %d\n", timeout); | |
1706 | reg &= ~(1 << 10); | |
1707 | ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); | |
1708 | timeout--; | |
1709 | } else { | |
1710 | PRINT_D(GENERIC_DBG, "Bit 10 reset after : Retry %d\n", timeout); | |
1711 | ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1712 | if (!ret) { | |
1713 | PRINT_ER("Error while reading reg\n"); | |
1714 | release_bus(RELEASE_ALLOW_SLEEP); | |
1715 | return ret; | |
1716 | } | |
1717 | PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg, timeout); | |
1718 | break; | |
1719 | } | |
1720 | ||
1721 | } while (timeout); | |
1722 | #if 1 | |
1723 | /******************************************************************************/ | |
1724 | /* This was add at Bug 4595 to reset the chip while maintaining the bus state */ | |
1725 | /******************************************************************************/ | |
1726 | reg = ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 8) | (1 << 9) | (1 << 26) | (1 << 29) | (1 << 30) | (1 << 31)); /**/ | |
1727 | /**/ | |
369f190a | 1728 | p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); /**/ |
c5c77ba1 JK |
1729 | reg = ~(1 << 10); /**/ |
1730 | /**/ | |
1731 | ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); /**/ | |
1732 | /******************************************************************************/ | |
1733 | #endif | |
1734 | ||
1735 | release_bus(RELEASE_ALLOW_SLEEP); | |
1736 | ||
1737 | return ret; | |
1738 | } | |
1739 | ||
1740 | static void wilc_wlan_cleanup(void) | |
1741 | { | |
1742 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
1743 | struct txq_entry_t *tqe; | |
1744 | struct rxq_entry_t *rqe; | |
fbc2fe16 | 1745 | u32 reg = 0; |
c5c77ba1 JK |
1746 | int ret; |
1747 | ||
1748 | p->quit = 1; | |
c5c77ba1 JK |
1749 | do { |
1750 | tqe = wilc_wlan_txq_remove_from_head(); | |
1751 | if (tqe == NULL) | |
1752 | break; | |
1753 | if (tqe->tx_complete_func) | |
1754 | tqe->tx_complete_func(tqe->priv, 0); | |
a18dd630 | 1755 | kfree(tqe); |
c5c77ba1 JK |
1756 | } while (1); |
1757 | ||
1758 | do { | |
1759 | rqe = wilc_wlan_rxq_remove(); | |
1760 | if (rqe == NULL) | |
1761 | break; | |
1762 | #ifdef MEMORY_DYNAMIC | |
a18dd630 | 1763 | kfree(tqe->buffer); |
c5c77ba1 | 1764 | #endif |
a18dd630 | 1765 | kfree(rqe); |
c5c77ba1 JK |
1766 | } while (1); |
1767 | ||
1768 | /** | |
1769 | * clean up buffer | |
1770 | **/ | |
1771 | ||
c5c77ba1 | 1772 | #ifdef MEMORY_STATIC |
a18dd630 GKH |
1773 | kfree(p->rx_buffer); |
1774 | p->rx_buffer = NULL; | |
c5c77ba1 | 1775 | #endif |
a18dd630 | 1776 | kfree(p->tx_buffer); |
c5c77ba1 JK |
1777 | |
1778 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
1779 | ||
1780 | ||
1781 | ret = p->hif_func.hif_read_reg(WILC_GP_REG_0, ®); | |
1782 | if (!ret) { | |
1783 | PRINT_ER("Error while reading reg\n"); | |
1784 | release_bus(RELEASE_ALLOW_SLEEP); | |
1785 | } | |
1786 | PRINT_ER("Writing ABORT reg\n"); | |
1787 | ret = p->hif_func.hif_write_reg(WILC_GP_REG_0, (reg | ABORT_INT)); | |
1788 | if (!ret) { | |
1789 | PRINT_ER("Error while writing reg\n"); | |
1790 | release_bus(RELEASE_ALLOW_SLEEP); | |
1791 | } | |
1792 | release_bus(RELEASE_ALLOW_SLEEP); | |
1793 | /** | |
1794 | * io clean up | |
1795 | **/ | |
1796 | p->hif_func.hif_deinit(NULL); | |
1797 | ||
1798 | } | |
1799 | ||
fbc2fe16 | 1800 | static int wilc_wlan_cfg_commit(int type, u32 drvHandler) |
c5c77ba1 JK |
1801 | { |
1802 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
1803 | wilc_cfg_frame_t *cfg = &p->cfg_frame; | |
1804 | int total_len = p->cfg_frame_offset + 4 + DRIVER_HANDLER_SIZE; | |
1805 | int seq_no = p->cfg_seq_no % 256; | |
4e4467fd | 1806 | int driver_handler = (u32)drvHandler; |
c5c77ba1 JK |
1807 | |
1808 | ||
1809 | /** | |
1810 | * Set up header | |
1811 | **/ | |
1812 | if (type == WILC_CFG_SET) { /* Set */ | |
1813 | cfg->wid_header[0] = 'W'; | |
1814 | } else { /* Query */ | |
1815 | cfg->wid_header[0] = 'Q'; | |
1816 | } | |
1817 | cfg->wid_header[1] = seq_no; /* sequence number */ | |
51e825f7 CL |
1818 | cfg->wid_header[2] = (u8)total_len; |
1819 | cfg->wid_header[3] = (u8)(total_len >> 8); | |
1820 | cfg->wid_header[4] = (u8)driver_handler; | |
1821 | cfg->wid_header[5] = (u8)(driver_handler >> 8); | |
1822 | cfg->wid_header[6] = (u8)(driver_handler >> 16); | |
1823 | cfg->wid_header[7] = (u8)(driver_handler >> 24); | |
c5c77ba1 JK |
1824 | p->cfg_seq_no = seq_no; |
1825 | ||
1826 | /** | |
1827 | * Add to TX queue | |
1828 | **/ | |
1829 | ||
1830 | /*Edited by Amr - BugID_4720*/ | |
1831 | if (!wilc_wlan_txq_add_cfg_pkt(&cfg->wid_header[0], total_len)) | |
1832 | return -1; | |
1833 | ||
1834 | return 0; | |
1835 | } | |
1836 | ||
fbc2fe16 | 1837 | static int wilc_wlan_cfg_set(int start, u32 wid, u8 *buffer, u32 buffer_size, int commit, u32 drvHandler) |
c5c77ba1 JK |
1838 | { |
1839 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
fbc2fe16 | 1840 | u32 offset; |
c5c77ba1 JK |
1841 | int ret_size; |
1842 | ||
1843 | ||
1844 | if (p->cfg_frame_in_use) | |
1845 | return 0; | |
1846 | ||
1847 | if (start) | |
1848 | p->cfg_frame_offset = 0; | |
1849 | ||
1850 | offset = p->cfg_frame_offset; | |
ec53adfe | 1851 | ret_size = p->cif_func.cfg_wid_set(p->cfg_frame.frame, offset, (u16)wid, buffer, buffer_size); |
c5c77ba1 JK |
1852 | offset += ret_size; |
1853 | p->cfg_frame_offset = offset; | |
1854 | ||
1855 | if (commit) { | |
1856 | PRINT_D(TX_DBG, "[WILC]PACKET Commit with sequence number %d\n", p->cfg_seq_no); | |
1857 | PRINT_D(RX_DBG, "Processing cfg_set()\n"); | |
1858 | p->cfg_frame_in_use = 1; | |
1859 | ||
1860 | /*Edited by Amr - BugID_4720*/ | |
1861 | if (wilc_wlan_cfg_commit(WILC_CFG_SET, drvHandler)) | |
1862 | ret_size = 0; /* BugID_5213 */ | |
1863 | ||
1864 | if (p->os_func.os_wait(p->cfg_wait, CFG_PKTS_TIMEOUT)) { | |
1865 | PRINT_D(TX_DBG, "Set Timed Out\n"); | |
1866 | ret_size = 0; | |
1867 | } | |
1868 | p->cfg_frame_in_use = 0; | |
1869 | p->cfg_frame_offset = 0; | |
1870 | p->cfg_seq_no += 1; | |
1871 | ||
1872 | } | |
1873 | ||
1874 | return ret_size; | |
1875 | } | |
fbc2fe16 | 1876 | static int wilc_wlan_cfg_get(int start, u32 wid, int commit, u32 drvHandler) |
c5c77ba1 JK |
1877 | { |
1878 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
fbc2fe16 | 1879 | u32 offset; |
c5c77ba1 JK |
1880 | int ret_size; |
1881 | ||
1882 | ||
1883 | if (p->cfg_frame_in_use) | |
1884 | return 0; | |
1885 | ||
1886 | if (start) | |
1887 | p->cfg_frame_offset = 0; | |
1888 | ||
1889 | offset = p->cfg_frame_offset; | |
ec53adfe | 1890 | ret_size = p->cif_func.cfg_wid_get(p->cfg_frame.frame, offset, (u16)wid); |
c5c77ba1 JK |
1891 | offset += ret_size; |
1892 | p->cfg_frame_offset = offset; | |
1893 | ||
1894 | if (commit) { | |
1895 | p->cfg_frame_in_use = 1; | |
1896 | ||
1897 | /*Edited by Amr - BugID_4720*/ | |
1898 | if (wilc_wlan_cfg_commit(WILC_CFG_QUERY, drvHandler)) | |
1899 | ret_size = 0; /* BugID_5213 */ | |
1900 | ||
1901 | ||
1902 | if (p->os_func.os_wait(p->cfg_wait, CFG_PKTS_TIMEOUT)) { | |
1903 | PRINT_D(TX_DBG, "Get Timed Out\n"); | |
1904 | ret_size = 0; | |
1905 | } | |
1906 | PRINT_D(GENERIC_DBG, "[WILC]Get Response received\n"); | |
1907 | p->cfg_frame_in_use = 0; | |
1908 | p->cfg_frame_offset = 0; | |
1909 | p->cfg_seq_no += 1; | |
1910 | } | |
1911 | ||
1912 | return ret_size; | |
1913 | } | |
1914 | ||
fbc2fe16 | 1915 | static int wilc_wlan_cfg_get_val(u32 wid, u8 *buffer, u32 buffer_size) |
c5c77ba1 JK |
1916 | { |
1917 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
1918 | int ret; | |
1919 | ||
ec53adfe | 1920 | ret = p->cif_func.cfg_wid_get_val((u16)wid, buffer, buffer_size); |
c5c77ba1 JK |
1921 | |
1922 | return ret; | |
1923 | } | |
1924 | ||
1925 | void wilc_bus_set_max_speed(void) | |
1926 | { | |
1927 | ||
1928 | /* Increase bus speed to max possible. */ | |
1929 | g_wlan.hif_func.hif_set_max_bus_speed(); | |
1930 | } | |
1931 | ||
1932 | void wilc_bus_set_default_speed(void) | |
1933 | { | |
1934 | ||
1935 | /* Restore bus speed to default. */ | |
1936 | g_wlan.hif_func.hif_set_default_bus_speed(); | |
1937 | } | |
fbc2fe16 | 1938 | u32 init_chip(void) |
c5c77ba1 | 1939 | { |
fbc2fe16 CL |
1940 | u32 chipid; |
1941 | u32 reg, ret = 0; | |
c5c77ba1 | 1942 | |
c5c77ba1 | 1943 | acquire_bus(ACQUIRE_ONLY); |
c5c77ba1 | 1944 | |
72ed4dc7 | 1945 | chipid = wilc_get_chipid(true); |
c5c77ba1 JK |
1946 | |
1947 | ||
1948 | ||
1949 | if ((chipid & 0xfff) != 0xa0) { | |
1950 | /** | |
1951 | * Avoid booting from boot ROM. Make sure that Drive IRQN [SDIO platform] | |
1952 | * or SD_DAT3 [SPI platform] to ?1? | |
1953 | **/ | |
1954 | /* Set cortus reset register to register control. */ | |
1955 | ret = g_wlan.hif_func.hif_read_reg(0x1118, ®); | |
1956 | if (!ret) { | |
1957 | wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1118 ...\n"); | |
1958 | return ret; | |
1959 | } | |
1960 | reg |= (1 << 0); | |
1961 | ret = g_wlan.hif_func.hif_write_reg(0x1118, reg); | |
1962 | if (!ret) { | |
1963 | wilc_debug(N_ERR, "[wilc start]: fail write reg 0x1118 ...\n"); | |
1964 | return ret; | |
1965 | } | |
1966 | /** | |
1967 | * Write branch intruction to IRAM (0x71 trap) at location 0xFFFF0000 | |
1968 | * (Cortus map) or C0000 (AHB map). | |
1969 | **/ | |
1970 | ret = g_wlan.hif_func.hif_write_reg(0xc0000, 0x71); | |
1971 | if (!ret) { | |
1972 | wilc_debug(N_ERR, "[wilc start]: fail write reg 0xc0000 ...\n"); | |
1973 | return ret; | |
1974 | } | |
1975 | } | |
1976 | ||
c5c77ba1 JK |
1977 | release_bus(RELEASE_ONLY); |
1978 | ||
1979 | return ret; | |
1980 | ||
1981 | } | |
1982 | ||
fbc2fe16 | 1983 | u32 wilc_get_chipid(u8 update) |
c5c77ba1 | 1984 | { |
fbc2fe16 | 1985 | static u32 chipid; |
c5c77ba1 JK |
1986 | /* SDIO can't read into global variables */ |
1987 | /* Use this variable as a temp, then copy to the global */ | |
fbc2fe16 CL |
1988 | u32 tempchipid = 0; |
1989 | u32 rfrevid; | |
c5c77ba1 JK |
1990 | |
1991 | if (chipid == 0 || update != 0) { | |
1992 | g_wlan.hif_func.hif_read_reg(0x1000, &tempchipid); | |
1993 | g_wlan.hif_func.hif_read_reg(0x13f4, &rfrevid); | |
1994 | if (!ISWILC1000(tempchipid)) { | |
1995 | chipid = 0; | |
1996 | goto _fail_; | |
1997 | } | |
1998 | if (tempchipid == 0x1002a0) { | |
1999 | if (rfrevid == 0x1) { /* 1002A0 */ | |
2000 | } else { /* if (rfrevid == 0x2) */ /* 1002A1 */ | |
2001 | tempchipid = 0x1002a1; | |
2002 | } | |
2003 | } else if (tempchipid == 0x1002b0) { | |
2004 | if (rfrevid == 3) { /* 1002B0 */ | |
2005 | } else if (rfrevid == 4) { /* 1002B1 */ | |
2006 | tempchipid = 0x1002b1; | |
2007 | } else { /* if(rfrevid == 5) */ /* 1002B2 */ | |
2008 | tempchipid = 0x1002b2; | |
2009 | } | |
2010 | } else { | |
2011 | } | |
2012 | ||
2013 | chipid = tempchipid; | |
2014 | } | |
2015 | _fail_: | |
2016 | return chipid; | |
2017 | } | |
2018 | ||
2019 | #ifdef COMPLEMENT_BOOT | |
51e825f7 | 2020 | u8 core_11b_ready(void) |
c5c77ba1 | 2021 | { |
fbc2fe16 | 2022 | u32 reg_val; |
c5c77ba1 JK |
2023 | |
2024 | acquire_bus(ACQUIRE_ONLY); | |
2025 | g_wlan.hif_func.hif_write_reg(0x16082c, 1); | |
2026 | g_wlan.hif_func.hif_write_reg(0x161600, 0x90); | |
2027 | g_wlan.hif_func.hif_read_reg(0x161600, ®_val); | |
2028 | release_bus(RELEASE_ONLY); | |
2029 | ||
2030 | if (reg_val == 0x90) | |
2031 | return 0; | |
2032 | else | |
2033 | return 1; | |
2034 | } | |
2035 | #endif | |
2036 | ||
2037 | int wilc_wlan_init(wilc_wlan_inp_t *inp, wilc_wlan_oup_t *oup) | |
2038 | { | |
2039 | ||
2040 | int ret = 0; | |
2041 | ||
2042 | PRINT_D(INIT_DBG, "Initializing WILC_Wlan ...\n"); | |
2043 | ||
2044 | memset((void *)&g_wlan, 0, sizeof(wilc_wlan_dev_t)); | |
2045 | ||
2046 | /** | |
2047 | * store the input | |
2048 | **/ | |
2049 | memcpy((void *)&g_wlan.os_func, (void *)&inp->os_func, sizeof(wilc_wlan_os_func_t)); | |
2050 | memcpy((void *)&g_wlan.io_func, (void *)&inp->io_func, sizeof(wilc_wlan_io_func_t)); | |
2051 | memcpy((void *)&g_wlan.net_func, (void *)&inp->net_func, sizeof(wilc_wlan_net_func_t)); | |
2052 | memcpy((void *)&g_wlan.indicate_func, (void *)&inp->indicate_func, sizeof(wilc_wlan_net_func_t)); | |
2053 | g_wlan.hif_lock = inp->os_context.hif_critical_section; | |
2054 | g_wlan.txq_lock = inp->os_context.txq_critical_section; | |
2055 | ||
2056 | /*Added by Amr - BugID_4720*/ | |
2057 | g_wlan.txq_add_to_head_lock = inp->os_context.txq_add_to_head_critical_section; | |
2058 | ||
2059 | /*Added by Amr - BugID_4720*/ | |
2060 | g_wlan.txq_spinlock = inp->os_context.txq_spin_lock; | |
2061 | ||
2062 | g_wlan.rxq_lock = inp->os_context.rxq_critical_section; | |
2063 | g_wlan.txq_wait = inp->os_context.txq_wait_event; | |
2064 | g_wlan.rxq_wait = inp->os_context.rxq_wait_event; | |
2065 | g_wlan.cfg_wait = inp->os_context.cfg_wait_event; | |
2066 | g_wlan.tx_buffer_size = inp->os_context.tx_buffer_size; | |
2067 | #if defined (MEMORY_STATIC) | |
2068 | g_wlan.rx_buffer_size = inp->os_context.rx_buffer_size; | |
2069 | #endif | |
c5c77ba1 JK |
2070 | /*** |
2071 | * host interface init | |
2072 | **/ | |
c5c77ba1 JK |
2073 | if ((inp->io_func.io_type & 0x1) == HIF_SDIO) { |
2074 | if (!hif_sdio.hif_init(inp, wilc_debug)) { | |
2075 | /* EIO 5 */ | |
2076 | ret = -5; | |
2077 | goto _fail_; | |
2078 | } | |
2079 | memcpy((void *)&g_wlan.hif_func, &hif_sdio, sizeof(wilc_hif_func_t)); | |
2080 | } else { | |
2081 | if ((inp->io_func.io_type & 0x1) == HIF_SPI) { | |
2082 | /** | |
2083 | * TODO: | |
2084 | **/ | |
2085 | if (!hif_spi.hif_init(inp, wilc_debug)) { | |
2086 | /* EIO 5 */ | |
2087 | ret = -5; | |
2088 | goto _fail_; | |
2089 | } | |
2090 | memcpy((void *)&g_wlan.hif_func, &hif_spi, sizeof(wilc_hif_func_t)); | |
2091 | } else { | |
2092 | /* EIO 5 */ | |
2093 | ret = -5; | |
2094 | goto _fail_; | |
2095 | } | |
2096 | } | |
2097 | ||
2098 | /*** | |
2099 | * mac interface init | |
2100 | **/ | |
2101 | if (!mac_cfg.cfg_init(wilc_debug)) { | |
2102 | /* ENOBUFS 105 */ | |
2103 | ret = -105; | |
2104 | goto _fail_; | |
2105 | } | |
2106 | memcpy((void *)&g_wlan.cif_func, &mac_cfg, sizeof(wilc_cfg_func_t)); | |
2107 | ||
2108 | ||
2109 | /** | |
2110 | * alloc tx, rx buffer | |
2111 | **/ | |
b1413b60 | 2112 | if (g_wlan.tx_buffer == NULL) |
f019b9d9 | 2113 | g_wlan.tx_buffer = kmalloc(g_wlan.tx_buffer_size, GFP_KERNEL); |
7a8fd841 | 2114 | PRINT_D(TX_DBG, "g_wlan.tx_buffer = %p\n", g_wlan.tx_buffer); |
c5c77ba1 | 2115 | |
b1413b60 | 2116 | if (g_wlan.tx_buffer == NULL) { |
c5c77ba1 JK |
2117 | /* ENOBUFS 105 */ |
2118 | ret = -105; | |
2119 | PRINT_ER("Can't allocate Tx Buffer"); | |
2120 | goto _fail_; | |
2121 | } | |
2122 | ||
2123 | /* rx_buffer is not used unless we activate USE_MEM STATIC which is not applicable, allocating such memory is useless*/ | |
2124 | #if defined (MEMORY_STATIC) | |
b1413b60 | 2125 | if (g_wlan.rx_buffer == NULL) |
f019b9d9 | 2126 | g_wlan.rx_buffer = kmalloc(g_wlan.rx_buffer_size, GFP_KERNEL); |
7a8fd841 | 2127 | PRINT_D(TX_DBG, "g_wlan.rx_buffer =%p\n", g_wlan.rx_buffer); |
b1413b60 | 2128 | if (g_wlan.rx_buffer == NULL) { |
c5c77ba1 JK |
2129 | /* ENOBUFS 105 */ |
2130 | ret = -105; | |
2131 | PRINT_ER("Can't allocate Rx Buffer"); | |
2132 | goto _fail_; | |
2133 | } | |
2134 | #endif | |
2135 | ||
2136 | /** | |
2137 | * export functions | |
2138 | **/ | |
2139 | oup->wlan_firmware_download = wilc_wlan_firmware_download; | |
2140 | oup->wlan_start = wilc_wlan_start; | |
2141 | oup->wlan_stop = wilc_wlan_stop; | |
2142 | oup->wlan_add_to_tx_que = wilc_wlan_txq_add_net_pkt; | |
2143 | oup->wlan_handle_tx_que = wilc_wlan_handle_txq; | |
2144 | oup->wlan_handle_rx_que = wilc_wlan_handle_rxq; | |
c5c77ba1 JK |
2145 | oup->wlan_handle_rx_isr = wilc_handle_isr; |
2146 | oup->wlan_cleanup = wilc_wlan_cleanup; | |
2147 | oup->wlan_cfg_set = wilc_wlan_cfg_set; | |
2148 | oup->wlan_cfg_get = wilc_wlan_cfg_get; | |
2149 | oup->wlan_cfg_get_value = wilc_wlan_cfg_get_val; | |
2150 | ||
2151 | /*Bug3959: transmitting mgmt frames received from host*/ | |
2152 | #if defined(WILC_AP_EXTERNAL_MLME) || defined(WILC_P2P) | |
2153 | oup->wlan_add_mgmt_to_tx_que = wilc_wlan_txq_add_mgmt_pkt; | |
c5c77ba1 JK |
2154 | #endif |
2155 | ||
2156 | if (!init_chip()) { | |
2157 | /* EIO 5 */ | |
2158 | ret = -5; | |
2159 | goto _fail_; | |
2160 | } | |
2161 | #ifdef TCP_ACK_FILTER | |
2162 | Init_TCP_tracking(); | |
2163 | #endif | |
2164 | ||
c5c77ba1 JK |
2165 | return 1; |
2166 | ||
2167 | _fail_: | |
2168 | ||
c5c77ba1 | 2169 | #ifdef MEMORY_STATIC |
a18dd630 GKH |
2170 | kfree(g_wlan.rx_buffer); |
2171 | g_wlan.rx_buffer = NULL; | |
c5c77ba1 | 2172 | #endif |
a18dd630 GKH |
2173 | kfree(g_wlan.tx_buffer); |
2174 | g_wlan.tx_buffer = NULL; | |
c5c77ba1 | 2175 | |
c5c77ba1 JK |
2176 | return ret; |
2177 | ||
2178 | } | |
2179 | ||
2180 | #define BIT31 (1 << 31) | |
72ed4dc7 | 2181 | u16 Set_machw_change_vir_if(bool bValue) |
c5c77ba1 | 2182 | { |
d85f5326 | 2183 | u16 ret; |
4e4467fd | 2184 | u32 reg; |
c5c77ba1 JK |
2185 | |
2186 | /*Reset WILC_CHANGING_VIR_IF register to allow adding futrue keys to CE H/W*/ | |
5e150b52 | 2187 | mutex_lock((&g_wlan)->hif_lock); |
c5c77ba1 JK |
2188 | ret = (&g_wlan)->hif_func.hif_read_reg(WILC_CHANGING_VIR_IF, ®); |
2189 | if (!ret) { | |
2190 | PRINT_ER("Error while Reading reg WILC_CHANGING_VIR_IF\n"); | |
2191 | } | |
2192 | ||
78174ada | 2193 | if (bValue) |
c5c77ba1 | 2194 | reg |= (BIT31); |
78174ada | 2195 | else |
c5c77ba1 | 2196 | reg &= ~(BIT31); |
c5c77ba1 JK |
2197 | |
2198 | ret = (&g_wlan)->hif_func.hif_write_reg(WILC_CHANGING_VIR_IF, reg); | |
2199 | ||
2200 | if (!ret) { | |
2201 | PRINT_ER("Error while writing reg WILC_CHANGING_VIR_IF\n"); | |
2202 | } | |
5e150b52 | 2203 | mutex_unlock((&g_wlan)->hif_lock); |
c5c77ba1 JK |
2204 | |
2205 | return ret; | |
2206 | } |