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staging: wilc1000: use u8 instead of uint8_t
[deliverable/linux.git] / drivers / staging / wilc1000 / wilc_wlan.h
CommitLineData
c5c77ba1
JK		 1#ifndef WILC_WLAN_H
2#define WILC_WLAN_H
3
36a24b4e 4#include "wilc_oswrapper.h"
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JK		 5
6
7#define ISWILC1000(id) (((id & 0xfffff000) == 0x100000) ? 1 : 0)
8
9
10/********************************************
11 *
12 * Mac eth header length
13 *
14 ********************************************/
15#define DRIVER_HANDLER_SIZE 4
16#define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */
17#define SUB_MSDU_HEADER_LENGTH 14
18#define SNAP_HDR_LEN 8
19#define ETHERNET_HDR_LEN 14
20#define WORD_ALIGNMENT_PAD 0
21
22#define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + SUB_MSDU_HEADER_LENGTH + \
23 SNAP_HDR_LEN - ETHERNET_HDR_LEN + WORD_ALIGNMENT_PAD)
24
25/*Bug3959: transmitting mgmt frames received from host*/
26#define HOST_HDR_OFFSET 4
27#define ETHERNET_HDR_LEN 14
28#define IP_HDR_LEN 20
29#define IP_HDR_OFFSET ETHERNET_HDR_LEN
30#define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
31#define UDP_HDR_LEN 8
32#define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
33#define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
34
35#define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
36 ETH_CONFIG_PKT_HDR_LEN)
37#define ACTION 0xD0
38#define PROBE_REQ 0x40
c5c77ba1
JK		 39
40/********************************************
41 *
42 * Endian Conversion
43 *
44 ********************************************/
45
46#define BYTE_SWAP(val) ((((val) & 0x000000FF) << 24) + \
47 (((val) & 0x0000FF00) << 8) + \
48 (((val) & 0x00FF0000) >> 8) + \
49 (((val) & 0xFF000000) >> 24))
50
51/********************************************
52 *
53 * Register Defines
54 *
55 ********************************************/
56#define WILC_PERIPH_REG_BASE 0x1000
57/*BugID_5137*/
58#define WILC_CHANGING_VIR_IF (0x108c)
59#define WILC_CHIPID (WILC_PERIPH_REG_BASE)
60#define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
61#define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
62#define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
63#define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
64#define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
65#define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
66#define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
67#define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
68#define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
69#define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428)
70#define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
71#define WILC_INTR_ENABLE (WILC_INTR_REG_BASE)
72#define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
73
74#define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
75#define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
76#define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
77#define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
78
79#define WILC_VMM_TBL_SIZE 64
80#define WILC_VMM_TX_TBL_BASE (0x150400)
81#define WILC_VMM_RX_TBL_BASE (0x150500)
82
83#define WILC_VMM_BASE 0x150000
84#define WILC_VMM_CORE_CTL (WILC_VMM_BASE)
85#define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
86#define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
87#define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
88#define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
89#define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
90#define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
91#define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
92
93#define WILC_SPI_REG_BASE 0xe800
94#define WILC_SPI_CTL (WILC_SPI_REG_BASE)
95#define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
96#define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
97#define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
98#define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
99#define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
100#define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
101#define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
102
103#define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - WILC_SPI_REG_BASE)
104
105#define WILC_AHB_DATA_MEM_BASE 0x30000
106#define WILC_AHB_SHARE_MEM_BASE 0xd0000
107
108#define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE /* Bug 4477 fix */
109#define WILC_VMM_TBL_RX_SHADOW_SIZE (256) /* Bug 4477 fix */
110
111#define WILC_GP_REG_0 0x149c
112#define WILC_GP_REG_1 0x14a0
113
114#define rHAVE_SDIO_IRQ_GPIO_BIT (0)
115#define rHAVE_USE_PMU_BIT (1)
116#define rHAVE_SLEEP_CLK_SRC_RTC_BIT (2)
117#define rHAVE_SLEEP_CLK_SRC_XO_BIT (3)
118#define rHAVE_EXT_PA_INV_TX_RX_BIT (4)
119#define rHAVE_LEGACY_RF_SETTINGS_BIT (5)
120#define rHAVE_XTAL_24_BIT (6)
121#define rHAVE_DISABLE_WILC_UART_BIT (7)
122
123
124#define WILC_HAVE_SDIO_IRQ_GPIO (1 << rHAVE_SDIO_IRQ_GPIO_BIT)
125#define WILC_HAVE_USE_PMU (1 << rHAVE_USE_PMU_BIT)
126#define WILC_HAVE_SLEEP_CLK_SRC_RTC (1 << rHAVE_SLEEP_CLK_SRC_RTC_BIT)
127#define WILC_HAVE_SLEEP_CLK_SRC_XO (1 << rHAVE_SLEEP_CLK_SRC_XO_BIT)
128#define WILC_HAVE_EXT_PA_INV_TX_RX (1 << rHAVE_EXT_PA_INV_TX_RX_BIT)
129#define WILC_HAVE_LEGACY_RF_SETTINGS (1 << rHAVE_LEGACY_RF_SETTINGS_BIT)
130#define WILC_HAVE_XTAL_24 (1 << rHAVE_XTAL_24_BIT)
131#define WILC_HAVE_DISABLE_WILC_UART (1 << rHAVE_DISABLE_WILC_UART_BIT)
132
133
134/********************************************
135 *
136 * Wlan Defines
137 *
138 ********************************************/
139#define WILC_CFG_PKT 1
140#define WILC_NET_PKT 0
141/*Bug3959: transmitting mgmt frames received from host*/
142#ifdef WILC_AP_EXTERNAL_MLME
143#define WILC_MGMT_PKT 2
144
c5c77ba1
JK		 145#endif /*WILC_AP_EXTERNAL_MLME*/
146#define WILC_CFG_SET 1
147#define WILC_CFG_QUERY 0
148
149#define WILC_CFG_RSP 1
150#define WILC_CFG_RSP_STATUS 2
151#define WILC_CFG_RSP_SCAN 3
152
153#ifdef WILC_SDIO
154#define WILC_PLL_TO 4
155#else
156#define WILC_PLL_TO 2
157#endif
158
159
160#define ABORT_INT (1 << 31)
161
162/*******************************************/
163/* E0 and later Interrupt flags. */
164/*******************************************/
165/*******************************************/
166/* E0 and later Interrupt flags. */
167/* IRQ Status word */
168/* 15:0 = DMA count in words. */
169/* 16: INT0 flag */
170/* 17: INT1 flag */
171/* 18: INT2 flag */
172/* 19: INT3 flag */
173/* 20: INT4 flag */
174/* 21: INT5 flag */
175/*******************************************/
176#define IRG_FLAGS_OFFSET 16
177#define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1)
178#define INT_0 (1 << (IRG_FLAGS_OFFSET))
179#define INT_1 (1 << (IRG_FLAGS_OFFSET + 1))
180#define INT_2 (1 << (IRG_FLAGS_OFFSET + 2))
181#define INT_3 (1 << (IRG_FLAGS_OFFSET + 3))
182#define INT_4 (1 << (IRG_FLAGS_OFFSET + 4))
183#define INT_5 (1 << (IRG_FLAGS_OFFSET + 5))
184#define MAX_NUM_INT (6)
185
186/*******************************************/
187/* E0 and later Interrupt flags. */
188/* IRQ Clear word */
189/* 0: Clear INT0 */
190/* 1: Clear INT1 */
191/* 2: Clear INT2 */
192/* 3: Clear INT3 */
193/* 4: Clear INT4 */
194/* 5: Clear INT5 */
195/* 6: Select VMM table 1 */
196/* 7: Select VMM table 2 */
197/* 8: Enable VMM */
198/*******************************************/
199#define CLR_INT0 (1 << 0)
200#define CLR_INT1 (1 << 1)
201#define CLR_INT2 (1 << 2)
202#define CLR_INT3 (1 << 3)
203#define CLR_INT4 (1 << 4)
204#define CLR_INT5 (1 << 5)
205#define SEL_VMM_TBL0 (1 << 6)
206#define SEL_VMM_TBL1 (1 << 7)
207#define EN_VMM (1 << 8)
208
209#define DATA_INT_EXT INT_0
210#define PLL_INT_EXT INT_1
211#define SLEEP_INT_EXT INT_2
212#define ALL_INT_EXT (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT)
213#define NUM_INT_EXT (3)
214
215#define DATA_INT_CLR CLR_INT0
216#define PLL_INT_CLR CLR_INT1
217#define SLEEP_INT_CLR CLR_INT2
218
219#define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
220#define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
221
222
223/*time for expiring the semaphores of cfg packets*/
224#define CFG_PKTS_TIMEOUT 2000
225/********************************************
226 *
227 * Debug Type
228 *
229 ********************************************/
230typedef void (*wilc_debug_func)(uint32_t, char *, ...);
231
232/********************************************
233 *
234 * Tx/Rx Queue Structure
235 *
236 ********************************************/
237
238struct txq_entry_t {
239 struct txq_entry_t *next;
240 struct txq_entry_t *prev;
241 int type;
242 int tcp_PendingAck_index;
51e825f7 243 u8 *buffer;
c5c77ba1
JK		 244 int buffer_size;
245 void *priv;
246 int status;
247 void (*tx_complete_func)(void *, int);
248};
249
250struct rxq_entry_t {
251 struct rxq_entry_t *next;
51e825f7 252 u8 *buffer;
c5c77ba1
JK		 253 int buffer_size;
254};
255
256/********************************************
257 *
258 * Host IF Structure
259 *
260 ********************************************/
261
262typedef struct {
263 int (*hif_init)(wilc_wlan_inp_t *, wilc_debug_func);
264 int (*hif_deinit)(void *);
265 int (*hif_read_reg)(uint32_t, uint32_t *);
266 int (*hif_write_reg)(uint32_t, uint32_t);
51e825f7
CL		 267 int (*hif_block_rx)(uint32_t, u8 *, uint32_t);
268 int (*hif_block_tx)(uint32_t, u8 *, uint32_t);
c5c77ba1
JK		 269 int (*hif_sync)(void);
270 int (*hif_clear_int)(void);
271 int (*hif_read_int)(uint32_t *);
272 int (*hif_clear_int_ext)(uint32_t);
273 int (*hif_read_size)(uint32_t *);
51e825f7
CL		 274 int (*hif_block_tx_ext)(uint32_t, u8 *, uint32_t);
275 int (*hif_block_rx_ext)(uint32_t, u8 *, uint32_t);
c5c77ba1
JK		 276 int (*hif_sync_ext)(int);
277 void (*hif_set_max_bus_speed)(void);
278 void (*hif_set_default_bus_speed)(void);
279} wilc_hif_func_t;
280
281/********************************************
282 *
283 * Configuration Structure
284 *
285 ********************************************/
286
287#define MAX_CFG_FRAME_SIZE 1468
288
289typedef struct {
51e825f7
CL		 290 u8 ether_header[14];
291 u8 ip_header[20];
292 u8 udp_header[8];
293 u8 wid_header[8];
294 u8 frame[MAX_CFG_FRAME_SIZE];
c5c77ba1
JK		 295} wilc_cfg_frame_t;
296
297typedef struct {
51e825f7 298 int (*wlan_tx)(u8 *, uint32_t, wilc_tx_complete_func_t);
c5c77ba1
JK		 299} wilc_wlan_cfg_func_t;
300
301typedef struct {
302 int type;
303 uint32_t seq_no;
304} wilc_cfg_rsp_t;
305
306typedef struct {
51e825f7
CL		 307 int (*cfg_wid_set)(u8 *, uint32_t, uint16_t, u8 *, int);
308 int (*cfg_wid_get)(u8 *, uint32_t, uint16_t);
309 int (*cfg_wid_get_val)(uint16_t, u8 *, uint32_t);
310 int (*rx_indicate)(u8 *, int, wilc_cfg_rsp_t *);
c5c77ba1
JK		 311 int (*cfg_init)(wilc_debug_func);
312} wilc_cfg_func_t;
313
314#endif
Linux kernel - Deliverables
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