[deliverable/linux.git] / drivers / staging / winbond / wb35reg_s.h

#ifndef __WINBOND_WB35REG_S_H
#define __WINBOND_WB35REG_S_H

#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/atomic.h>

/* =========================================================================
 *
 *			HAL setting function
 *
 *		========================================
 *		|Uxx| 	|Dxx|	|Mxx|	|BB|	|RF|
 *		========================================
 *			|					|
 *		Wb35Reg_Read		Wb35Reg_Write
 *
 *		----------------------------------------
 *				WbUsb_CallUSBDASync	supplied By WbUsb module
 * ==========================================================================
 */
#define GetBit(dwData, i)	(dwData & (0x00000001 << i))
#define SetBit(dwData, i)	(dwData | (0x00000001 << i))
#define ClearBit(dwData, i)	(dwData & ~(0x00000001 << i))

#define	IGNORE_INCREMENT	0
#define	AUTO_INCREMENT		0
#define	NO_INCREMENT		1
#define REG_DIRECTION(_x, _y)	((_y)->DIRECT == 0 ? usb_rcvctrlpipe(_x, 0) : usb_sndctrlpipe(_x, 0))
#define REG_BUF_SIZE(_x)	((_x)->bRequest == 0x04 ? cpu_to_le16((_x)->wLength) : 4)

#define BB48_DEFAULT_AL2230_11B		0x0033447c
#define BB4C_DEFAULT_AL2230_11B		0x0A00FEFF
#define BB48_DEFAULT_AL2230_11G		0x00332C1B
#define BB4C_DEFAULT_AL2230_11G		0x0A00FEFF


#define BB48_DEFAULT_WB242_11B		0x00292315	/* backoff  2dB */
#define BB4C_DEFAULT_WB242_11B		0x0800FEFF	/* backoff  2dB */
#define BB48_DEFAULT_WB242_11G		0x00453B24
#define BB4C_DEFAULT_WB242_11G		0x0E00FEFF

/*
 * ====================================
 *  Default setting for Mxx
 * ====================================
 */
#define DEFAULT_CWMIN			31	/* (M2C) CWmin. Its value is in the range 0-31. */
#define DEFAULT_CWMAX			1023	/* (M2C) CWmax. Its value is in the range 0-1023. */
#define DEFAULT_AID			1	/* (M34) AID. Its value is in the range 1-2007. */

#ifdef _USE_FALLBACK_RATE_
#define DEFAULT_RATE_RETRY_LIMIT	2	/* (M38) as named */
#else
#define DEFAULT_RATE_RETRY_LIMIT	7	/* (M38) as named */
#endif

#define DEFAULT_LONG_RETRY_LIMIT	7	/* (M38) LongRetryLimit. Its value is in the range 0-15. */
#define DEFAULT_SHORT_RETRY_LIMIT	7	/* (M38) ShortRetryLimit. Its value is in the range 0-15. */
#define DEFAULT_PIFST			25	/* (M3C) PIFS Time. Its value is in the range 0-65535. */
#define DEFAULT_EIFST			354	/* (M3C) EIFS Time. Its value is in the range 0-1048575. */
#define DEFAULT_DIFST			45	/* (M3C) DIFS Time. Its value is in the range 0-65535. */
#define DEFAULT_SIFST			5	/* (M3C) SIFS Time. Its value is in the range 0-65535. */
#define DEFAULT_OSIFST			10	/* (M3C) Original SIFS Time. Its value is in the range 0-15. */
#define DEFAULT_ATIMWD			0	/* (M40) ATIM Window. Its value is in the range 0-65535. */
#define DEFAULT_SLOT_TIME		20	/* (M40) ($) SlotTime. Its value is in the range 0-255. */
#define DEFAULT_MAX_TX_MSDU_LIFE_TIME	512	/* (M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. */
#define DEFAULT_BEACON_INTERVAL		500	/* (M48) Beacon Interval. Its value is in the range 0-65535. */
#define DEFAULT_PROBE_DELAY_TIME	200	/* (M48) Probe Delay Time. Its value is in the range 0-65535. */
#define DEFAULT_PROTOCOL_VERSION	0	/* (M4C) */
#define DEFAULT_MAC_POWER_STATE		2	/* (M4C) 2: MAC at power active */
#define DEFAULT_DTIM_ALERT_TIME		0


struct wb35_reg_queue {
	struct urb	*urb;
	void		*pUsbReq;
	void		*Next;
	union {
		u32	VALUE;
		u32	*pBuffer;
	};
	u8		RESERVED[4];	/* space reserved for communication */
	u16		INDEX;		/* For storing the register index */
	u8		RESERVED_VALID;	/* Indicate whether the RESERVED space is valid at this command. */
	u8		DIRECT;		/* 0:In   1:Out */
};

/*
 * ====================================
 * Internal variable for module
 * ====================================
 */
#define MAX_SQ3_FILTER_SIZE		5
struct wb35_reg {
	/*
	 * ============================
	 *  Register Bank backup
	 * ============================
	 */
	u32	U1B0;			/* bit16 record the h/w radio on/off status */
	u32	U1BC_LEDConfigure;
	u32	D00_DmaControl;
	u32	M00_MacControl;
	union {
		struct {
			u32	M04_MulticastAddress1;
			u32	M08_MulticastAddress2;
		};
		u8		Multicast[8];	/* contents of card multicast registers */
	};

	u32	M24_MacControl;
	u32	M28_MacControl;
	u32	M2C_MacControl;
	u32	M38_MacControl;
	u32	M3C_MacControl;
	u32	M40_MacControl;
	u32	M44_MacControl;
	u32	M48_MacControl;
	u32	M4C_MacStatus;
	u32	M60_MacControl;
	u32	M68_MacControl;
	u32	M70_MacControl;
	u32	M74_MacControl;
	u32	M78_ERPInformation;
	u32	M7C_MacControl;
	u32	M80_MacControl;
	u32	M84_MacControl;
	u32	M88_MacControl;
	u32	M98_MacControl;

	/* Baseband register */
	u32	BB0C;	/* Used for LNA calculation */
	u32	BB2C;
	u32	BB30;	/* 11b acquisition control register */
	u32	BB3C;
	u32	BB48;
	u32	BB4C;
	u32	BB50;	/* mode control register */
	u32	BB54;
	u32	BB58;	/* IQ_ALPHA */
	u32	BB5C;	/* For test */
	u32	BB60;	/* for WTO read value */

	/* VM */
	spinlock_t	EP0VM_spin_lock; /* 4B */
	u32		EP0VM_status; /* $$ */
	struct wb35_reg_queue *reg_first;
	struct wb35_reg_queue *reg_last;
	atomic_t	RegFireCount;

	/* Hardware status */
	u8	EP0vm_state;
	u8	mac_power_save;
	u8	EEPROMPhyType; /*
				* 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
				* 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
				* 32 ~ Reserved
				* 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
				* 48 ~ 255 ARE RESERVED.
				*/
	u8	EEPROMRegion;	/* Region setting in EEPROM */

	u32	SyncIoPause; /* If user use the Sync Io to access Hw, then pause the async access */

	u8	LNAValue[4]; /* Table for speed up running */
	u32	SQ3_filter[MAX_SQ3_FILTER_SIZE];
	u32	SQ3_index;
};
#endif
Commit	Line	Data
80aba536 PE	1	#ifndef __WINBOND_WB35REG_S_H
	2	#define __WINBOND_WB35REG_S_H
	3
	4	#include <linux/spinlock.h>
	5	#include <linux/types.h>
	6	#include <asm/atomic.h>
	7
25e47dfc LL	8	/* =========================================================================
	9	*
	10	* HAL setting function
	11	*
	12	* ========================================
	13	* \|Uxx\| \|Dxx\| \|Mxx\| \|BB\| \|RF\|
	14	* ========================================
	15	* \| \|
	16	* Wb35Reg_Read Wb35Reg_Write
	17	*
	18	* ----------------------------------------
	19	* WbUsb_CallUSBDASync supplied By WbUsb module
	20	* ==========================================================================
	21	*/
	22	#define GetBit(dwData, i) (dwData & (0x00000001 << i))
	23	#define SetBit(dwData, i) (dwData \| (0x00000001 << i))
	24	#define ClearBit(dwData, i) (dwData & ~(0x00000001 << i))
	25
	26	#define IGNORE_INCREMENT 0
	27	#define AUTO_INCREMENT 0
	28	#define NO_INCREMENT 1
	29	#define REG_DIRECTION(_x, _y) ((_y)->DIRECT == 0 ? usb_rcvctrlpipe(_x, 0) : usb_sndctrlpipe(_x, 0))
	30	#define REG_BUF_SIZE(_x) ((_x)->bRequest == 0x04 ? cpu_to_le16((_x)->wLength) : 4)
	31
66101de1 PM	32	#define BB48_DEFAULT_AL2230_11B 0x0033447c
	33	#define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF
	34	#define BB48_DEFAULT_AL2230_11G 0x00332C1B
	35	#define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF
	36
	37
25e47dfc LL	38	#define BB48_DEFAULT_WB242_11B 0x00292315 /* backoff 2dB */
25e47dfc LL	39	#define BB4C_DEFAULT_WB242_11B 0x0800FEFF /* backoff 2dB */
66101de1 PM	40	#define BB48_DEFAULT_WB242_11G 0x00453B24
	41	#define BB4C_DEFAULT_WB242_11G 0x0E00FEFF
	42
25e47dfc LL	43	/*
	44	* ====================================
	45	* Default setting for Mxx
	46	* ====================================
	47	*/
	48	#define DEFAULT_CWMIN 31 /* (M2C) CWmin. Its value is in the range 0-31. */
	49	#define DEFAULT_CWMAX 1023 /* (M2C) CWmax. Its value is in the range 0-1023. */
	50	#define DEFAULT_AID 1 /* (M34) AID. Its value is in the range 1-2007. */
66101de1 PM	51
66101de1 PM	52	#ifdef _USE_FALLBACK_RATE_
25e47dfc	53	#define DEFAULT_RATE_RETRY_LIMIT 2 /* (M38) as named */
66101de1	54	#else
25e47dfc	55	#define DEFAULT_RATE_RETRY_LIMIT 7 /* (M38) as named */
66101de1 PM	56	#endif
66101de1 PM	57
25e47dfc LL	58	#define DEFAULT_LONG_RETRY_LIMIT 7 /* (M38) LongRetryLimit. Its value is in the range 0-15. */
	59	#define DEFAULT_SHORT_RETRY_LIMIT 7 /* (M38) ShortRetryLimit. Its value is in the range 0-15. */
	60	#define DEFAULT_PIFST 25 /* (M3C) PIFS Time. Its value is in the range 0-65535. */
	61	#define DEFAULT_EIFST 354 /* (M3C) EIFS Time. Its value is in the range 0-1048575. */
	62	#define DEFAULT_DIFST 45 /* (M3C) DIFS Time. Its value is in the range 0-65535. */
	63	#define DEFAULT_SIFST 5 /* (M3C) SIFS Time. Its value is in the range 0-65535. */
	64	#define DEFAULT_OSIFST 10 /* (M3C) Original SIFS Time. Its value is in the range 0-15. */
	65	#define DEFAULT_ATIMWD 0 /* (M40) ATIM Window. Its value is in the range 0-65535. */
	66	#define DEFAULT_SLOT_TIME 20 /* (M40) ($) SlotTime. Its value is in the range 0-255. */
	67	#define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 /* (M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. */
	68	#define DEFAULT_BEACON_INTERVAL 500 /* (M48) Beacon Interval. Its value is in the range 0-65535. */
	69	#define DEFAULT_PROBE_DELAY_TIME 200 /* (M48) Probe Delay Time. Its value is in the range 0-65535. */
	70	#define DEFAULT_PROTOCOL_VERSION 0 /* (M4C) */
	71	#define DEFAULT_MAC_POWER_STATE 2 /* (M4C) 2: MAC at power active */
	72	#define DEFAULT_DTIM_ALERT_TIME 0
66101de1 PM	73
66101de1 PM	74
f37435ce	75	struct wb35_reg_queue {
25e47dfc	76	struct urb *urb;
f37435ce PE	77	void *pUsbReq;
	78	void *Next;
	79	union {
66101de1	80	u32 VALUE;
f37435ce	81	u32 *pBuffer;
66101de1	82	};
25e47dfc LL	83	u8 RESERVED[4]; /* space reserved for communication */
	84	u16 INDEX; /* For storing the register index */
	85	u8 RESERVED_VALID; /* Indicate whether the RESERVED space is valid at this command. */
	86	u8 DIRECT; /* 0:In 1:Out */
f37435ce	87	};
66101de1	88
25e47dfc LL	89	/*
	90	* ====================================
	91	* Internal variable for module
	92	* ====================================
	93	*/
66101de1	94	#define MAX_SQ3_FILTER_SIZE 5
65144de7	95	struct wb35_reg {
25e47dfc LL	96	/*
	97	* ============================
	98	* Register Bank backup
	99	* ============================
	100	*/
	101	u32 U1B0; /* bit16 record the h/w radio on/off status */
66101de1 PM	102	u32 U1BC_LEDConfigure;
	103	u32 D00_DmaControl;
	104	u32 M00_MacControl;
	105	union {
	106	struct {
	107	u32 M04_MulticastAddress1;
	108	u32 M08_MulticastAddress2;
	109	};
25e47dfc	110	u8 Multicast[8]; /* contents of card multicast registers */
66101de1 PM	111	};
	112
	113	u32 M24_MacControl;
	114	u32 M28_MacControl;
	115	u32 M2C_MacControl;
	116	u32 M38_MacControl;
25e47dfc	117	u32 M3C_MacControl;
66101de1	118	u32 M40_MacControl;
25e47dfc LL	119	u32 M44_MacControl;
25e47dfc LL	120	u32 M48_MacControl;
66101de1	121	u32 M4C_MacStatus;
25e47dfc LL	122	u32 M60_MacControl;
	123	u32 M68_MacControl;
	124	u32 M70_MacControl;
	125	u32 M74_MacControl;
	126	u32 M78_ERPInformation;
	127	u32 M7C_MacControl;
	128	u32 M80_MacControl;
	129	u32 M84_MacControl;
	130	u32 M88_MacControl;
	131	u32 M98_MacControl;
	132
	133	/* Baseband register */
	134	u32 BB0C; /* Used for LNA calculation */
	135	u32 BB2C;
	136	u32 BB30; /* 11b acquisition control register */
66101de1	137	u32 BB3C;
25e47dfc LL	138	u32 BB48;
	139	u32 BB4C;
	140	u32 BB50; /* mode control register */
66101de1	141	u32 BB54;
25e47dfc LL	142	u32 BB58; /* IQ_ALPHA */
	143	u32 BB5C; /* For test */
	144	u32 BB60; /* for WTO read value */
	145
	146	/* VM */
	147	spinlock_t EP0VM_spin_lock; /* 4B */
	148	u32 EP0VM_status; /* $$ */
f37435ce PE	149	struct wb35_reg_queue *reg_first;
f37435ce PE	150	struct wb35_reg_queue *reg_last;
25e47dfc	151	atomic_t RegFireCount;
66101de1	152
25e47dfc	153	/* Hardware status */
66101de1 PM	154	u8 EP0vm_state;
66101de1 PM	155	u8 mac_power_save;
25e47dfc LL	156	u8 EEPROMPhyType; /*
	157	* 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
	158	* 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
	159	* 32 ~ Reserved
	160	* 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
	161	* 48 ~ 255 ARE RESERVED.
	162	*/
	163	u8 EEPROMRegion; /* Region setting in EEPROM */
	164
	165	u32 SyncIoPause; /* If user use the Sync Io to access Hw, then pause the async access */
	166
	167	u8 LNAValue[4]; /* Table for speed up running */
66101de1 PM	168	u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];
66101de1 PM	169	u32 SQ3_index;
65144de7	170	};
80aba536	171	#endif