[deliverable/linux.git] / drivers / staging / winbond / wbhal.h

#ifndef __WINBOND_WBHAL_S_H
#define __WINBOND_WBHAL_S_H

#include <linux/types.h>
#include <linux/if_ether.h> /* for ETH_ALEN */

#define HAL_LED_SET_MASK	0x001c
#define HAL_LED_SET_SHIFT	2

/* supported RF type */
#define RF_MAXIM_2825		0
#define RF_MAXIM_2827		1
#define RF_MAXIM_2828		2
#define RF_MAXIM_2829		3
#define RF_MAXIM_V1		15
#define RF_AIROHA_2230		16
#define RF_AIROHA_7230		17
#define RF_AIROHA_2230S		18
#define RF_WB_242		33
#define RF_WB_242_1		34
#define RF_DECIDE_BY_INF	255

/*
 * ----------------------------------------------------------------
 * The follow define connect to upper layer
 *	User must modify for connection between HAL and upper layer
 * ----------------------------------------------------------------
 */

/*
 * ==============================
 * Common define
 * ==============================
 */
/* Bit 5 */
#define HAL_USB_MODE_BURST(_H)			(_H->SoftwareSet & 0x20)

/* Scan interval */
#define SCAN_MAX_CHNL_TIME			(50)

/* For TxL2 Frame typr recognise */
#define FRAME_TYPE_802_3_DATA			0
#define FRAME_TYPE_802_11_MANAGEMENT		1
#define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE	2
#define FRAME_TYPE_802_11_CONTROL		3
#define FRAME_TYPE_802_11_DATA			4
#define FRAME_TYPE_PROMISCUOUS			5

/* The follow definition is used for convert the frame------------ */
#define DOT_11_SEQUENCE_OFFSET			22 /* Sequence control offset */
#define DOT_3_TYPE_OFFSET			12
#define DOT_11_MAC_HEADER_SIZE			24
#define DOT_11_SNAP_SIZE			6
#define DOT_11_TYPE_OFFSET			30 /* The start offset of 802.11 Frame. Type encapsulation. */
#define DEFAULT_SIFSTIME			10
#define DEFAULT_FRAGMENT_THRESHOLD		2346 /* No fragment */
#define DEFAULT_MSDU_LIFE_TIME			0xffff

#define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME		(144 + 48)
#define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME		(72 + 24)
#define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION	(16 + 4 + 6)
#define Tsym						4

/*  Frame Type of Bits (2, 3)----------------------------------- */
#define MAC_TYPE_MANAGEMENT			0x00
#define MAC_TYPE_CONTROL			0x04
#define MAC_TYPE_DATA				0x08
#define MASK_FRAGMENT_NUMBER			0x000F
#define SEQUENCE_NUMBER_SHIFT			4

#define  HAL_WOL_TYPE_WAKEUP_FRAME		0x01
#define  HAL_WOL_TYPE_MAGIC_PACKET		0x02

#define HAL_KEYTYPE_WEP40			0
#define HAL_KEYTYPE_WEP104			1
#define HAL_KEYTYPE_TKIP			2 /* 128 bit key */
#define HAL_KEYTYPE_AES_CCMP			3 /* 128 bit key */

/* For VM state */
enum {
	VM_STOP = 0,
	VM_RUNNING,
	VM_COMPLETED
};

/*
 * ================================
 * Normal Key table format
 * ================================
 */

/* The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX */
#define MAX_KEY_TABLE			24 /* 24 entry for storing key data */
#define GROUP_KEY_START_INDEX		4
#define MAPPING_KEY_START_INDEX		8

/*
 * =========================================
 * Descriptor
 * =========================================
 */
#define MAX_DESCRIPTOR_BUFFER_INDEX	8 /* Have to multiple of 2 */
#define FLAG_ERROR_TX_MASK		0x000000bf
#define FLAG_ERROR_RX_MASK		0x0000083f

#define FLAG_BAND_RX_MASK		0x10000000 /* Bit 28 */

struct R00_descriptor {
	union {
		u32	value;
#ifdef _BIG_ENDIAN_
		struct {
			u32	R00_packet_or_buffer_status:1;
			u32	R00_packet_in_fifo:1;
			u32	R00_RESERVED:2;
			u32	R00_receive_byte_count:12;
			u32	R00_receive_time_index:16;
		};
#else
		struct {
			u32	R00_receive_time_index:16;
			u32	R00_receive_byte_count:12;
			u32	R00_RESERVED:2;
			u32	R00_packet_in_fifo:1;
			u32	R00_packet_or_buffer_status:1;
		};
#endif
	};
};

struct T00_descriptor {
	union {
		u32	value;
#ifdef _BIG_ENDIAN_
		struct {
			u32	T00_first_mpdu:1; /* for hardware use */
			u32	T00_last_mpdu:1; /* for hardware use */
			u32	T00_IsLastMpdu:1;/* 0:not 1:Yes for software used */
			u32	T00_IgnoreResult:1;/* The same mechanism with T00 setting. */
			u32	T00_RESERVED_ID:2;/* 3 bit ID reserved */
			u32	T00_tx_packet_id:4;
			u32	T00_RESERVED:4;
			u32	T00_header_length:6;
			u32	T00_frame_length:12;
		};
#else
		struct {
			u32	T00_frame_length:12;
			u32	T00_header_length:6;
			u32	T00_RESERVED:4;
			u32	T00_tx_packet_id:4;
			u32	T00_RESERVED_ID:2; /* 3 bit ID reserved */
			u32	T00_IgnoreResult:1; /* The same mechanism with T00 setting. */
			u32	T00_IsLastMpdu:1; /* 0:not 1:Yes for software used */
			u32	T00_last_mpdu:1; /* for hardware use */
			u32	T00_first_mpdu:1; /* for hardware use */
		};
#endif
	};
};

struct R01_descriptor {
	union {
		u32	value;
#ifdef _BIG_ENDIAN_
		struct {
			u32	R01_RESERVED:3;
			u32	R01_mod_type:1;
			u32	R01_pre_type:1;
			u32	R01_data_rate:3;
			u32	R01_AGC_state:8;
			u32	R01_LNA_state:2;
			u32	R01_decryption_method:2;
			u32	R01_mic_error:1;
			u32	R01_replay:1;
			u32	R01_broadcast_frame:1;
			u32	R01_multicast_frame:1;
			u32	R01_directed_frame:1;
			u32	R01_receive_frame_antenna_selection:1;
			u32	R01_frame_receive_during_atim_window:1;
			u32	R01_protocol_version_error:1;
			u32	R01_authentication_frame_icv_error:1;
			u32	R01_null_key_to_authentication_frame:1;
			u32	R01_icv_error:1;
			u32	R01_crc_error:1;
		};
#else
		struct {
			u32	R01_crc_error:1;
			u32	R01_icv_error:1;
			u32	R01_null_key_to_authentication_frame:1;
			u32	R01_authentication_frame_icv_error:1;
			u32	R01_protocol_version_error:1;
			u32	R01_frame_receive_during_atim_window:1;
			u32	R01_receive_frame_antenna_selection:1;
			u32	R01_directed_frame:1;
			u32	R01_multicast_frame:1;
			u32	R01_broadcast_frame:1;
			u32	R01_replay:1;
			u32	R01_mic_error:1;
			u32	R01_decryption_method:2;
			u32	R01_LNA_state:2;
			u32	R01_AGC_state:8;
			u32	R01_data_rate:3;
			u32	R01_pre_type:1;
			u32	R01_mod_type:1;
			u32	R01_RESERVED:3;
		};
#endif
	};
};

struct T01_descriptor {
	union {
		u32	value;
#ifdef _BIG_ENDIAN_
		struct {
			u32	T01_rts_cts_duration:16;
			u32	T01_fall_back_rate:3;
			u32	T01_add_rts:1;
			u32	T01_add_cts:1;
			u32	T01_modulation_type:1;
			u32	T01_plcp_header_length:1;
			u32	T01_transmit_rate:3;
			u32	T01_wep_id:2;
			u32	T01_add_challenge_text:1;
			u32	T01_inhibit_crc:1;
			u32	T01_loop_back_wep_mode:1;
			u32	T01_retry_abort_enable:1;
		};
#else
		struct {
			u32	T01_retry_abort_enable:1;
			u32	T01_loop_back_wep_mode:1;
			u32	T01_inhibit_crc:1;
			u32	T01_add_challenge_text:1;
			u32	T01_wep_id:2;
			u32	T01_transmit_rate:3;
			u32	T01_plcp_header_length:1;
			u32	T01_modulation_type:1;
			u32	T01_add_cts:1;
			u32	T01_add_rts:1;
			u32	T01_fall_back_rate:3;
			u32	T01_rts_cts_duration:16;
		};
#endif
	};
};

struct T02_descriptor {
	union {
		u32	value;
#ifdef _BIG_ENDIAN_
		struct {
			u32	T02_IsLastMpdu:1; /* The same mechanism with T00 setting */
			u32	T02_IgnoreResult:1; /* The same mechanism with T00 setting. */
			u32	T02_RESERVED_ID:2; /* The same mechanism with T00 setting */
			u32	T02_Tx_PktID:4;
			u32	T02_MPDU_Cnt:4;
			u32	T02_RTS_Cnt:4;
			u32	T02_RESERVED:7;
			u32	T02_transmit_complete:1;
			u32	T02_transmit_abort_due_to_TBTT:1;
			u32	T02_effective_transmission_rate:1;
			u32	T02_transmit_without_encryption_due_to_wep_on_false:1;
			u32	T02_discard_due_to_null_wep_key:1;
			u32	T02_RESERVED_1:1;
			u32	T02_out_of_MaxTxMSDULiftTime:1;
			u32	T02_transmit_abort:1;
			u32	T02_transmit_fail:1;
		};
#else
		struct {
			u32	T02_transmit_fail:1;
			u32	T02_transmit_abort:1;
			u32	T02_out_of_MaxTxMSDULiftTime:1;
			u32	T02_RESERVED_1:1;
			u32	T02_discard_due_to_null_wep_key:1;
			u32	T02_transmit_without_encryption_due_to_wep_on_false:1;
			u32	T02_effective_transmission_rate:1;
			u32	T02_transmit_abort_due_to_TBTT:1;
			u32	T02_transmit_complete:1;
			u32	T02_RESERVED:7;
			u32	T02_RTS_Cnt:4;
			u32	T02_MPDU_Cnt:4;
			u32	T02_Tx_PktID:4;
			u32	T02_RESERVED_ID:2; /* The same mechanism with T00 setting */
			u32	T02_IgnoreResult:1; /* The same mechanism with T00 setting. */
			u32	T02_IsLastMpdu:1; /* The same mechanism with T00 setting */
		};
#endif
	};
};

struct wb35_descriptor { /* Skip length = 8 DWORD */
	/* ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition */
	u8	Descriptor_ID;
	/* ----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ */
	u8	RESERVED[3];

	u16	FragmentThreshold;
	u8	InternalUsed; /* Only can be used by operation of descriptor definition */
	u8	Type; /* 0: 802.3 1:802.11 data frame 2:802.11 management frame */

	u8	PreambleMode;/* 0: short 1:long */
	u8	TxRate;
	u8	FragmentCount;
	u8	EapFix; /* For speed up key install */

	/* For R00 and T00 ------------------------------ */
	union {
		struct R00_descriptor	R00;
		struct T00_descriptor	T00;
	};

	/* For R01 and T01 ------------------------------ */
	union {
		struct R01_descriptor	R01;
		struct T01_descriptor	T01;
	};

	/* For R02 and T02 ------------------------------ */
	union {
		u32		R02;
		struct T02_descriptor	T02;
	};

	/* For R03 and T03 ------------------------------ */
	/* For software used */
	union {
		u32	R03;
		u32	T03;
		struct {
			u8	buffer_number;
			u8	buffer_start_index;
			u16	buffer_total_size;
		};
	};

	/* For storing the buffer */
	u16	buffer_size[MAX_DESCRIPTOR_BUFFER_INDEX];
	void	*buffer_address[MAX_DESCRIPTOR_BUFFER_INDEX];
};

#define MAX_TXVGA_EEPROM		9	/* How many word(u16) of EEPROM will be used for TxVGA */
#define MAX_RF_PARAMETER		32

struct txvga_for_50 {
	u8	ChanNo;
	u8	TxVgaValue;
};

/*
 * ==============================================
 * Device related include
 * ==============================================
 */

#include "wb35reg_s.h"
#include "wb35tx_s.h"
#include "wb35rx_s.h"

/* For Hal using ============================================ */
struct hw_data {
	/* For compatible with 33 */
	u32	revision;
	u32	BB3c_cal; /* The value for Tx calibration comes from EEPROM */
	u32	BB54_cal; /* The value for Rx calibration comes from EEPROM */

	/* For surprise remove */
	u32	SurpriseRemove; /* 0: Normal 1: Surprise remove */
	u8	IsKeyPreSet;
	u8	CalOneTime;

	u8	VCO_trim;

	u32	FragCount;
	u32	DMAFix; /* V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. */

	/*
	 * ===============================================
	 * Definition for MAC address
	 * ===============================================
	 */
	u8	PermanentMacAddress[ETH_ALEN + 2]; /* The Ethernet addr that are stored in EEPROM. + 2 to 8-byte alignment */
	u8	CurrentMacAddress[ETH_ALEN + 2]; /* The Enthernet addr that are in used. + 2 to 8-byte alignment */

	/*
	 * =========================================
	 * Definition for 802.11
	 * =========================================
	 */
	u8	*bssid_pointer; /* Used by hal_get_bssid for return value */
	u8	bssid[8]; /* Only 6 byte will be used. 8 byte is required for read buffer */
	u8	ssid[32]; /* maximum ssid length is 32 byte */

	u16	AID;
	u8	ssid_length;
	u8	Channel;

	u16	ListenInterval;
	u16	CapabilityInformation;

	u16	BeaconPeriod;
	u16	ProbeDelay;

	u8	bss_type;/* 0: IBSS_NET or 1:ESS_NET */
	u8	preamble;/* 0: short preamble, 1: long preamble */
	u8	slot_time_select; /* 9 or 20 value */
	u8	phy_type; /* Phy select */

	u32	phy_para[MAX_RF_PARAMETER];
	u32	phy_number;

	u32	CurrentRadioSw; /* 0:On 1:Off */
	u32	CurrentRadioHw; /* 0:On 1:Off */

	u8	*power_save_point; /* Used by hal_get_power_save_mode for return value */
	u8	cwmin;
	u8	desired_power_save;
	u8	dtim; /* Is running dtim */
	u8	mapping_key_replace_index; /* In Key table, the next index be replaced */

	u16	MaxReceiveLifeTime;
	u16	FragmentThreshold;
	u16	FragmentThreshold_tmp;
	u16	cwmax;

	u8	Key_slot[MAX_KEY_TABLE][8]; /* Ownership record for key slot. For Alignment */
	u32	Key_content[MAX_KEY_TABLE][12]; /* 10DW for each entry + 2 for burst command (Off and On valid bit) */
	u8	CurrentDefaultKeyIndex;
	u32	CurrentDefaultKeyLength;

	/*
	 * ==================================================
	 * Variable for each module
	 * ==================================================
	 */
	struct usb_device	*udev;
	struct wb35_reg		reg;	/* Need Wb35Reg.h */
	struct wb35_tx		Wb35Tx; /* Need Wb35Tx.h */
	struct wb35_rx		Wb35Rx; /* Need Wb35Rx.h */

	struct timer_list	LEDTimer; /* For LED */

	u32			LEDpoint; /* For LED */

	u32			dto_tx_retry_count;
	u32			dto_tx_frag_count;
	u32			rx_ok_count[13]; /* index=0: total rx ok */
	u32			rx_err_count[13]; /* index=0: total rx err */

	/* for Tx debug */
	u32			tx_TBTT_start_count;
	u32			tx_ETR_count;
	u32			tx_WepOn_false_count;
	u32			tx_Null_key_count;
	u32			tx_retry_count[8];

	u8			PowerIndexFromEEPROM; /* For 2412MHz */
	u8			power_index;
	u8			IsWaitJoinComplete; /* TRUE: set join request */
	u8			band;

	u16			SoftwareSet;
	u16			Reserved_s;

	u32			IsInitOK; /* 0: Driver starting 1: Driver init OK */

	/* For Phy calibration */
	s32			iq_rsdl_gain_tx_d2;
	s32			iq_rsdl_phase_tx_d2;
	u32			txvga_setting_for_cal;

	u8			TxVgaSettingInEEPROM[(((MAX_TXVGA_EEPROM * 2) + 3) & ~0x03)]; /* For EEPROM value */
	u8			TxVgaFor24[16]; /* Max is 14, 2 for alignment */
	struct txvga_for_50		TxVgaFor50[36];	/* 35 channels in 5G. 35x2 = 70 byte. 2 for alignments */

	u16			Scan_Interval;
	u16			RESERVED6;

	/* LED control */
	u32		LED_control;
	/*
	 * LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
	 * Gray_Led
	 *		For Led gray setting
	 * Led
	 *		0: normal control,
	 *			LED behavior will decide by EEPROM setting
	 *		1: Turn off specific LED
	 *		2: Always on specific LED
	 *		3: slow blinking specific LED
	 *		4: fast blinking specific LED
	 *		5: WPS led control is set. Led0 is Red, Led1 id Green
	 *
	 * Led[1] is parameter for WPS LED mode
	 *		1:InProgress
	 *		2: Error
	 *		3: Session overlap
	 *		4: Success control
	 */
	u32		LED_LinkOn;	/* Turn LED on control */
	u32		LED_Scanning;	/* Let LED in scan process control */
	u32		LED_Blinking;	/* Temp variable for shining */
	u32		RxByteCountLast;
	u32		TxByteCountLast;

	/* For global timer */
	u32		time_count;	/* TICK_TIME_100ms 1 = 100ms */
};

#endif
Commit	Line	Data
80aba536 PE	1	#ifndef __WINBOND_WBHAL_S_H
	2	#define __WINBOND_WBHAL_S_H
	3
	4	#include <linux/types.h>
bd37b7fd	5	#include <linux/if_ether.h> /* for ETH_ALEN */
80aba536	6
5a7df3c4 LL	7	#define HAL_LED_SET_MASK 0x001c
5a7df3c4 LL	8	#define HAL_LED_SET_SHIFT 2
66101de1	9
5a7df3c4	10	/* supported RF type */
66101de1 PM	11	#define RF_MAXIM_2825 0
	12	#define RF_MAXIM_2827 1
	13	#define RF_MAXIM_2828 2
	14	#define RF_MAXIM_2829 3
5a7df3c4	15	#define RF_MAXIM_V1 15
66101de1 PM	16	#define RF_AIROHA_2230 16
66101de1 PM	17	#define RF_AIROHA_7230 17
5a7df3c4 LL	18	#define RF_AIROHA_2230S 18
	19	#define RF_WB_242 33
	20	#define RF_WB_242_1 34
66101de1 PM	21	#define RF_DECIDE_BY_INF 255
66101de1 PM	22
5a7df3c4 LL	23	/*
	24	* ----------------------------------------------------------------
	25	* The follow define connect to upper layer
	26	* User must modify for connection between HAL and upper layer
	27	* ----------------------------------------------------------------
	28	*/
	29
	30	/*
	31	* ==============================
	32	* Common define
	33	* ==============================
	34	*/
	35	/* Bit 5 */
	36	#define HAL_USB_MODE_BURST(_H) (_H->SoftwareSet & 0x20)
	37
	38	/* Scan interval */
	39	#define SCAN_MAX_CHNL_TIME (50)
	40
	41	/* For TxL2 Frame typr recognise */
66101de1 PM	42	#define FRAME_TYPE_802_3_DATA 0
66101de1 PM	43	#define FRAME_TYPE_802_11_MANAGEMENT 1
5a7df3c4	44	#define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2
66101de1 PM	45	#define FRAME_TYPE_802_11_CONTROL 3
	46	#define FRAME_TYPE_802_11_DATA 4
	47	#define FRAME_TYPE_PROMISCUOUS 5
	48
5a7df3c4 LL	49	/* The follow definition is used for convert the frame------------ */
5a7df3c4 LL	50	#define DOT_11_SEQUENCE_OFFSET 22 /* Sequence control offset */
66101de1	51	#define DOT_3_TYPE_OFFSET 12
5a7df3c4	52	#define DOT_11_MAC_HEADER_SIZE 24
66101de1	53	#define DOT_11_SNAP_SIZE 6
5a7df3c4	54	#define DOT_11_TYPE_OFFSET 30 /* The start offset of 802.11 Frame. Type encapsulation. */
66101de1	55	#define DEFAULT_SIFSTIME 10
5a7df3c4	56	#define DEFAULT_FRAGMENT_THRESHOLD 2346 /* No fragment */
66101de1 PM	57	#define DEFAULT_MSDU_LIFE_TIME 0xffff
66101de1 PM	58
5a7df3c4 LL	59	#define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144 + 48)
	60	#define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72 + 24)
	61	#define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16 + 4 + 6)
	62	#define Tsym 4
66101de1	63
5a7df3c4	64	/* Frame Type of Bits (2, 3)----------------------------------- */
66101de1 PM	65	#define MAC_TYPE_MANAGEMENT 0x00
	66	#define MAC_TYPE_CONTROL 0x04
	67	#define MAC_TYPE_DATA 0x08
5a7df3c4 LL	68	#define MASK_FRAGMENT_NUMBER 0x000F
5a7df3c4 LL	69	#define SEQUENCE_NUMBER_SHIFT 4
66101de1 PM	70
	71	#define HAL_WOL_TYPE_WAKEUP_FRAME 0x01
	72	#define HAL_WOL_TYPE_MAGIC_PACKET 0x02
	73
5a7df3c4 LL	74	#define HAL_KEYTYPE_WEP40 0
	75	#define HAL_KEYTYPE_WEP104 1
	76	#define HAL_KEYTYPE_TKIP 2 /* 128 bit key */
	77	#define HAL_KEYTYPE_AES_CCMP 3 /* 128 bit key */
66101de1	78
5a7df3c4	79	/* For VM state */
66101de1 PM	80	enum {
	81	VM_STOP = 0,
	82	VM_RUNNING,
	83	VM_COMPLETED
	84	};
	85
5a7df3c4 LL	86	/*
	87	* ================================
	88	* Normal Key table format
	89	* ================================
	90	*/
	91
	92	/* The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX */
	93	#define MAX_KEY_TABLE 24 /* 24 entry for storing key data */
66101de1 PM	94	#define GROUP_KEY_START_INDEX 4
66101de1 PM	95	#define MAPPING_KEY_START_INDEX 8
66101de1	96
5a7df3c4 LL	97	/*
	98	* =========================================
	99	* Descriptor
	100	* =========================================
	101	*/
	102	#define MAX_DESCRIPTOR_BUFFER_INDEX 8 /* Have to multiple of 2 */
	103	#define FLAG_ERROR_TX_MASK 0x000000bf
	104	#define FLAG_ERROR_RX_MASK 0x0000083f
	105
	106	#define FLAG_BAND_RX_MASK 0x10000000 /* Bit 28 */
	107
c4d562a9	108	struct R00_descriptor {
5a7df3c4	109	union {
66101de1	110	u32 value;
5a7df3c4 LL	111	#ifdef _BIG_ENDIAN_
5a7df3c4 LL	112	struct {
66101de1 PM	113	u32 R00_packet_or_buffer_status:1;
	114	u32 R00_packet_in_fifo:1;
	115	u32 R00_RESERVED:2;
	116	u32 R00_receive_byte_count:12;
	117	u32 R00_receive_time_index:16;
	118	};
5a7df3c4 LL	119	#else
5a7df3c4 LL	120	struct {
66101de1 PM	121	u32 R00_receive_time_index:16;
	122	u32 R00_receive_byte_count:12;
	123	u32 R00_RESERVED:2;
	124	u32 R00_packet_in_fifo:1;
	125	u32 R00_packet_or_buffer_status:1;
	126	};
5a7df3c4	127	#endif
66101de1	128	};
c4d562a9	129	};
66101de1	130
c4d562a9	131	struct T00_descriptor {
5a7df3c4	132	union {
66101de1	133	u32 value;
5a7df3c4 LL	134	#ifdef _BIG_ENDIAN_
	135	struct {
	136	u32 T00_first_mpdu:1; /* for hardware use */
	137	u32 T00_last_mpdu:1; /* for hardware use */
	138	u32 T00_IsLastMpdu:1;/* 0:not 1:Yes for software used */
	139	u32 T00_IgnoreResult:1;/* The same mechanism with T00 setting. */
	140	u32 T00_RESERVED_ID:2;/* 3 bit ID reserved */
	141	u32 T00_tx_packet_id:4;
66101de1 PM	142	u32 T00_RESERVED:4;
	143	u32 T00_header_length:6;
	144	u32 T00_frame_length:12;
	145	};
5a7df3c4 LL	146	#else
5a7df3c4 LL	147	struct {
66101de1 PM	148	u32 T00_frame_length:12;
	149	u32 T00_header_length:6;
	150	u32 T00_RESERVED:4;
5a7df3c4 LL	151	u32 T00_tx_packet_id:4;
	152	u32 T00_RESERVED_ID:2; /* 3 bit ID reserved */
	153	u32 T00_IgnoreResult:1; /* The same mechanism with T00 setting. */
	154	u32 T00_IsLastMpdu:1; /* 0:not 1:Yes for software used */
	155	u32 T00_last_mpdu:1; /* for hardware use */
	156	u32 T00_first_mpdu:1; /* for hardware use */
66101de1	157	};
5a7df3c4	158	#endif
66101de1	159	};
c4d562a9	160	};
66101de1	161
c4d562a9	162	struct R01_descriptor {
5a7df3c4	163	union {
66101de1	164	u32 value;
5a7df3c4 LL	165	#ifdef _BIG_ENDIAN_
5a7df3c4 LL	166	struct {
66101de1 PM	167	u32 R01_RESERVED:3;
	168	u32 R01_mod_type:1;
	169	u32 R01_pre_type:1;
	170	u32 R01_data_rate:3;
	171	u32 R01_AGC_state:8;
	172	u32 R01_LNA_state:2;
	173	u32 R01_decryption_method:2;
	174	u32 R01_mic_error:1;
	175	u32 R01_replay:1;
	176	u32 R01_broadcast_frame:1;
	177	u32 R01_multicast_frame:1;
	178	u32 R01_directed_frame:1;
	179	u32 R01_receive_frame_antenna_selection:1;
	180	u32 R01_frame_receive_during_atim_window:1;
	181	u32 R01_protocol_version_error:1;
	182	u32 R01_authentication_frame_icv_error:1;
	183	u32 R01_null_key_to_authentication_frame:1;
	184	u32 R01_icv_error:1;
	185	u32 R01_crc_error:1;
	186	};
5a7df3c4 LL	187	#else
5a7df3c4 LL	188	struct {
66101de1 PM	189	u32 R01_crc_error:1;
	190	u32 R01_icv_error:1;
	191	u32 R01_null_key_to_authentication_frame:1;
	192	u32 R01_authentication_frame_icv_error:1;
	193	u32 R01_protocol_version_error:1;
	194	u32 R01_frame_receive_during_atim_window:1;
	195	u32 R01_receive_frame_antenna_selection:1;
	196	u32 R01_directed_frame:1;
	197	u32 R01_multicast_frame:1;
	198	u32 R01_broadcast_frame:1;
	199	u32 R01_replay:1;
	200	u32 R01_mic_error:1;
	201	u32 R01_decryption_method:2;
	202	u32 R01_LNA_state:2;
	203	u32 R01_AGC_state:8;
	204	u32 R01_data_rate:3;
	205	u32 R01_pre_type:1;
	206	u32 R01_mod_type:1;
	207	u32 R01_RESERVED:3;
	208	};
5a7df3c4	209	#endif
66101de1	210	};
c4d562a9	211	};
66101de1	212
c4d562a9	213	struct T01_descriptor {
5a7df3c4	214	union {
66101de1	215	u32 value;
5a7df3c4 LL	216	#ifdef _BIG_ENDIAN_
5a7df3c4 LL	217	struct {
66101de1 PM	218	u32 T01_rts_cts_duration:16;
	219	u32 T01_fall_back_rate:3;
	220	u32 T01_add_rts:1;
	221	u32 T01_add_cts:1;
	222	u32 T01_modulation_type:1;
	223	u32 T01_plcp_header_length:1;
	224	u32 T01_transmit_rate:3;
	225	u32 T01_wep_id:2;
	226	u32 T01_add_challenge_text:1;
	227	u32 T01_inhibit_crc:1;
	228	u32 T01_loop_back_wep_mode:1;
5ee60a70	229	u32 T01_retry_abort_enable:1;
66101de1	230	};
5a7df3c4 LL	231	#else
5a7df3c4 LL	232	struct {
5ee60a70	233	u32 T01_retry_abort_enable:1;
66101de1 PM	234	u32 T01_loop_back_wep_mode:1;
	235	u32 T01_inhibit_crc:1;
	236	u32 T01_add_challenge_text:1;
	237	u32 T01_wep_id:2;
	238	u32 T01_transmit_rate:3;
	239	u32 T01_plcp_header_length:1;
	240	u32 T01_modulation_type:1;
	241	u32 T01_add_cts:1;
	242	u32 T01_add_rts:1;
	243	u32 T01_fall_back_rate:3;
	244	u32 T01_rts_cts_duration:16;
	245	};
5a7df3c4	246	#endif
66101de1	247	};
c4d562a9	248	};
66101de1	249
c4d562a9	250	struct T02_descriptor {
5a7df3c4	251	union {
66101de1	252	u32 value;
5a7df3c4 LL	253	#ifdef _BIG_ENDIAN_
	254	struct {
	255	u32 T02_IsLastMpdu:1; /* The same mechanism with T00 setting */
	256	u32 T02_IgnoreResult:1; /* The same mechanism with T00 setting. */
	257	u32 T02_RESERVED_ID:2; /* The same mechanism with T00 setting */
66101de1 PM	258	u32 T02_Tx_PktID:4;
	259	u32 T02_MPDU_Cnt:4;
	260	u32 T02_RTS_Cnt:4;
	261	u32 T02_RESERVED:7;
	262	u32 T02_transmit_complete:1;
	263	u32 T02_transmit_abort_due_to_TBTT:1;
	264	u32 T02_effective_transmission_rate:1;
	265	u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
	266	u32 T02_discard_due_to_null_wep_key:1;
	267	u32 T02_RESERVED_1:1;
	268	u32 T02_out_of_MaxTxMSDULiftTime:1;
	269	u32 T02_transmit_abort:1;
	270	u32 T02_transmit_fail:1;
	271	};
5a7df3c4 LL	272	#else
5a7df3c4 LL	273	struct {
66101de1 PM	274	u32 T02_transmit_fail:1;
	275	u32 T02_transmit_abort:1;
	276	u32 T02_out_of_MaxTxMSDULiftTime:1;
	277	u32 T02_RESERVED_1:1;
	278	u32 T02_discard_due_to_null_wep_key:1;
	279	u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
	280	u32 T02_effective_transmission_rate:1;
	281	u32 T02_transmit_abort_due_to_TBTT:1;
	282	u32 T02_transmit_complete:1;
	283	u32 T02_RESERVED:7;
	284	u32 T02_RTS_Cnt:4;
	285	u32 T02_MPDU_Cnt:4;
	286	u32 T02_Tx_PktID:4;
5a7df3c4 LL	287	u32 T02_RESERVED_ID:2; /* The same mechanism with T00 setting */
	288	u32 T02_IgnoreResult:1; /* The same mechanism with T00 setting. */
	289	u32 T02_IsLastMpdu:1; /* The same mechanism with T00 setting */
66101de1	290	};
5a7df3c4	291	#endif
66101de1	292	};
c4d562a9	293	};
66101de1	294
5a7df3c4 LL	295	struct wb35_descriptor { /* Skip length = 8 DWORD */
5a7df3c4 LL	296	/* ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition */
66101de1	297	u8 Descriptor_ID;
5a7df3c4	298	/* ----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ */
66101de1 PM	299	u8 RESERVED[3];
	300
	301	u16 FragmentThreshold;
5a7df3c4 LL	302	u8 InternalUsed; /* Only can be used by operation of descriptor definition */
5a7df3c4 LL	303	u8 Type; /* 0: 802.3 1:802.11 data frame 2:802.11 management frame */
66101de1	304
5a7df3c4	305	u8 PreambleMode;/* 0: short 1:long */
66101de1 PM	306	u8 TxRate;
66101de1 PM	307	u8 FragmentCount;
5a7df3c4	308	u8 EapFix; /* For speed up key install */
66101de1	309
5a7df3c4 LL	310	/* For R00 and T00 ------------------------------ */
5a7df3c4 LL	311	union {
c4d562a9 PE	312	struct R00_descriptor R00;
c4d562a9 PE	313	struct T00_descriptor T00;
66101de1 PM	314	};
66101de1 PM	315
5a7df3c4 LL	316	/* For R01 and T01 ------------------------------ */
5a7df3c4 LL	317	union {
c4d562a9 PE	318	struct R01_descriptor R01;
c4d562a9 PE	319	struct T01_descriptor T01;
66101de1 PM	320	};
66101de1 PM	321
5a7df3c4 LL	322	/* For R02 and T02 ------------------------------ */
	323	union {
	324	u32 R02;
c4d562a9	325	struct T02_descriptor T02;
66101de1 PM	326	};
66101de1 PM	327
5a7df3c4 LL	328	/* For R03 and T03 ------------------------------ */
	329	/* For software used */
	330	union {
66101de1 PM	331	u32 R03;
66101de1 PM	332	u32 T03;
5a7df3c4	333	struct {
66101de1 PM	334	u8 buffer_number;
	335	u8 buffer_start_index;
	336	u16 buffer_total_size;
	337	};
	338	};
	339
5a7df3c4 LL	340	/* For storing the buffer */
	341	u16 buffer_size[MAX_DESCRIPTOR_BUFFER_INDEX];
	342	void *buffer_address[MAX_DESCRIPTOR_BUFFER_INDEX];
27d46421	343	};
66101de1	344
5a7df3c4 LL	345	#define MAX_TXVGA_EEPROM 9 /* How many word(u16) of EEPROM will be used for TxVGA */
5a7df3c4 LL	346	#define MAX_RF_PARAMETER 32
66101de1	347
c4d562a9	348	struct txvga_for_50 {
5a7df3c4 LL	349	u8 ChanNo;
5a7df3c4 LL	350	u8 TxVgaValue;
c4d562a9	351	};
66101de1	352
5a7df3c4 LL	353	/*
	354	* ==============================================
	355	* Device related include
	356	* ==============================================
	357	*/
66101de1	358
9ce922fd PE	359	#include "wb35reg_s.h"
	360	#include "wb35tx_s.h"
	361	#include "wb35rx_s.h"
66101de1	362
5a7df3c4	363	/* For Hal using ============================================ */
8e41b4b6	364	struct hw_data {
5a7df3c4	365	/* For compatible with 33 */
66101de1	366	u32 revision;
5a7df3c4 LL	367	u32 BB3c_cal; /* The value for Tx calibration comes from EEPROM */
5a7df3c4 LL	368	u32 BB54_cal; /* The value for Rx calibration comes from EEPROM */
66101de1	369
5a7df3c4 LL	370	/* For surprise remove */
5a7df3c4 LL	371	u32 SurpriseRemove; /* 0: Normal 1: Surprise remove */
66101de1	372	u8 IsKeyPreSet;
5a7df3c4	373	u8 CalOneTime;
66101de1 PM	374
	375	u8 VCO_trim;
	376
66101de1	377	u32 FragCount;
5a7df3c4 LL	378	u32 DMAFix; /* V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. */
	379
	380	/*
	381	* ===============================================
	382	* Definition for MAC address
	383	* ===============================================
	384	*/
	385	u8 PermanentMacAddress[ETH_ALEN + 2]; /* The Ethernet addr that are stored in EEPROM. + 2 to 8-byte alignment */
	386	u8 CurrentMacAddress[ETH_ALEN + 2]; /* The Enthernet addr that are in used. + 2 to 8-byte alignment */
	387
	388	/*
	389	* =========================================
	390	* Definition for 802.11
	391	* =========================================
	392	*/
	393	u8 bssid_pointer; / Used by hal_get_bssid for return value */
	394	u8 bssid[8]; /* Only 6 byte will be used. 8 byte is required for read buffer */
	395	u8 ssid[32]; /* maximum ssid length is 32 byte */
66101de1 PM	396
	397	u16 AID;
	398	u8 ssid_length;
	399	u8 Channel;
	400
	401	u16 ListenInterval;
	402	u16 CapabilityInformation;
	403
	404	u16 BeaconPeriod;
	405	u16 ProbeDelay;
	406
5a7df3c4 LL	407	u8 bss_type;/* 0: IBSS_NET or 1:ESS_NET */
	408	u8 preamble;/* 0: short preamble, 1: long preamble */
	409	u8 slot_time_select; /* 9 or 20 value */
	410	u8 phy_type; /* Phy select */
66101de1 PM	411
	412	u32 phy_para[MAX_RF_PARAMETER];
	413	u32 phy_number;
	414
5a7df3c4 LL	415	u32 CurrentRadioSw; /* 0:On 1:Off */
5a7df3c4 LL	416	u32 CurrentRadioHw; /* 0:On 1:Off */
66101de1	417
5a7df3c4	418	u8 power_save_point; / Used by hal_get_power_save_mode for return value */
66101de1 PM	419	u8 cwmin;
66101de1 PM	420	u8 desired_power_save;
5a7df3c4 LL	421	u8 dtim; /* Is running dtim */
5a7df3c4 LL	422	u8 mapping_key_replace_index; /* In Key table, the next index be replaced */
66101de1 PM	423
	424	u16 MaxReceiveLifeTime;
	425	u16 FragmentThreshold;
	426	u16 FragmentThreshold_tmp;
	427	u16 cwmax;
	428
5a7df3c4 LL	429	u8 Key_slot[MAX_KEY_TABLE][8]; /* Ownership record for key slot. For Alignment */
5a7df3c4 LL	430	u32 Key_content[MAX_KEY_TABLE][12]; /* 10DW for each entry + 2 for burst command (Off and On valid bit) */
66101de1 PM	431	u8 CurrentDefaultKeyIndex;
	432	u32 CurrentDefaultKeyLength;
	433
5a7df3c4 LL	434	/*
	435	* ==================================================
	436	* Variable for each module
	437	* ==================================================
	438	*/
2894c6cd	439	struct usb_device *udev;
5a7df3c4 LL	440	struct wb35_reg reg; /* Need Wb35Reg.h */
	441	struct wb35_tx Wb35Tx; /* Need Wb35Tx.h */
	442	struct wb35_rx Wb35Rx; /* Need Wb35Rx.h */
66101de1	443
5a7df3c4	444	struct timer_list LEDTimer; /* For LED */
66101de1	445
5a7df3c4	446	u32 LEDpoint; /* For LED */
66101de1	447
5a7df3c4 LL	448	u32 dto_tx_retry_count;
	449	u32 dto_tx_frag_count;
	450	u32 rx_ok_count[13]; /* index=0: total rx ok */
	451	u32 rx_err_count[13]; /* index=0: total rx err */
66101de1	452
5a7df3c4	453	/* for Tx debug */
66101de1 PM	454	u32 tx_TBTT_start_count;
	455	u32 tx_ETR_count;
	456	u32 tx_WepOn_false_count;
	457	u32 tx_Null_key_count;
	458	u32 tx_retry_count[8];
	459
5a7df3c4 LL	460	u8 PowerIndexFromEEPROM; /* For 2412MHz */
	461	u8 power_index;
	462	u8 IsWaitJoinComplete; /* TRUE: set join request */
	463	u8 band;
66101de1	464
5a7df3c4 LL	465	u16 SoftwareSet;
5a7df3c4 LL	466	u16 Reserved_s;
66101de1	467
5a7df3c4	468	u32 IsInitOK; /* 0: Driver starting 1: Driver init OK */
66101de1	469
5a7df3c4 LL	470	/* For Phy calibration */
	471	s32 iq_rsdl_gain_tx_d2;
	472	s32 iq_rsdl_phase_tx_d2;
	473	u32 txvga_setting_for_cal;
66101de1	474
5a7df3c4 LL	475	u8 TxVgaSettingInEEPROM[(((MAX_TXVGA_EEPROM * 2) + 3) & ~0x03)]; /* For EEPROM value */
5a7df3c4 LL	476	u8 TxVgaFor24[16]; /* Max is 14, 2 for alignment */
c4d562a9	477	struct txvga_for_50 TxVgaFor50[36]; /* 35 channels in 5G. 35x2 = 70 byte. 2 for alignments */
66101de1	478
5a7df3c4 LL	479	u16 Scan_Interval;
5a7df3c4 LL	480	u16 RESERVED6;
66101de1	481
5a7df3c4	482	/* LED control */
66101de1	483	u32 LED_control;
5a7df3c4 LL	484	/*
	485	* LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
	486	* Gray_Led
	487	* For Led gray setting
	488	* Led
	489	* 0: normal control,
	490	* LED behavior will decide by EEPROM setting
	491	* 1: Turn off specific LED
	492	* 2: Always on specific LED
	493	* 3: slow blinking specific LED
	494	* 4: fast blinking specific LED
	495	* 5: WPS led control is set. Led0 is Red, Led1 id Green
	496	*
	497	* Led[1] is parameter for WPS LED mode
	498	* 1:InProgress
	499	* 2: Error
	500	* 3: Session overlap
	501	* 4: Success control
	502	*/
	503	u32 LED_LinkOn; /* Turn LED on control */
	504	u32 LED_Scanning; /* Let LED in scan process control */
	505	u32 LED_Blinking; /* Temp variable for shining */
66101de1 PM	506	u32 RxByteCountLast;
	507	u32 TxByteCountLast;
	508
5a7df3c4 LL	509	/* For global timer */
5a7df3c4 LL	510	u32 time_count; /* TICK_TIME_100ms 1 = 100ms */
8e41b4b6	511	};
66101de1	512
80aba536	513	#endif