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Merge tag 'wireless-drivers-for-davem-2016-06-04' of git://git.kernel.org/pub/scm...
[deliverable/linux.git] / drivers / staging / xgifb / vb_init.c
CommitLineData
949eb0ae 1#include <linux/delay.h>
02a81dd9 2#include <linux/vmalloc.h>
6048d761 3
d7636e0b 4#include "XGIfb.h"
d7636e0b 5#include "vb_def.h"
d7636e0b 6#include "vb_util.h"
7#include "vb_setmode.h"
e054102b 8#include "vb_init.h"
d6461e49
PH		 9static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
10 { 16, 0x45},
11 { 8, 0x35},
12 { 4, 0x31},
13 { 2, 0x21} };
14
15static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
16 { 128, 0x5D},
17 { 64, 0x59},
18 { 64, 0x4D},
19 { 32, 0x55},
20 { 32, 0x49},
21 { 32, 0x3D},
22 { 16, 0x51},
23 { 16, 0x45},
24 { 16, 0x39},
25 { 8, 0x41},
26 { 8, 0x35},
27 { 4, 0x31} };
d7636e0b 28
02a81dd9
AK		 29#define XGIFB_ROM_SIZE 65536
30
bf32fcb9
KT		 31static unsigned char
32XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
d7636e0b 34{
b9ebf5e5 35 unsigned char data, temp;
d7636e0b 36
b9ebf5e5 37 if (HwDeviceExtension->jChipType < XG20) {
6d12dae4
PH		 38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
39 if (data == 0)
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
41 0x02) >> 1;
42 return data;
b9ebf5e5 43 } else if (HwDeviceExtension->jChipType == XG27) {
58839b01 44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
bf32fcb9 45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
6490311f 46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
b9ebf5e5
AK		 47 data = 0; /* DDR */
48 else
49 data = 1; /* DDRII */
50 return data;
51 } else if (HwDeviceExtension->jChipType == XG21) {
bf32fcb9
KT		 52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
d8acac94 54 usleep_range(800, 1800);
b9bf6e4e 55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
bf32fcb9 56 /* GPIOF 0:DVI 1:DVO */
fb70b191 57 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5 58 /* HOTPLUG_SUPPORT */
bf32fcb9 59 /* for current XG20 & XG21, GPIOH is floating, driver will
288f152c
JR		 60 * fix DDR temporarily
61 */
fb70b191
PH		 62 /* DVI read GPIOH */
63 data &= 0x01; /* 1=DDRII, 0=DDR */
b9ebf5e5 64 /* ~HOTPLUG_SUPPORT */
b9bf6e4e 65 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
b9ebf5e5 66 return data;
9c8c8315
TG		 67 }
68 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
d7636e0b 69
9c8c8315
TG		 70 if (data == 1)
71 data++;
d7636e0b 72
9c8c8315 73 return data;
b9ebf5e5 74}
d7636e0b 75
bf32fcb9
KT		 76static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
77 struct vb_device_info *pVBInfo)
b9ebf5e5 78{
8104e329
AK		 79 xgifb_reg_set(P3c4, 0x18, 0x01);
80 xgifb_reg_set(P3c4, 0x19, 0x20);
81 xgifb_reg_set(P3c4, 0x16, 0x00);
82 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 83
d8acac94 84 usleep_range(3, 1003);
6d12dae4
PH		 85 xgifb_reg_set(P3c4, 0x18, 0x00);
86 xgifb_reg_set(P3c4, 0x19, 0x20);
87 xgifb_reg_set(P3c4, 0x16, 0x00);
88 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 89
d8acac94 90 usleep_range(60, 1060);
597d96b6 91 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329 92 xgifb_reg_set(P3c4, 0x19, 0x01);
0904f7f3
AK		 93 xgifb_reg_set(P3c4, 0x16, 0x03);
94 xgifb_reg_set(P3c4, 0x16, 0x83);
d8acac94 95 usleep_range(1, 1001);
8104e329 96 xgifb_reg_set(P3c4, 0x1B, 0x03);
d8acac94 97 usleep_range(500, 1500);
597d96b6 98 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329 99 xgifb_reg_set(P3c4, 0x19, 0x00);
0904f7f3
AK		 100 xgifb_reg_set(P3c4, 0x16, 0x03);
101 xgifb_reg_set(P3c4, 0x16, 0x83);
8104e329 102 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 103}
d7636e0b 104
b053af16 105static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
b9ebf5e5 106{
bf32fcb9
KT		 107 xgifb_reg_set(pVBInfo->P3c4,
108 0x28,
2af1a29d 109 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
bf32fcb9
KT		 110 xgifb_reg_set(pVBInfo->P3c4,
111 0x29,
2af1a29d 112 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
bf32fcb9
KT		 113 xgifb_reg_set(pVBInfo->P3c4,
114 0x2A,
2af1a29d 115 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
bf32fcb9
KT		 116
117 xgifb_reg_set(pVBInfo->P3c4,
118 0x2E,
9b047458 119 XGI340_ECLKData[pVBInfo->ram_type].SR2E);
bf32fcb9
KT		 120 xgifb_reg_set(pVBInfo->P3c4,
121 0x2F,
9b047458 122 XGI340_ECLKData[pVBInfo->ram_type].SR2F);
bf32fcb9
KT		 123 xgifb_reg_set(pVBInfo->P3c4,
124 0x30,
9b047458 125 XGI340_ECLKData[pVBInfo->ram_type].SR30);
b9ebf5e5 126}
d7636e0b 127
b9ebf5e5
AK		 128static void XGINew_DDRII_Bootup_XG27(
129 struct xgi_hw_device_info *HwDeviceExtension,
130 unsigned long P3c4, struct vb_device_info *pVBInfo)
131{
132 unsigned long P3d4 = P3c4 + 0x10;
694683f6 133
2af1a29d 134 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b053af16 135 XGINew_SetMemoryClock(pVBInfo);
d7636e0b 136
b9ebf5e5 137 /* Set Double Frequency */
6d12dae4 138 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
d7636e0b 139
d8acac94 140 usleep_range(200, 1200);
d7636e0b 141
8104e329
AK		 142 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
143 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
144 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 145 usleep_range(15, 1015);
8104e329 146 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 147 usleep_range(15, 1015);
d7636e0b 148
8104e329
AK		 149 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
150 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
151 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 152 usleep_range(15, 1015);
8104e329 153 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 154 usleep_range(15, 1015);
d7636e0b 155
8104e329
AK		 156 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
157 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
158 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 159 usleep_range(30, 1030);
8104e329 160 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 161 usleep_range(15, 1015);
d7636e0b 162
8104e329
AK		 163 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
164 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
165 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
d8acac94 166 usleep_range(30, 1030);
8104e329
AK		 167 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
168 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
d7636e0b 169
8104e329 170 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
d8acac94 171 usleep_range(60, 1060);
8104e329 172 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
d7636e0b 173
8104e329
AK		 174 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
175 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
176 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
d7636e0b 177
d8acac94 178 usleep_range(30, 1030);
8104e329 179 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
d8acac94 180 usleep_range(15, 1015);
d7636e0b 181
8104e329
AK		 182 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
183 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
184 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 185 usleep_range(30, 1030);
8104e329 186 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 187 usleep_range(15, 1015);
d7636e0b 188
8104e329
AK		 189 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
190 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
191 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
d8acac94 192 usleep_range(30, 1030);
8104e329 193 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
d8acac94 194 usleep_range(15, 1015);
d7636e0b 195
bf32fcb9
KT		 196 /* Set SR1B refresh control 000:close; 010:open */
197 xgifb_reg_set(P3c4, 0x1B, 0x04);
d8acac94 198 usleep_range(200, 1200);
b9ebf5e5 199}
d7636e0b 200
b9ebf5e5
AK		 201static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
202 unsigned long P3c4, struct vb_device_info *pVBInfo)
203{
204 unsigned long P3d4 = P3c4 + 0x10;
d7636e0b 205
2af1a29d 206 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b053af16 207 XGINew_SetMemoryClock(pVBInfo);
d7636e0b 208
8104e329 209 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
d7636e0b 210
d8acac94 211 usleep_range(200, 1200);
8104e329
AK		 212 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
213 xgifb_reg_set(P3c4, 0x19, 0x80);
214 xgifb_reg_set(P3c4, 0x16, 0x05);
215 xgifb_reg_set(P3c4, 0x16, 0x85);
216
217 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
218 xgifb_reg_set(P3c4, 0x19, 0xC0);
219 xgifb_reg_set(P3c4, 0x16, 0x05);
220 xgifb_reg_set(P3c4, 0x16, 0x85);
221
222 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
223 xgifb_reg_set(P3c4, 0x19, 0x40);
224 xgifb_reg_set(P3c4, 0x16, 0x05);
225 xgifb_reg_set(P3c4, 0x16, 0x85);
226
8104e329
AK		 227 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
228 xgifb_reg_set(P3c4, 0x19, 0x02);
229 xgifb_reg_set(P3c4, 0x16, 0x05);
230 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 231
d8acac94 232 usleep_range(15, 1015);
8104e329 233 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
d8acac94 234 usleep_range(30, 1030);
8104e329 235 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
d8acac94 236 usleep_range(100, 1100);
a24d60f4 237
8104e329
AK		 238 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
239 xgifb_reg_set(P3c4, 0x19, 0x00);
240 xgifb_reg_set(P3c4, 0x16, 0x05);
241 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 242
d8acac94 243 usleep_range(200, 1200);
b9ebf5e5 244}
a24d60f4 245
bf32fcb9
KT		 246static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
247 struct vb_device_info *pVBInfo)
b9ebf5e5 248{
8104e329
AK		 249 xgifb_reg_set(P3c4, 0x18, 0x01);
250 xgifb_reg_set(P3c4, 0x19, 0x40);
251 xgifb_reg_set(P3c4, 0x16, 0x00);
252 xgifb_reg_set(P3c4, 0x16, 0x80);
d8acac94 253 usleep_range(60, 1060);
a24d60f4 254
8104e329
AK		 255 xgifb_reg_set(P3c4, 0x18, 0x00);
256 xgifb_reg_set(P3c4, 0x19, 0x40);
257 xgifb_reg_set(P3c4, 0x16, 0x00);
258 xgifb_reg_set(P3c4, 0x16, 0x80);
d8acac94 259 usleep_range(60, 1060);
597d96b6 260 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 261 xgifb_reg_set(P3c4, 0x19, 0x01);
262 xgifb_reg_set(P3c4, 0x16, 0x03);
263 xgifb_reg_set(P3c4, 0x16, 0x83);
d8acac94 264 usleep_range(1, 1001);
8104e329 265 xgifb_reg_set(P3c4, 0x1B, 0x03);
d8acac94 266 usleep_range(500, 1500);
597d96b6 267 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 268 xgifb_reg_set(P3c4, 0x19, 0x00);
269 xgifb_reg_set(P3c4, 0x16, 0x03);
270 xgifb_reg_set(P3c4, 0x16, 0x83);
271 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 272}
a24d60f4 273
b9ebf5e5
AK		 274static void XGINew_DDR1x_DefaultRegister(
275 struct xgi_hw_device_info *HwDeviceExtension,
276 unsigned long Port, struct vb_device_info *pVBInfo)
277{
278 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 279
b9ebf5e5 280 if (HwDeviceExtension->jChipType >= XG20) {
b053af16 281 XGINew_SetMemoryClock(pVBInfo);
bf32fcb9
KT		 282 xgifb_reg_set(P3d4,
283 0x82,
2af1a29d 284 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
bf32fcb9
KT		 285 xgifb_reg_set(P3d4,
286 0x85,
2af1a29d 287 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
bf32fcb9
KT		 288 xgifb_reg_set(P3d4,
289 0x86,
2af1a29d 290 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
a24d60f4 291
8104e329
AK		 292 xgifb_reg_set(P3d4, 0x98, 0x01);
293 xgifb_reg_set(P3d4, 0x9A, 0x02);
a24d60f4 294
b9ebf5e5
AK		 295 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
296 } else {
b053af16 297 XGINew_SetMemoryClock(pVBInfo);
a24d60f4 298
b9ebf5e5 299 switch (HwDeviceExtension->jChipType) {
b9ebf5e5 300 case XG42:
bf32fcb9
KT		 301 /* CR82 */
302 xgifb_reg_set(P3d4,
303 0x82,
2af1a29d 304 pVBInfo->CR40[11][pVBInfo->ram_type]);
bf32fcb9
KT		 305 /* CR85 */
306 xgifb_reg_set(P3d4,
307 0x85,
2af1a29d 308 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 309 /* CR86 */
310 xgifb_reg_set(P3d4,
311 0x86,
2af1a29d 312 pVBInfo->CR40[13][pVBInfo->ram_type]);
b9ebf5e5
AK		 313 break;
314 default:
8104e329
AK		 315 xgifb_reg_set(P3d4, 0x82, 0x88);
316 xgifb_reg_set(P3d4, 0x86, 0x00);
bf32fcb9
KT		 317 /* Insert read command for delay */
318 xgifb_reg_get(P3d4, 0x86);
8104e329 319 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 320 xgifb_reg_get(P3d4, 0x86);
bf32fcb9
KT		 321 xgifb_reg_set(P3d4,
322 0x86,
2af1a29d 323 pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 324 xgifb_reg_set(P3d4, 0x82, 0x77);
325 xgifb_reg_set(P3d4, 0x85, 0x00);
bf32fcb9
KT		 326
327 /* Insert read command for delay */
328 xgifb_reg_get(P3d4, 0x85);
8104e329 329 xgifb_reg_set(P3d4, 0x85, 0x88);
bf32fcb9
KT		 330
331 /* Insert read command for delay */
332 xgifb_reg_get(P3d4, 0x85);
333 /* CR85 */
334 xgifb_reg_set(P3d4,
335 0x85,
2af1a29d 336 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 337 /* CR82 */
338 xgifb_reg_set(P3d4,
339 0x82,
2af1a29d 340 pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 341 break;
a24d60f4 342 }
a24d60f4 343
8104e329
AK		 344 xgifb_reg_set(P3d4, 0x97, 0x00);
345 xgifb_reg_set(P3d4, 0x98, 0x01);
346 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 347 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
348 }
349}
a24d60f4 350
b9ebf5e5
AK		 351static void XGINew_DDR2_DefaultRegister(
352 struct xgi_hw_device_info *HwDeviceExtension,
353 unsigned long Port, struct vb_device_info *pVBInfo)
354{
355 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 356
bf32fcb9 357 /* keep following setting sequence, each setting in
56e18f8c
CB		 358 * the same reg insert idle
359 */
8104e329
AK		 360 xgifb_reg_set(P3d4, 0x82, 0x77);
361 xgifb_reg_set(P3d4, 0x86, 0x00);
58839b01 362 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
8104e329 363 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 364 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
bf32fcb9 365 /* CR86 */
2af1a29d 366 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 367 xgifb_reg_set(P3d4, 0x82, 0x77);
368 xgifb_reg_set(P3d4, 0x85, 0x00);
58839b01 369 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
8104e329 370 xgifb_reg_set(P3d4, 0x85, 0x88);
58839b01 371 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
2af1a29d
AK		 372 xgifb_reg_set(P3d4,
373 0x85,
374 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
b9ebf5e5 375 if (HwDeviceExtension->jChipType == XG27)
bf32fcb9 376 /* CR82 */
2af1a29d 377 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 378 else
8104e329 379 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
a24d60f4 380
8104e329
AK		 381 xgifb_reg_set(P3d4, 0x98, 0x01);
382 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 383 if (HwDeviceExtension->jChipType == XG27)
384 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
385 else
386 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
387}
a24d60f4 388
0141bb2e
PH		 389static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
390 u8 shift_factor, u8 mask1, u8 mask2)
391{
392 u8 j;
694683f6 393
0141bb2e
PH		 394 for (j = 0; j < 4; j++) {
395 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
396 xgifb_reg_set(P3d4, reg, temp2);
397 xgifb_reg_get(P3d4, reg);
398 temp2 &= mask1;
399 temp2 += mask2;
400 }
401}
402
b9ebf5e5
AK		 403static void XGINew_SetDRAMDefaultRegister340(
404 struct xgi_hw_device_info *HwDeviceExtension,
405 unsigned long Port, struct vb_device_info *pVBInfo)
406{
fc008aff 407 unsigned char temp, temp1, temp2, temp3, j, k;
a24d60f4 408
b9ebf5e5 409 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 410
2af1a29d
AK		 411 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
412 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
413 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
414 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
a24d60f4 415
1504ecbe 416 /* CR6B DQS fine tune delay */
6a7fd2db 417 temp = 0xaa;
1504ecbe 418 XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
a24d60f4 419
1504ecbe
PH		 420 /* CR6E DQM fine tune delay */
421 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
a24d60f4 422
b9ebf5e5
AK		 423 temp3 = 0;
424 for (k = 0; k < 4; k++) {
bf32fcb9
KT		 425 /* CR6E_D[1:0] select channel */
426 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
1504ecbe 427 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
b9ebf5e5
AK		 428 temp3 += 0x01;
429 }
a24d60f4 430
2af1a29d
AK		 431 xgifb_reg_set(P3d4,
432 0x80,
433 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
434 xgifb_reg_set(P3d4,
435 0x81,
436 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
a24d60f4 437
b9ebf5e5 438 temp2 = 0x80;
bf32fcb9 439 /* CR89 terminator type select */
0141bb2e 440 XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
a24d60f4 441
7e29d632 442 temp = 0;
b9ebf5e5
AK		 443 temp1 = temp & 0x03;
444 temp2 |= temp1;
8104e329 445 xgifb_reg_set(P3d4, 0x89, temp2);
a24d60f4 446
2af1a29d 447 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
b9ebf5e5
AK		 448 temp1 = temp & 0x0F;
449 temp2 = (temp >> 4) & 0x07;
450 temp3 = temp & 0x80;
8104e329
AK		 451 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
452 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
b9bf6e4e 453 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
2af1a29d
AK		 454 xgifb_reg_set(P3d4,
455 0x41,
456 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
a24d60f4 457
b9ebf5e5 458 if (HwDeviceExtension->jChipType == XG27)
6d12dae4 459 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
a24d60f4 460
bf32fcb9 461 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
8104e329 462 xgifb_reg_set(P3d4, (0x90 + j),
2af1a29d 463 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
a24d60f4 464
bf32fcb9 465 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
8104e329 466 xgifb_reg_set(P3d4, (0xC3 + j),
2af1a29d 467 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
a24d60f4 468
bf32fcb9 469 for (j = 0; j < 2; j++) /* CR8A - CR8B */
8104e329 470 xgifb_reg_set(P3d4, (0x8A + j),
2af1a29d 471 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
a24d60f4 472
18408da0 473 if (HwDeviceExtension->jChipType == XG42)
8104e329 474 xgifb_reg_set(P3d4, 0x8C, 0x87);
a24d60f4 475
2af1a29d
AK		 476 xgifb_reg_set(P3d4,
477 0x59,
478 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
a24d60f4 479
8104e329
AK		 480 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
481 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
6d12dae4 482 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
2af1a29d 483 if (pVBInfo->ram_type) {
8104e329 484 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
b9ebf5e5 485 if (HwDeviceExtension->jChipType == XG27)
8104e329 486 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
a24d60f4 487
b9ebf5e5 488 } else {
8104e329 489 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
b9ebf5e5 490 }
8104e329 491 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
a24d60f4 492
b9ebf5e5
AK		 493 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
494 if (temp == 0) {
495 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
496 } else {
8104e329 497 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
b9ebf5e5
AK		 498 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
499 }
d7ab4a4f 500 xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
b9ebf5e5 501}
a24d60f4 502
d6461e49
PH		 503static unsigned short XGINew_SetDRAMSize20Reg(
504 unsigned short dram_size,
b9ebf5e5 505 struct vb_device_info *pVBInfo)
d7636e0b 506{
b9ebf5e5
AK		 507 unsigned short data = 0, memsize = 0;
508 int RankSize;
509 unsigned char ChannelNo;
d7636e0b 510
d6461e49 511 RankSize = dram_size * pVBInfo->ram_bus / 8;
58839b01 512 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
b9ebf5e5 513 data &= 0x80;
d7636e0b 514
b9ebf5e5
AK		 515 if (data == 0x80)
516 RankSize *= 2;
a24d60f4 517
b9ebf5e5 518 data = 0;
a24d60f4 519
ee055a48 520 if (pVBInfo->ram_channel == 3)
b9ebf5e5
AK		 521 ChannelNo = 4;
522 else
ee055a48 523 ChannelNo = pVBInfo->ram_channel;
a24d60f4 524
b9ebf5e5
AK		 525 if (ChannelNo * RankSize <= 256) {
526 while ((RankSize >>= 1) > 0)
527 data += 0x10;
a24d60f4 528
b9ebf5e5 529 memsize = data >> 4;
a24d60f4 530
949eb0ae 531 /* Fix DRAM Sizing Error */
bf32fcb9
KT		 532 xgifb_reg_set(pVBInfo->P3c4,
533 0x14,
534 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
535 (data & 0xF0));
d8acac94 536 usleep_range(15, 1015);
b9ebf5e5
AK		 537 }
538 return memsize;
539}
a24d60f4 540
b9ebf5e5
AK		 541static int XGINew_ReadWriteRest(unsigned short StopAddr,
542 unsigned short StartAddr, struct vb_device_info *pVBInfo)
543{
544 int i;
545 unsigned long Position = 0;
c44fa627 546 void __iomem *fbaddr = pVBInfo->FBAddr;
a24d60f4 547
c44fa627 548 writel(Position, fbaddr + Position);
a24d60f4 549
b9ebf5e5
AK		 550 for (i = StartAddr; i <= StopAddr; i++) {
551 Position = 1 << i;
c44fa627 552 writel(Position, fbaddr + Position);
b9ebf5e5 553 }
a24d60f4 554
d3d62d1d
CB		 555 /* Fix #1759 Memory Size error in Multi-Adapter. */
556 usleep_range(500, 1500);
a24d60f4 557
b9ebf5e5
AK		 558 Position = 0;
559
c44fa627 560 if (readl(fbaddr + Position) != Position)
b9ebf5e5 561 return 0;
d7636e0b 562
b9ebf5e5
AK		 563 for (i = StartAddr; i <= StopAddr; i++) {
564 Position = 1 << i;
c44fa627 565 if (readl(fbaddr + Position) != Position)
b9ebf5e5
AK		 566 return 0;
567 }
568 return 1;
d7636e0b 569}
a24d60f4 570
b9ebf5e5 571static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
d7636e0b 572{
b9ebf5e5 573 unsigned char data;
a24d60f4 574
58839b01 575 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
a24d60f4 576
b9ebf5e5 577 if ((data & 0x10) == 0) {
58839b01 578 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
b9ebf5e5
AK		 579 data = (data & 0x02) >> 1;
580 return data;
b9ebf5e5 581 }
9c8c8315 582 return data & 0x01;
b9ebf5e5 583}
a24d60f4 584
b9ebf5e5
AK		 585static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
586 struct vb_device_info *pVBInfo)
587{
588 unsigned char data;
a24d60f4 589
b9ebf5e5
AK		 590 switch (HwDeviceExtension->jChipType) {
591 case XG20:
592 case XG21:
58839b01 593 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
b9ebf5e5 594 data = data & 0x01;
ee055a48 595 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
a24d60f4 596
b9ebf5e5 597 if (data == 0) { /* Single_32_16 */
a24d60f4 598
b9ebf5e5
AK		 599 if ((HwDeviceExtension->ulVideoMemorySize - 1)
600 > 0x1000000) {
2f0f395e 601 pVBInfo->ram_bus = 32; /* 32 bits */
bf32fcb9
KT		 602 /* 22bit + 2 rank + 32bit */
603 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 604 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
d8acac94 605 usleep_range(15, 1015);
a24d60f4 606
b9ebf5e5
AK		 607 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
608 return;
d7636e0b 609
bf32fcb9
KT		 610 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
611 0x800000) {
612 /* 22bit + 1 rank + 32bit */
613 xgifb_reg_set(pVBInfo->P3c4,
614 0x13,
615 0x31);
616 xgifb_reg_set(pVBInfo->P3c4,
617 0x14,
618 0x42);
d8acac94 619 usleep_range(15, 1015);
a24d60f4 620
bf32fcb9
KT		 621 if (XGINew_ReadWriteRest(23,
622 23,
623 pVBInfo) == 1)
b9ebf5e5
AK		 624 return;
625 }
626 }
a24d60f4 627
bf32fcb9
KT		 628 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
629 0x800000) {
2f0f395e 630 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 631 /* 22bit + 2 rank + 16bit */
632 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 633 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
d8acac94 634 usleep_range(15, 1015);
a24d60f4 635
b9ebf5e5
AK		 636 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
637 return;
9c8c8315
TG		 638 xgifb_reg_set(pVBInfo->P3c4,
639 0x13,
640 0x31);
d8acac94 641 usleep_range(15, 1015);
b9ebf5e5 642 }
a24d60f4 643
b9ebf5e5 644 } else { /* Dual_16_8 */
bf32fcb9
KT		 645 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
646 0x800000) {
2f0f395e 647 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 648 /* (0x31:12x8x2) 22bit + 2 rank */
649 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
650 /* 0x41:16Mx16 bit*/
651 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
d8acac94 652 usleep_range(15, 1015);
a24d60f4 653
b9ebf5e5
AK		 654 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
655 return;
a24d60f4 656
bf32fcb9
KT		 657 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
658 0x400000) {
659 /* (0x31:12x8x2) 22bit + 1 rank */
660 xgifb_reg_set(pVBInfo->P3c4,
661 0x13,
662 0x31);
663 /* 0x31:8Mx16 bit*/
664 xgifb_reg_set(pVBInfo->P3c4,
665 0x14,
666 0x31);
d8acac94 667 usleep_range(15, 1015);
a24d60f4 668
bf32fcb9
KT		 669 if (XGINew_ReadWriteRest(22,
670 22,
671 pVBInfo) == 1)
b9ebf5e5
AK		 672 return;
673 }
674 }
a24d60f4 675
bf32fcb9
KT		 676 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
677 0x400000) {
2f0f395e 678 pVBInfo->ram_bus = 8; /* 8 bits */
bf32fcb9
KT		 679 /* (0x31:12x8x2) 22bit + 2 rank */
680 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
681 /* 0x30:8Mx8 bit*/
682 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
d8acac94 683 usleep_range(15, 1015);
d7636e0b 684
b9ebf5e5
AK		 685 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
686 return;
9c8c8315
TG		 687
688 /* (0x31:12x8x2) 22bit + 1 rank */
689 xgifb_reg_set(pVBInfo->P3c4,
690 0x13,
691 0x31);
d8acac94 692 usleep_range(15, 1015);
a24d60f4
PS		 693 }
694 }
b9ebf5e5 695 break;
a24d60f4 696
b9ebf5e5 697 case XG27:
2f0f395e 698 pVBInfo->ram_bus = 16; /* 16 bits */
ee055a48 699 pVBInfo->ram_channel = 1; /* Single channel */
8104e329 700 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
b9ebf5e5 701 break;
b9ebf5e5
AK		 702 case XG42:
703 /*
56e18f8c
CB		 704 * XG42 SR14 D[3] Reserve
705 * D[2] = 1, Dual Channel
706 * = 0, Single Channel
707 *
708 * It's Different from Other XG40 Series.
b9ebf5e5
AK		 709 */
710 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
2f0f395e 711 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 712 pVBInfo->ram_channel = 2; /* 2 Channel */
8104e329
AK		 713 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
714 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
a24d60f4 715
b9ebf5e5
AK		 716 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
717 return;
a24d60f4 718
8104e329
AK		 719 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
720 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
b9ebf5e5
AK		 721 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
722 return;
a24d60f4 723
ee055a48 724 pVBInfo->ram_channel = 1; /* Single Channel */
8104e329
AK		 725 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
726 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
d7636e0b 727
b9ebf5e5
AK		 728 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
729 return;
9c8c8315
TG		 730 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
731 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
b9ebf5e5 732 } else { /* DDR */
2f0f395e 733 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 734 pVBInfo->ram_channel = 1; /* 1 channels */
8104e329
AK		 735 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
736 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
d7636e0b 737
b9ebf5e5
AK		 738 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
739 return;
9c8c8315
TG		 740 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
741 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
b9ebf5e5 742 }
d7636e0b 743
b9ebf5e5 744 break;
d7636e0b 745
b9ebf5e5 746 default: /* XG40 */
d7636e0b 747
b9ebf5e5 748 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
2f0f395e 749 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 750 pVBInfo->ram_channel = 3;
8104e329
AK		 751 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
752 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
d7636e0b 753
b9ebf5e5
AK		 754 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
755 return;
d7636e0b 756
ee055a48 757 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 758 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
a24d60f4 759
b9ebf5e5
AK		 760 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
761 return;
d7636e0b 762
8104e329
AK		 763 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
764 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
d7636e0b 765
b9ebf5e5 766 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
ee055a48 767 pVBInfo->ram_channel = 3; /* 4 channels */
b9ebf5e5 768 } else {
ee055a48 769 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 770 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
b9ebf5e5
AK		 771 }
772 } else { /* DDR */
2f0f395e 773 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 774 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329
AK		 775 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
776 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
d7636e0b 777
9c8c8315 778 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
b9ebf5e5 779 return;
9c8c8315
TG		 780 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
781 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
b9ebf5e5
AK		 782 }
783 break;
a24d60f4 784 }
d7636e0b 785}
786
b9ebf5e5
AK		 787static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
788 struct vb_device_info *pVBInfo)
d7636e0b 789{
672f5ee2
PH		 790 u8 i, size;
791 unsigned short memsize, start_addr;
d6461e49 792 const unsigned short (*dram_table)[2];
d7636e0b 793
8104e329
AK		 794 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
795 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
b9ebf5e5 796 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
d7636e0b 797
b9ebf5e5 798 if (HwDeviceExtension->jChipType >= XG20) {
672f5ee2
PH		 799 dram_table = XGINew_DDRDRAM_TYPE20;
800 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
801 start_addr = 5;
b9ebf5e5 802 } else {
672f5ee2
PH		 803 dram_table = XGINew_DDRDRAM_TYPE340;
804 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
805 start_addr = 9;
806 }
807
808 for (i = 0; i < size; i++) {
4e55d0b3 809 /* SetDRAMSizingType */
d6461e49 810 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
d8acac94 811 usleep_range(50, 1050); /* should delay 50 ns */
4e55d0b3 812
d6461e49 813 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
672f5ee2
PH		 814
815 if (memsize == 0)
816 continue;
817
818 memsize += (pVBInfo->ram_channel - 2) + 20;
819 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
c3a56f75 820 (unsigned long)(1 << memsize))
672f5ee2
PH		 821 continue;
822
823 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
824 return 1;
a24d60f4 825 }
b9ebf5e5 826 return 0;
a24d60f4 827}
d7636e0b 828
fab04b97
AK		 829static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
830 struct xgi_hw_device_info *HwDeviceExtension,
a24d60f4 831 struct vb_device_info *pVBInfo)
d7636e0b 832{
b9ebf5e5 833 unsigned short data;
a24d60f4 834
b9ebf5e5 835 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 836
fab04b97 837 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
a24d60f4 838
58839b01 839 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9 840 /* disable read cache */
c3a56f75 841 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
fab04b97 842 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
a24d60f4 843
b9ebf5e5 844 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
58839b01 845 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9 846 /* enable read cache */
c3a56f75 847 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
b9ebf5e5 848}
a24d60f4 849
08ce239c 850static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
02a81dd9
AK		 851{
852 void __iomem *rom_address;
82986dd9 853 u8 *rom_copy;
02a81dd9 854
08ce239c 855 rom_address = pci_map_rom(dev, rom_size);
076e2358 856 if (!rom_address)
02a81dd9
AK		 857 return NULL;
858
859 rom_copy = vzalloc(XGIFB_ROM_SIZE);
076e2358 860 if (!rom_copy)
02a81dd9
AK		 861 goto done;
862
08ce239c
AK		 863 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
864 memcpy_fromio(rom_copy, rom_address, *rom_size);
02a81dd9
AK		 865
866done:
867 pci_unmap_rom(dev, rom_address);
868 return rom_copy;
869}
870
334ab072 871static bool xgifb_read_vbios(struct pci_dev *pdev)
b9ebf5e5 872{
02a81dd9 873 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
82986dd9 874 u8 *vbios;
b9ebf5e5 875 unsigned long i;
d1805b38 876 unsigned char j;
97f4532d 877 struct XGI21_LVDSCapStruct *lvds;
08ce239c 878 size_t vbios_size;
d1805b38 879 int entry;
a24d60f4 880
08ce239c 881 vbios = xgifb_copy_rom(pdev, &vbios_size);
076e2358 882 if (!vbios) {
be25aef0 883 dev_err(&pdev->dev, "Video BIOS not available\n");
c0d60da8 884 return false;
02a81dd9 885 }
08ce239c
AK		 886 if (vbios_size <= 0x65)
887 goto error;
25aa75f1
AK		 888 /*
889 * The user can ignore the LVDS bit in the BIOS and force the display
890 * type.
891 */
892 if (!(vbios[0x65] & 0x1) &&
893 (!xgifb_info->display2_force ||
894 xgifb_info->display2 != XGIFB_DISP_LCD)) {
02a81dd9 895 vfree(vbios);
c0d60da8 896 return false;
02a81dd9 897 }
08ce239c
AK		 898 if (vbios_size <= 0x317)
899 goto error;
4b21d990 900 i = vbios[0x316] | (vbios[0x317] << 8);
08ce239c
AK		 901 if (vbios_size <= i - 1)
902 goto error;
4b21d990 903 j = vbios[i - 1];
08ce239c
AK		 904 if (j == 0)
905 goto error;
bd761274
AK		 906 if (j == 0xff)
907 j = 1;
d1805b38
AK		 908 /*
909 * Read the LVDS table index scratch register set by the BIOS.
910 */
911 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
912 if (entry >= j)
913 entry = 0;
914 i += entry * 25;
fab04b97 915 lvds = &xgifb_info->lvds_data;
d1805b38
AK		 916 if (vbios_size <= i + 24)
917 goto error;
918 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
919 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
920 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
921 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
922 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
923 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
924 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
925 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
926 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
927 lvds->VCLKData1 = vbios[i + 18];
928 lvds->VCLKData2 = vbios[i + 19];
929 lvds->PSC_S1 = vbios[i + 20];
930 lvds->PSC_S2 = vbios[i + 21];
931 lvds->PSC_S3 = vbios[i + 22];
932 lvds->PSC_S4 = vbios[i + 23];
933 lvds->PSC_S5 = vbios[i + 24];
02a81dd9 934 vfree(vbios);
c0d60da8 935 return true;
08ce239c 936error:
be25aef0 937 dev_err(&pdev->dev, "Video BIOS corrupted\n");
08ce239c 938 vfree(vbios);
c0d60da8 939 return false;
b9ebf5e5 940}
a24d60f4 941
b053af16 942static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 943{
944 unsigned short tempbx = 0, temp, tempcx, CR3CData;
a24d60f4 945
58839b01 946 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
a24d60f4 947
b9ebf5e5
AK		 948 if (temp & Monitor1Sense)
949 tempbx |= ActiveCRT1;
950 if (temp & LCDSense)
951 tempbx |= ActiveLCD;
952 if (temp & Monitor2Sense)
953 tempbx |= ActiveCRT2;
954 if (temp & TVSense) {
955 tempbx |= ActiveTV;
956 if (temp & AVIDEOSense)
957 tempbx |= (ActiveAVideo << 8);
958 if (temp & SVIDEOSense)
959 tempbx |= (ActiveSVideo << 8);
960 if (temp & SCARTSense)
961 tempbx |= (ActiveSCART << 8);
962 if (temp & HiTVSense)
963 tempbx |= (ActiveHiTV << 8);
964 if (temp & YPbPrSense)
965 tempbx |= (ActiveYPbPr << 8);
966 }
a24d60f4 967
58839b01
AK		 968 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
969 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
a24d60f4 970
b9ebf5e5 971 if (tempbx & tempcx) {
58839b01 972 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
3bcc2460 973 if (!(CR3CData & DisplayDeviceFromCMOS))
b9ebf5e5 974 tempcx = 0x1FF0;
b9ebf5e5
AK		 975 } else {
976 tempcx = 0x1FF0;
b9ebf5e5 977 }
a24d60f4 978
b9ebf5e5 979 tempbx &= tempcx;
8104e329
AK		 980 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
981 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
b9ebf5e5 982}
d7636e0b 983
b053af16 984static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 985{
986 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
d7636e0b 987
58839b01
AK		 988 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
989 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
990 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
d7636e0b 991
b9ebf5e5
AK		 992 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
993 if (temp & ActiveCRT2)
994 tempcl = SetCRT2ToRAMDAC;
995 }
d7636e0b 996
b9ebf5e5
AK		 997 if (temp & ActiveLCD) {
998 tempcl |= SetCRT2ToLCD;
999 if (temp & DriverMode) {
1000 if (temp & ActiveTV) {
1001 tempch = SetToLCDA | EnableDualEdge;
1002 temp ^= SetCRT2ToLCD;
d7636e0b 1003
b9ebf5e5
AK		 1004 if ((temp >> 8) & ActiveAVideo)
1005 tempcl |= SetCRT2ToAVIDEO;
1006 if ((temp >> 8) & ActiveSVideo)
1007 tempcl |= SetCRT2ToSVIDEO;
1008 if ((temp >> 8) & ActiveSCART)
1009 tempcl |= SetCRT2ToSCART;
a24d60f4 1010
b9ebf5e5
AK		 1011 if (pVBInfo->IF_DEF_HiVision == 1) {
1012 if ((temp >> 8) & ActiveHiTV)
599801f9 1013 tempcl |= SetCRT2ToHiVision;
b9ebf5e5 1014 }
a24d60f4 1015
b9ebf5e5
AK		 1016 if (pVBInfo->IF_DEF_YPbPr == 1) {
1017 if ((temp >> 8) & ActiveYPbPr)
1018 tempch |= SetYPbPr;
1019 }
1020 }
1021 }
1022 } else {
1023 if ((temp >> 8) & ActiveAVideo)
1024 tempcl |= SetCRT2ToAVIDEO;
1025 if ((temp >> 8) & ActiveSVideo)
1026 tempcl |= SetCRT2ToSVIDEO;
1027 if ((temp >> 8) & ActiveSCART)
1028 tempcl |= SetCRT2ToSCART;
a24d60f4 1029
b9ebf5e5
AK		 1030 if (pVBInfo->IF_DEF_HiVision == 1) {
1031 if ((temp >> 8) & ActiveHiTV)
599801f9 1032 tempcl |= SetCRT2ToHiVision;
b9ebf5e5 1033 }
a24d60f4 1034
b9ebf5e5
AK		 1035 if (pVBInfo->IF_DEF_YPbPr == 1) {
1036 if ((temp >> 8) & ActiveYPbPr)
1037 tempch |= SetYPbPr;
1038 }
1039 }
d7636e0b 1040
b9ebf5e5
AK		 1041 tempcl |= SetSimuScanMode;
1042 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1043 || (temp & ActiveCRT2)))
6896b94e 1044 tempcl ^= (SetSimuScanMode | SwitchCRT2);
b9ebf5e5 1045 if ((temp & ActiveLCD) && (temp & ActiveTV))
6896b94e 1046 tempcl ^= (SetSimuScanMode | SwitchCRT2);
8104e329 1047 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
d7636e0b 1048
58839b01 1049 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
b9ebf5e5
AK		 1050 CR31Data &= ~(SetNotSimuMode >> 8);
1051 if (!(temp & ActiveCRT1))
1052 CR31Data |= (SetNotSimuMode >> 8);
1053 CR31Data &= ~(DisableCRT2Display >> 8);
1054 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1055 CR31Data |= (DisableCRT2Display >> 8);
8104e329 1056 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
d7636e0b 1057
58839b01 1058 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1059 CR38Data &= ~SetYPbPr;
1060 CR38Data |= tempch;
8104e329 1061 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
b9ebf5e5 1062}
a24d60f4 1063
40544b04
AK		 1064static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1065 *HwDeviceExtension,
1066 struct vb_device_info *pVBInfo)
1067{
bcd1f165
PH		 1068 unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1069
1070 switch (HwDeviceExtension->ulCRT2LCDType) {
1071 case LCD_640x480:
1072 case LCD_1024x600:
1073 case LCD_1152x864:
1074 case LCD_1280x960:
1075 case LCD_1152x768:
1076 case LCD_1920x1440:
1077 case LCD_2048x1536:
1078 temp = 0; /* overwrite used ulCRT2LCDType */
1079 break;
1080 case LCD_UNKNOWN: /* unknown lcd, do nothing */
40544b04 1081 return 0;
40544b04 1082 }
bcd1f165
PH		 1083 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1084 return 1;
40544b04
AK		 1085}
1086
c0d60da8 1087static void XGINew_GetXG21Sense(struct pci_dev *pdev,
b9ebf5e5
AK		 1088 struct vb_device_info *pVBInfo)
1089{
c0d60da8 1090 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
b9ebf5e5 1091 unsigned char Temp;
a24d60f4 1092
334ab072 1093 if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
b9bf6e4e 1094 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1095 /* LVDS on chip */
1096 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
b9ebf5e5 1097 } else {
bf32fcb9
KT		 1098 /* Enable GPIOA/B read */
1099 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1100 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
b9ebf5e5 1101 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
c0d60da8 1102 XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
b9bf6e4e 1103 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1104 /* Enable read GPIOF */
1105 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
9195ba09
PH		 1106 if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1107 Temp = 0xA0; /* Only DVO on chip */
a24d60f4 1108 else
9195ba09
PH		 1109 Temp = 0x80; /* TMDS on chip */
1110 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
bf32fcb9
KT		 1111 /* Disable read GPIOF */
1112 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
a24d60f4 1113 }
b9ebf5e5 1114 }
b9ebf5e5 1115}
a24d60f4 1116
b053af16 1117static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
b9ebf5e5
AK		 1118{
1119 unsigned char Temp, bCR4A;
a24d60f4 1120
58839b01 1121 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1122 /* Enable GPIOA/B/C read */
1123 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
58839b01 1124 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
8104e329 1125 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
a24d60f4 1126
b9ebf5e5 1127 if (Temp <= 0x02) {
bf32fcb9
KT		 1128 /* LVDS setting */
1129 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
8104e329 1130 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
b9ebf5e5 1131 } else {
bf32fcb9
KT		 1132 /* TMDS/DVO setting */
1133 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
b9ebf5e5 1134 }
b9bf6e4e 1135 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
b9ebf5e5 1136}
a24d60f4 1137
b9ebf5e5
AK		 1138static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1139{
1140 unsigned char CR38, CR4A, temp;
a24d60f4 1141
58839b01 1142 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1143 /* enable GPIOE read */
1144 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
58839b01 1145 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1146 temp = 0;
1147 if ((CR38 & 0xE0) > 0x80) {
58839b01 1148 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5
AK		 1149 temp &= 0x08;
1150 temp >>= 3;
1151 }
a24d60f4 1152
8104e329 1153 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1154
b9ebf5e5
AK		 1155 return temp;
1156}
a24d60f4 1157
b9ebf5e5
AK		 1158static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1159{
1160 unsigned char CR4A, temp;
a24d60f4 1161
58839b01 1162 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1163 /* enable GPIOA/B/C read */
1164 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1165 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
986eb9fa 1166 if (temp > 2)
2f123cbc 1167 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
a24d60f4 1168
8104e329 1169 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1170
b9ebf5e5
AK		 1171 return temp;
1172}
a24d60f4 1173
c976c781
AK		 1174static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1175{
1176 u8 flag;
1177
1178 flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1179 return flag == 1 || flag == 2;
1180}
1181
6048d761 1182unsigned char XGIInitNew(struct pci_dev *pdev)
b9ebf5e5 1183{
ab886ff8 1184 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
6048d761 1185 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
b9ebf5e5
AK		 1186 struct vb_device_info VBINF;
1187 struct vb_device_info *pVBInfo = &VBINF;
1188 unsigned char i, temp = 0, temp1;
a24d60f4 1189
b9ebf5e5 1190 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 1191
076e2358 1192 if (!pVBInfo->FBAddr) {
19185703 1193 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
b9ebf5e5
AK		 1194 return 0;
1195 }
a24d60f4 1196
56810a92 1197 XGIRegInit(pVBInfo, xgifb_info->vga_base);
d7636e0b 1198
b8e1cc5c
AK		 1199 outb(0x67, pVBInfo->P3c2);
1200
b9ebf5e5
AK		 1201 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1202
949eb0ae 1203 /* Openkey */
8104e329 1204 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
b9ebf5e5
AK		 1205
1206 /* GetXG21Sense (GPIO) */
1207 if (HwDeviceExtension->jChipType == XG21)
c0d60da8 1208 XGINew_GetXG21Sense(pdev, pVBInfo);
b9ebf5e5
AK		 1209
1210 if (HwDeviceExtension->jChipType == XG27)
b053af16 1211 XGINew_GetXG27Sense(pVBInfo);
b9ebf5e5 1212
949eb0ae 1213 /* Reset Extended register */
b9ebf5e5
AK		 1214
1215 for (i = 0x06; i < 0x20; i++)
8104e329 1216 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5
AK		 1217
1218 for (i = 0x21; i <= 0x27; i++)
8104e329 1219 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5 1220
06587335 1221 for (i = 0x31; i <= 0x3B; i++)
8104e329 1222 xgifb_reg_set(pVBInfo->P3c4, i, 0);
d7636e0b 1223
949eb0ae 1224 /* Auto over driver for XG42 */
bf32fcb9 1225 if (HwDeviceExtension->jChipType == XG42)
8104e329 1226 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
d7636e0b 1227
b9ebf5e5 1228 for (i = 0x79; i <= 0x7C; i++)
949eb0ae 1229 xgifb_reg_set(pVBInfo->P3d4, i, 0);
d7636e0b 1230
b9ebf5e5 1231 if (HwDeviceExtension->jChipType >= XG20)
6d12dae4 1232 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
a24d60f4 1233
949eb0ae 1234 /* SetDefExt1Regs begin */
6d12dae4 1235 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
b9ebf5e5 1236 if (HwDeviceExtension->jChipType == XG27) {
6d12dae4
PH		 1237 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1238 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
a24d60f4 1239 }
8104e329 1240 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
6d12dae4 1241 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
949eb0ae 1242 /* Frame buffer can read/write SR20 */
bf32fcb9 1243 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
949eb0ae 1244 /* H/W request for slow corner chip */
bf32fcb9 1245 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
949eb0ae 1246 if (HwDeviceExtension->jChipType == XG27)
6d12dae4 1247 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
a24d60f4 1248
949eb0ae 1249 if (HwDeviceExtension->jChipType < XG20) {
6048d761
AK		 1250 u32 Temp;
1251
06587335
AK		 1252 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1253 for (i = 0x47; i <= 0x4C; i++)
bf32fcb9
KT		 1254 xgifb_reg_set(pVBInfo->P3d4,
1255 i,
ea12b4e0 1256 XGI340_AGPReg[i - 0x47]);
06587335
AK		 1257
1258 for (i = 0x70; i <= 0x71; i++)
bf32fcb9
KT		 1259 xgifb_reg_set(pVBInfo->P3d4,
1260 i,
ea12b4e0 1261 XGI340_AGPReg[6 + i - 0x70]);
06587335
AK		 1262
1263 for (i = 0x74; i <= 0x77; i++)
bf32fcb9
KT		 1264 xgifb_reg_set(pVBInfo->P3d4,
1265 i,
ea12b4e0 1266 XGI340_AGPReg[8 + i - 0x74]);
06587335 1267
6048d761 1268 pci_read_config_dword(pdev, 0x50, &Temp);
06587335
AK		 1269 Temp >>= 20;
1270 Temp &= 0xF;
1271
1272 if (Temp == 1)
8104e329 1273 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
b9ebf5e5 1274 } /* != XG20 */
a24d60f4 1275
b9ebf5e5 1276 /* Set PCI */
6d12dae4
PH		 1277 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1278 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
38c09652 1279 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
a24d60f4 1280
949eb0ae 1281 if (HwDeviceExtension->jChipType < XG20) {
b9ebf5e5 1282 /* Set VB */
b053af16 1283 XGI_UnLockCRT2(pVBInfo);
949eb0ae 1284 /* disable VideoCapture */
bf32fcb9 1285 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
8104e329 1286 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
bf32fcb9 1287 /* chk if BCLK>=100MHz */
9388ad9c 1288 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
a24d60f4 1289
bf32fcb9 1290 xgifb_reg_set(pVBInfo->Part1Port,
6d12dae4 1291 0x02, XGI330_CRT2Data_1_2);
a24d60f4 1292
8104e329 1293 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
b9ebf5e5 1294 } /* != XG20 */
a24d60f4 1295
8104e329 1296 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
b9ebf5e5 1297
bf32fcb9
KT		 1298 if ((HwDeviceExtension->jChipType == XG42) &&
1299 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1300 /* Not DDR */
1301 xgifb_reg_set(pVBInfo->P3c4,
1302 0x31,
6d12dae4 1303 (XGI330_SR31 & 0x3F) | 0x40);
bf32fcb9
KT		 1304 xgifb_reg_set(pVBInfo->P3c4,
1305 0x32,
6d12dae4 1306 (XGI330_SR32 & 0xFC) | 0x01);
a24d60f4 1307 } else {
6d12dae4
PH		 1308 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1309 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
b9ebf5e5 1310 }
6d12dae4 1311 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
a24d60f4 1312
949eb0ae 1313 if (HwDeviceExtension->jChipType < XG20) {
c976c781 1314 if (xgifb_bridge_is_on(pVBInfo)) {
6bc54277
AK		 1315 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1316 xgifb_reg_set(pVBInfo->Part4Port,
1317 0x0D, XGI330_CRT2Data_4_D);
1318 xgifb_reg_set(pVBInfo->Part4Port,
1319 0x0E, XGI330_CRT2Data_4_E);
1320 xgifb_reg_set(pVBInfo->Part4Port,
1321 0x10, XGI330_CRT2Data_4_10);
1322 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
b053af16 1323 XGI_LockCRT2(pVBInfo);
a24d60f4 1324 }
b9ebf5e5 1325 } /* != XG20 */
a24d60f4 1326
b9ebf5e5 1327 XGI_SenseCRT1(pVBInfo);
d7636e0b 1328
b9ebf5e5 1329 if (HwDeviceExtension->jChipType == XG21) {
bf32fcb9
KT		 1330 xgifb_reg_and_or(pVBInfo->P3d4,
1331 0x32,
1332 ~Monitor1Sense,
1333 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1334 temp = GetXG21FPBits(pVBInfo);
ec9e5d3e 1335 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
a24d60f4 1336 }
b9ebf5e5 1337 if (HwDeviceExtension->jChipType == XG27) {
bf32fcb9
KT		 1338 xgifb_reg_and_or(pVBInfo->P3d4,
1339 0x32,
1340 ~Monitor1Sense,
1341 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1342 temp = GetXG27FPBits(pVBInfo);
ec9e5d3e 1343 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
b9ebf5e5 1344 }
d7636e0b 1345
2af1a29d 1346 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
d7636e0b 1347
bf32fcb9
KT		 1348 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1349 pVBInfo->P3d4,
1350 pVBInfo);
a24d60f4 1351
fab04b97 1352 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
d7636e0b 1353
38c09652
AK		 1354 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1355 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
d7636e0b 1356
b053af16
AK		 1357 XGINew_ChkSenseStatus(pVBInfo);
1358 XGINew_SetModeScratch(pVBInfo);
a24d60f4 1359
8104e329 1360 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
d7636e0b 1361
b9ebf5e5
AK		 1362 return 1;
1363} /* end of init */
Linux kernel - Deliverables
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