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staging: xgifb: vb_setmode: eliminate GetVGAType/Set_VGAType
[deliverable/linux.git] / drivers / staging / xgifb / vb_init.c
CommitLineData
d7636e0b 1#include <linux/types.h>
2#include <linux/delay.h> /* udelay */
6048d761
AK		 3#include <linux/pci.h>
4
4b495462 5#include "vgatypes.h"
d7636e0b 6#include "XGIfb.h"
d7636e0b 7
8#include "vb_def.h"
9#include "vb_struct.h"
10#include "vb_util.h"
11#include "vb_setmode.h"
12#include "vb_init.h"
d7636e0b 13
d7636e0b 14
bf32fcb9 15#include <linux/io.h>
d7636e0b 16
4397c7f0 17static const unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
82d6eb5b
BP		 18 { 2, 13, 9, 64, 0x45},
19 { 2, 12, 9, 32, 0x35},
20 { 2, 12, 8, 16, 0x31},
21 { 2, 11, 8, 8, 0x21} };
22
4397c7f0 23static const unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
82d6eb5b
BP		 24 { 2, 14, 11, 128, 0x5D},
25 { 2, 14, 10, 64, 0x59},
26 { 2, 13, 11, 64, 0x4D},
27 { 2, 14, 9, 32, 0x55},
28 { 2, 13, 10, 32, 0x49},
29 { 2, 12, 11, 32, 0x3D},
30 { 2, 14, 8, 16, 0x51},
31 { 2, 13, 9, 16, 0x45},
32 { 2, 12, 10, 16, 0x39},
33 { 2, 13, 8, 8, 0x41},
34 { 2, 12, 9, 8, 0x35},
35 { 2, 12, 8, 4, 0x31} };
d7636e0b 36
bf32fcb9
KT		 37static unsigned char
38XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
39 struct vb_device_info *pVBInfo)
d7636e0b 40{
b9ebf5e5 41 unsigned char data, temp;
d7636e0b 42
b9ebf5e5
AK		 43 if (HwDeviceExtension->jChipType < XG20) {
44 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
45 data = *pVBInfo->pSoftSetting & 0x07;
46 return data;
47 } else {
58839b01 48 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
b9ebf5e5 49 if (data == 0)
bf32fcb9
KT		 50 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
51 0x02) >> 1;
b9ebf5e5
AK		 52 return data;
53 }
54 } else if (HwDeviceExtension->jChipType == XG27) {
55 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
56 data = *pVBInfo->pSoftSetting & 0x07;
57 return data;
58 }
58839b01 59 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
bf32fcb9
KT		 60 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
61 if ((temp & 0x88) == 0x80)
b9ebf5e5
AK		 62 data = 0; /* DDR */
63 else
64 data = 1; /* DDRII */
65 return data;
66 } else if (HwDeviceExtension->jChipType == XG21) {
bf32fcb9
KT		 67 /* Independent GPIO control */
68 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
c45715bb 69 udelay(800);
b9bf6e4e 70 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
bf32fcb9
KT		 71 /* GPIOF 0:DVI 1:DVO */
72 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5 73 /* HOTPLUG_SUPPORT */
bf32fcb9
KT		 74 /* for current XG20 & XG21, GPIOH is floating, driver will
75 * fix DDR temporarily */
b9ebf5e5
AK		 76 if (temp & 0x01) /* DVI read GPIOH */
77 data = 1; /* DDRII */
78 else
79 data = 0; /* DDR */
80 /* ~HOTPLUG_SUPPORT */
b9bf6e4e 81 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
b9ebf5e5
AK		 82 return data;
83 } else {
58839b01 84 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
d7636e0b 85
b9ebf5e5
AK		 86 if (data == 1)
87 data++;
d7636e0b 88
b9ebf5e5
AK		 89 return data;
90 }
91}
d7636e0b 92
bf32fcb9
KT		 93static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
94 struct vb_device_info *pVBInfo)
b9ebf5e5 95{
8104e329
AK		 96 xgifb_reg_set(P3c4, 0x18, 0x01);
97 xgifb_reg_set(P3c4, 0x19, 0x20);
98 xgifb_reg_set(P3c4, 0x16, 0x00);
99 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 100
b9ebf5e5 101 if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
c83c620a 102 mdelay(3);
8104e329
AK		 103 xgifb_reg_set(P3c4, 0x18, 0x00);
104 xgifb_reg_set(P3c4, 0x19, 0x20);
105 xgifb_reg_set(P3c4, 0x16, 0x00);
106 xgifb_reg_set(P3c4, 0x16, 0x80);
a24d60f4 107 }
d7636e0b 108
c45715bb 109 udelay(60);
2af1a29d
AK		 110 xgifb_reg_set(P3c4,
111 0x18,
112 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 113 xgifb_reg_set(P3c4, 0x19, 0x01);
114 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
115 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
c83c620a 116 mdelay(1);
8104e329 117 xgifb_reg_set(P3c4, 0x1B, 0x03);
c45715bb 118 udelay(500);
2af1a29d
AK		 119 xgifb_reg_set(P3c4,
120 0x18,
121 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 122 xgifb_reg_set(P3c4, 0x19, 0x00);
123 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
124 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
125 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 126}
d7636e0b 127
b9ebf5e5
AK		 128static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
129 struct vb_device_info *pVBInfo)
130{
d7636e0b 131
bf32fcb9
KT		 132 xgifb_reg_set(pVBInfo->P3c4,
133 0x28,
2af1a29d 134 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
bf32fcb9
KT		 135 xgifb_reg_set(pVBInfo->P3c4,
136 0x29,
2af1a29d 137 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
bf32fcb9
KT		 138 xgifb_reg_set(pVBInfo->P3c4,
139 0x2A,
2af1a29d 140 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
bf32fcb9
KT		 141
142 xgifb_reg_set(pVBInfo->P3c4,
143 0x2E,
2af1a29d 144 pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
bf32fcb9
KT		 145 xgifb_reg_set(pVBInfo->P3c4,
146 0x2F,
2af1a29d 147 pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
bf32fcb9
KT		 148 xgifb_reg_set(pVBInfo->P3c4,
149 0x30,
2af1a29d 150 pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
bf32fcb9
KT		 151
152 /* [Vicent] 2004/07/07,
153 * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
154 /* [Hsuan] 2004/08/20,
155 * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
156 * Set SR32 D[1:0] = 10b */
b9ebf5e5 157 if (HwDeviceExtension->jChipType == XG42) {
2af1a29d
AK		 158 if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
159 (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
160 (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
161 (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
162 ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
163 (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
bf32fcb9
KT		 164 xgifb_reg_set(pVBInfo->P3c4,
165 0x32,
166 ((unsigned char) xgifb_reg_get(
167 pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
b9ebf5e5
AK		 168 }
169}
d7636e0b 170
b9ebf5e5
AK		 171static void XGINew_DDRII_Bootup_XG27(
172 struct xgi_hw_device_info *HwDeviceExtension,
173 unsigned long P3c4, struct vb_device_info *pVBInfo)
174{
175 unsigned long P3d4 = P3c4 + 0x10;
2af1a29d 176 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b9ebf5e5 177 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
d7636e0b 178
b9ebf5e5 179 /* Set Double Frequency */
8104e329
AK		 180 /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
181 xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
d7636e0b 182
c45715bb 183 udelay(200);
d7636e0b 184
8104e329
AK		 185 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
186 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
187 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 188 udelay(15);
8104e329 189 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 190 udelay(15);
d7636e0b 191
8104e329
AK		 192 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
193 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
194 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 195 udelay(15);
8104e329 196 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 197 udelay(15);
d7636e0b 198
8104e329
AK		 199 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
200 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
201 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 202 udelay(30);
8104e329 203 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 204 udelay(15);
d7636e0b 205
8104e329
AK		 206 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
207 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
208 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
c45715bb 209 udelay(30);
8104e329
AK		 210 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
211 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
c45715bb 212 /* udelay(15); */
d7636e0b 213
8104e329 214 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
c45715bb 215 udelay(60);
8104e329 216 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
d7636e0b 217
8104e329
AK		 218 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
219 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
220 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
d7636e0b 221
c45715bb 222 udelay(30);
8104e329 223 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
c45715bb 224 udelay(15);
d7636e0b 225
8104e329
AK		 226 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
227 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
228 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 229 udelay(30);
8104e329 230 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 231 udelay(15);
d7636e0b 232
8104e329
AK		 233 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
234 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
235 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 236 udelay(30);
8104e329 237 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 238 udelay(15);
d7636e0b 239
bf32fcb9
KT		 240 /* Set SR1B refresh control 000:close; 010:open */
241 xgifb_reg_set(P3c4, 0x1B, 0x04);
c45715bb 242 udelay(200);
d7636e0b 243
b9ebf5e5 244}
d7636e0b 245
b9ebf5e5
AK		 246static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
247 unsigned long P3c4, struct vb_device_info *pVBInfo)
248{
249 unsigned long P3d4 = P3c4 + 0x10;
d7636e0b 250
2af1a29d 251 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b9ebf5e5 252 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
d7636e0b 253
8104e329 254 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
d7636e0b 255
c45715bb 256 udelay(200);
8104e329
AK		 257 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
258 xgifb_reg_set(P3c4, 0x19, 0x80);
259 xgifb_reg_set(P3c4, 0x16, 0x05);
260 xgifb_reg_set(P3c4, 0x16, 0x85);
261
262 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
263 xgifb_reg_set(P3c4, 0x19, 0xC0);
264 xgifb_reg_set(P3c4, 0x16, 0x05);
265 xgifb_reg_set(P3c4, 0x16, 0x85);
266
267 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
268 xgifb_reg_set(P3c4, 0x19, 0x40);
269 xgifb_reg_set(P3c4, 0x16, 0x05);
270 xgifb_reg_set(P3c4, 0x16, 0x85);
271
272 /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
273 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
274 xgifb_reg_set(P3c4, 0x19, 0x02);
275 xgifb_reg_set(P3c4, 0x16, 0x05);
276 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 277
c45715bb 278 udelay(15);
8104e329 279 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
c45715bb 280 udelay(30);
8104e329 281 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
c45715bb 282 udelay(100);
a24d60f4 283
8104e329
AK		 284 /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
285 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
286 xgifb_reg_set(P3c4, 0x19, 0x00);
287 xgifb_reg_set(P3c4, 0x16, 0x05);
288 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 289
c45715bb 290 udelay(200);
b9ebf5e5 291}
a24d60f4 292
bf32fcb9
KT		 293static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
294 struct vb_device_info *pVBInfo)
b9ebf5e5 295{
8104e329
AK		 296 xgifb_reg_set(P3c4, 0x18, 0x01);
297 xgifb_reg_set(P3c4, 0x19, 0x40);
298 xgifb_reg_set(P3c4, 0x16, 0x00);
299 xgifb_reg_set(P3c4, 0x16, 0x80);
c45715bb 300 udelay(60);
a24d60f4 301
8104e329
AK		 302 xgifb_reg_set(P3c4, 0x18, 0x00);
303 xgifb_reg_set(P3c4, 0x19, 0x40);
304 xgifb_reg_set(P3c4, 0x16, 0x00);
305 xgifb_reg_set(P3c4, 0x16, 0x80);
c45715bb 306 udelay(60);
2af1a29d
AK		 307 xgifb_reg_set(P3c4,
308 0x18,
309 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 310 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
311 xgifb_reg_set(P3c4, 0x19, 0x01);
312 xgifb_reg_set(P3c4, 0x16, 0x03);
313 xgifb_reg_set(P3c4, 0x16, 0x83);
c83c620a 314 mdelay(1);
8104e329 315 xgifb_reg_set(P3c4, 0x1B, 0x03);
c45715bb 316 udelay(500);
8104e329 317 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
2af1a29d
AK		 318 xgifb_reg_set(P3c4,
319 0x18,
320 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 321 xgifb_reg_set(P3c4, 0x19, 0x00);
322 xgifb_reg_set(P3c4, 0x16, 0x03);
323 xgifb_reg_set(P3c4, 0x16, 0x83);
324 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 325}
a24d60f4 326
b9ebf5e5
AK		 327static void XGINew_DDR1x_DefaultRegister(
328 struct xgi_hw_device_info *HwDeviceExtension,
329 unsigned long Port, struct vb_device_info *pVBInfo)
330{
331 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 332
b9ebf5e5
AK		 333 if (HwDeviceExtension->jChipType >= XG20) {
334 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
bf32fcb9
KT		 335 xgifb_reg_set(P3d4,
336 0x82,
2af1a29d 337 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
bf32fcb9
KT		 338 xgifb_reg_set(P3d4,
339 0x85,
2af1a29d 340 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
bf32fcb9
KT		 341 xgifb_reg_set(P3d4,
342 0x86,
2af1a29d 343 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
a24d60f4 344
8104e329
AK		 345 xgifb_reg_set(P3d4, 0x98, 0x01);
346 xgifb_reg_set(P3d4, 0x9A, 0x02);
a24d60f4 347
b9ebf5e5
AK		 348 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
349 } else {
350 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
a24d60f4 351
b9ebf5e5
AK		 352 switch (HwDeviceExtension->jChipType) {
353 case XG41:
354 case XG42:
bf32fcb9
KT		 355 /* CR82 */
356 xgifb_reg_set(P3d4,
357 0x82,
2af1a29d 358 pVBInfo->CR40[11][pVBInfo->ram_type]);
bf32fcb9
KT		 359 /* CR85 */
360 xgifb_reg_set(P3d4,
361 0x85,
2af1a29d 362 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 363 /* CR86 */
364 xgifb_reg_set(P3d4,
365 0x86,
2af1a29d 366 pVBInfo->CR40[13][pVBInfo->ram_type]);
b9ebf5e5
AK		 367 break;
368 default:
8104e329
AK		 369 xgifb_reg_set(P3d4, 0x82, 0x88);
370 xgifb_reg_set(P3d4, 0x86, 0x00);
bf32fcb9
KT		 371 /* Insert read command for delay */
372 xgifb_reg_get(P3d4, 0x86);
8104e329 373 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 374 xgifb_reg_get(P3d4, 0x86);
bf32fcb9
KT		 375 xgifb_reg_set(P3d4,
376 0x86,
2af1a29d 377 pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 378 xgifb_reg_set(P3d4, 0x82, 0x77);
379 xgifb_reg_set(P3d4, 0x85, 0x00);
bf32fcb9
KT		 380
381 /* Insert read command for delay */
382 xgifb_reg_get(P3d4, 0x85);
8104e329 383 xgifb_reg_set(P3d4, 0x85, 0x88);
bf32fcb9
KT		 384
385 /* Insert read command for delay */
386 xgifb_reg_get(P3d4, 0x85);
387 /* CR85 */
388 xgifb_reg_set(P3d4,
389 0x85,
2af1a29d 390 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 391 /* CR82 */
392 xgifb_reg_set(P3d4,
393 0x82,
2af1a29d 394 pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 395 break;
a24d60f4 396 }
a24d60f4 397
8104e329
AK		 398 xgifb_reg_set(P3d4, 0x97, 0x00);
399 xgifb_reg_set(P3d4, 0x98, 0x01);
400 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 401 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
402 }
403}
a24d60f4 404
b9ebf5e5
AK		 405static void XGINew_DDR2_DefaultRegister(
406 struct xgi_hw_device_info *HwDeviceExtension,
407 unsigned long Port, struct vb_device_info *pVBInfo)
408{
409 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 410
bf32fcb9
KT		 411 /* keep following setting sequence, each setting in
412 * the same reg insert idle */
8104e329
AK		 413 xgifb_reg_set(P3d4, 0x82, 0x77);
414 xgifb_reg_set(P3d4, 0x86, 0x00);
58839b01 415 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
8104e329 416 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 417 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
bf32fcb9 418 /* CR86 */
2af1a29d 419 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 420 xgifb_reg_set(P3d4, 0x82, 0x77);
421 xgifb_reg_set(P3d4, 0x85, 0x00);
58839b01 422 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
8104e329 423 xgifb_reg_set(P3d4, 0x85, 0x88);
58839b01 424 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
2af1a29d
AK		 425 xgifb_reg_set(P3d4,
426 0x85,
427 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
b9ebf5e5 428 if (HwDeviceExtension->jChipType == XG27)
bf32fcb9 429 /* CR82 */
2af1a29d 430 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 431 else
8104e329 432 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
a24d60f4 433
8104e329
AK		 434 xgifb_reg_set(P3d4, 0x98, 0x01);
435 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 436 if (HwDeviceExtension->jChipType == XG27)
437 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
438 else
439 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
440}
a24d60f4 441
b9ebf5e5
AK		 442static void XGINew_SetDRAMDefaultRegister340(
443 struct xgi_hw_device_info *HwDeviceExtension,
444 unsigned long Port, struct vb_device_info *pVBInfo)
445{
446 unsigned char temp, temp1, temp2, temp3, i, j, k;
a24d60f4 447
b9ebf5e5 448 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 449
2af1a29d
AK		 450 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
451 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
452 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
453 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
a24d60f4 454
b9ebf5e5
AK		 455 temp2 = 0;
456 for (i = 0; i < 4; i++) {
bf32fcb9 457 /* CR6B DQS fine tune delay */
2af1a29d 458 temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
b9ebf5e5
AK		 459 for (j = 0; j < 4; j++) {
460 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
461 temp2 |= temp1;
8104e329 462 xgifb_reg_set(P3d4, 0x6B, temp2);
bf32fcb9
KT		 463 /* Insert read command for delay */
464 xgifb_reg_get(P3d4, 0x6B);
b9ebf5e5
AK		 465 temp2 &= 0xF0;
466 temp2 += 0x10;
467 }
a24d60f4 468 }
a24d60f4 469
b9ebf5e5
AK		 470 temp2 = 0;
471 for (i = 0; i < 4; i++) {
bf32fcb9 472 /* CR6E DQM fine tune delay */
2af1a29d 473 temp = pVBInfo->CR6E[pVBInfo->ram_type][i];
b9ebf5e5
AK		 474 for (j = 0; j < 4; j++) {
475 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
476 temp2 |= temp1;
8104e329 477 xgifb_reg_set(P3d4, 0x6E, temp2);
bf32fcb9
KT		 478 /* Insert read command for delay */
479 xgifb_reg_get(P3d4, 0x6E);
b9ebf5e5
AK		 480 temp2 &= 0xF0;
481 temp2 += 0x10;
a24d60f4 482 }
b9ebf5e5 483 }
a24d60f4 484
b9ebf5e5
AK		 485 temp3 = 0;
486 for (k = 0; k < 4; k++) {
bf32fcb9
KT		 487 /* CR6E_D[1:0] select channel */
488 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
b9ebf5e5
AK		 489 temp2 = 0;
490 for (i = 0; i < 8; i++) {
bf32fcb9 491 /* CR6F DQ fine tune delay */
2af1a29d 492 temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];
b9ebf5e5
AK		 493 for (j = 0; j < 4; j++) {
494 temp1 = (temp >> (2 * j)) & 0x03;
495 temp2 |= temp1;
8104e329 496 xgifb_reg_set(P3d4, 0x6F, temp2);
bf32fcb9
KT		 497 /* Insert read command for delay */
498 xgifb_reg_get(P3d4, 0x6F);
b9ebf5e5
AK		 499 temp2 &= 0xF8;
500 temp2 += 0x08;
501 }
502 }
503 temp3 += 0x01;
504 }
a24d60f4 505
2af1a29d
AK		 506 xgifb_reg_set(P3d4,
507 0x80,
508 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
509 xgifb_reg_set(P3d4,
510 0x81,
511 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
a24d60f4 512
b9ebf5e5 513 temp2 = 0x80;
bf32fcb9 514 /* CR89 terminator type select */
2af1a29d 515 temp = pVBInfo->CR89[pVBInfo->ram_type][0];
b9ebf5e5
AK		 516 for (j = 0; j < 4; j++) {
517 temp1 = (temp >> (2 * j)) & 0x03;
518 temp2 |= temp1;
8104e329 519 xgifb_reg_set(P3d4, 0x89, temp2);
58839b01 520 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
b9ebf5e5
AK		 521 temp2 &= 0xF0;
522 temp2 += 0x10;
600a710b 523 }
a24d60f4 524
2af1a29d 525 temp = pVBInfo->CR89[pVBInfo->ram_type][1];
b9ebf5e5
AK		 526 temp1 = temp & 0x03;
527 temp2 |= temp1;
8104e329 528 xgifb_reg_set(P3d4, 0x89, temp2);
a24d60f4 529
2af1a29d 530 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
b9ebf5e5
AK		 531 temp1 = temp & 0x0F;
532 temp2 = (temp >> 4) & 0x07;
533 temp3 = temp & 0x80;
8104e329
AK		 534 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
535 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
b9bf6e4e 536 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
2af1a29d
AK		 537 xgifb_reg_set(P3d4,
538 0x41,
539 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
a24d60f4 540
b9ebf5e5 541 if (HwDeviceExtension->jChipType == XG27)
8104e329 542 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
a24d60f4 543
bf32fcb9 544 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
8104e329 545 xgifb_reg_set(P3d4, (0x90 + j),
2af1a29d 546 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
a24d60f4 547
bf32fcb9 548 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
8104e329 549 xgifb_reg_set(P3d4, (0xC3 + j),
2af1a29d 550 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
a24d60f4 551
bf32fcb9 552 for (j = 0; j < 2; j++) /* CR8A - CR8B */
8104e329 553 xgifb_reg_set(P3d4, (0x8A + j),
2af1a29d 554 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
a24d60f4 555
bf32fcb9
KT		 556 if ((HwDeviceExtension->jChipType == XG41) ||
557 (HwDeviceExtension->jChipType == XG42))
8104e329 558 xgifb_reg_set(P3d4, 0x8C, 0x87);
a24d60f4 559
2af1a29d
AK		 560 xgifb_reg_set(P3d4,
561 0x59,
562 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
a24d60f4 563
8104e329
AK		 564 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
565 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
566 xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
2af1a29d 567 if (pVBInfo->ram_type) {
8104e329
AK		 568 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
569 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
b9ebf5e5 570 if (HwDeviceExtension->jChipType == XG27)
8104e329 571 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
a24d60f4 572
b9ebf5e5 573 } else {
8104e329 574 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
b9ebf5e5 575 }
8104e329 576 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
a24d60f4 577
b9ebf5e5
AK		 578 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
579 if (temp == 0) {
580 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
581 } else {
8104e329 582 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
b9ebf5e5
AK		 583 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
584 }
2af1a29d
AK		 585 xgifb_reg_set(P3c4,
586 0x1B,
587 pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
b9ebf5e5 588}
a24d60f4 589
b9ebf5e5 590static void XGINew_SetDRAMSizingType(int index,
4397c7f0 591 const unsigned short DRAMTYPE_TABLE[][5],
b9ebf5e5
AK		 592 struct vb_device_info *pVBInfo)
593{
594 unsigned short data;
a24d60f4 595
b9ebf5e5 596 data = DRAMTYPE_TABLE[index][4];
ec9e5d3e 597 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
c45715bb 598 udelay(15);
b9ebf5e5
AK		 599 /* should delay 50 ns */
600}
a24d60f4 601
b9ebf5e5 602static unsigned short XGINew_SetDRAMSizeReg(int index,
4397c7f0 603 const unsigned short DRAMTYPE_TABLE[][5],
b9ebf5e5
AK		 604 struct vb_device_info *pVBInfo)
605{
606 unsigned short data = 0, memsize = 0;
607 int RankSize;
608 unsigned char ChannelNo;
a24d60f4 609
2f0f395e 610 RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 32;
58839b01 611 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
b9ebf5e5 612 data &= 0x80;
d7636e0b 613
b9ebf5e5
AK		 614 if (data == 0x80)
615 RankSize *= 2;
d7636e0b 616
b9ebf5e5 617 data = 0;
a24d60f4 618
ee055a48 619 if (pVBInfo->ram_channel == 3)
b9ebf5e5
AK		 620 ChannelNo = 4;
621 else
ee055a48 622 ChannelNo = pVBInfo->ram_channel;
a24d60f4 623
b9ebf5e5
AK		 624 if (ChannelNo * RankSize <= 256) {
625 while ((RankSize >>= 1) > 0)
626 data += 0x10;
a24d60f4 627
b9ebf5e5 628 memsize = data >> 4;
a24d60f4 629
b9ebf5e5 630 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
bf32fcb9
KT		 631 xgifb_reg_set(pVBInfo->P3c4,
632 0x14,
633 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
634 (data & 0xF0));
a24d60f4 635
ee055a48 636 /* data |= pVBInfo->ram_channel << 2; */
2f0f395e 637 /* data |= (pVBInfo->ram_bus / 64) << 1; */
8104e329 638 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
a24d60f4 639
b9ebf5e5
AK		 640 /* should delay */
641 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
a24d60f4 642 }
b9ebf5e5 643 return memsize;
d7636e0b 644}
645
b9ebf5e5 646static unsigned short XGINew_SetDRAMSize20Reg(int index,
4397c7f0 647 const unsigned short DRAMTYPE_TABLE[][5],
b9ebf5e5 648 struct vb_device_info *pVBInfo)
d7636e0b 649{
b9ebf5e5
AK		 650 unsigned short data = 0, memsize = 0;
651 int RankSize;
652 unsigned char ChannelNo;
d7636e0b 653
2f0f395e 654 RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 8;
58839b01 655 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
b9ebf5e5 656 data &= 0x80;
d7636e0b 657
b9ebf5e5
AK		 658 if (data == 0x80)
659 RankSize *= 2;
a24d60f4 660
b9ebf5e5 661 data = 0;
a24d60f4 662
ee055a48 663 if (pVBInfo->ram_channel == 3)
b9ebf5e5
AK		 664 ChannelNo = 4;
665 else
ee055a48 666 ChannelNo = pVBInfo->ram_channel;
a24d60f4 667
b9ebf5e5
AK		 668 if (ChannelNo * RankSize <= 256) {
669 while ((RankSize >>= 1) > 0)
670 data += 0x10;
a24d60f4 671
b9ebf5e5 672 memsize = data >> 4;
a24d60f4 673
b9ebf5e5 674 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
bf32fcb9
KT		 675 xgifb_reg_set(pVBInfo->P3c4,
676 0x14,
677 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
678 (data & 0xF0));
c45715bb 679 udelay(15);
a24d60f4 680
ee055a48 681 /* data |= pVBInfo->ram_channel << 2; */
2f0f395e 682 /* data |= (pVBInfo->ram_bus / 64) << 1; */
8104e329 683 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
a24d60f4 684
b9ebf5e5
AK		 685 /* should delay */
686 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
687 }
688 return memsize;
689}
a24d60f4 690
b9ebf5e5
AK		 691static int XGINew_ReadWriteRest(unsigned short StopAddr,
692 unsigned short StartAddr, struct vb_device_info *pVBInfo)
693{
694 int i;
695 unsigned long Position = 0;
c44fa627 696 void __iomem *fbaddr = pVBInfo->FBAddr;
a24d60f4 697
c44fa627 698 writel(Position, fbaddr + Position);
a24d60f4 699
b9ebf5e5
AK		 700 for (i = StartAddr; i <= StopAddr; i++) {
701 Position = 1 << i;
c44fa627 702 writel(Position, fbaddr + Position);
b9ebf5e5 703 }
a24d60f4 704
bf32fcb9
KT		 705 udelay(500); /* [Vicent] 2004/04/16.
706 Fix #1759 Memory Size error in Multi-Adapter. */
a24d60f4 707
b9ebf5e5
AK		 708 Position = 0;
709
c44fa627 710 if (readl(fbaddr + Position) != Position)
b9ebf5e5 711 return 0;
d7636e0b 712
b9ebf5e5
AK		 713 for (i = StartAddr; i <= StopAddr; i++) {
714 Position = 1 << i;
c44fa627 715 if (readl(fbaddr + Position) != Position)
b9ebf5e5
AK		 716 return 0;
717 }
718 return 1;
d7636e0b 719}
a24d60f4 720
b9ebf5e5 721static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
d7636e0b 722{
b9ebf5e5 723 unsigned char data;
a24d60f4 724
58839b01 725 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
a24d60f4 726
b9ebf5e5 727 if ((data & 0x10) == 0) {
58839b01 728 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
b9ebf5e5
AK		 729 data = (data & 0x02) >> 1;
730 return data;
731 } else {
732 return data & 0x01;
733 }
734}
a24d60f4 735
b9ebf5e5
AK		 736static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
737 struct vb_device_info *pVBInfo)
738{
739 unsigned char data;
a24d60f4 740
b9ebf5e5
AK		 741 switch (HwDeviceExtension->jChipType) {
742 case XG20:
743 case XG21:
58839b01 744 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
b9ebf5e5 745 data = data & 0x01;
ee055a48 746 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
a24d60f4 747
b9ebf5e5 748 if (data == 0) { /* Single_32_16 */
a24d60f4 749
b9ebf5e5
AK		 750 if ((HwDeviceExtension->ulVideoMemorySize - 1)
751 > 0x1000000) {
a24d60f4 752
2f0f395e 753 pVBInfo->ram_bus = 32; /* 32 bits */
bf32fcb9
KT		 754 /* 22bit + 2 rank + 32bit */
755 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 756 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
c45715bb 757 udelay(15);
a24d60f4 758
b9ebf5e5
AK		 759 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
760 return;
d7636e0b 761
bf32fcb9
KT		 762 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
763 0x800000) {
764 /* 22bit + 1 rank + 32bit */
765 xgifb_reg_set(pVBInfo->P3c4,
766 0x13,
767 0x31);
768 xgifb_reg_set(pVBInfo->P3c4,
769 0x14,
770 0x42);
c45715bb 771 udelay(15);
a24d60f4 772
bf32fcb9
KT		 773 if (XGINew_ReadWriteRest(23,
774 23,
775 pVBInfo) == 1)
b9ebf5e5
AK		 776 return;
777 }
778 }
a24d60f4 779
bf32fcb9
KT		 780 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
781 0x800000) {
2f0f395e 782 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 783 /* 22bit + 2 rank + 16bit */
784 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 785 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
c45715bb 786 udelay(15);
a24d60f4 787
b9ebf5e5
AK		 788 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
789 return;
790 else
bf32fcb9
KT		 791 xgifb_reg_set(pVBInfo->P3c4,
792 0x13,
793 0x31);
c45715bb 794 udelay(15);
b9ebf5e5 795 }
a24d60f4 796
b9ebf5e5 797 } else { /* Dual_16_8 */
bf32fcb9
KT		 798 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
799 0x800000) {
2f0f395e 800 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 801 /* (0x31:12x8x2) 22bit + 2 rank */
802 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
803 /* 0x41:16Mx16 bit*/
804 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
c45715bb 805 udelay(15);
a24d60f4 806
b9ebf5e5
AK		 807 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
808 return;
a24d60f4 809
bf32fcb9
KT		 810 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
811 0x400000) {
812 /* (0x31:12x8x2) 22bit + 1 rank */
813 xgifb_reg_set(pVBInfo->P3c4,
814 0x13,
815 0x31);
816 /* 0x31:8Mx16 bit*/
817 xgifb_reg_set(pVBInfo->P3c4,
818 0x14,
819 0x31);
c45715bb 820 udelay(15);
a24d60f4 821
bf32fcb9
KT		 822 if (XGINew_ReadWriteRest(22,
823 22,
824 pVBInfo) == 1)
b9ebf5e5
AK		 825 return;
826 }
827 }
a24d60f4 828
bf32fcb9
KT		 829 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
830 0x400000) {
2f0f395e 831 pVBInfo->ram_bus = 8; /* 8 bits */
bf32fcb9
KT		 832 /* (0x31:12x8x2) 22bit + 2 rank */
833 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
834 /* 0x30:8Mx8 bit*/
835 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
c45715bb 836 udelay(15);
d7636e0b 837
b9ebf5e5
AK		 838 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
839 return;
bf32fcb9
KT		 840 else /* (0x31:12x8x2) 22bit + 1 rank */
841 xgifb_reg_set(pVBInfo->P3c4,
842 0x13,
843 0x31);
c45715bb 844 udelay(15);
a24d60f4
PS		 845 }
846 }
b9ebf5e5 847 break;
a24d60f4 848
b9ebf5e5 849 case XG27:
2f0f395e 850 pVBInfo->ram_bus = 16; /* 16 bits */
ee055a48 851 pVBInfo->ram_channel = 1; /* Single channel */
8104e329 852 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
b9ebf5e5
AK		 853 break;
854 case XG41:
855 if (XGINew_CheckFrequence(pVBInfo) == 1) {
2f0f395e 856 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 857 pVBInfo->ram_channel = 3; /* Quad Channel */
8104e329
AK		 858 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
859 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
a24d60f4 860
b9ebf5e5
AK		 861 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
862 return;
a24d60f4 863
ee055a48 864 pVBInfo->ram_channel = 2; /* Dual channels */
8104e329 865 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
a24d60f4 866
b9ebf5e5
AK		 867 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
868 return;
a24d60f4 869
8104e329 870 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
a24d60f4 871
b9ebf5e5
AK		 872 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
873 return;
a24d60f4 874
ee055a48 875 pVBInfo->ram_channel = 3;
8104e329
AK		 876 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
877 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
a24d60f4 878
b9ebf5e5
AK		 879 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
880 return;
a24d60f4 881
8104e329 882 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
a24d60f4 883
b9ebf5e5
AK		 884 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
885 return;
886 else
8104e329 887 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
b9ebf5e5 888 } else { /* DDR */
2f0f395e 889 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 890 pVBInfo->ram_channel = 2; /* Dual channels */
8104e329
AK		 891 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
892 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
a24d60f4 893
b9ebf5e5
AK		 894 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
895 return;
a24d60f4 896
ee055a48 897 pVBInfo->ram_channel = 1; /* Single channels */
8104e329 898 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
a24d60f4 899
b9ebf5e5
AK		 900 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
901 return;
d7636e0b 902
8104e329 903 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
d7636e0b 904
b9ebf5e5
AK		 905 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
906 return;
d7636e0b 907
ee055a48 908 pVBInfo->ram_channel = 2; /* Dual channels */
8104e329
AK		 909 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
910 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
d7636e0b 911
b9ebf5e5
AK		 912 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
913 return;
d7636e0b 914
ee055a48 915 pVBInfo->ram_channel = 1; /* Single channels */
8104e329 916 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
d7636e0b 917
b9ebf5e5
AK		 918 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
919 return;
920 else
8104e329 921 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
b9ebf5e5 922 }
d7636e0b 923
b9ebf5e5 924 break;
d7636e0b 925
b9ebf5e5
AK		 926 case XG42:
927 /*
928 XG42 SR14 D[3] Reserve
929 D[2] = 1, Dual Channel
930 = 0, Single Channel
a24d60f4 931
b9ebf5e5
AK		 932 It's Different from Other XG40 Series.
933 */
934 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
2f0f395e 935 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 936 pVBInfo->ram_channel = 2; /* 2 Channel */
8104e329
AK		 937 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
938 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
a24d60f4 939
b9ebf5e5
AK		 940 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
941 return;
a24d60f4 942
8104e329
AK		 943 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
944 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
b9ebf5e5
AK		 945 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
946 return;
a24d60f4 947
ee055a48 948 pVBInfo->ram_channel = 1; /* Single Channel */
8104e329
AK		 949 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
950 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
d7636e0b 951
b9ebf5e5
AK		 952 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
953 return;
954 else {
8104e329
AK		 955 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
956 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
b9ebf5e5
AK		 957 }
958 } else { /* DDR */
2f0f395e 959 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 960 pVBInfo->ram_channel = 1; /* 1 channels */
8104e329
AK		 961 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
962 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
d7636e0b 963
b9ebf5e5
AK		 964 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
965 return;
966 else {
8104e329
AK		 967 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
968 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
b9ebf5e5
AK		 969 }
970 }
d7636e0b 971
b9ebf5e5 972 break;
d7636e0b 973
b9ebf5e5 974 default: /* XG40 */
d7636e0b 975
b9ebf5e5 976 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
2f0f395e 977 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 978 pVBInfo->ram_channel = 3;
8104e329
AK		 979 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
980 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
d7636e0b 981
b9ebf5e5
AK		 982 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
983 return;
d7636e0b 984
ee055a48 985 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 986 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
a24d60f4 987
b9ebf5e5
AK		 988 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
989 return;
d7636e0b 990
8104e329
AK		 991 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
992 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
d7636e0b 993
b9ebf5e5 994 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
ee055a48 995 pVBInfo->ram_channel = 3; /* 4 channels */
b9ebf5e5 996 } else {
ee055a48 997 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 998 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
b9ebf5e5
AK		 999 }
1000 } else { /* DDR */
2f0f395e 1001 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 1002 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329
AK		 1003 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
1004 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
d7636e0b 1005
b9ebf5e5
AK		 1006 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
1007 return;
1008 } else {
8104e329
AK		 1009 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
1010 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
b9ebf5e5
AK		 1011 }
1012 }
1013 break;
a24d60f4 1014 }
d7636e0b 1015}
1016
b9ebf5e5
AK		 1017static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1018 struct vb_device_info *pVBInfo)
d7636e0b 1019{
a24d60f4 1020 int i;
b9ebf5e5 1021 unsigned short memsize, addr;
d7636e0b 1022
8104e329
AK		 1023 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1024 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
b9ebf5e5 1025 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
d7636e0b 1026
b9ebf5e5
AK		 1027 if (HwDeviceExtension->jChipType >= XG20) {
1028 for (i = 0; i < 12; i++) {
bf32fcb9
KT		 1029 XGINew_SetDRAMSizingType(i,
1030 XGINew_DDRDRAM_TYPE20,
1031 pVBInfo);
1032 memsize = XGINew_SetDRAMSize20Reg(i,
1033 XGINew_DDRDRAM_TYPE20,
1034 pVBInfo);
b9ebf5e5
AK		 1035 if (memsize == 0)
1036 continue;
d7636e0b 1037
ee055a48 1038 addr = memsize + (pVBInfo->ram_channel - 2) + 20;
bf32fcb9
KT		 1039 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1040 (unsigned long) (1 << addr))
b9ebf5e5 1041 continue;
d7636e0b 1042
b9ebf5e5
AK		 1043 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1044 return 1;
1045 }
1046 } else {
1047 for (i = 0; i < 4; i++) {
bf32fcb9
KT		 1048 XGINew_SetDRAMSizingType(i,
1049 XGINew_DDRDRAM_TYPE340,
1050 pVBInfo);
1051 memsize = XGINew_SetDRAMSizeReg(i,
1052 XGINew_DDRDRAM_TYPE340,
1053 pVBInfo);
d7636e0b 1054
b9ebf5e5
AK		 1055 if (memsize == 0)
1056 continue;
d7636e0b 1057
ee055a48 1058 addr = memsize + (pVBInfo->ram_channel - 2) + 20;
bf32fcb9
KT		 1059 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1060 (unsigned long) (1 << addr))
b9ebf5e5 1061 continue;
a24d60f4 1062
b9ebf5e5
AK		 1063 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1064 return 1;
1065 }
a24d60f4 1066 }
b9ebf5e5 1067 return 0;
a24d60f4 1068}
d7636e0b 1069
b9ebf5e5 1070static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
a24d60f4 1071 struct vb_device_info *pVBInfo)
d7636e0b 1072{
b9ebf5e5 1073 unsigned short data;
a24d60f4 1074
b9ebf5e5
AK		 1075 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1076 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 1077
b9ebf5e5 1078 XGISetModeNew(HwDeviceExtension, 0x2e);
a24d60f4 1079
58839b01 1080 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9
KT		 1081 /* disable read cache */
1082 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
b9ebf5e5 1083 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
a24d60f4 1084
58839b01 1085 /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
b9ebf5e5 1086 /* data |= 0x20 ; */
8104e329 1087 /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
b9ebf5e5 1088 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
58839b01 1089 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9
KT		 1090 /* enable read cache */
1091 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
b9ebf5e5 1092}
a24d60f4 1093
bf32fcb9
KT		 1094static void ReadVBIOSTablData(unsigned char ChipType,
1095 struct vb_device_info *pVBInfo)
b9ebf5e5 1096{
bf32fcb9
KT		 1097 volatile unsigned char *pVideoMemory =
1098 (unsigned char *) pVBInfo->ROMAddr;
b9ebf5e5
AK		 1099 unsigned long i;
1100 unsigned char j, k;
1101 /* Volari customize data area end */
a24d60f4 1102
b9ebf5e5
AK		 1103 if (ChipType == XG21) {
1104 pVBInfo->IF_DEF_LVDS = 0;
1105 if (pVideoMemory[0x65] & 0x1) {
1106 pVBInfo->IF_DEF_LVDS = 1;
1107 i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1108 j = pVideoMemory[i - 1];
1109 if (j != 0xff) {
1110 k = 0;
1111 do {
bf32fcb9
KT		 1112 pVBInfo->XG21_LVDSCapList[k].
1113 LVDS_Capability
1114 = pVideoMemory[i] |
1115 (pVideoMemory[i + 1] << 8);
b9ebf5e5 1116 pVBInfo->XG21_LVDSCapList[k].LVDSHT
bf32fcb9
KT		 1117 = pVideoMemory[i + 2] |
1118 (pVideoMemory[i + 3] << 8);
b9ebf5e5 1119 pVBInfo->XG21_LVDSCapList[k].LVDSVT
bf32fcb9
KT		 1120 = pVideoMemory[i + 4] |
1121 (pVideoMemory[i + 5] << 8);
b9ebf5e5 1122 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
bf32fcb9
KT		 1123 = pVideoMemory[i + 6] |
1124 (pVideoMemory[i + 7] << 8);
b9ebf5e5 1125 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
bf32fcb9
KT		 1126 = pVideoMemory[i + 8] |
1127 (pVideoMemory[i + 9] << 8);
b9ebf5e5 1128 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
bf32fcb9
KT		 1129 = pVideoMemory[i + 10] |
1130 (pVideoMemory[i + 11] << 8);
b9ebf5e5 1131 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
bf32fcb9
KT		 1132 = pVideoMemory[i + 12] |
1133 (pVideoMemory[i + 13] << 8);
b9ebf5e5 1134 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
bf32fcb9
KT		 1135 = pVideoMemory[i + 14] |
1136 (pVideoMemory[i + 15] << 8);
b9ebf5e5 1137 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
bf32fcb9
KT		 1138 = pVideoMemory[i + 16] |
1139 (pVideoMemory[i + 17] << 8);
b9ebf5e5
AK		 1140 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1141 = pVideoMemory[i + 18];
1142 pVBInfo->XG21_LVDSCapList[k].VCLKData2
1143 = pVideoMemory[i + 19];
1144 pVBInfo->XG21_LVDSCapList[k].PSC_S1
1145 = pVideoMemory[i + 20];
1146 pVBInfo->XG21_LVDSCapList[k].PSC_S2
1147 = pVideoMemory[i + 21];
1148 pVBInfo->XG21_LVDSCapList[k].PSC_S3
1149 = pVideoMemory[i + 22];
1150 pVBInfo->XG21_LVDSCapList[k].PSC_S4
1151 = pVideoMemory[i + 23];
1152 pVBInfo->XG21_LVDSCapList[k].PSC_S5
1153 = pVideoMemory[i + 24];
1154 i += 25;
1155 j--;
1156 k++;
bf32fcb9
KT		 1157 } while ((j > 0) &&
1158 (k < (sizeof(XGI21_LCDCapList) /
1159 sizeof(struct
1160 XGI21_LVDSCapStruct))));
b9ebf5e5
AK		 1161 } else {
1162 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
bf32fcb9
KT		 1163 = pVideoMemory[i] |
1164 (pVideoMemory[i + 1] << 8);
b9ebf5e5 1165 pVBInfo->XG21_LVDSCapList[0].LVDSHT
bf32fcb9
KT		 1166 = pVideoMemory[i + 2] |
1167 (pVideoMemory[i + 3] << 8);
b9ebf5e5 1168 pVBInfo->XG21_LVDSCapList[0].LVDSVT
bf32fcb9
KT		 1169 = pVideoMemory[i + 4] |
1170 (pVideoMemory[i + 5] << 8);
b9ebf5e5 1171 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
bf32fcb9
KT		 1172 = pVideoMemory[i + 6] |
1173 (pVideoMemory[i + 7] << 8);
b9ebf5e5 1174 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
bf32fcb9
KT		 1175 = pVideoMemory[i + 8] |
1176 (pVideoMemory[i + 9] << 8);
b9ebf5e5 1177 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
bf32fcb9
KT		 1178 = pVideoMemory[i + 10] |
1179 (pVideoMemory[i + 11] << 8);
b9ebf5e5 1180 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
bf32fcb9
KT		 1181 = pVideoMemory[i + 12] |
1182 (pVideoMemory[i + 13] << 8);
b9ebf5e5 1183 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
bf32fcb9
KT		 1184 = pVideoMemory[i + 14] |
1185 (pVideoMemory[i + 15] << 8);
b9ebf5e5 1186 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
bf32fcb9
KT		 1187 = pVideoMemory[i + 16] |
1188 (pVideoMemory[i + 17] << 8);
b9ebf5e5
AK		 1189 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1190 = pVideoMemory[i + 18];
1191 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1192 = pVideoMemory[i + 19];
1193 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1194 = pVideoMemory[i + 20];
1195 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1196 = pVideoMemory[i + 21];
1197 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1198 = pVideoMemory[i + 22];
1199 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1200 = pVideoMemory[i + 23];
1201 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1202 = pVideoMemory[i + 24];
a24d60f4 1203 }
b9ebf5e5
AK		 1204 }
1205 }
1206}
a24d60f4 1207
b9ebf5e5
AK		 1208static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1209 struct vb_device_info *pVBInfo)
1210{
1211 unsigned short tempbx = 0, temp, tempcx, CR3CData;
a24d60f4 1212
58839b01 1213 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
a24d60f4 1214
b9ebf5e5
AK		 1215 if (temp & Monitor1Sense)
1216 tempbx |= ActiveCRT1;
1217 if (temp & LCDSense)
1218 tempbx |= ActiveLCD;
1219 if (temp & Monitor2Sense)
1220 tempbx |= ActiveCRT2;
1221 if (temp & TVSense) {
1222 tempbx |= ActiveTV;
1223 if (temp & AVIDEOSense)
1224 tempbx |= (ActiveAVideo << 8);
1225 if (temp & SVIDEOSense)
1226 tempbx |= (ActiveSVideo << 8);
1227 if (temp & SCARTSense)
1228 tempbx |= (ActiveSCART << 8);
1229 if (temp & HiTVSense)
1230 tempbx |= (ActiveHiTV << 8);
1231 if (temp & YPbPrSense)
1232 tempbx |= (ActiveYPbPr << 8);
1233 }
a24d60f4 1234
58839b01
AK		 1235 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1236 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
a24d60f4 1237
b9ebf5e5 1238 if (tempbx & tempcx) {
58839b01 1239 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
b9ebf5e5
AK		 1240 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1241 tempcx = 0x1FF0;
1242 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1243 tempbx = 0x1FF0;
a24d60f4 1244 }
b9ebf5e5
AK		 1245 } else {
1246 tempcx = 0x1FF0;
1247 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1248 tempbx = 0x1FF0;
1249 }
a24d60f4 1250
b9ebf5e5 1251 tempbx &= tempcx;
8104e329
AK		 1252 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1253 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
b9ebf5e5 1254}
d7636e0b 1255
b9ebf5e5
AK		 1256static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1257 struct vb_device_info *pVBInfo)
1258{
1259 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
d7636e0b 1260
58839b01
AK		 1261 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1262 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1263 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
d7636e0b 1264
b9ebf5e5
AK		 1265 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1266 if (temp & ActiveCRT2)
1267 tempcl = SetCRT2ToRAMDAC;
1268 }
d7636e0b 1269
b9ebf5e5
AK		 1270 if (temp & ActiveLCD) {
1271 tempcl |= SetCRT2ToLCD;
1272 if (temp & DriverMode) {
1273 if (temp & ActiveTV) {
1274 tempch = SetToLCDA | EnableDualEdge;
1275 temp ^= SetCRT2ToLCD;
d7636e0b 1276
b9ebf5e5
AK		 1277 if ((temp >> 8) & ActiveAVideo)
1278 tempcl |= SetCRT2ToAVIDEO;
1279 if ((temp >> 8) & ActiveSVideo)
1280 tempcl |= SetCRT2ToSVIDEO;
1281 if ((temp >> 8) & ActiveSCART)
1282 tempcl |= SetCRT2ToSCART;
a24d60f4 1283
b9ebf5e5
AK		 1284 if (pVBInfo->IF_DEF_HiVision == 1) {
1285 if ((temp >> 8) & ActiveHiTV)
1286 tempcl |= SetCRT2ToHiVisionTV;
1287 }
a24d60f4 1288
b9ebf5e5
AK		 1289 if (pVBInfo->IF_DEF_YPbPr == 1) {
1290 if ((temp >> 8) & ActiveYPbPr)
1291 tempch |= SetYPbPr;
1292 }
1293 }
1294 }
1295 } else {
1296 if ((temp >> 8) & ActiveAVideo)
1297 tempcl |= SetCRT2ToAVIDEO;
1298 if ((temp >> 8) & ActiveSVideo)
1299 tempcl |= SetCRT2ToSVIDEO;
1300 if ((temp >> 8) & ActiveSCART)
1301 tempcl |= SetCRT2ToSCART;
a24d60f4 1302
b9ebf5e5
AK		 1303 if (pVBInfo->IF_DEF_HiVision == 1) {
1304 if ((temp >> 8) & ActiveHiTV)
1305 tempcl |= SetCRT2ToHiVisionTV;
1306 }
a24d60f4 1307
b9ebf5e5
AK		 1308 if (pVBInfo->IF_DEF_YPbPr == 1) {
1309 if ((temp >> 8) & ActiveYPbPr)
1310 tempch |= SetYPbPr;
1311 }
1312 }
d7636e0b 1313
b9ebf5e5
AK		 1314 tempcl |= SetSimuScanMode;
1315 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1316 || (temp & ActiveCRT2)))
1317 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1318 if ((temp & ActiveLCD) && (temp & ActiveTV))
1319 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
8104e329 1320 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
d7636e0b 1321
58839b01 1322 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
b9ebf5e5
AK		 1323 CR31Data &= ~(SetNotSimuMode >> 8);
1324 if (!(temp & ActiveCRT1))
1325 CR31Data |= (SetNotSimuMode >> 8);
1326 CR31Data &= ~(DisableCRT2Display >> 8);
1327 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1328 CR31Data |= (DisableCRT2Display >> 8);
8104e329 1329 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
d7636e0b 1330
58839b01 1331 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1332 CR38Data &= ~SetYPbPr;
1333 CR38Data |= tempch;
8104e329 1334 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
d7636e0b 1335
b9ebf5e5 1336}
a24d60f4 1337
40544b04
AK		 1338static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1339 *HwDeviceExtension,
1340 struct vb_device_info *pVBInfo)
1341{
1342 unsigned short temp;
1343
1344 /* add lcd sense */
1345 if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1346 return 0;
1347 } else {
1348 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1349 switch (HwDeviceExtension->ulCRT2LCDType) {
1350 case LCD_INVALID:
1351 case LCD_800x600:
1352 case LCD_1024x768:
1353 case LCD_1280x1024:
1354 break;
1355
1356 case LCD_640x480:
1357 case LCD_1024x600:
1358 case LCD_1152x864:
1359 case LCD_1280x960:
1360 case LCD_1152x768:
1361 temp = 0;
1362 break;
1363
1364 case LCD_1400x1050:
1365 case LCD_1280x768:
1366 case LCD_1600x1200:
1367 break;
1368
1369 case LCD_1920x1440:
1370 case LCD_2048x1536:
1371 temp = 0;
1372 break;
1373
1374 default:
1375 break;
1376 }
1377 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1378 return 1;
1379 }
1380}
1381
b9ebf5e5
AK		 1382static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1383 struct vb_device_info *pVBInfo)
1384{
1385 unsigned char Temp;
1386 volatile unsigned char *pVideoMemory =
1387 (unsigned char *) pVBInfo->ROMAddr;
a24d60f4 1388
b9ebf5e5 1389 pVBInfo->IF_DEF_LVDS = 0;
a24d60f4 1390
b9ebf5e5
AK		 1391#if 1
1392 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1393 pVBInfo->IF_DEF_LVDS = 1;
b9bf6e4e 1394 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1395 /* LVDS on chip */
1396 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
b9ebf5e5
AK		 1397 } else {
1398#endif
bf32fcb9
KT		 1399 /* Enable GPIOA/B read */
1400 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1401 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
b9ebf5e5
AK		 1402 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1403 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
b9bf6e4e 1404 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1405 /* Enable read GPIOF */
1406 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
58839b01 1407 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
b9ebf5e5 1408 if (!Temp)
bf32fcb9
KT		 1409 xgifb_reg_and_or(pVBInfo->P3d4,
1410 0x38,
1411 ~0xE0,
1412 0x80); /* TMDS on chip */
a24d60f4 1413 else
bf32fcb9
KT		 1414 xgifb_reg_and_or(pVBInfo->P3d4,
1415 0x38,
1416 ~0xE0,
1417 0xA0); /* Only DVO on chip */
1418 /* Disable read GPIOF */
1419 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
a24d60f4 1420 }
b9ebf5e5
AK		 1421#if 1
1422 }
1423#endif
1424}
a24d60f4 1425
b9ebf5e5
AK		 1426static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1427 struct vb_device_info *pVBInfo)
1428{
1429 unsigned char Temp, bCR4A;
a24d60f4 1430
b9ebf5e5 1431 pVBInfo->IF_DEF_LVDS = 0;
58839b01 1432 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1433 /* Enable GPIOA/B/C read */
1434 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
58839b01 1435 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
8104e329 1436 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
a24d60f4 1437
b9ebf5e5
AK		 1438 if (Temp <= 0x02) {
1439 pVBInfo->IF_DEF_LVDS = 1;
bf32fcb9
KT		 1440 /* LVDS setting */
1441 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
8104e329 1442 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
b9ebf5e5 1443 } else {
bf32fcb9
KT		 1444 /* TMDS/DVO setting */
1445 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
b9ebf5e5 1446 }
b9bf6e4e 1447 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
a24d60f4 1448
b9ebf5e5 1449}
a24d60f4 1450
b9ebf5e5
AK		 1451static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1452{
1453 unsigned char CR38, CR4A, temp;
a24d60f4 1454
58839b01 1455 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1456 /* enable GPIOE read */
1457 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
58839b01 1458 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1459 temp = 0;
1460 if ((CR38 & 0xE0) > 0x80) {
58839b01 1461 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5
AK		 1462 temp &= 0x08;
1463 temp >>= 3;
1464 }
a24d60f4 1465
8104e329 1466 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1467
b9ebf5e5
AK		 1468 return temp;
1469}
a24d60f4 1470
b9ebf5e5
AK		 1471static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1472{
1473 unsigned char CR4A, temp;
a24d60f4 1474
58839b01 1475 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1476 /* enable GPIOA/B/C read */
1477 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1478 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5
AK		 1479 if (temp <= 2)
1480 temp &= 0x03;
1481 else
1482 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
a24d60f4 1483
8104e329 1484 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1485
b9ebf5e5
AK		 1486 return temp;
1487}
a24d60f4 1488
6048d761 1489unsigned char XGIInitNew(struct pci_dev *pdev)
b9ebf5e5 1490{
ab886ff8 1491 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
6048d761 1492 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
b9ebf5e5
AK		 1493 struct vb_device_info VBINF;
1494 struct vb_device_info *pVBInfo = &VBINF;
1495 unsigned char i, temp = 0, temp1;
1496 /* VBIOSVersion[5]; */
1497 volatile unsigned char *pVideoMemory;
a24d60f4 1498
b9ebf5e5 1499 /* unsigned long j, k; */
a24d60f4 1500
b9ebf5e5 1501 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
a24d60f4 1502
b9ebf5e5 1503 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 1504
b9ebf5e5 1505 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
a24d60f4 1506
b9ebf5e5 1507 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
a24d60f4 1508
b9ebf5e5 1509 /* Newdebugcode(0x99); */
a24d60f4 1510
a24d60f4 1511
b9ebf5e5
AK		 1512 /* if (pVBInfo->ROMAddr == 0) */
1513 /* return(0); */
a24d60f4 1514
b9ebf5e5
AK		 1515 if (pVBInfo->FBAddr == NULL) {
1516 printk("\n pVBInfo->FBAddr == 0 ");
1517 return 0;
1518 }
1519 printk("1");
1520 if (pVBInfo->BaseAddr == 0) {
1521 printk("\npVBInfo->BaseAddr == 0 ");
1522 return 0;
1523 }
1524 printk("2");
a24d60f4 1525
efdf4ee7 1526 outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
a24d60f4 1527
b9ebf5e5
AK		 1528 pVBInfo->ISXPDOS = 0;
1529 printk("3");
d7636e0b 1530
b9ebf5e5 1531 printk("4");
a24d60f4 1532
b9ebf5e5 1533 /* VBIOSVersion[4] = 0x0; */
a24d60f4 1534
b9ebf5e5 1535 /* 09/07/99 modify by domao */
a24d60f4 1536
b9ebf5e5
AK		 1537 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1538 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1539 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1540 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1541 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1542 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1543 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1544 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1545 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1546 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1547 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1548 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1549 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1550 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1551 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1552 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1553 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1554 printk("5");
d7636e0b 1555
b9ebf5e5 1556 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
bf32fcb9
KT		 1557 /* Run XGI_GetVBType before InitTo330Pointer */
1558 XGI_GetVBType(pVBInfo);
a24d60f4 1559
b9ebf5e5
AK		 1560 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1561
1562 /* ReadVBIOSData */
1563 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1564
1565 /* 1.Openkey */
8104e329 1566 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
b9ebf5e5
AK		 1567 printk("6");
1568
1569 /* GetXG21Sense (GPIO) */
1570 if (HwDeviceExtension->jChipType == XG21)
1571 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1572
1573 if (HwDeviceExtension->jChipType == XG27)
1574 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1575
1576 printk("7");
1577
1578 /* 2.Reset Extended register */
1579
1580 for (i = 0x06; i < 0x20; i++)
8104e329 1581 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5
AK		 1582
1583 for (i = 0x21; i <= 0x27; i++)
8104e329 1584 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5
AK		 1585
1586 /* for(i = 0x06; i <= 0x27; i++) */
8104e329 1587 /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
b9ebf5e5
AK		 1588
1589 printk("8");
1590
06587335 1591 for (i = 0x31; i <= 0x3B; i++)
8104e329 1592 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5 1593 printk("9");
d7636e0b 1594
bf32fcb9
KT		 1595 /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1596 if (HwDeviceExtension->jChipType == XG42)
8104e329 1597 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
d7636e0b 1598
b9ebf5e5 1599 /* for (i = 0x30; i <= 0x3F; i++) */
8104e329 1600 /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
a24d60f4 1601
b9ebf5e5 1602 for (i = 0x79; i <= 0x7C; i++)
8104e329 1603 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
d7636e0b 1604
b9ebf5e5 1605 printk("10");
a24d60f4 1606
b9ebf5e5 1607 if (HwDeviceExtension->jChipType >= XG20)
8104e329 1608 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
a24d60f4 1609
b9ebf5e5
AK		 1610 /* 3.SetMemoryClock
1611
2af1a29d 1612 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
fd0ad470 1613 */
b9ebf5e5
AK		 1614
1615 printk("11");
1616
1617 /* 4.SetDefExt1Regs begin */
8104e329 1618 xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
b9ebf5e5 1619 if (HwDeviceExtension->jChipType == XG27) {
8104e329
AK		 1620 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1621 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
a24d60f4 1622 }
8104e329
AK		 1623 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1624 xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1625 /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
bf32fcb9
KT		 1626 /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1627 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1628 /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1629 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
b9ebf5e5 1630 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
8104e329 1631 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
a24d60f4 1632
b9ebf5e5 1633 /* SR11 = 0x0F; */
8104e329 1634 /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
a24d60f4 1635
b9ebf5e5
AK		 1636 printk("12");
1637
1638 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
6048d761
AK		 1639 u32 Temp;
1640
b9ebf5e5
AK		 1641 /* Set AGP Rate */
1642 /*
58839b01 1643 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
b9ebf5e5
AK		 1644 temp1 &= 0x02;
1645 if (temp1 == 0x02) {
3d2a60a2 1646 outl(0x80000000, 0xcf8);
f5b571fa 1647 ChipsetID = inl(0x0cfc);
3d2a60a2 1648 outl(0x8000002C, 0xcf8);
f5b571fa 1649 VendorID = inl(0x0cfc);
b9ebf5e5 1650 VendorID &= 0x0000FFFF;
3d2a60a2 1651 outl(0x8001002C, 0xcf8);
f5b571fa 1652 GraphicVendorID = inl(0x0cfc);
b9ebf5e5
AK		 1653 GraphicVendorID &= 0x0000FFFF;
1654
1655 if (ChipsetID == 0x7301039)
8104e329 1656 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
b9ebf5e5
AK		 1657
1658 ChipsetID &= 0x0000FFFF;
1659
bf32fcb9
KT		 1660 if ((ChipsetID == 0x700E) ||
1661 (ChipsetID == 0x1022) ||
1662 (ChipsetID == 0x1106) ||
1663 (ChipsetID == 0x10DE)) {
b9ebf5e5 1664 if (ChipsetID == 0x1106) {
bf32fcb9
KT		 1665 if ((VendorID == 0x1019) &&
1666 (GraphicVendorID == 0x1019))
1667 xgifb_reg_set(pVBInfo->P3d4,
1668 0x5F,
1669 0x0D);
b9ebf5e5 1670 else
bf32fcb9
KT		 1671 xgifb_reg_set(pVBInfo->P3d4,
1672 0x5F,
1673 0x0B);
b9ebf5e5 1674 } else {
bf32fcb9
KT		 1675 xgifb_reg_set(pVBInfo->P3d4,
1676 0x5F,
1677 0x0B);
b9ebf5e5
AK		 1678 }
1679 }
a24d60f4 1680 }
b9ebf5e5 1681 */
a24d60f4 1682
b9ebf5e5
AK		 1683 printk("13");
1684
06587335
AK		 1685 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1686 for (i = 0x47; i <= 0x4C; i++)
bf32fcb9
KT		 1687 xgifb_reg_set(pVBInfo->P3d4,
1688 i,
1689 pVBInfo->AGPReg[i - 0x47]);
06587335
AK		 1690
1691 for (i = 0x70; i <= 0x71; i++)
bf32fcb9
KT		 1692 xgifb_reg_set(pVBInfo->P3d4,
1693 i,
1694 pVBInfo->AGPReg[6 + i - 0x70]);
06587335
AK		 1695
1696 for (i = 0x74; i <= 0x77; i++)
bf32fcb9
KT		 1697 xgifb_reg_set(pVBInfo->P3d4,
1698 i,
1699 pVBInfo->AGPReg[8 + i - 0x74]);
06587335
AK		 1700 /* Set AGP customize registers (in SetDefAGPRegs) End */
1701 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
3d2a60a2 1702 /* outl(0x80000000, 0xcf8); */
f5b571fa 1703 /* ChipsetID = inl(0x0cfc); */
06587335 1704 /* if (ChipsetID == 0x25308086) */
8104e329 1705 /* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
06587335 1706
6048d761 1707 pci_read_config_dword(pdev, 0x50, &Temp);
06587335
AK		 1708 Temp >>= 20;
1709 Temp &= 0xF;
1710
1711 if (Temp == 1)
8104e329 1712 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
b9ebf5e5 1713 printk("14");
b9ebf5e5 1714 } /* != XG20 */
a24d60f4 1715
b9ebf5e5 1716 /* Set PCI */
8104e329
AK		 1717 xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1718 xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1719 xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
b9ebf5e5 1720 printk("15");
a24d60f4 1721
b9ebf5e5
AK		 1722 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1723 /* Set VB */
1724 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
bf32fcb9
KT		 1725 /* alan, disable VideoCapture */
1726 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
8104e329 1727 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
bf32fcb9
KT		 1728 /* chk if BCLK>=100MHz */
1729 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
b9ebf5e5 1730 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
a24d60f4 1731
bf32fcb9
KT		 1732 xgifb_reg_set(pVBInfo->Part1Port,
1733 0x02,
1734 (*pVBInfo->pCRT2Data_1_2));
a24d60f4 1735
b9ebf5e5 1736 printk("16");
a24d60f4 1737
8104e329 1738 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
b9ebf5e5 1739 } /* != XG20 */
a24d60f4 1740
8104e329 1741 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
b9ebf5e5 1742
bf32fcb9
KT		 1743 if ((HwDeviceExtension->jChipType == XG42) &&
1744 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1745 /* Not DDR */
1746 xgifb_reg_set(pVBInfo->P3c4,
1747 0x31,
1748 (*pVBInfo->pSR31 & 0x3F) | 0x40);
1749 xgifb_reg_set(pVBInfo->P3c4,
1750 0x32,
1751 (*pVBInfo->pSR32 & 0xFC) | 0x01);
a24d60f4 1752 } else {
8104e329
AK		 1753 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1754 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
b9ebf5e5 1755 }
8104e329 1756 xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
b9ebf5e5 1757 printk("17");
a24d60f4 1758
b9ebf5e5 1759 /*
b9ebf5e5 1760 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
a24d60f4 1761
b9ebf5e5
AK		 1762 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1763 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1764 if (pVBInfo->IF_DEF_LVDS == 0) {
8104e329 1765 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
bf32fcb9
KT		 1766 xgifb_reg_set(pVBInfo->Part4Port,
1767 0x0D,
1768 *pVBInfo->pCRT2Data_4_D);
1769 xgifb_reg_set(pVBInfo->Part4Port,
1770 0x0E,
1771 *pVBInfo->pCRT2Data_4_E);
1772 xgifb_reg_set(pVBInfo->Part4Port,
1773 0x10,
1774 *pVBInfo->pCRT2Data_4_10);
8104e329 1775 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
b9ebf5e5
AK		 1776 }
1777
1778 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
a24d60f4 1779 }
b9ebf5e5
AK		 1780 } /* != XG20 */
1781 printk("18");
a24d60f4 1782
b9ebf5e5 1783 printk("181");
a24d60f4 1784
b9ebf5e5 1785 printk("182");
a24d60f4 1786
b9ebf5e5 1787 XGI_SenseCRT1(pVBInfo);
d7636e0b 1788
b9ebf5e5
AK		 1789 printk("183");
1790 /* XGINew_DetectMonitor(HwDeviceExtension); */
b9ebf5e5
AK		 1791 if (HwDeviceExtension->jChipType == XG21) {
1792 printk("186");
d7636e0b 1793
bf32fcb9
KT		 1794 xgifb_reg_and_or(pVBInfo->P3d4,
1795 0x32,
1796 ~Monitor1Sense,
1797 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1798 temp = GetXG21FPBits(pVBInfo);
ec9e5d3e 1799 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
b9ebf5e5 1800 printk("187");
d7636e0b 1801
a24d60f4 1802 }
b9ebf5e5 1803 if (HwDeviceExtension->jChipType == XG27) {
bf32fcb9
KT		 1804 xgifb_reg_and_or(pVBInfo->P3d4,
1805 0x32,
1806 ~Monitor1Sense,
1807 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1808 temp = GetXG27FPBits(pVBInfo);
ec9e5d3e 1809 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
b9ebf5e5
AK		 1810 }
1811 printk("19");
d7636e0b 1812
2af1a29d 1813 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
d7636e0b 1814
bf32fcb9
KT		 1815 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1816 pVBInfo->P3d4,
1817 pVBInfo);
a24d60f4 1818
06587335
AK		 1819 printk("20");
1820 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1821 printk("21");
d7636e0b 1822
b9ebf5e5 1823 printk("22");
d7636e0b 1824
b9ebf5e5
AK		 1825 /* SetDefExt2Regs begin */
1826 /*
1827 AGP = 1;
58839b01 1828 temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
b9ebf5e5
AK		 1829 temp &= 0x30;
1830 if (temp == 0x30)
1831 AGP = 0;
d7636e0b 1832
b9ebf5e5
AK		 1833 if (AGP == 0)
1834 *pVBInfo->pSR21 &= 0xEF;
d7636e0b 1835
8104e329 1836 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
b9ebf5e5
AK		 1837 if (AGP == 1)
1838 *pVBInfo->pSR22 &= 0x20;
8104e329 1839 xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
b9ebf5e5
AK		 1840 */
1841 /* base = 0x80000000; */
1842 /* OutPortLong(0xcf8, base); */
1843 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1844 /* if (Temp == 0x1039) { */
bf32fcb9
KT		 1845 xgifb_reg_set(pVBInfo->P3c4,
1846 0x22,
1847 (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
b9ebf5e5 1848 /* } else { */
8104e329 1849 /* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
b9ebf5e5 1850 /* } */
d7636e0b 1851
8104e329 1852 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
d7636e0b 1853
b9ebf5e5 1854 printk("23");
d7636e0b 1855
b9ebf5e5
AK		 1856 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1857 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
a24d60f4 1858
b9ebf5e5 1859 printk("24");
a24d60f4 1860
8104e329
AK		 1861 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1862 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
b9ebf5e5 1863 printk("25");
d7636e0b 1864
b9ebf5e5
AK		 1865 return 1;
1866} /* end of init */
Linux kernel - Deliverables
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