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Merge 3.9-rc5 into staging-next
[deliverable/linux.git] / drivers / staging / xgifb / vb_init.c
CommitLineData
949eb0ae 1#include <linux/delay.h>
02a81dd9 2#include <linux/vmalloc.h>
6048d761 3
d7636e0b 4#include "XGIfb.h"
d7636e0b 5#include "vb_def.h"
d7636e0b 6#include "vb_util.h"
7#include "vb_setmode.h"
e054102b 8#include "vb_init.h"
d6461e49
PH		 9static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
10 { 16, 0x45},
11 { 8, 0x35},
12 { 4, 0x31},
13 { 2, 0x21} };
14
15static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
16 { 128, 0x5D},
17 { 64, 0x59},
18 { 64, 0x4D},
19 { 32, 0x55},
20 { 32, 0x49},
21 { 32, 0x3D},
22 { 16, 0x51},
23 { 16, 0x45},
24 { 16, 0x39},
25 { 8, 0x41},
26 { 8, 0x35},
27 { 4, 0x31} };
d7636e0b 28
02a81dd9
AK		 29#define XGIFB_ROM_SIZE 65536
30
bf32fcb9
KT		 31static unsigned char
32XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
d7636e0b 34{
b9ebf5e5 35 unsigned char data, temp;
d7636e0b 36
b9ebf5e5 37 if (HwDeviceExtension->jChipType < XG20) {
6d12dae4
PH		 38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
39 if (data == 0)
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
41 0x02) >> 1;
42 return data;
b9ebf5e5 43 } else if (HwDeviceExtension->jChipType == XG27) {
58839b01 44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
bf32fcb9 45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
6490311f 46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
b9ebf5e5
AK		 47 data = 0; /* DDR */
48 else
49 data = 1; /* DDRII */
50 return data;
51 } else if (HwDeviceExtension->jChipType == XG21) {
bf32fcb9
KT		 52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
c45715bb 54 udelay(800);
b9bf6e4e 55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
bf32fcb9
KT		 56 /* GPIOF 0:DVI 1:DVO */
57 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5 58 /* HOTPLUG_SUPPORT */
bf32fcb9
KT		 59 /* for current XG20 & XG21, GPIOH is floating, driver will
60 * fix DDR temporarily */
b9ebf5e5
AK		 61 if (temp & 0x01) /* DVI read GPIOH */
62 data = 1; /* DDRII */
63 else
64 data = 0; /* DDR */
65 /* ~HOTPLUG_SUPPORT */
b9bf6e4e 66 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
b9ebf5e5
AK		 67 return data;
68 } else {
58839b01 69 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
d7636e0b 70
b9ebf5e5
AK		 71 if (data == 1)
72 data++;
d7636e0b 73
b9ebf5e5
AK		 74 return data;
75 }
76}
d7636e0b 77
bf32fcb9
KT		 78static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
79 struct vb_device_info *pVBInfo)
b9ebf5e5 80{
8104e329
AK		 81 xgifb_reg_set(P3c4, 0x18, 0x01);
82 xgifb_reg_set(P3c4, 0x19, 0x20);
83 xgifb_reg_set(P3c4, 0x16, 0x00);
84 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 85
6d12dae4
PH		 86 mdelay(3);
87 xgifb_reg_set(P3c4, 0x18, 0x00);
88 xgifb_reg_set(P3c4, 0x19, 0x20);
89 xgifb_reg_set(P3c4, 0x16, 0x00);
90 xgifb_reg_set(P3c4, 0x16, 0x80);
d7636e0b 91
c45715bb 92 udelay(60);
597d96b6 93 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329 94 xgifb_reg_set(P3c4, 0x19, 0x01);
0904f7f3
AK		 95 xgifb_reg_set(P3c4, 0x16, 0x03);
96 xgifb_reg_set(P3c4, 0x16, 0x83);
c83c620a 97 mdelay(1);
8104e329 98 xgifb_reg_set(P3c4, 0x1B, 0x03);
c45715bb 99 udelay(500);
597d96b6 100 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329 101 xgifb_reg_set(P3c4, 0x19, 0x00);
0904f7f3
AK		 102 xgifb_reg_set(P3c4, 0x16, 0x03);
103 xgifb_reg_set(P3c4, 0x16, 0x83);
8104e329 104 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 105}
d7636e0b 106
b9ebf5e5
AK		 107static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
108 struct vb_device_info *pVBInfo)
109{
d7636e0b 110
bf32fcb9
KT		 111 xgifb_reg_set(pVBInfo->P3c4,
112 0x28,
2af1a29d 113 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
bf32fcb9
KT		 114 xgifb_reg_set(pVBInfo->P3c4,
115 0x29,
2af1a29d 116 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
bf32fcb9
KT		 117 xgifb_reg_set(pVBInfo->P3c4,
118 0x2A,
2af1a29d 119 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
bf32fcb9
KT		 120
121 xgifb_reg_set(pVBInfo->P3c4,
122 0x2E,
9b047458 123 XGI340_ECLKData[pVBInfo->ram_type].SR2E);
bf32fcb9
KT		 124 xgifb_reg_set(pVBInfo->P3c4,
125 0x2F,
9b047458 126 XGI340_ECLKData[pVBInfo->ram_type].SR2F);
bf32fcb9
KT		 127 xgifb_reg_set(pVBInfo->P3c4,
128 0x30,
9b047458 129 XGI340_ECLKData[pVBInfo->ram_type].SR30);
b9ebf5e5 130}
d7636e0b 131
b9ebf5e5
AK		 132static void XGINew_DDRII_Bootup_XG27(
133 struct xgi_hw_device_info *HwDeviceExtension,
134 unsigned long P3c4, struct vb_device_info *pVBInfo)
135{
136 unsigned long P3d4 = P3c4 + 0x10;
2af1a29d 137 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b9ebf5e5 138 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
d7636e0b 139
b9ebf5e5 140 /* Set Double Frequency */
6d12dae4 141 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
d7636e0b 142
c45715bb 143 udelay(200);
d7636e0b 144
8104e329
AK		 145 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
146 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
147 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 148 udelay(15);
8104e329 149 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 150 udelay(15);
d7636e0b 151
8104e329
AK		 152 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
153 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
154 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 155 udelay(15);
8104e329 156 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 157 udelay(15);
d7636e0b 158
8104e329
AK		 159 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
160 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
161 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 162 udelay(30);
8104e329 163 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 164 udelay(15);
d7636e0b 165
8104e329
AK		 166 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
167 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
168 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
c45715bb 169 udelay(30);
8104e329
AK		 170 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
171 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
d7636e0b 172
8104e329 173 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
c45715bb 174 udelay(60);
8104e329 175 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
d7636e0b 176
8104e329
AK		 177 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
178 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
179 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
d7636e0b 180
c45715bb 181 udelay(30);
8104e329 182 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
c45715bb 183 udelay(15);
d7636e0b 184
8104e329
AK		 185 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
186 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
187 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 188 udelay(30);
8104e329 189 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 190 udelay(15);
d7636e0b 191
8104e329
AK		 192 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
193 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
194 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
c45715bb 195 udelay(30);
8104e329 196 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
c45715bb 197 udelay(15);
d7636e0b 198
bf32fcb9
KT		 199 /* Set SR1B refresh control 000:close; 010:open */
200 xgifb_reg_set(P3c4, 0x1B, 0x04);
c45715bb 201 udelay(200);
d7636e0b 202
b9ebf5e5 203}
d7636e0b 204
b9ebf5e5
AK		 205static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
206 unsigned long P3c4, struct vb_device_info *pVBInfo)
207{
208 unsigned long P3d4 = P3c4 + 0x10;
d7636e0b 209
2af1a29d 210 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
b9ebf5e5 211 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
d7636e0b 212
8104e329 213 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
d7636e0b 214
c45715bb 215 udelay(200);
8104e329
AK		 216 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
217 xgifb_reg_set(P3c4, 0x19, 0x80);
218 xgifb_reg_set(P3c4, 0x16, 0x05);
219 xgifb_reg_set(P3c4, 0x16, 0x85);
220
221 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
222 xgifb_reg_set(P3c4, 0x19, 0xC0);
223 xgifb_reg_set(P3c4, 0x16, 0x05);
224 xgifb_reg_set(P3c4, 0x16, 0x85);
225
226 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
227 xgifb_reg_set(P3c4, 0x19, 0x40);
228 xgifb_reg_set(P3c4, 0x16, 0x05);
229 xgifb_reg_set(P3c4, 0x16, 0x85);
230
8104e329
AK		 231 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
232 xgifb_reg_set(P3c4, 0x19, 0x02);
233 xgifb_reg_set(P3c4, 0x16, 0x05);
234 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 235
c45715bb 236 udelay(15);
8104e329 237 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
c45715bb 238 udelay(30);
8104e329 239 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
c45715bb 240 udelay(100);
a24d60f4 241
8104e329
AK		 242 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
243 xgifb_reg_set(P3c4, 0x19, 0x00);
244 xgifb_reg_set(P3c4, 0x16, 0x05);
245 xgifb_reg_set(P3c4, 0x16, 0x85);
a24d60f4 246
c45715bb 247 udelay(200);
b9ebf5e5 248}
a24d60f4 249
bf32fcb9
KT		 250static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
251 struct vb_device_info *pVBInfo)
b9ebf5e5 252{
8104e329
AK		 253 xgifb_reg_set(P3c4, 0x18, 0x01);
254 xgifb_reg_set(P3c4, 0x19, 0x40);
255 xgifb_reg_set(P3c4, 0x16, 0x00);
256 xgifb_reg_set(P3c4, 0x16, 0x80);
c45715bb 257 udelay(60);
a24d60f4 258
8104e329
AK		 259 xgifb_reg_set(P3c4, 0x18, 0x00);
260 xgifb_reg_set(P3c4, 0x19, 0x40);
261 xgifb_reg_set(P3c4, 0x16, 0x00);
262 xgifb_reg_set(P3c4, 0x16, 0x80);
c45715bb 263 udelay(60);
597d96b6 264 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 265 xgifb_reg_set(P3c4, 0x19, 0x01);
266 xgifb_reg_set(P3c4, 0x16, 0x03);
267 xgifb_reg_set(P3c4, 0x16, 0x83);
c83c620a 268 mdelay(1);
8104e329 269 xgifb_reg_set(P3c4, 0x1B, 0x03);
c45715bb 270 udelay(500);
597d96b6 271 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
8104e329
AK		 272 xgifb_reg_set(P3c4, 0x19, 0x00);
273 xgifb_reg_set(P3c4, 0x16, 0x03);
274 xgifb_reg_set(P3c4, 0x16, 0x83);
275 xgifb_reg_set(P3c4, 0x1B, 0x00);
b9ebf5e5 276}
a24d60f4 277
b9ebf5e5
AK		 278static void XGINew_DDR1x_DefaultRegister(
279 struct xgi_hw_device_info *HwDeviceExtension,
280 unsigned long Port, struct vb_device_info *pVBInfo)
281{
282 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 283
b9ebf5e5
AK		 284 if (HwDeviceExtension->jChipType >= XG20) {
285 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
bf32fcb9
KT		 286 xgifb_reg_set(P3d4,
287 0x82,
2af1a29d 288 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
bf32fcb9
KT		 289 xgifb_reg_set(P3d4,
290 0x85,
2af1a29d 291 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
bf32fcb9
KT		 292 xgifb_reg_set(P3d4,
293 0x86,
2af1a29d 294 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
a24d60f4 295
8104e329
AK		 296 xgifb_reg_set(P3d4, 0x98, 0x01);
297 xgifb_reg_set(P3d4, 0x9A, 0x02);
a24d60f4 298
b9ebf5e5
AK		 299 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
300 } else {
301 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
a24d60f4 302
b9ebf5e5 303 switch (HwDeviceExtension->jChipType) {
b9ebf5e5 304 case XG42:
bf32fcb9
KT		 305 /* CR82 */
306 xgifb_reg_set(P3d4,
307 0x82,
2af1a29d 308 pVBInfo->CR40[11][pVBInfo->ram_type]);
bf32fcb9
KT		 309 /* CR85 */
310 xgifb_reg_set(P3d4,
311 0x85,
2af1a29d 312 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 313 /* CR86 */
314 xgifb_reg_set(P3d4,
315 0x86,
2af1a29d 316 pVBInfo->CR40[13][pVBInfo->ram_type]);
b9ebf5e5
AK		 317 break;
318 default:
8104e329
AK		 319 xgifb_reg_set(P3d4, 0x82, 0x88);
320 xgifb_reg_set(P3d4, 0x86, 0x00);
bf32fcb9
KT		 321 /* Insert read command for delay */
322 xgifb_reg_get(P3d4, 0x86);
8104e329 323 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 324 xgifb_reg_get(P3d4, 0x86);
bf32fcb9
KT		 325 xgifb_reg_set(P3d4,
326 0x86,
2af1a29d 327 pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 328 xgifb_reg_set(P3d4, 0x82, 0x77);
329 xgifb_reg_set(P3d4, 0x85, 0x00);
bf32fcb9
KT		 330
331 /* Insert read command for delay */
332 xgifb_reg_get(P3d4, 0x85);
8104e329 333 xgifb_reg_set(P3d4, 0x85, 0x88);
bf32fcb9
KT		 334
335 /* Insert read command for delay */
336 xgifb_reg_get(P3d4, 0x85);
337 /* CR85 */
338 xgifb_reg_set(P3d4,
339 0x85,
2af1a29d 340 pVBInfo->CR40[12][pVBInfo->ram_type]);
bf32fcb9
KT		 341 /* CR82 */
342 xgifb_reg_set(P3d4,
343 0x82,
2af1a29d 344 pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 345 break;
a24d60f4 346 }
a24d60f4 347
8104e329
AK		 348 xgifb_reg_set(P3d4, 0x97, 0x00);
349 xgifb_reg_set(P3d4, 0x98, 0x01);
350 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 351 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
352 }
353}
a24d60f4 354
b9ebf5e5
AK		 355static void XGINew_DDR2_DefaultRegister(
356 struct xgi_hw_device_info *HwDeviceExtension,
357 unsigned long Port, struct vb_device_info *pVBInfo)
358{
359 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 360
bf32fcb9
KT		 361 /* keep following setting sequence, each setting in
362 * the same reg insert idle */
8104e329
AK		 363 xgifb_reg_set(P3d4, 0x82, 0x77);
364 xgifb_reg_set(P3d4, 0x86, 0x00);
58839b01 365 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
8104e329 366 xgifb_reg_set(P3d4, 0x86, 0x88);
58839b01 367 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
bf32fcb9 368 /* CR86 */
2af1a29d 369 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
8104e329
AK		 370 xgifb_reg_set(P3d4, 0x82, 0x77);
371 xgifb_reg_set(P3d4, 0x85, 0x00);
58839b01 372 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
8104e329 373 xgifb_reg_set(P3d4, 0x85, 0x88);
58839b01 374 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
2af1a29d
AK		 375 xgifb_reg_set(P3d4,
376 0x85,
377 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
b9ebf5e5 378 if (HwDeviceExtension->jChipType == XG27)
bf32fcb9 379 /* CR82 */
2af1a29d 380 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
b9ebf5e5 381 else
8104e329 382 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
a24d60f4 383
8104e329
AK		 384 xgifb_reg_set(P3d4, 0x98, 0x01);
385 xgifb_reg_set(P3d4, 0x9A, 0x02);
b9ebf5e5
AK		 386 if (HwDeviceExtension->jChipType == XG27)
387 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
388 else
389 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
390}
a24d60f4 391
0141bb2e
PH		 392static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
393 u8 shift_factor, u8 mask1, u8 mask2)
394{
395 u8 j;
396 for (j = 0; j < 4; j++) {
397 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
398 xgifb_reg_set(P3d4, reg, temp2);
399 xgifb_reg_get(P3d4, reg);
400 temp2 &= mask1;
401 temp2 += mask2;
402 }
403}
404
b9ebf5e5
AK		 405static void XGINew_SetDRAMDefaultRegister340(
406 struct xgi_hw_device_info *HwDeviceExtension,
407 unsigned long Port, struct vb_device_info *pVBInfo)
408{
fc008aff 409 unsigned char temp, temp1, temp2, temp3, j, k;
a24d60f4 410
b9ebf5e5 411 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
a24d60f4 412
2af1a29d
AK		 413 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
414 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
415 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
416 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
a24d60f4 417
1504ecbe 418 /* CR6B DQS fine tune delay */
6a7fd2db 419 temp = 0xaa;
1504ecbe 420 XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
a24d60f4 421
1504ecbe
PH		 422 /* CR6E DQM fine tune delay */
423 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
a24d60f4 424
b9ebf5e5
AK		 425 temp3 = 0;
426 for (k = 0; k < 4; k++) {
bf32fcb9
KT		 427 /* CR6E_D[1:0] select channel */
428 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
1504ecbe 429 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
b9ebf5e5
AK		 430 temp3 += 0x01;
431 }
a24d60f4 432
2af1a29d
AK		 433 xgifb_reg_set(P3d4,
434 0x80,
435 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
436 xgifb_reg_set(P3d4,
437 0x81,
438 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
a24d60f4 439
b9ebf5e5 440 temp2 = 0x80;
bf32fcb9 441 /* CR89 terminator type select */
0141bb2e 442 XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
a24d60f4 443
7e29d632 444 temp = 0;
b9ebf5e5
AK		 445 temp1 = temp & 0x03;
446 temp2 |= temp1;
8104e329 447 xgifb_reg_set(P3d4, 0x89, temp2);
a24d60f4 448
2af1a29d 449 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
b9ebf5e5
AK		 450 temp1 = temp & 0x0F;
451 temp2 = (temp >> 4) & 0x07;
452 temp3 = temp & 0x80;
8104e329
AK		 453 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
454 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
b9bf6e4e 455 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
2af1a29d
AK		 456 xgifb_reg_set(P3d4,
457 0x41,
458 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
a24d60f4 459
b9ebf5e5 460 if (HwDeviceExtension->jChipType == XG27)
6d12dae4 461 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
a24d60f4 462
bf32fcb9 463 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
8104e329 464 xgifb_reg_set(P3d4, (0x90 + j),
2af1a29d 465 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
a24d60f4 466
bf32fcb9 467 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
8104e329 468 xgifb_reg_set(P3d4, (0xC3 + j),
2af1a29d 469 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
a24d60f4 470
bf32fcb9 471 for (j = 0; j < 2; j++) /* CR8A - CR8B */
8104e329 472 xgifb_reg_set(P3d4, (0x8A + j),
2af1a29d 473 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
a24d60f4 474
18408da0 475 if (HwDeviceExtension->jChipType == XG42)
8104e329 476 xgifb_reg_set(P3d4, 0x8C, 0x87);
a24d60f4 477
2af1a29d
AK		 478 xgifb_reg_set(P3d4,
479 0x59,
480 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
a24d60f4 481
8104e329
AK		 482 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
483 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
6d12dae4 484 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
2af1a29d 485 if (pVBInfo->ram_type) {
8104e329 486 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
b9ebf5e5 487 if (HwDeviceExtension->jChipType == XG27)
8104e329 488 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
a24d60f4 489
b9ebf5e5 490 } else {
8104e329 491 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
b9ebf5e5 492 }
8104e329 493 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
a24d60f4 494
b9ebf5e5
AK		 495 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
496 if (temp == 0) {
497 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
498 } else {
8104e329 499 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
b9ebf5e5
AK		 500 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
501 }
d7ab4a4f 502 xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
b9ebf5e5 503}
a24d60f4 504
a24d60f4 505
d6461e49
PH		 506static unsigned short XGINew_SetDRAMSize20Reg(
507 unsigned short dram_size,
b9ebf5e5 508 struct vb_device_info *pVBInfo)
d7636e0b 509{
b9ebf5e5
AK		 510 unsigned short data = 0, memsize = 0;
511 int RankSize;
512 unsigned char ChannelNo;
d7636e0b 513
d6461e49 514 RankSize = dram_size * pVBInfo->ram_bus / 8;
58839b01 515 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
b9ebf5e5 516 data &= 0x80;
d7636e0b 517
b9ebf5e5
AK		 518 if (data == 0x80)
519 RankSize *= 2;
a24d60f4 520
b9ebf5e5 521 data = 0;
a24d60f4 522
ee055a48 523 if (pVBInfo->ram_channel == 3)
b9ebf5e5
AK		 524 ChannelNo = 4;
525 else
ee055a48 526 ChannelNo = pVBInfo->ram_channel;
a24d60f4 527
b9ebf5e5
AK		 528 if (ChannelNo * RankSize <= 256) {
529 while ((RankSize >>= 1) > 0)
530 data += 0x10;
a24d60f4 531
b9ebf5e5 532 memsize = data >> 4;
a24d60f4 533
949eb0ae 534 /* Fix DRAM Sizing Error */
bf32fcb9
KT		 535 xgifb_reg_set(pVBInfo->P3c4,
536 0x14,
537 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
538 (data & 0xF0));
c45715bb 539 udelay(15);
b9ebf5e5
AK		 540 }
541 return memsize;
542}
a24d60f4 543
b9ebf5e5
AK		 544static int XGINew_ReadWriteRest(unsigned short StopAddr,
545 unsigned short StartAddr, struct vb_device_info *pVBInfo)
546{
547 int i;
548 unsigned long Position = 0;
c44fa627 549 void __iomem *fbaddr = pVBInfo->FBAddr;
a24d60f4 550
c44fa627 551 writel(Position, fbaddr + Position);
a24d60f4 552
b9ebf5e5
AK		 553 for (i = StartAddr; i <= StopAddr; i++) {
554 Position = 1 << i;
c44fa627 555 writel(Position, fbaddr + Position);
b9ebf5e5 556 }
a24d60f4 557
949eb0ae 558 udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
a24d60f4 559
b9ebf5e5
AK		 560 Position = 0;
561
c44fa627 562 if (readl(fbaddr + Position) != Position)
b9ebf5e5 563 return 0;
d7636e0b 564
b9ebf5e5
AK		 565 for (i = StartAddr; i <= StopAddr; i++) {
566 Position = 1 << i;
c44fa627 567 if (readl(fbaddr + Position) != Position)
b9ebf5e5
AK		 568 return 0;
569 }
570 return 1;
d7636e0b 571}
a24d60f4 572
b9ebf5e5 573static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
d7636e0b 574{
b9ebf5e5 575 unsigned char data;
a24d60f4 576
58839b01 577 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
a24d60f4 578
b9ebf5e5 579 if ((data & 0x10) == 0) {
58839b01 580 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
b9ebf5e5
AK		 581 data = (data & 0x02) >> 1;
582 return data;
583 } else {
584 return data & 0x01;
585 }
586}
a24d60f4 587
b9ebf5e5
AK		 588static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
589 struct vb_device_info *pVBInfo)
590{
591 unsigned char data;
a24d60f4 592
b9ebf5e5
AK		 593 switch (HwDeviceExtension->jChipType) {
594 case XG20:
595 case XG21:
58839b01 596 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
b9ebf5e5 597 data = data & 0x01;
ee055a48 598 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
a24d60f4 599
b9ebf5e5 600 if (data == 0) { /* Single_32_16 */
a24d60f4 601
b9ebf5e5
AK		 602 if ((HwDeviceExtension->ulVideoMemorySize - 1)
603 > 0x1000000) {
a24d60f4 604
2f0f395e 605 pVBInfo->ram_bus = 32; /* 32 bits */
bf32fcb9
KT		 606 /* 22bit + 2 rank + 32bit */
607 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 608 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
c45715bb 609 udelay(15);
a24d60f4 610
b9ebf5e5
AK		 611 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
612 return;
d7636e0b 613
bf32fcb9
KT		 614 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
615 0x800000) {
616 /* 22bit + 1 rank + 32bit */
617 xgifb_reg_set(pVBInfo->P3c4,
618 0x13,
619 0x31);
620 xgifb_reg_set(pVBInfo->P3c4,
621 0x14,
622 0x42);
c45715bb 623 udelay(15);
a24d60f4 624
bf32fcb9
KT		 625 if (XGINew_ReadWriteRest(23,
626 23,
627 pVBInfo) == 1)
b9ebf5e5
AK		 628 return;
629 }
630 }
a24d60f4 631
bf32fcb9
KT		 632 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
633 0x800000) {
2f0f395e 634 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 635 /* 22bit + 2 rank + 16bit */
636 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
8104e329 637 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
c45715bb 638 udelay(15);
a24d60f4 639
b9ebf5e5
AK		 640 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
641 return;
642 else
bf32fcb9
KT		 643 xgifb_reg_set(pVBInfo->P3c4,
644 0x13,
645 0x31);
c45715bb 646 udelay(15);
b9ebf5e5 647 }
a24d60f4 648
b9ebf5e5 649 } else { /* Dual_16_8 */
bf32fcb9
KT		 650 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
651 0x800000) {
2f0f395e 652 pVBInfo->ram_bus = 16; /* 16 bits */
bf32fcb9
KT		 653 /* (0x31:12x8x2) 22bit + 2 rank */
654 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
655 /* 0x41:16Mx16 bit*/
656 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
c45715bb 657 udelay(15);
a24d60f4 658
b9ebf5e5
AK		 659 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
660 return;
a24d60f4 661
bf32fcb9
KT		 662 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
663 0x400000) {
664 /* (0x31:12x8x2) 22bit + 1 rank */
665 xgifb_reg_set(pVBInfo->P3c4,
666 0x13,
667 0x31);
668 /* 0x31:8Mx16 bit*/
669 xgifb_reg_set(pVBInfo->P3c4,
670 0x14,
671 0x31);
c45715bb 672 udelay(15);
a24d60f4 673
bf32fcb9
KT		 674 if (XGINew_ReadWriteRest(22,
675 22,
676 pVBInfo) == 1)
b9ebf5e5
AK		 677 return;
678 }
679 }
a24d60f4 680
bf32fcb9
KT		 681 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
682 0x400000) {
2f0f395e 683 pVBInfo->ram_bus = 8; /* 8 bits */
bf32fcb9
KT		 684 /* (0x31:12x8x2) 22bit + 2 rank */
685 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
686 /* 0x30:8Mx8 bit*/
687 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
c45715bb 688 udelay(15);
d7636e0b 689
b9ebf5e5
AK		 690 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
691 return;
bf32fcb9
KT		 692 else /* (0x31:12x8x2) 22bit + 1 rank */
693 xgifb_reg_set(pVBInfo->P3c4,
694 0x13,
695 0x31);
c45715bb 696 udelay(15);
a24d60f4
PS		 697 }
698 }
b9ebf5e5 699 break;
a24d60f4 700
b9ebf5e5 701 case XG27:
2f0f395e 702 pVBInfo->ram_bus = 16; /* 16 bits */
ee055a48 703 pVBInfo->ram_channel = 1; /* Single channel */
8104e329 704 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
b9ebf5e5 705 break;
b9ebf5e5
AK		 706 case XG42:
707 /*
708 XG42 SR14 D[3] Reserve
709 D[2] = 1, Dual Channel
710 = 0, Single Channel
a24d60f4 711
b9ebf5e5
AK		 712 It's Different from Other XG40 Series.
713 */
714 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
2f0f395e 715 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 716 pVBInfo->ram_channel = 2; /* 2 Channel */
8104e329
AK		 717 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
718 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
a24d60f4 719
b9ebf5e5
AK		 720 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
721 return;
a24d60f4 722
8104e329
AK		 723 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
724 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
b9ebf5e5
AK		 725 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
726 return;
a24d60f4 727
ee055a48 728 pVBInfo->ram_channel = 1; /* Single Channel */
8104e329
AK		 729 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
730 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
d7636e0b 731
b9ebf5e5
AK		 732 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
733 return;
734 else {
8104e329
AK		 735 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
736 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
b9ebf5e5
AK		 737 }
738 } else { /* DDR */
2f0f395e 739 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 740 pVBInfo->ram_channel = 1; /* 1 channels */
8104e329
AK		 741 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
742 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
d7636e0b 743
b9ebf5e5
AK		 744 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
745 return;
746 else {
8104e329
AK		 747 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
748 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
b9ebf5e5
AK		 749 }
750 }
d7636e0b 751
b9ebf5e5 752 break;
d7636e0b 753
b9ebf5e5 754 default: /* XG40 */
d7636e0b 755
b9ebf5e5 756 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
2f0f395e 757 pVBInfo->ram_bus = 32; /* 32 bits */
ee055a48 758 pVBInfo->ram_channel = 3;
8104e329
AK		 759 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
760 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
d7636e0b 761
b9ebf5e5
AK		 762 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
763 return;
d7636e0b 764
ee055a48 765 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 766 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
a24d60f4 767
b9ebf5e5
AK		 768 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
769 return;
d7636e0b 770
8104e329
AK		 771 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
772 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
d7636e0b 773
b9ebf5e5 774 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
ee055a48 775 pVBInfo->ram_channel = 3; /* 4 channels */
b9ebf5e5 776 } else {
ee055a48 777 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329 778 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
b9ebf5e5
AK		 779 }
780 } else { /* DDR */
2f0f395e 781 pVBInfo->ram_bus = 64; /* 64 bits */
ee055a48 782 pVBInfo->ram_channel = 2; /* 2 channels */
8104e329
AK		 783 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
784 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
d7636e0b 785
b9ebf5e5
AK		 786 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
787 return;
788 } else {
8104e329
AK		 789 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
790 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
b9ebf5e5
AK		 791 }
792 }
793 break;
a24d60f4 794 }
d7636e0b 795}
796
b9ebf5e5
AK		 797static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
798 struct vb_device_info *pVBInfo)
d7636e0b 799{
672f5ee2
PH		 800 u8 i, size;
801 unsigned short memsize, start_addr;
d6461e49 802 const unsigned short (*dram_table)[2];
d7636e0b 803
8104e329
AK		 804 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
805 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
b9ebf5e5 806 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
d7636e0b 807
b9ebf5e5 808 if (HwDeviceExtension->jChipType >= XG20) {
672f5ee2
PH		 809 dram_table = XGINew_DDRDRAM_TYPE20;
810 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
811 start_addr = 5;
b9ebf5e5 812 } else {
672f5ee2
PH		 813 dram_table = XGINew_DDRDRAM_TYPE340;
814 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
815 start_addr = 9;
816 }
817
818 for (i = 0; i < size; i++) {
4e55d0b3 819 /* SetDRAMSizingType */
d6461e49 820 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
4e55d0b3
PH		 821 udelay(15); /* should delay 50 ns */
822
d6461e49 823 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
672f5ee2
PH		 824
825 if (memsize == 0)
826 continue;
827
828 memsize += (pVBInfo->ram_channel - 2) + 20;
829 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
830 (unsigned long) (1 << memsize))
831 continue;
832
833 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
834 return 1;
a24d60f4 835 }
b9ebf5e5 836 return 0;
a24d60f4 837}
d7636e0b 838
fab04b97
AK		 839static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
840 struct xgi_hw_device_info *HwDeviceExtension,
a24d60f4 841 struct vb_device_info *pVBInfo)
d7636e0b 842{
b9ebf5e5 843 unsigned short data;
a24d60f4 844
b9ebf5e5 845 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 846
fab04b97 847 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
a24d60f4 848
58839b01 849 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9
KT		 850 /* disable read cache */
851 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
fab04b97 852 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
a24d60f4 853
b9ebf5e5 854 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
58839b01 855 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
bf32fcb9
KT		 856 /* enable read cache */
857 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
b9ebf5e5 858}
a24d60f4 859
08ce239c 860static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
02a81dd9
AK		 861{
862 void __iomem *rom_address;
82986dd9 863 u8 *rom_copy;
02a81dd9 864
08ce239c 865 rom_address = pci_map_rom(dev, rom_size);
02a81dd9
AK		 866 if (rom_address == NULL)
867 return NULL;
868
869 rom_copy = vzalloc(XGIFB_ROM_SIZE);
870 if (rom_copy == NULL)
871 goto done;
872
08ce239c
AK		 873 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
874 memcpy_fromio(rom_copy, rom_address, *rom_size);
02a81dd9
AK		 875
876done:
877 pci_unmap_rom(dev, rom_address);
878 return rom_copy;
879}
880
c0d60da8 881static bool xgifb_read_vbios(struct pci_dev *pdev,
bf32fcb9 882 struct vb_device_info *pVBInfo)
b9ebf5e5 883{
02a81dd9 884 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
82986dd9 885 u8 *vbios;
b9ebf5e5 886 unsigned long i;
d1805b38 887 unsigned char j;
97f4532d 888 struct XGI21_LVDSCapStruct *lvds;
08ce239c 889 size_t vbios_size;
d1805b38 890 int entry;
a24d60f4 891
08ce239c 892 vbios = xgifb_copy_rom(pdev, &vbios_size);
02a81dd9 893 if (vbios == NULL) {
be25aef0 894 dev_err(&pdev->dev, "Video BIOS not available\n");
c0d60da8 895 return false;
02a81dd9 896 }
08ce239c
AK		 897 if (vbios_size <= 0x65)
898 goto error;
25aa75f1
AK		 899 /*
900 * The user can ignore the LVDS bit in the BIOS and force the display
901 * type.
902 */
903 if (!(vbios[0x65] & 0x1) &&
904 (!xgifb_info->display2_force ||
905 xgifb_info->display2 != XGIFB_DISP_LCD)) {
02a81dd9 906 vfree(vbios);
c0d60da8 907 return false;
02a81dd9 908 }
08ce239c
AK		 909 if (vbios_size <= 0x317)
910 goto error;
4b21d990 911 i = vbios[0x316] | (vbios[0x317] << 8);
08ce239c
AK		 912 if (vbios_size <= i - 1)
913 goto error;
4b21d990 914 j = vbios[i - 1];
08ce239c
AK		 915 if (j == 0)
916 goto error;
bd761274
AK		 917 if (j == 0xff)
918 j = 1;
d1805b38
AK		 919 /*
920 * Read the LVDS table index scratch register set by the BIOS.
921 */
922 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
923 if (entry >= j)
924 entry = 0;
925 i += entry * 25;
fab04b97 926 lvds = &xgifb_info->lvds_data;
d1805b38
AK		 927 if (vbios_size <= i + 24)
928 goto error;
929 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
930 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
931 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
932 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
933 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
934 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
935 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
936 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
937 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
938 lvds->VCLKData1 = vbios[i + 18];
939 lvds->VCLKData2 = vbios[i + 19];
940 lvds->PSC_S1 = vbios[i + 20];
941 lvds->PSC_S2 = vbios[i + 21];
942 lvds->PSC_S3 = vbios[i + 22];
943 lvds->PSC_S4 = vbios[i + 23];
944 lvds->PSC_S5 = vbios[i + 24];
02a81dd9 945 vfree(vbios);
c0d60da8 946 return true;
08ce239c 947error:
be25aef0 948 dev_err(&pdev->dev, "Video BIOS corrupted\n");
08ce239c 949 vfree(vbios);
c0d60da8 950 return false;
b9ebf5e5 951}
a24d60f4 952
b9ebf5e5
AK		 953static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
954 struct vb_device_info *pVBInfo)
955{
956 unsigned short tempbx = 0, temp, tempcx, CR3CData;
a24d60f4 957
58839b01 958 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
a24d60f4 959
b9ebf5e5
AK		 960 if (temp & Monitor1Sense)
961 tempbx |= ActiveCRT1;
962 if (temp & LCDSense)
963 tempbx |= ActiveLCD;
964 if (temp & Monitor2Sense)
965 tempbx |= ActiveCRT2;
966 if (temp & TVSense) {
967 tempbx |= ActiveTV;
968 if (temp & AVIDEOSense)
969 tempbx |= (ActiveAVideo << 8);
970 if (temp & SVIDEOSense)
971 tempbx |= (ActiveSVideo << 8);
972 if (temp & SCARTSense)
973 tempbx |= (ActiveSCART << 8);
974 if (temp & HiTVSense)
975 tempbx |= (ActiveHiTV << 8);
976 if (temp & YPbPrSense)
977 tempbx |= (ActiveYPbPr << 8);
978 }
a24d60f4 979
58839b01
AK		 980 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
981 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
a24d60f4 982
b9ebf5e5 983 if (tempbx & tempcx) {
58839b01 984 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
3bcc2460 985 if (!(CR3CData & DisplayDeviceFromCMOS))
b9ebf5e5 986 tempcx = 0x1FF0;
b9ebf5e5
AK		 987 } else {
988 tempcx = 0x1FF0;
b9ebf5e5 989 }
a24d60f4 990
b9ebf5e5 991 tempbx &= tempcx;
8104e329
AK		 992 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
993 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
b9ebf5e5 994}
d7636e0b 995
b9ebf5e5
AK		 996static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
997 struct vb_device_info *pVBInfo)
998{
999 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
d7636e0b 1000
58839b01
AK		 1001 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1002 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1003 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
d7636e0b 1004
b9ebf5e5
AK		 1005 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1006 if (temp & ActiveCRT2)
1007 tempcl = SetCRT2ToRAMDAC;
1008 }
d7636e0b 1009
b9ebf5e5
AK		 1010 if (temp & ActiveLCD) {
1011 tempcl |= SetCRT2ToLCD;
1012 if (temp & DriverMode) {
1013 if (temp & ActiveTV) {
1014 tempch = SetToLCDA | EnableDualEdge;
1015 temp ^= SetCRT2ToLCD;
d7636e0b 1016
b9ebf5e5
AK		 1017 if ((temp >> 8) & ActiveAVideo)
1018 tempcl |= SetCRT2ToAVIDEO;
1019 if ((temp >> 8) & ActiveSVideo)
1020 tempcl |= SetCRT2ToSVIDEO;
1021 if ((temp >> 8) & ActiveSCART)
1022 tempcl |= SetCRT2ToSCART;
a24d60f4 1023
b9ebf5e5
AK		 1024 if (pVBInfo->IF_DEF_HiVision == 1) {
1025 if ((temp >> 8) & ActiveHiTV)
599801f9 1026 tempcl |= SetCRT2ToHiVision;
b9ebf5e5 1027 }
a24d60f4 1028
b9ebf5e5
AK		 1029 if (pVBInfo->IF_DEF_YPbPr == 1) {
1030 if ((temp >> 8) & ActiveYPbPr)
1031 tempch |= SetYPbPr;
1032 }
1033 }
1034 }
1035 } else {
1036 if ((temp >> 8) & ActiveAVideo)
1037 tempcl |= SetCRT2ToAVIDEO;
1038 if ((temp >> 8) & ActiveSVideo)
1039 tempcl |= SetCRT2ToSVIDEO;
1040 if ((temp >> 8) & ActiveSCART)
1041 tempcl |= SetCRT2ToSCART;
a24d60f4 1042
b9ebf5e5
AK		 1043 if (pVBInfo->IF_DEF_HiVision == 1) {
1044 if ((temp >> 8) & ActiveHiTV)
599801f9 1045 tempcl |= SetCRT2ToHiVision;
b9ebf5e5 1046 }
a24d60f4 1047
b9ebf5e5
AK		 1048 if (pVBInfo->IF_DEF_YPbPr == 1) {
1049 if ((temp >> 8) & ActiveYPbPr)
1050 tempch |= SetYPbPr;
1051 }
1052 }
d7636e0b 1053
b9ebf5e5
AK		 1054 tempcl |= SetSimuScanMode;
1055 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1056 || (temp & ActiveCRT2)))
6896b94e 1057 tempcl ^= (SetSimuScanMode | SwitchCRT2);
b9ebf5e5 1058 if ((temp & ActiveLCD) && (temp & ActiveTV))
6896b94e 1059 tempcl ^= (SetSimuScanMode | SwitchCRT2);
8104e329 1060 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
d7636e0b 1061
58839b01 1062 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
b9ebf5e5
AK		 1063 CR31Data &= ~(SetNotSimuMode >> 8);
1064 if (!(temp & ActiveCRT1))
1065 CR31Data |= (SetNotSimuMode >> 8);
1066 CR31Data &= ~(DisableCRT2Display >> 8);
1067 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1068 CR31Data |= (DisableCRT2Display >> 8);
8104e329 1069 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
d7636e0b 1070
58839b01 1071 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1072 CR38Data &= ~SetYPbPr;
1073 CR38Data |= tempch;
8104e329 1074 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
d7636e0b 1075
b9ebf5e5 1076}
a24d60f4 1077
40544b04
AK		 1078static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1079 *HwDeviceExtension,
1080 struct vb_device_info *pVBInfo)
1081{
1082 unsigned short temp;
1083
1084 /* add lcd sense */
1085 if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1086 return 0;
1087 } else {
1088 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1089 switch (HwDeviceExtension->ulCRT2LCDType) {
1090 case LCD_INVALID:
1091 case LCD_800x600:
1092 case LCD_1024x768:
1093 case LCD_1280x1024:
1094 break;
1095
1096 case LCD_640x480:
1097 case LCD_1024x600:
1098 case LCD_1152x864:
1099 case LCD_1280x960:
1100 case LCD_1152x768:
1101 temp = 0;
1102 break;
1103
1104 case LCD_1400x1050:
1105 case LCD_1280x768:
1106 case LCD_1600x1200:
1107 break;
1108
1109 case LCD_1920x1440:
1110 case LCD_2048x1536:
1111 temp = 0;
1112 break;
1113
1114 default:
1115 break;
1116 }
1117 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1118 return 1;
1119 }
1120}
1121
c0d60da8 1122static void XGINew_GetXG21Sense(struct pci_dev *pdev,
b9ebf5e5
AK		 1123 struct vb_device_info *pVBInfo)
1124{
c0d60da8 1125 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
b9ebf5e5 1126 unsigned char Temp;
a24d60f4 1127
c0d60da8 1128 if (xgifb_read_vbios(pdev, pVBInfo)) { /* For XG21 LVDS */
b9bf6e4e 1129 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1130 /* LVDS on chip */
1131 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
b9ebf5e5 1132 } else {
bf32fcb9
KT		 1133 /* Enable GPIOA/B read */
1134 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1135 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
b9ebf5e5 1136 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
c0d60da8 1137 XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
b9bf6e4e 1138 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
bf32fcb9
KT		 1139 /* Enable read GPIOF */
1140 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
58839b01 1141 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
b9ebf5e5 1142 if (!Temp)
bf32fcb9
KT		 1143 xgifb_reg_and_or(pVBInfo->P3d4,
1144 0x38,
1145 ~0xE0,
1146 0x80); /* TMDS on chip */
a24d60f4 1147 else
bf32fcb9
KT		 1148 xgifb_reg_and_or(pVBInfo->P3d4,
1149 0x38,
1150 ~0xE0,
1151 0xA0); /* Only DVO on chip */
1152 /* Disable read GPIOF */
1153 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
a24d60f4 1154 }
b9ebf5e5 1155 }
b9ebf5e5 1156}
a24d60f4 1157
b9ebf5e5
AK		 1158static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1159 struct vb_device_info *pVBInfo)
1160{
1161 unsigned char Temp, bCR4A;
a24d60f4 1162
58839b01 1163 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1164 /* Enable GPIOA/B/C read */
1165 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
58839b01 1166 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
8104e329 1167 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
a24d60f4 1168
b9ebf5e5 1169 if (Temp <= 0x02) {
bf32fcb9
KT		 1170 /* LVDS setting */
1171 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
8104e329 1172 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
b9ebf5e5 1173 } else {
bf32fcb9
KT		 1174 /* TMDS/DVO setting */
1175 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
b9ebf5e5 1176 }
b9bf6e4e 1177 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
a24d60f4 1178
b9ebf5e5 1179}
a24d60f4 1180
b9ebf5e5
AK		 1181static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1182{
1183 unsigned char CR38, CR4A, temp;
a24d60f4 1184
58839b01 1185 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1186 /* enable GPIOE read */
1187 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
58839b01 1188 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
b9ebf5e5
AK		 1189 temp = 0;
1190 if ((CR38 & 0xE0) > 0x80) {
58839b01 1191 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5
AK		 1192 temp &= 0x08;
1193 temp >>= 3;
1194 }
a24d60f4 1195
8104e329 1196 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1197
b9ebf5e5
AK		 1198 return temp;
1199}
a24d60f4 1200
b9ebf5e5
AK		 1201static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1202{
1203 unsigned char CR4A, temp;
a24d60f4 1204
58839b01 1205 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
bf32fcb9
KT		 1206 /* enable GPIOA/B/C read */
1207 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
58839b01 1208 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
b9ebf5e5
AK		 1209 if (temp <= 2)
1210 temp &= 0x03;
1211 else
2f123cbc 1212 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
a24d60f4 1213
8104e329 1214 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
a24d60f4 1215
b9ebf5e5
AK		 1216 return temp;
1217}
a24d60f4 1218
6048d761 1219unsigned char XGIInitNew(struct pci_dev *pdev)
b9ebf5e5 1220{
ab886ff8 1221 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
6048d761 1222 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
b9ebf5e5
AK		 1223 struct vb_device_info VBINF;
1224 struct vb_device_info *pVBInfo = &VBINF;
1225 unsigned char i, temp = 0, temp1;
a24d60f4 1226
b9ebf5e5 1227 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
a24d60f4 1228
b9ebf5e5 1229 if (pVBInfo->FBAddr == NULL) {
19185703 1230 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
b9ebf5e5
AK		 1231 return 0;
1232 }
a24d60f4 1233
56810a92 1234 XGIRegInit(pVBInfo, xgifb_info->vga_base);
d7636e0b 1235
b8e1cc5c
AK		 1236 outb(0x67, pVBInfo->P3c2);
1237
949eb0ae 1238 if (HwDeviceExtension->jChipType < XG20)
bf32fcb9
KT		 1239 /* Run XGI_GetVBType before InitTo330Pointer */
1240 XGI_GetVBType(pVBInfo);
a24d60f4 1241
b9ebf5e5
AK		 1242 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1243
949eb0ae 1244 /* Openkey */
8104e329 1245 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
b9ebf5e5
AK		 1246
1247 /* GetXG21Sense (GPIO) */
1248 if (HwDeviceExtension->jChipType == XG21)
c0d60da8 1249 XGINew_GetXG21Sense(pdev, pVBInfo);
b9ebf5e5
AK		 1250
1251 if (HwDeviceExtension->jChipType == XG27)
1252 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1253
949eb0ae 1254 /* Reset Extended register */
b9ebf5e5
AK		 1255
1256 for (i = 0x06; i < 0x20; i++)
8104e329 1257 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5
AK		 1258
1259 for (i = 0x21; i <= 0x27; i++)
8104e329 1260 xgifb_reg_set(pVBInfo->P3c4, i, 0);
b9ebf5e5 1261
06587335 1262 for (i = 0x31; i <= 0x3B; i++)
8104e329 1263 xgifb_reg_set(pVBInfo->P3c4, i, 0);
d7636e0b 1264
949eb0ae 1265 /* Auto over driver for XG42 */
bf32fcb9 1266 if (HwDeviceExtension->jChipType == XG42)
8104e329 1267 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
d7636e0b 1268
b9ebf5e5 1269 for (i = 0x79; i <= 0x7C; i++)
949eb0ae 1270 xgifb_reg_set(pVBInfo->P3d4, i, 0);
d7636e0b 1271
b9ebf5e5 1272 if (HwDeviceExtension->jChipType >= XG20)
6d12dae4 1273 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
a24d60f4 1274
949eb0ae 1275 /* SetDefExt1Regs begin */
6d12dae4 1276 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
b9ebf5e5 1277 if (HwDeviceExtension->jChipType == XG27) {
6d12dae4
PH		 1278 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1279 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
a24d60f4 1280 }
8104e329 1281 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
6d12dae4 1282 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
949eb0ae 1283 /* Frame buffer can read/write SR20 */
bf32fcb9 1284 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
949eb0ae 1285 /* H/W request for slow corner chip */
bf32fcb9 1286 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
949eb0ae 1287 if (HwDeviceExtension->jChipType == XG27)
6d12dae4 1288 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
a24d60f4 1289
949eb0ae 1290 if (HwDeviceExtension->jChipType < XG20) {
6048d761
AK		 1291 u32 Temp;
1292
06587335
AK		 1293 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1294 for (i = 0x47; i <= 0x4C; i++)
bf32fcb9
KT		 1295 xgifb_reg_set(pVBInfo->P3d4,
1296 i,
ea12b4e0 1297 XGI340_AGPReg[i - 0x47]);
06587335
AK		 1298
1299 for (i = 0x70; i <= 0x71; i++)
bf32fcb9
KT		 1300 xgifb_reg_set(pVBInfo->P3d4,
1301 i,
ea12b4e0 1302 XGI340_AGPReg[6 + i - 0x70]);
06587335
AK		 1303
1304 for (i = 0x74; i <= 0x77; i++)
bf32fcb9
KT		 1305 xgifb_reg_set(pVBInfo->P3d4,
1306 i,
ea12b4e0 1307 XGI340_AGPReg[8 + i - 0x74]);
06587335 1308
6048d761 1309 pci_read_config_dword(pdev, 0x50, &Temp);
06587335
AK		 1310 Temp >>= 20;
1311 Temp &= 0xF;
1312
1313 if (Temp == 1)
8104e329 1314 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
b9ebf5e5 1315 } /* != XG20 */
a24d60f4 1316
b9ebf5e5 1317 /* Set PCI */
6d12dae4
PH		 1318 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1319 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
38c09652 1320 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
a24d60f4 1321
949eb0ae 1322 if (HwDeviceExtension->jChipType < XG20) {
b9ebf5e5
AK		 1323 /* Set VB */
1324 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
949eb0ae 1325 /* disable VideoCapture */
bf32fcb9 1326 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
8104e329 1327 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
bf32fcb9 1328 /* chk if BCLK>=100MHz */
9388ad9c 1329 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
b9ebf5e5 1330 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
a24d60f4 1331
bf32fcb9 1332 xgifb_reg_set(pVBInfo->Part1Port,
6d12dae4 1333 0x02, XGI330_CRT2Data_1_2);
a24d60f4 1334
8104e329 1335 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
b9ebf5e5 1336 } /* != XG20 */
a24d60f4 1337
8104e329 1338 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
b9ebf5e5 1339
bf32fcb9
KT		 1340 if ((HwDeviceExtension->jChipType == XG42) &&
1341 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1342 /* Not DDR */
1343 xgifb_reg_set(pVBInfo->P3c4,
1344 0x31,
6d12dae4 1345 (XGI330_SR31 & 0x3F) | 0x40);
bf32fcb9
KT		 1346 xgifb_reg_set(pVBInfo->P3c4,
1347 0x32,
6d12dae4 1348 (XGI330_SR32 & 0xFC) | 0x01);
a24d60f4 1349 } else {
6d12dae4
PH		 1350 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1351 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
b9ebf5e5 1352 }
6d12dae4 1353 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
a24d60f4 1354
949eb0ae 1355 if (HwDeviceExtension->jChipType < XG20) {
b9ebf5e5 1356 if (XGI_BridgeIsOn(pVBInfo) == 1) {
6bc54277
AK		 1357 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1358 xgifb_reg_set(pVBInfo->Part4Port,
1359 0x0D, XGI330_CRT2Data_4_D);
1360 xgifb_reg_set(pVBInfo->Part4Port,
1361 0x0E, XGI330_CRT2Data_4_E);
1362 xgifb_reg_set(pVBInfo->Part4Port,
1363 0x10, XGI330_CRT2Data_4_10);
1364 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
b9ebf5e5 1365 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
a24d60f4 1366 }
b9ebf5e5 1367 } /* != XG20 */
a24d60f4 1368
b9ebf5e5 1369 XGI_SenseCRT1(pVBInfo);
d7636e0b 1370
b9ebf5e5 1371 if (HwDeviceExtension->jChipType == XG21) {
d7636e0b 1372
bf32fcb9
KT		 1373 xgifb_reg_and_or(pVBInfo->P3d4,
1374 0x32,
1375 ~Monitor1Sense,
1376 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1377 temp = GetXG21FPBits(pVBInfo);
ec9e5d3e 1378 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
d7636e0b 1379
a24d60f4 1380 }
b9ebf5e5 1381 if (HwDeviceExtension->jChipType == XG27) {
bf32fcb9
KT		 1382 xgifb_reg_and_or(pVBInfo->P3d4,
1383 0x32,
1384 ~Monitor1Sense,
1385 Monitor1Sense); /* Z9 default has CRT */
b9ebf5e5 1386 temp = GetXG27FPBits(pVBInfo);
ec9e5d3e 1387 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
b9ebf5e5 1388 }
d7636e0b 1389
2af1a29d 1390 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
d7636e0b 1391
bf32fcb9
KT		 1392 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1393 pVBInfo->P3d4,
1394 pVBInfo);
a24d60f4 1395
fab04b97 1396 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
d7636e0b 1397
38c09652
AK		 1398 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1399 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
d7636e0b 1400
b9ebf5e5
AK		 1401 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1402 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
a24d60f4 1403
8104e329 1404 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
d7636e0b 1405
b9ebf5e5
AK		 1406 return 1;
1407} /* end of init */
Linux kernel - Deliverables
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