projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Thermal: Dove: Add Themal sensor support for Dove.
[deliverable/linux.git] / drivers / thermal / exynos_thermal.c
CommitLineData
9d97e5c8 1/*
c48cbba6 2 * exynos_thermal.c - Samsung EXYNOS TMU (Thermal Management Unit)
9d97e5c8
DK		 3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
c48cbba6 6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
9d97e5c8
DK		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/err.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/workqueue.h>
32#include <linux/sysfs.h>
33#include <linux/kobject.h>
34#include <linux/io.h>
35#include <linux/mutex.h>
c48cbba6 36#include <linux/platform_data/exynos_thermal.h>
7e0b55e6
ADK		 37#include <linux/thermal.h>
38#include <linux/cpufreq.h>
39#include <linux/cpu_cooling.h>
f22d9c03
ADK		 40#include <linux/of.h>
41
42#include <plat/cpu.h>
43
44/* Exynos generic registers */
45#define EXYNOS_TMU_REG_TRIMINFO 0x0
46#define EXYNOS_TMU_REG_CONTROL 0x20
47#define EXYNOS_TMU_REG_STATUS 0x28
48#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
49#define EXYNOS_TMU_REG_INTEN 0x70
50#define EXYNOS_TMU_REG_INTSTAT 0x74
51#define EXYNOS_TMU_REG_INTCLEAR 0x78
52
53#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
54#define EXYNOS_TMU_GAIN_SHIFT 8
55#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
56#define EXYNOS_TMU_CORE_ON 3
57#define EXYNOS_TMU_CORE_OFF 2
58#define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
59
60/* Exynos4210 specific registers */
61#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
62#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
63#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
64#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
65#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
66#define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
67#define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
68#define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
69#define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
70
71#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
72#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
73#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
74#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
75#define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
76
77/* Exynos5250 and Exynos4412 specific registers */
78#define EXYNOS_TMU_TRIMINFO_CON 0x14
79#define EXYNOS_THD_TEMP_RISE 0x50
80#define EXYNOS_THD_TEMP_FALL 0x54
81#define EXYNOS_EMUL_CON 0x80
82
83#define EXYNOS_TRIMINFO_RELOAD 0x1
84#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
3ad9524a 85#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
f22d9c03
ADK		 86#define EXYNOS_MUX_ADDR_VALUE 6
87#define EXYNOS_MUX_ADDR_SHIFT 20
88#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
89
90#define EFUSE_MIN_VALUE 40
91#define EFUSE_MAX_VALUE 100
92
93/* In-kernel thermal framework related macros & definations */
94#define SENSOR_NAME_LEN 16
95#define MAX_TRIP_COUNT 8
96#define MAX_COOLING_DEVICE 4
97
98#define ACTIVE_INTERVAL 500
99#define IDLE_INTERVAL 10000
7e0b55e6 100#define MCELSIUS 1000
f22d9c03 101
bbf63be4
JL		 102#ifdef CONFIG_EXYNOS_THERMAL_EMUL
103#define EXYNOS_EMUL_TIME 0x57F0
104#define EXYNOS_EMUL_TIME_SHIFT 16
105#define EXYNOS_EMUL_DATA_SHIFT 8
106#define EXYNOS_EMUL_DATA_MASK 0xFF
107#define EXYNOS_EMUL_ENABLE 0x1
108#endif /* CONFIG_EXYNOS_THERMAL_EMUL */
109
f22d9c03
ADK		 110/* CPU Zone information */
111#define PANIC_ZONE 4
112#define WARN_ZONE 3
113#define MONITOR_ZONE 2
114#define SAFE_ZONE 1
115
116#define GET_ZONE(trip) (trip + 2)
117#define GET_TRIP(zone) (zone - 2)
118
7e0b55e6
ADK		 119#define EXYNOS_ZONE_COUNT 3
120
f22d9c03
ADK		 121struct exynos_tmu_data {
122 struct exynos_tmu_platform_data *pdata;
9d97e5c8
DK		 123 struct resource *mem;
124 void __iomem *base;
125 int irq;
f22d9c03 126 enum soc_type soc;
9d97e5c8
DK		 127 struct work_struct irq_work;
128 struct mutex lock;
129 struct clk *clk;
130 u8 temp_error1, temp_error2;
131};
132
7e0b55e6
ADK		 133struct thermal_trip_point_conf {
134 int trip_val[MAX_TRIP_COUNT];
135 int trip_count;
136};
137
138struct thermal_cooling_conf {
139 struct freq_clip_table freq_data[MAX_TRIP_COUNT];
140 int freq_clip_count;
141};
142
143struct thermal_sensor_conf {
144 char name[SENSOR_NAME_LEN];
145 int (*read_temperature)(void *data);
146 struct thermal_trip_point_conf trip_data;
147 struct thermal_cooling_conf cooling_data;
148 void *private_data;
149};
150
151struct exynos_thermal_zone {
152 enum thermal_device_mode mode;
153 struct thermal_zone_device *therm_dev;
154 struct thermal_cooling_device *cool_dev[MAX_COOLING_DEVICE];
155 unsigned int cool_dev_size;
156 struct platform_device *exynos4_dev;
157 struct thermal_sensor_conf *sensor_conf;
158 bool bind;
159};
160
161static struct exynos_thermal_zone *th_zone;
162static void exynos_unregister_thermal(void);
163static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf);
164
165/* Get mode callback functions for thermal zone */
166static int exynos_get_mode(struct thermal_zone_device *thermal,
167 enum thermal_device_mode *mode)
168{
169 if (th_zone)
170 *mode = th_zone->mode;
171 return 0;
172}
173
174/* Set mode callback functions for thermal zone */
175static int exynos_set_mode(struct thermal_zone_device *thermal,
176 enum thermal_device_mode mode)
177{
178 if (!th_zone->therm_dev) {
179 pr_notice("thermal zone not registered\n");
180 return 0;
181 }
182
183 mutex_lock(&th_zone->therm_dev->lock);
184
185 if (mode == THERMAL_DEVICE_ENABLED)
186 th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
187 else
188 th_zone->therm_dev->polling_delay = 0;
189
190 mutex_unlock(&th_zone->therm_dev->lock);
191
192 th_zone->mode = mode;
193 thermal_zone_device_update(th_zone->therm_dev);
194 pr_info("thermal polling set for duration=%d msec\n",
195 th_zone->therm_dev->polling_delay);
196 return 0;
197}
198
199
200/* Get trip type callback functions for thermal zone */
201static int exynos_get_trip_type(struct thermal_zone_device *thermal, int trip,
202 enum thermal_trip_type *type)
203{
204 switch (GET_ZONE(trip)) {
205 case MONITOR_ZONE:
206 case WARN_ZONE:
207 *type = THERMAL_TRIP_ACTIVE;
208 break;
209 case PANIC_ZONE:
210 *type = THERMAL_TRIP_CRITICAL;
211 break;
212 default:
213 return -EINVAL;
214 }
215 return 0;
216}
217
218/* Get trip temperature callback functions for thermal zone */
219static int exynos_get_trip_temp(struct thermal_zone_device *thermal, int trip,
220 unsigned long *temp)
221{
222 if (trip < GET_TRIP(MONITOR_ZONE) || trip > GET_TRIP(PANIC_ZONE))
223 return -EINVAL;
224
225 *temp = th_zone->sensor_conf->trip_data.trip_val[trip];
226 /* convert the temperature into millicelsius */
227 *temp = *temp * MCELSIUS;
228
229 return 0;
230}
231
232/* Get critical temperature callback functions for thermal zone */
233static int exynos_get_crit_temp(struct thermal_zone_device *thermal,
234 unsigned long *temp)
235{
236 int ret;
237 /* Panic zone */
238 ret = exynos_get_trip_temp(thermal, GET_TRIP(PANIC_ZONE), temp);
239 return ret;
240}
241
242static int exynos_get_frequency_level(unsigned int cpu, unsigned int freq)
243{
244 int i = 0, ret = -EINVAL;
245 struct cpufreq_frequency_table *table = NULL;
246#ifdef CONFIG_CPU_FREQ
247 table = cpufreq_frequency_get_table(cpu);
248#endif
249 if (!table)
250 return ret;
251
252 while (table[i].frequency != CPUFREQ_TABLE_END) {
253 if (table[i].frequency == CPUFREQ_ENTRY_INVALID)
254 continue;
255 if (table[i].frequency == freq)
256 return i;
257 i++;
258 }
259 return ret;
260}
261
262/* Bind callback functions for thermal zone */
263static int exynos_bind(struct thermal_zone_device *thermal,
264 struct thermal_cooling_device *cdev)
265{
266 int ret = 0, i, tab_size, level;
267 struct freq_clip_table *tab_ptr, *clip_data;
268 struct thermal_sensor_conf *data = th_zone->sensor_conf;
269
270 tab_ptr = (struct freq_clip_table *)data->cooling_data.freq_data;
271 tab_size = data->cooling_data.freq_clip_count;
272
273 if (tab_ptr == NULL || tab_size == 0)
274 return -EINVAL;
275
276 /* find the cooling device registered*/
277 for (i = 0; i < th_zone->cool_dev_size; i++)
278 if (cdev == th_zone->cool_dev[i])
279 break;
280
281 /* No matching cooling device */
282 if (i == th_zone->cool_dev_size)
283 return 0;
284
285 /* Bind the thermal zone to the cpufreq cooling device */
286 for (i = 0; i < tab_size; i++) {
287 clip_data = (struct freq_clip_table *)&(tab_ptr[i]);
288 level = exynos_get_frequency_level(0, clip_data->freq_clip_max);
289 if (level < 0)
290 return 0;
291 switch (GET_ZONE(i)) {
292 case MONITOR_ZONE:
293 case WARN_ZONE:
294 if (thermal_zone_bind_cooling_device(thermal, i, cdev,
295 level, level)) {
296 pr_err("error binding cdev inst %d\n", i);
297 ret = -EINVAL;
298 }
299 th_zone->bind = true;
300 break;
301 default:
302 ret = -EINVAL;
303 }
304 }
305
306 return ret;
307}
308
309/* Unbind callback functions for thermal zone */
310static int exynos_unbind(struct thermal_zone_device *thermal,
311 struct thermal_cooling_device *cdev)
312{
313 int ret = 0, i, tab_size;
314 struct thermal_sensor_conf *data = th_zone->sensor_conf;
315
316 if (th_zone->bind == false)
317 return 0;
318
319 tab_size = data->cooling_data.freq_clip_count;
320
321 if (tab_size == 0)
322 return -EINVAL;
323
324 /* find the cooling device registered*/
325 for (i = 0; i < th_zone->cool_dev_size; i++)
326 if (cdev == th_zone->cool_dev[i])
327 break;
328
329 /* No matching cooling device */
330 if (i == th_zone->cool_dev_size)
331 return 0;
332
333 /* Bind the thermal zone to the cpufreq cooling device */
334 for (i = 0; i < tab_size; i++) {
335 switch (GET_ZONE(i)) {
336 case MONITOR_ZONE:
337 case WARN_ZONE:
338 if (thermal_zone_unbind_cooling_device(thermal, i,
339 cdev)) {
340 pr_err("error unbinding cdev inst=%d\n", i);
341 ret = -EINVAL;
342 }
343 th_zone->bind = false;
344 break;
345 default:
346 ret = -EINVAL;
347 }
348 }
349 return ret;
350}
351
352/* Get temperature callback functions for thermal zone */
353static int exynos_get_temp(struct thermal_zone_device *thermal,
354 unsigned long *temp)
355{
356 void *data;
357
358 if (!th_zone->sensor_conf) {
359 pr_info("Temperature sensor not initialised\n");
360 return -EINVAL;
361 }
362 data = th_zone->sensor_conf->private_data;
363 *temp = th_zone->sensor_conf->read_temperature(data);
364 /* convert the temperature into millicelsius */
365 *temp = *temp * MCELSIUS;
366 return 0;
367}
368
369/* Get the temperature trend */
370static int exynos_get_trend(struct thermal_zone_device *thermal,
371 int trip, enum thermal_trend *trend)
372{
3ad9524a
ADK		 373 int ret;
374 unsigned long trip_temp;
375
376 ret = exynos_get_trip_temp(thermal, trip, &trip_temp);
377 if (ret < 0)
378 return ret;
379
380 if (thermal->temperature >= trip_temp)
7e0b55e6
ADK		 381 *trend = THERMAL_TREND_RAISING;
382 else
383 *trend = THERMAL_TREND_DROPPING;
384
385 return 0;
386}
387/* Operation callback functions for thermal zone */
388static struct thermal_zone_device_ops const exynos_dev_ops = {
389 .bind = exynos_bind,
390 .unbind = exynos_unbind,
391 .get_temp = exynos_get_temp,
392 .get_trend = exynos_get_trend,
393 .get_mode = exynos_get_mode,
394 .set_mode = exynos_set_mode,
395 .get_trip_type = exynos_get_trip_type,
396 .get_trip_temp = exynos_get_trip_temp,
397 .get_crit_temp = exynos_get_crit_temp,
398};
399
400/*
401 * This function may be called from interrupt based temperature sensor
402 * when threshold is changed.
403 */
404static void exynos_report_trigger(void)
405{
406 unsigned int i;
407 char data[10];
408 char *envp[] = { data, NULL };
409
410 if (!th_zone || !th_zone->therm_dev)
411 return;
412 if (th_zone->bind == false) {
413 for (i = 0; i < th_zone->cool_dev_size; i++) {
414 if (!th_zone->cool_dev[i])
415 continue;
416 exynos_bind(th_zone->therm_dev,
417 th_zone->cool_dev[i]);
418 }
419 }
420
421 thermal_zone_device_update(th_zone->therm_dev);
422
423 mutex_lock(&th_zone->therm_dev->lock);
424 /* Find the level for which trip happened */
425 for (i = 0; i < th_zone->sensor_conf->trip_data.trip_count; i++) {
426 if (th_zone->therm_dev->last_temperature <
427 th_zone->sensor_conf->trip_data.trip_val[i] * MCELSIUS)
428 break;
429 }
430
431 if (th_zone->mode == THERMAL_DEVICE_ENABLED) {
432 if (i > 0)
433 th_zone->therm_dev->polling_delay = ACTIVE_INTERVAL;
434 else
435 th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
436 }
437
438 snprintf(data, sizeof(data), "%u", i);
439 kobject_uevent_env(&th_zone->therm_dev->device.kobj, KOBJ_CHANGE, envp);
440 mutex_unlock(&th_zone->therm_dev->lock);
441}
442
443/* Register with the in-kernel thermal management */
444static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf)
445{
446 int ret;
447 struct cpumask mask_val;
448
449 if (!sensor_conf || !sensor_conf->read_temperature) {
450 pr_err("Temperature sensor not initialised\n");
451 return -EINVAL;
452 }
453
454 th_zone = kzalloc(sizeof(struct exynos_thermal_zone), GFP_KERNEL);
455 if (!th_zone)
456 return -ENOMEM;
457
458 th_zone->sensor_conf = sensor_conf;
459 cpumask_set_cpu(0, &mask_val);
460 th_zone->cool_dev[0] = cpufreq_cooling_register(&mask_val);
461 if (IS_ERR(th_zone->cool_dev[0])) {
462 pr_err("Failed to register cpufreq cooling device\n");
463 ret = -EINVAL;
464 goto err_unregister;
465 }
466 th_zone->cool_dev_size++;
467
468 th_zone->therm_dev = thermal_zone_device_register(sensor_conf->name,
50125a9b 469 EXYNOS_ZONE_COUNT, 0, NULL, &exynos_dev_ops, NULL, 0,
7e0b55e6
ADK		 470 IDLE_INTERVAL);
471
472 if (IS_ERR(th_zone->therm_dev)) {
473 pr_err("Failed to register thermal zone device\n");
474 ret = -EINVAL;
475 goto err_unregister;
476 }
477 th_zone->mode = THERMAL_DEVICE_ENABLED;
478
479 pr_info("Exynos: Kernel Thermal management registered\n");
480
481 return 0;
482
483err_unregister:
484 exynos_unregister_thermal();
485 return ret;
486}
487
488/* Un-Register with the in-kernel thermal management */
489static void exynos_unregister_thermal(void)
490{
491 int i;
492
c072fed9
SK		 493 if (!th_zone)
494 return;
495
496 if (th_zone->therm_dev)
7e0b55e6
ADK		 497 thermal_zone_device_unregister(th_zone->therm_dev);
498
499 for (i = 0; i < th_zone->cool_dev_size; i++) {
c072fed9 500 if (th_zone->cool_dev[i])
7e0b55e6
ADK		 501 cpufreq_cooling_unregister(th_zone->cool_dev[i]);
502 }
503
504 kfree(th_zone);
505 pr_info("Exynos: Kernel Thermal management unregistered\n");
506}
507
9d97e5c8
DK		 508/*
509 * TMU treats temperature as a mapped temperature code.
510 * The temperature is converted differently depending on the calibration type.
511 */
f22d9c03 512static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
9d97e5c8 513{
f22d9c03 514 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 515 int temp_code;
516
f22d9c03
ADK		 517 if (data->soc == SOC_ARCH_EXYNOS4210)
518 /* temp should range between 25 and 125 */
519 if (temp < 25 || temp > 125) {
520 temp_code = -EINVAL;
521 goto out;
522 }
9d97e5c8
DK		 523
524 switch (pdata->cal_type) {
525 case TYPE_TWO_POINT_TRIMMING:
526 temp_code = (temp - 25) *
527 (data->temp_error2 - data->temp_error1) /
528 (85 - 25) + data->temp_error1;
529 break;
530 case TYPE_ONE_POINT_TRIMMING:
531 temp_code = temp + data->temp_error1 - 25;
532 break;
533 default:
f22d9c03 534 temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
9d97e5c8
DK		 535 break;
536 }
537out:
538 return temp_code;
539}
540
541/*
542 * Calculate a temperature value from a temperature code.
543 * The unit of the temperature is degree Celsius.
544 */
f22d9c03 545static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
9d97e5c8 546{
f22d9c03 547 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 548 int temp;
549
f22d9c03
ADK		 550 if (data->soc == SOC_ARCH_EXYNOS4210)
551 /* temp_code should range between 75 and 175 */
552 if (temp_code < 75 || temp_code > 175) {
553 temp = -ENODATA;
554 goto out;
555 }
9d97e5c8
DK		 556
557 switch (pdata->cal_type) {
558 case TYPE_TWO_POINT_TRIMMING:
559 temp = (temp_code - data->temp_error1) * (85 - 25) /
560 (data->temp_error2 - data->temp_error1) + 25;
561 break;
562 case TYPE_ONE_POINT_TRIMMING:
563 temp = temp_code - data->temp_error1 + 25;
564 break;
565 default:
f22d9c03 566 temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
9d97e5c8
DK		 567 break;
568 }
569out:
570 return temp;
571}
572
f22d9c03 573static int exynos_tmu_initialize(struct platform_device *pdev)
9d97e5c8 574{
f22d9c03
ADK		 575 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
576 struct exynos_tmu_platform_data *pdata = data->pdata;
577 unsigned int status, trim_info, rising_threshold;
9d97e5c8
DK		 578 int ret = 0, threshold_code;
579
580 mutex_lock(&data->lock);
581 clk_enable(data->clk);
582
f22d9c03 583 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
9d97e5c8
DK		 584 if (!status) {
585 ret = -EBUSY;
586 goto out;
587 }
588
f22d9c03
ADK		 589 if (data->soc == SOC_ARCH_EXYNOS) {
590 __raw_writel(EXYNOS_TRIMINFO_RELOAD,
591 data->base + EXYNOS_TMU_TRIMINFO_CON);
592 }
9d97e5c8 593 /* Save trimming info in order to perform calibration */
f22d9c03
ADK		 594 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
595 data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
596 data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
597
598 if ((EFUSE_MIN_VALUE > data->temp_error1) ||
599 (data->temp_error1 > EFUSE_MAX_VALUE) ||
600 (data->temp_error2 != 0))
601 data->temp_error1 = pdata->efuse_value;
602
603 if (data->soc == SOC_ARCH_EXYNOS4210) {
604 /* Write temperature code for threshold */
605 threshold_code = temp_to_code(data, pdata->threshold);
606 if (threshold_code < 0) {
607 ret = threshold_code;
608 goto out;
609 }
610 writeb(threshold_code,
611 data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
612
613 writeb(pdata->trigger_levels[0],
614 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0);
615 writeb(pdata->trigger_levels[1],
616 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL1);
617 writeb(pdata->trigger_levels[2],
618 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL2);
619 writeb(pdata->trigger_levels[3],
620 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL3);
621
622 writel(EXYNOS4210_TMU_INTCLEAR_VAL,
623 data->base + EXYNOS_TMU_REG_INTCLEAR);
624 } else if (data->soc == SOC_ARCH_EXYNOS) {
625 /* Write temperature code for threshold */
626 threshold_code = temp_to_code(data, pdata->trigger_levels[0]);
627 if (threshold_code < 0) {
628 ret = threshold_code;
629 goto out;
630 }
631 rising_threshold = threshold_code;
632 threshold_code = temp_to_code(data, pdata->trigger_levels[1]);
633 if (threshold_code < 0) {
634 ret = threshold_code;
635 goto out;
636 }
637 rising_threshold |= (threshold_code << 8);
638 threshold_code = temp_to_code(data, pdata->trigger_levels[2]);
639 if (threshold_code < 0) {
640 ret = threshold_code;
641 goto out;
642 }
643 rising_threshold |= (threshold_code << 16);
644
645 writel(rising_threshold,
646 data->base + EXYNOS_THD_TEMP_RISE);
647 writel(0, data->base + EXYNOS_THD_TEMP_FALL);
648
649 writel(EXYNOS_TMU_CLEAR_RISE_INT|EXYNOS_TMU_CLEAR_FALL_INT,
650 data->base + EXYNOS_TMU_REG_INTCLEAR);
9d97e5c8 651 }
9d97e5c8
DK		 652out:
653 clk_disable(data->clk);
654 mutex_unlock(&data->lock);
655
656 return ret;
657}
658
f22d9c03 659static void exynos_tmu_control(struct platform_device *pdev, bool on)
9d97e5c8 660{
f22d9c03
ADK		 661 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
662 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 663 unsigned int con, interrupt_en;
664
665 mutex_lock(&data->lock);
666 clk_enable(data->clk);
667
f22d9c03
ADK		 668 con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
669 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
670
671 if (data->soc == SOC_ARCH_EXYNOS) {
672 con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
673 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
674 }
675
9d97e5c8 676 if (on) {
f22d9c03 677 con |= EXYNOS_TMU_CORE_ON;
9d97e5c8
DK		 678 interrupt_en = pdata->trigger_level3_en << 12 |
679 pdata->trigger_level2_en << 8 |
680 pdata->trigger_level1_en << 4 |
681 pdata->trigger_level0_en;
682 } else {
f22d9c03 683 con |= EXYNOS_TMU_CORE_OFF;
9d97e5c8
DK		 684 interrupt_en = 0; /* Disable all interrupts */
685 }
f22d9c03
ADK		 686 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
687 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
9d97e5c8
DK		 688
689 clk_disable(data->clk);
690 mutex_unlock(&data->lock);
691}
692
f22d9c03 693static int exynos_tmu_read(struct exynos_tmu_data *data)
9d97e5c8
DK		 694{
695 u8 temp_code;
696 int temp;
697
698 mutex_lock(&data->lock);
699 clk_enable(data->clk);
700
f22d9c03 701 temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
9d97e5c8
DK		 702 temp = code_to_temp(data, temp_code);
703
704 clk_disable(data->clk);
705 mutex_unlock(&data->lock);
706
707 return temp;
708}
709
f22d9c03 710static void exynos_tmu_work(struct work_struct *work)
9d97e5c8 711{
f22d9c03
ADK		 712 struct exynos_tmu_data *data = container_of(work,
713 struct exynos_tmu_data, irq_work);
9d97e5c8 714
3ad9524a 715 exynos_report_trigger();
9d97e5c8
DK		 716 mutex_lock(&data->lock);
717 clk_enable(data->clk);
f22d9c03
ADK		 718 if (data->soc == SOC_ARCH_EXYNOS)
719 writel(EXYNOS_TMU_CLEAR_RISE_INT,
720 data->base + EXYNOS_TMU_REG_INTCLEAR);
721 else
722 writel(EXYNOS4210_TMU_INTCLEAR_VAL,
723 data->base + EXYNOS_TMU_REG_INTCLEAR);
9d97e5c8
DK		 724 clk_disable(data->clk);
725 mutex_unlock(&data->lock);
3ad9524a 726
f22d9c03 727 enable_irq(data->irq);
9d97e5c8
DK		 728}
729
f22d9c03 730static irqreturn_t exynos_tmu_irq(int irq, void *id)
9d97e5c8 731{
f22d9c03 732 struct exynos_tmu_data *data = id;
9d97e5c8
DK		 733
734 disable_irq_nosync(irq);
735 schedule_work(&data->irq_work);
736
737 return IRQ_HANDLED;
738}
7e0b55e6
ADK		 739static struct thermal_sensor_conf exynos_sensor_conf = {
740 .name = "exynos-therm",
741 .read_temperature = (int (*)(void *))exynos_tmu_read,
17be868e
ADK		 742};
743
744#if defined(CONFIG_CPU_EXYNOS4210)
745static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
746 .threshold = 80,
747 .trigger_levels[0] = 5,
748 .trigger_levels[1] = 20,
749 .trigger_levels[2] = 30,
750 .trigger_level0_en = 1,
751 .trigger_level1_en = 1,
752 .trigger_level2_en = 1,
753 .trigger_level3_en = 0,
754 .gain = 15,
755 .reference_voltage = 7,
756 .cal_type = TYPE_ONE_POINT_TRIMMING,
757 .freq_tab[0] = {
758 .freq_clip_max = 800 * 1000,
759 .temp_level = 85,
760 },
761 .freq_tab[1] = {
762 .freq_clip_max = 200 * 1000,
763 .temp_level = 100,
764 },
765 .freq_tab_count = 2,
766 .type = SOC_ARCH_EXYNOS4210,
767};
768#define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
769#else
770#define EXYNOS4210_TMU_DRV_DATA (NULL)
771#endif
772
773#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
774static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
775 .trigger_levels[0] = 85,
776 .trigger_levels[1] = 103,
777 .trigger_levels[2] = 110,
778 .trigger_level0_en = 1,
779 .trigger_level1_en = 1,
780 .trigger_level2_en = 1,
781 .trigger_level3_en = 0,
782 .gain = 8,
783 .reference_voltage = 16,
784 .noise_cancel_mode = 4,
785 .cal_type = TYPE_ONE_POINT_TRIMMING,
786 .efuse_value = 55,
787 .freq_tab[0] = {
788 .freq_clip_max = 800 * 1000,
789 .temp_level = 85,
790 },
791 .freq_tab[1] = {
792 .freq_clip_max = 200 * 1000,
793 .temp_level = 103,
794 },
795 .freq_tab_count = 2,
796 .type = SOC_ARCH_EXYNOS,
797};
798#define EXYNOS_TMU_DRV_DATA (&exynos_default_tmu_data)
799#else
800#define EXYNOS_TMU_DRV_DATA (NULL)
801#endif
802
803#ifdef CONFIG_OF
804static const struct of_device_id exynos_tmu_match[] = {
805 {
806 .compatible = "samsung,exynos4210-tmu",
807 .data = (void *)EXYNOS4210_TMU_DRV_DATA,
808 },
809 {
810 .compatible = "samsung,exynos5250-tmu",
811 .data = (void *)EXYNOS_TMU_DRV_DATA,
812 },
813 {},
814};
815MODULE_DEVICE_TABLE(of, exynos_tmu_match);
17be868e
ADK		 816#endif
817
818static struct platform_device_id exynos_tmu_driver_ids[] = {
819 {
820 .name = "exynos4210-tmu",
821 .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
822 },
823 {
824 .name = "exynos5250-tmu",
825 .driver_data = (kernel_ulong_t)EXYNOS_TMU_DRV_DATA,
826 },
827 { },
828};
3ae53b1e 829MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
17be868e
ADK		 830
831static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
832 struct platform_device *pdev)
833{
834#ifdef CONFIG_OF
835 if (pdev->dev.of_node) {
836 const struct of_device_id *match;
837 match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
838 if (!match)
839 return NULL;
840 return (struct exynos_tmu_platform_data *) match->data;
841 }
842#endif
843 return (struct exynos_tmu_platform_data *)
844 platform_get_device_id(pdev)->driver_data;
7e0b55e6 845}
bbf63be4
JL		 846
847#ifdef CONFIG_EXYNOS_THERMAL_EMUL
848static ssize_t exynos_tmu_emulation_show(struct device *dev,
849 struct device_attribute *attr,
850 char *buf)
851{
852 struct platform_device *pdev = container_of(dev,
853 struct platform_device, dev);
854 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
855 unsigned int reg;
856 u8 temp_code;
857 int temp = 0;
858
859 if (data->soc == SOC_ARCH_EXYNOS4210)
860 goto out;
861
862 mutex_lock(&data->lock);
863 clk_enable(data->clk);
864 reg = readl(data->base + EXYNOS_EMUL_CON);
865 clk_disable(data->clk);
866 mutex_unlock(&data->lock);
867
868 if (reg & EXYNOS_EMUL_ENABLE) {
869 reg >>= EXYNOS_EMUL_DATA_SHIFT;
870 temp_code = reg & EXYNOS_EMUL_DATA_MASK;
871 temp = code_to_temp(data, temp_code);
872 }
873out:
874 return sprintf(buf, "%d\n", temp * MCELSIUS);
875}
876
877static ssize_t exynos_tmu_emulation_store(struct device *dev,
878 struct device_attribute *attr,
879 const char *buf, size_t count)
880{
881 struct platform_device *pdev = container_of(dev,
882 struct platform_device, dev);
883 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
884 unsigned int reg;
885 int temp;
886
887 if (data->soc == SOC_ARCH_EXYNOS4210)
888 goto out;
889
890 if (!sscanf(buf, "%d\n", &temp) || temp < 0)
891 return -EINVAL;
892
893 mutex_lock(&data->lock);
894 clk_enable(data->clk);
895
896 reg = readl(data->base + EXYNOS_EMUL_CON);
897
898 if (temp) {
899 /* Both CELSIUS and MCELSIUS type are available for input */
900 if (temp > MCELSIUS)
901 temp /= MCELSIUS;
902
903 reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) |
904 (temp_to_code(data, (temp / MCELSIUS))
905 << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE;
906 } else {
907 reg &= ~EXYNOS_EMUL_ENABLE;
908 }
909
910 writel(reg, data->base + EXYNOS_EMUL_CON);
911
912 clk_disable(data->clk);
913 mutex_unlock(&data->lock);
914
915out:
916 return count;
917}
918
919static DEVICE_ATTR(emulation, 0644, exynos_tmu_emulation_show,
920 exynos_tmu_emulation_store);
921static int create_emulation_sysfs(struct device *dev)
922{
923 return device_create_file(dev, &dev_attr_emulation);
924}
925static void remove_emulation_sysfs(struct device *dev)
926{
927 device_remove_file(dev, &dev_attr_emulation);
928}
929#else
930static inline int create_emulation_sysfs(struct device *dev) { return 0; }
931static inline void remove_emulation_sysfs(struct device *dev) {}
932#endif
933
f22d9c03 934static int __devinit exynos_tmu_probe(struct platform_device *pdev)
9d97e5c8 935{
f22d9c03
ADK		 936 struct exynos_tmu_data *data;
937 struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
7e0b55e6 938 int ret, i;
9d97e5c8 939
17be868e
ADK		 940 if (!pdata)
941 pdata = exynos_get_driver_data(pdev);
942
9d97e5c8
DK		 943 if (!pdata) {
944 dev_err(&pdev->dev, "No platform init data supplied.\n");
945 return -ENODEV;
946 }
79e093c3
ADK		 947 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
948 GFP_KERNEL);
9d97e5c8
DK		 949 if (!data) {
950 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
951 return -ENOMEM;
952 }
953
954 data->irq = platform_get_irq(pdev, 0);
955 if (data->irq < 0) {
9d97e5c8 956 dev_err(&pdev->dev, "Failed to get platform irq\n");
79e093c3 957 return data->irq;
9d97e5c8
DK		 958 }
959
f22d9c03 960 INIT_WORK(&data->irq_work, exynos_tmu_work);
9d97e5c8
DK		 961
962 data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
963 if (!data->mem) {
9d97e5c8 964 dev_err(&pdev->dev, "Failed to get platform resource\n");
79e093c3 965 return -ENOENT;
9d97e5c8
DK		 966 }
967
79e093c3 968 data->base = devm_request_and_ioremap(&pdev->dev, data->mem);
9d97e5c8 969 if (!data->base) {
9d97e5c8 970 dev_err(&pdev->dev, "Failed to ioremap memory\n");
79e093c3 971 return -ENODEV;
9d97e5c8
DK		 972 }
973
79e093c3 974 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
f22d9c03 975 IRQF_TRIGGER_RISING, "exynos-tmu", data);
9d97e5c8
DK		 976 if (ret) {
977 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
79e093c3 978 return ret;
9d97e5c8
DK		 979 }
980
981 data->clk = clk_get(NULL, "tmu_apbif");
982 if (IS_ERR(data->clk)) {
9d97e5c8 983 dev_err(&pdev->dev, "Failed to get clock\n");
79e093c3 984 return PTR_ERR(data->clk);
9d97e5c8
DK		 985 }
986
f22d9c03
ADK		 987 if (pdata->type == SOC_ARCH_EXYNOS ||
988 pdata->type == SOC_ARCH_EXYNOS4210)
989 data->soc = pdata->type;
990 else {
991 ret = -EINVAL;
992 dev_err(&pdev->dev, "Platform not supported\n");
993 goto err_clk;
994 }
995
9d97e5c8
DK		 996 data->pdata = pdata;
997 platform_set_drvdata(pdev, data);
998 mutex_init(&data->lock);
999
f22d9c03 1000 ret = exynos_tmu_initialize(pdev);
9d97e5c8
DK		 1001 if (ret) {
1002 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1003 goto err_clk;
1004 }
1005
f22d9c03 1006 exynos_tmu_control(pdev, true);
9d97e5c8 1007
7e0b55e6
ADK		 1008 /* Register the sensor with thermal management interface */
1009 (&exynos_sensor_conf)->private_data = data;
1010 exynos_sensor_conf.trip_data.trip_count = pdata->trigger_level0_en +
1011 pdata->trigger_level1_en + pdata->trigger_level2_en +
1012 pdata->trigger_level3_en;
1013
1014 for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
1015 exynos_sensor_conf.trip_data.trip_val[i] =
1016 pdata->threshold + pdata->trigger_levels[i];
1017
1018 exynos_sensor_conf.cooling_data.freq_clip_count =
1019 pdata->freq_tab_count;
1020 for (i = 0; i < pdata->freq_tab_count; i++) {
1021 exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
1022 pdata->freq_tab[i].freq_clip_max;
1023 exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
1024 pdata->freq_tab[i].temp_level;
1025 }
1026
1027 ret = exynos_register_thermal(&exynos_sensor_conf);
1028 if (ret) {
1029 dev_err(&pdev->dev, "Failed to register thermal interface\n");
1030 goto err_clk;
1031 }
bbf63be4
JL		 1032
1033 ret = create_emulation_sysfs(&pdev->dev);
1034 if (ret)
1035 dev_err(&pdev->dev, "Failed to create emulation mode sysfs node\n");
1036
9d97e5c8 1037 return 0;
9d97e5c8
DK		 1038err_clk:
1039 platform_set_drvdata(pdev, NULL);
1040 clk_put(data->clk);
9d97e5c8
DK		 1041 return ret;
1042}
1043
f22d9c03 1044static int __devexit exynos_tmu_remove(struct platform_device *pdev)
9d97e5c8 1045{
f22d9c03 1046 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
9d97e5c8 1047
bbf63be4
JL		 1048 remove_emulation_sysfs(&pdev->dev);
1049
f22d9c03 1050 exynos_tmu_control(pdev, false);
9d97e5c8 1051
7e0b55e6
ADK		 1052 exynos_unregister_thermal();
1053
9d97e5c8
DK		 1054 clk_put(data->clk);
1055
9d97e5c8
DK		 1056 platform_set_drvdata(pdev, NULL);
1057
9d97e5c8
DK		 1058 return 0;
1059}
1060
08cd6753 1061#ifdef CONFIG_PM_SLEEP
f22d9c03 1062static int exynos_tmu_suspend(struct device *dev)
9d97e5c8 1063{
f22d9c03 1064 exynos_tmu_control(to_platform_device(dev), false);
9d97e5c8
DK		 1065
1066 return 0;
1067}
1068
f22d9c03 1069static int exynos_tmu_resume(struct device *dev)
9d97e5c8 1070{
08cd6753
RW		 1071 struct platform_device *pdev = to_platform_device(dev);
1072
f22d9c03
ADK		 1073 exynos_tmu_initialize(pdev);
1074 exynos_tmu_control(pdev, true);
9d97e5c8
DK		 1075
1076 return 0;
1077}
08cd6753 1078
f22d9c03
ADK		 1079static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1080 exynos_tmu_suspend, exynos_tmu_resume);
1081#define EXYNOS_TMU_PM (&exynos_tmu_pm)
9d97e5c8 1082#else
f22d9c03 1083#define EXYNOS_TMU_PM NULL
9d97e5c8
DK		 1084#endif
1085
f22d9c03 1086static struct platform_driver exynos_tmu_driver = {
9d97e5c8 1087 .driver = {
f22d9c03 1088 .name = "exynos-tmu",
9d97e5c8 1089 .owner = THIS_MODULE,
f22d9c03 1090 .pm = EXYNOS_TMU_PM,
caa5cbd5 1091 .of_match_table = of_match_ptr(exynos_tmu_match),
9d97e5c8 1092 },
f22d9c03
ADK		 1093 .probe = exynos_tmu_probe,
1094 .remove = __devexit_p(exynos_tmu_remove),
17be868e 1095 .id_table = exynos_tmu_driver_ids,
9d97e5c8
DK		 1096};
1097
f22d9c03 1098module_platform_driver(exynos_tmu_driver);
9d97e5c8 1099
f22d9c03 1100MODULE_DESCRIPTION("EXYNOS TMU Driver");
9d97e5c8
DK		 1101MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1102MODULE_LICENSE("GPL");
f22d9c03 1103MODULE_ALIAS("platform:exynos-tmu");
Linux kernel - Deliverables
This page took 0.138547 seconds and 5 git commands to generate.