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[deliverable/linux.git] / drivers / thermal / exynos_thermal.c
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9d97e5c8 1/*
c48cbba6 2 * exynos_thermal.c - Samsung EXYNOS TMU (Thermal Management Unit)
9d97e5c8
DK		 3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
c48cbba6 6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
9d97e5c8
DK		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/err.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/workqueue.h>
32#include <linux/sysfs.h>
33#include <linux/kobject.h>
34#include <linux/io.h>
35#include <linux/mutex.h>
c48cbba6 36#include <linux/platform_data/exynos_thermal.h>
7e0b55e6
ADK		 37#include <linux/thermal.h>
38#include <linux/cpufreq.h>
39#include <linux/cpu_cooling.h>
f22d9c03
ADK		 40#include <linux/of.h>
41
42#include <plat/cpu.h>
43
44/* Exynos generic registers */
45#define EXYNOS_TMU_REG_TRIMINFO 0x0
46#define EXYNOS_TMU_REG_CONTROL 0x20
47#define EXYNOS_TMU_REG_STATUS 0x28
48#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
49#define EXYNOS_TMU_REG_INTEN 0x70
50#define EXYNOS_TMU_REG_INTSTAT 0x74
51#define EXYNOS_TMU_REG_INTCLEAR 0x78
52
53#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
54#define EXYNOS_TMU_GAIN_SHIFT 8
55#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
56#define EXYNOS_TMU_CORE_ON 3
57#define EXYNOS_TMU_CORE_OFF 2
58#define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
59
60/* Exynos4210 specific registers */
61#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
62#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
63#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
64#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
65#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
66#define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
67#define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
68#define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
69#define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
70
71#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
72#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
73#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
74#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
75#define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
76
77/* Exynos5250 and Exynos4412 specific registers */
78#define EXYNOS_TMU_TRIMINFO_CON 0x14
79#define EXYNOS_THD_TEMP_RISE 0x50
80#define EXYNOS_THD_TEMP_FALL 0x54
81#define EXYNOS_EMUL_CON 0x80
82
83#define EXYNOS_TRIMINFO_RELOAD 0x1
84#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
85#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 16)
86#define EXYNOS_MUX_ADDR_VALUE 6
87#define EXYNOS_MUX_ADDR_SHIFT 20
88#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
89
90#define EFUSE_MIN_VALUE 40
91#define EFUSE_MAX_VALUE 100
92
93/* In-kernel thermal framework related macros & definations */
94#define SENSOR_NAME_LEN 16
95#define MAX_TRIP_COUNT 8
96#define MAX_COOLING_DEVICE 4
97
98#define ACTIVE_INTERVAL 500
99#define IDLE_INTERVAL 10000
7e0b55e6 100#define MCELSIUS 1000
f22d9c03 101
bbf63be4
JL		 102#ifdef CONFIG_EXYNOS_THERMAL_EMUL
103#define EXYNOS_EMUL_TIME 0x57F0
104#define EXYNOS_EMUL_TIME_SHIFT 16
105#define EXYNOS_EMUL_DATA_SHIFT 8
106#define EXYNOS_EMUL_DATA_MASK 0xFF
107#define EXYNOS_EMUL_ENABLE 0x1
108#endif /* CONFIG_EXYNOS_THERMAL_EMUL */
109
f22d9c03
ADK		 110/* CPU Zone information */
111#define PANIC_ZONE 4
112#define WARN_ZONE 3
113#define MONITOR_ZONE 2
114#define SAFE_ZONE 1
115
116#define GET_ZONE(trip) (trip + 2)
117#define GET_TRIP(zone) (zone - 2)
118
7e0b55e6
ADK		 119#define EXYNOS_ZONE_COUNT 3
120
f22d9c03
ADK		 121struct exynos_tmu_data {
122 struct exynos_tmu_platform_data *pdata;
9d97e5c8
DK		 123 struct resource *mem;
124 void __iomem *base;
125 int irq;
f22d9c03 126 enum soc_type soc;
9d97e5c8
DK		 127 struct work_struct irq_work;
128 struct mutex lock;
129 struct clk *clk;
130 u8 temp_error1, temp_error2;
131};
132
7e0b55e6
ADK		 133struct thermal_trip_point_conf {
134 int trip_val[MAX_TRIP_COUNT];
135 int trip_count;
136};
137
138struct thermal_cooling_conf {
139 struct freq_clip_table freq_data[MAX_TRIP_COUNT];
140 int freq_clip_count;
141};
142
143struct thermal_sensor_conf {
144 char name[SENSOR_NAME_LEN];
145 int (*read_temperature)(void *data);
146 struct thermal_trip_point_conf trip_data;
147 struct thermal_cooling_conf cooling_data;
148 void *private_data;
149};
150
151struct exynos_thermal_zone {
152 enum thermal_device_mode mode;
153 struct thermal_zone_device *therm_dev;
154 struct thermal_cooling_device *cool_dev[MAX_COOLING_DEVICE];
155 unsigned int cool_dev_size;
156 struct platform_device *exynos4_dev;
157 struct thermal_sensor_conf *sensor_conf;
158 bool bind;
159};
160
161static struct exynos_thermal_zone *th_zone;
162static void exynos_unregister_thermal(void);
163static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf);
164
165/* Get mode callback functions for thermal zone */
166static int exynos_get_mode(struct thermal_zone_device *thermal,
167 enum thermal_device_mode *mode)
168{
169 if (th_zone)
170 *mode = th_zone->mode;
171 return 0;
172}
173
174/* Set mode callback functions for thermal zone */
175static int exynos_set_mode(struct thermal_zone_device *thermal,
176 enum thermal_device_mode mode)
177{
178 if (!th_zone->therm_dev) {
179 pr_notice("thermal zone not registered\n");
180 return 0;
181 }
182
183 mutex_lock(&th_zone->therm_dev->lock);
184
185 if (mode == THERMAL_DEVICE_ENABLED)
186 th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
187 else
188 th_zone->therm_dev->polling_delay = 0;
189
190 mutex_unlock(&th_zone->therm_dev->lock);
191
192 th_zone->mode = mode;
193 thermal_zone_device_update(th_zone->therm_dev);
194 pr_info("thermal polling set for duration=%d msec\n",
195 th_zone->therm_dev->polling_delay);
196 return 0;
197}
198
199
200/* Get trip type callback functions for thermal zone */
201static int exynos_get_trip_type(struct thermal_zone_device *thermal, int trip,
202 enum thermal_trip_type *type)
203{
204 switch (GET_ZONE(trip)) {
205 case MONITOR_ZONE:
206 case WARN_ZONE:
207 *type = THERMAL_TRIP_ACTIVE;
208 break;
209 case PANIC_ZONE:
210 *type = THERMAL_TRIP_CRITICAL;
211 break;
212 default:
213 return -EINVAL;
214 }
215 return 0;
216}
217
218/* Get trip temperature callback functions for thermal zone */
219static int exynos_get_trip_temp(struct thermal_zone_device *thermal, int trip,
220 unsigned long *temp)
221{
222 if (trip < GET_TRIP(MONITOR_ZONE) || trip > GET_TRIP(PANIC_ZONE))
223 return -EINVAL;
224
225 *temp = th_zone->sensor_conf->trip_data.trip_val[trip];
226 /* convert the temperature into millicelsius */
227 *temp = *temp * MCELSIUS;
228
229 return 0;
230}
231
232/* Get critical temperature callback functions for thermal zone */
233static int exynos_get_crit_temp(struct thermal_zone_device *thermal,
234 unsigned long *temp)
235{
236 int ret;
237 /* Panic zone */
238 ret = exynos_get_trip_temp(thermal, GET_TRIP(PANIC_ZONE), temp);
239 return ret;
240}
241
242static int exynos_get_frequency_level(unsigned int cpu, unsigned int freq)
243{
244 int i = 0, ret = -EINVAL;
245 struct cpufreq_frequency_table *table = NULL;
246#ifdef CONFIG_CPU_FREQ
247 table = cpufreq_frequency_get_table(cpu);
248#endif
249 if (!table)
250 return ret;
251
252 while (table[i].frequency != CPUFREQ_TABLE_END) {
253 if (table[i].frequency == CPUFREQ_ENTRY_INVALID)
254 continue;
255 if (table[i].frequency == freq)
256 return i;
257 i++;
258 }
259 return ret;
260}
261
262/* Bind callback functions for thermal zone */
263static int exynos_bind(struct thermal_zone_device *thermal,
264 struct thermal_cooling_device *cdev)
265{
266 int ret = 0, i, tab_size, level;
267 struct freq_clip_table *tab_ptr, *clip_data;
268 struct thermal_sensor_conf *data = th_zone->sensor_conf;
269
270 tab_ptr = (struct freq_clip_table *)data->cooling_data.freq_data;
271 tab_size = data->cooling_data.freq_clip_count;
272
273 if (tab_ptr == NULL || tab_size == 0)
274 return -EINVAL;
275
276 /* find the cooling device registered*/
277 for (i = 0; i < th_zone->cool_dev_size; i++)
278 if (cdev == th_zone->cool_dev[i])
279 break;
280
281 /* No matching cooling device */
282 if (i == th_zone->cool_dev_size)
283 return 0;
284
285 /* Bind the thermal zone to the cpufreq cooling device */
286 for (i = 0; i < tab_size; i++) {
287 clip_data = (struct freq_clip_table *)&(tab_ptr[i]);
288 level = exynos_get_frequency_level(0, clip_data->freq_clip_max);
289 if (level < 0)
290 return 0;
291 switch (GET_ZONE(i)) {
292 case MONITOR_ZONE:
293 case WARN_ZONE:
294 if (thermal_zone_bind_cooling_device(thermal, i, cdev,
295 level, level)) {
296 pr_err("error binding cdev inst %d\n", i);
297 ret = -EINVAL;
298 }
299 th_zone->bind = true;
300 break;
301 default:
302 ret = -EINVAL;
303 }
304 }
305
306 return ret;
307}
308
309/* Unbind callback functions for thermal zone */
310static int exynos_unbind(struct thermal_zone_device *thermal,
311 struct thermal_cooling_device *cdev)
312{
313 int ret = 0, i, tab_size;
314 struct thermal_sensor_conf *data = th_zone->sensor_conf;
315
316 if (th_zone->bind == false)
317 return 0;
318
319 tab_size = data->cooling_data.freq_clip_count;
320
321 if (tab_size == 0)
322 return -EINVAL;
323
324 /* find the cooling device registered*/
325 for (i = 0; i < th_zone->cool_dev_size; i++)
326 if (cdev == th_zone->cool_dev[i])
327 break;
328
329 /* No matching cooling device */
330 if (i == th_zone->cool_dev_size)
331 return 0;
332
333 /* Bind the thermal zone to the cpufreq cooling device */
334 for (i = 0; i < tab_size; i++) {
335 switch (GET_ZONE(i)) {
336 case MONITOR_ZONE:
337 case WARN_ZONE:
338 if (thermal_zone_unbind_cooling_device(thermal, i,
339 cdev)) {
340 pr_err("error unbinding cdev inst=%d\n", i);
341 ret = -EINVAL;
342 }
343 th_zone->bind = false;
344 break;
345 default:
346 ret = -EINVAL;
347 }
348 }
349 return ret;
350}
351
352/* Get temperature callback functions for thermal zone */
353static int exynos_get_temp(struct thermal_zone_device *thermal,
354 unsigned long *temp)
355{
356 void *data;
357
358 if (!th_zone->sensor_conf) {
359 pr_info("Temperature sensor not initialised\n");
360 return -EINVAL;
361 }
362 data = th_zone->sensor_conf->private_data;
363 *temp = th_zone->sensor_conf->read_temperature(data);
364 /* convert the temperature into millicelsius */
365 *temp = *temp * MCELSIUS;
366 return 0;
367}
368
369/* Get the temperature trend */
370static int exynos_get_trend(struct thermal_zone_device *thermal,
371 int trip, enum thermal_trend *trend)
372{
373 if (thermal->temperature >= trip)
374 *trend = THERMAL_TREND_RAISING;
375 else
376 *trend = THERMAL_TREND_DROPPING;
377
378 return 0;
379}
380/* Operation callback functions for thermal zone */
381static struct thermal_zone_device_ops const exynos_dev_ops = {
382 .bind = exynos_bind,
383 .unbind = exynos_unbind,
384 .get_temp = exynos_get_temp,
385 .get_trend = exynos_get_trend,
386 .get_mode = exynos_get_mode,
387 .set_mode = exynos_set_mode,
388 .get_trip_type = exynos_get_trip_type,
389 .get_trip_temp = exynos_get_trip_temp,
390 .get_crit_temp = exynos_get_crit_temp,
391};
392
393/*
394 * This function may be called from interrupt based temperature sensor
395 * when threshold is changed.
396 */
397static void exynos_report_trigger(void)
398{
399 unsigned int i;
400 char data[10];
401 char *envp[] = { data, NULL };
402
403 if (!th_zone || !th_zone->therm_dev)
404 return;
405 if (th_zone->bind == false) {
406 for (i = 0; i < th_zone->cool_dev_size; i++) {
407 if (!th_zone->cool_dev[i])
408 continue;
409 exynos_bind(th_zone->therm_dev,
410 th_zone->cool_dev[i]);
411 }
412 }
413
414 thermal_zone_device_update(th_zone->therm_dev);
415
416 mutex_lock(&th_zone->therm_dev->lock);
417 /* Find the level for which trip happened */
418 for (i = 0; i < th_zone->sensor_conf->trip_data.trip_count; i++) {
419 if (th_zone->therm_dev->last_temperature <
420 th_zone->sensor_conf->trip_data.trip_val[i] * MCELSIUS)
421 break;
422 }
423
424 if (th_zone->mode == THERMAL_DEVICE_ENABLED) {
425 if (i > 0)
426 th_zone->therm_dev->polling_delay = ACTIVE_INTERVAL;
427 else
428 th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
429 }
430
431 snprintf(data, sizeof(data), "%u", i);
432 kobject_uevent_env(&th_zone->therm_dev->device.kobj, KOBJ_CHANGE, envp);
433 mutex_unlock(&th_zone->therm_dev->lock);
434}
435
436/* Register with the in-kernel thermal management */
437static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf)
438{
439 int ret;
440 struct cpumask mask_val;
441
442 if (!sensor_conf || !sensor_conf->read_temperature) {
443 pr_err("Temperature sensor not initialised\n");
444 return -EINVAL;
445 }
446
447 th_zone = kzalloc(sizeof(struct exynos_thermal_zone), GFP_KERNEL);
448 if (!th_zone)
449 return -ENOMEM;
450
451 th_zone->sensor_conf = sensor_conf;
452 cpumask_set_cpu(0, &mask_val);
453 th_zone->cool_dev[0] = cpufreq_cooling_register(&mask_val);
454 if (IS_ERR(th_zone->cool_dev[0])) {
455 pr_err("Failed to register cpufreq cooling device\n");
456 ret = -EINVAL;
457 goto err_unregister;
458 }
459 th_zone->cool_dev_size++;
460
461 th_zone->therm_dev = thermal_zone_device_register(sensor_conf->name,
50125a9b 462 EXYNOS_ZONE_COUNT, 0, NULL, &exynos_dev_ops, NULL, 0,
7e0b55e6
ADK		 463 IDLE_INTERVAL);
464
465 if (IS_ERR(th_zone->therm_dev)) {
466 pr_err("Failed to register thermal zone device\n");
467 ret = -EINVAL;
468 goto err_unregister;
469 }
470 th_zone->mode = THERMAL_DEVICE_ENABLED;
471
472 pr_info("Exynos: Kernel Thermal management registered\n");
473
474 return 0;
475
476err_unregister:
477 exynos_unregister_thermal();
478 return ret;
479}
480
481/* Un-Register with the in-kernel thermal management */
482static void exynos_unregister_thermal(void)
483{
484 int i;
485
c072fed9
SK		 486 if (!th_zone)
487 return;
488
489 if (th_zone->therm_dev)
7e0b55e6
ADK		 490 thermal_zone_device_unregister(th_zone->therm_dev);
491
492 for (i = 0; i < th_zone->cool_dev_size; i++) {
c072fed9 493 if (th_zone->cool_dev[i])
7e0b55e6
ADK		 494 cpufreq_cooling_unregister(th_zone->cool_dev[i]);
495 }
496
497 kfree(th_zone);
498 pr_info("Exynos: Kernel Thermal management unregistered\n");
499}
500
9d97e5c8
DK		 501/*
502 * TMU treats temperature as a mapped temperature code.
503 * The temperature is converted differently depending on the calibration type.
504 */
f22d9c03 505static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
9d97e5c8 506{
f22d9c03 507 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 508 int temp_code;
509
f22d9c03
ADK		 510 if (data->soc == SOC_ARCH_EXYNOS4210)
511 /* temp should range between 25 and 125 */
512 if (temp < 25 || temp > 125) {
513 temp_code = -EINVAL;
514 goto out;
515 }
9d97e5c8
DK		 516
517 switch (pdata->cal_type) {
518 case TYPE_TWO_POINT_TRIMMING:
519 temp_code = (temp - 25) *
520 (data->temp_error2 - data->temp_error1) /
521 (85 - 25) + data->temp_error1;
522 break;
523 case TYPE_ONE_POINT_TRIMMING:
524 temp_code = temp + data->temp_error1 - 25;
525 break;
526 default:
f22d9c03 527 temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
9d97e5c8
DK		 528 break;
529 }
530out:
531 return temp_code;
532}
533
534/*
535 * Calculate a temperature value from a temperature code.
536 * The unit of the temperature is degree Celsius.
537 */
f22d9c03 538static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
9d97e5c8 539{
f22d9c03 540 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 541 int temp;
542
f22d9c03
ADK		 543 if (data->soc == SOC_ARCH_EXYNOS4210)
544 /* temp_code should range between 75 and 175 */
545 if (temp_code < 75 || temp_code > 175) {
546 temp = -ENODATA;
547 goto out;
548 }
9d97e5c8
DK		 549
550 switch (pdata->cal_type) {
551 case TYPE_TWO_POINT_TRIMMING:
552 temp = (temp_code - data->temp_error1) * (85 - 25) /
553 (data->temp_error2 - data->temp_error1) + 25;
554 break;
555 case TYPE_ONE_POINT_TRIMMING:
556 temp = temp_code - data->temp_error1 + 25;
557 break;
558 default:
f22d9c03 559 temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
9d97e5c8
DK		 560 break;
561 }
562out:
563 return temp;
564}
565
f22d9c03 566static int exynos_tmu_initialize(struct platform_device *pdev)
9d97e5c8 567{
f22d9c03
ADK		 568 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
569 struct exynos_tmu_platform_data *pdata = data->pdata;
570 unsigned int status, trim_info, rising_threshold;
9d97e5c8
DK		 571 int ret = 0, threshold_code;
572
573 mutex_lock(&data->lock);
574 clk_enable(data->clk);
575
f22d9c03 576 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
9d97e5c8
DK		 577 if (!status) {
578 ret = -EBUSY;
579 goto out;
580 }
581
f22d9c03
ADK		 582 if (data->soc == SOC_ARCH_EXYNOS) {
583 __raw_writel(EXYNOS_TRIMINFO_RELOAD,
584 data->base + EXYNOS_TMU_TRIMINFO_CON);
585 }
9d97e5c8 586 /* Save trimming info in order to perform calibration */
f22d9c03
ADK		 587 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
588 data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
589 data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
590
591 if ((EFUSE_MIN_VALUE > data->temp_error1) ||
592 (data->temp_error1 > EFUSE_MAX_VALUE) ||
593 (data->temp_error2 != 0))
594 data->temp_error1 = pdata->efuse_value;
595
596 if (data->soc == SOC_ARCH_EXYNOS4210) {
597 /* Write temperature code for threshold */
598 threshold_code = temp_to_code(data, pdata->threshold);
599 if (threshold_code < 0) {
600 ret = threshold_code;
601 goto out;
602 }
603 writeb(threshold_code,
604 data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
605
606 writeb(pdata->trigger_levels[0],
607 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0);
608 writeb(pdata->trigger_levels[1],
609 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL1);
610 writeb(pdata->trigger_levels[2],
611 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL2);
612 writeb(pdata->trigger_levels[3],
613 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL3);
614
615 writel(EXYNOS4210_TMU_INTCLEAR_VAL,
616 data->base + EXYNOS_TMU_REG_INTCLEAR);
617 } else if (data->soc == SOC_ARCH_EXYNOS) {
618 /* Write temperature code for threshold */
619 threshold_code = temp_to_code(data, pdata->trigger_levels[0]);
620 if (threshold_code < 0) {
621 ret = threshold_code;
622 goto out;
623 }
624 rising_threshold = threshold_code;
625 threshold_code = temp_to_code(data, pdata->trigger_levels[1]);
626 if (threshold_code < 0) {
627 ret = threshold_code;
628 goto out;
629 }
630 rising_threshold |= (threshold_code << 8);
631 threshold_code = temp_to_code(data, pdata->trigger_levels[2]);
632 if (threshold_code < 0) {
633 ret = threshold_code;
634 goto out;
635 }
636 rising_threshold |= (threshold_code << 16);
637
638 writel(rising_threshold,
639 data->base + EXYNOS_THD_TEMP_RISE);
640 writel(0, data->base + EXYNOS_THD_TEMP_FALL);
641
642 writel(EXYNOS_TMU_CLEAR_RISE_INT|EXYNOS_TMU_CLEAR_FALL_INT,
643 data->base + EXYNOS_TMU_REG_INTCLEAR);
9d97e5c8 644 }
9d97e5c8
DK		 645out:
646 clk_disable(data->clk);
647 mutex_unlock(&data->lock);
648
649 return ret;
650}
651
f22d9c03 652static void exynos_tmu_control(struct platform_device *pdev, bool on)
9d97e5c8 653{
f22d9c03
ADK		 654 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
655 struct exynos_tmu_platform_data *pdata = data->pdata;
9d97e5c8
DK		 656 unsigned int con, interrupt_en;
657
658 mutex_lock(&data->lock);
659 clk_enable(data->clk);
660
f22d9c03
ADK		 661 con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
662 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
663
664 if (data->soc == SOC_ARCH_EXYNOS) {
665 con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
666 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
667 }
668
9d97e5c8 669 if (on) {
f22d9c03 670 con |= EXYNOS_TMU_CORE_ON;
9d97e5c8
DK		 671 interrupt_en = pdata->trigger_level3_en << 12 |
672 pdata->trigger_level2_en << 8 |
673 pdata->trigger_level1_en << 4 |
674 pdata->trigger_level0_en;
675 } else {
f22d9c03 676 con |= EXYNOS_TMU_CORE_OFF;
9d97e5c8
DK		 677 interrupt_en = 0; /* Disable all interrupts */
678 }
f22d9c03
ADK		 679 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
680 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
9d97e5c8
DK		 681
682 clk_disable(data->clk);
683 mutex_unlock(&data->lock);
684}
685
f22d9c03 686static int exynos_tmu_read(struct exynos_tmu_data *data)
9d97e5c8
DK		 687{
688 u8 temp_code;
689 int temp;
690
691 mutex_lock(&data->lock);
692 clk_enable(data->clk);
693
f22d9c03 694 temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
9d97e5c8
DK		 695 temp = code_to_temp(data, temp_code);
696
697 clk_disable(data->clk);
698 mutex_unlock(&data->lock);
699
700 return temp;
701}
702
f22d9c03 703static void exynos_tmu_work(struct work_struct *work)
9d97e5c8 704{
f22d9c03
ADK		 705 struct exynos_tmu_data *data = container_of(work,
706 struct exynos_tmu_data, irq_work);
9d97e5c8
DK		 707
708 mutex_lock(&data->lock);
709 clk_enable(data->clk);
710
9d97e5c8 711
f22d9c03
ADK		 712 if (data->soc == SOC_ARCH_EXYNOS)
713 writel(EXYNOS_TMU_CLEAR_RISE_INT,
714 data->base + EXYNOS_TMU_REG_INTCLEAR);
715 else
716 writel(EXYNOS4210_TMU_INTCLEAR_VAL,
717 data->base + EXYNOS_TMU_REG_INTCLEAR);
9d97e5c8
DK		 718
719 clk_disable(data->clk);
720 mutex_unlock(&data->lock);
7e0b55e6 721 exynos_report_trigger();
f22d9c03 722 enable_irq(data->irq);
9d97e5c8
DK		 723}
724
f22d9c03 725static irqreturn_t exynos_tmu_irq(int irq, void *id)
9d97e5c8 726{
f22d9c03 727 struct exynos_tmu_data *data = id;
9d97e5c8
DK		 728
729 disable_irq_nosync(irq);
730 schedule_work(&data->irq_work);
731
732 return IRQ_HANDLED;
733}
7e0b55e6
ADK		 734static struct thermal_sensor_conf exynos_sensor_conf = {
735 .name = "exynos-therm",
736 .read_temperature = (int (*)(void *))exynos_tmu_read,
17be868e
ADK		 737};
738
739#if defined(CONFIG_CPU_EXYNOS4210)
740static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
741 .threshold = 80,
742 .trigger_levels[0] = 5,
743 .trigger_levels[1] = 20,
744 .trigger_levels[2] = 30,
745 .trigger_level0_en = 1,
746 .trigger_level1_en = 1,
747 .trigger_level2_en = 1,
748 .trigger_level3_en = 0,
749 .gain = 15,
750 .reference_voltage = 7,
751 .cal_type = TYPE_ONE_POINT_TRIMMING,
752 .freq_tab[0] = {
753 .freq_clip_max = 800 * 1000,
754 .temp_level = 85,
755 },
756 .freq_tab[1] = {
757 .freq_clip_max = 200 * 1000,
758 .temp_level = 100,
759 },
760 .freq_tab_count = 2,
761 .type = SOC_ARCH_EXYNOS4210,
762};
763#define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
764#else
765#define EXYNOS4210_TMU_DRV_DATA (NULL)
766#endif
767
768#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
769static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
770 .trigger_levels[0] = 85,
771 .trigger_levels[1] = 103,
772 .trigger_levels[2] = 110,
773 .trigger_level0_en = 1,
774 .trigger_level1_en = 1,
775 .trigger_level2_en = 1,
776 .trigger_level3_en = 0,
777 .gain = 8,
778 .reference_voltage = 16,
779 .noise_cancel_mode = 4,
780 .cal_type = TYPE_ONE_POINT_TRIMMING,
781 .efuse_value = 55,
782 .freq_tab[0] = {
783 .freq_clip_max = 800 * 1000,
784 .temp_level = 85,
785 },
786 .freq_tab[1] = {
787 .freq_clip_max = 200 * 1000,
788 .temp_level = 103,
789 },
790 .freq_tab_count = 2,
791 .type = SOC_ARCH_EXYNOS,
792};
793#define EXYNOS_TMU_DRV_DATA (&exynos_default_tmu_data)
794#else
795#define EXYNOS_TMU_DRV_DATA (NULL)
796#endif
797
798#ifdef CONFIG_OF
799static const struct of_device_id exynos_tmu_match[] = {
800 {
801 .compatible = "samsung,exynos4210-tmu",
802 .data = (void *)EXYNOS4210_TMU_DRV_DATA,
803 },
804 {
805 .compatible = "samsung,exynos5250-tmu",
806 .data = (void *)EXYNOS_TMU_DRV_DATA,
807 },
808 {},
809};
810MODULE_DEVICE_TABLE(of, exynos_tmu_match);
17be868e
ADK		 811#endif
812
813static struct platform_device_id exynos_tmu_driver_ids[] = {
814 {
815 .name = "exynos4210-tmu",
816 .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
817 },
818 {
819 .name = "exynos5250-tmu",
820 .driver_data = (kernel_ulong_t)EXYNOS_TMU_DRV_DATA,
821 },
822 { },
823};
3ae53b1e 824MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
17be868e
ADK		 825
826static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
827 struct platform_device *pdev)
828{
829#ifdef CONFIG_OF
830 if (pdev->dev.of_node) {
831 const struct of_device_id *match;
832 match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
833 if (!match)
834 return NULL;
835 return (struct exynos_tmu_platform_data *) match->data;
836 }
837#endif
838 return (struct exynos_tmu_platform_data *)
839 platform_get_device_id(pdev)->driver_data;
7e0b55e6 840}
bbf63be4
JL		 841
842#ifdef CONFIG_EXYNOS_THERMAL_EMUL
843static ssize_t exynos_tmu_emulation_show(struct device *dev,
844 struct device_attribute *attr,
845 char *buf)
846{
847 struct platform_device *pdev = container_of(dev,
848 struct platform_device, dev);
849 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
850 unsigned int reg;
851 u8 temp_code;
852 int temp = 0;
853
854 if (data->soc == SOC_ARCH_EXYNOS4210)
855 goto out;
856
857 mutex_lock(&data->lock);
858 clk_enable(data->clk);
859 reg = readl(data->base + EXYNOS_EMUL_CON);
860 clk_disable(data->clk);
861 mutex_unlock(&data->lock);
862
863 if (reg & EXYNOS_EMUL_ENABLE) {
864 reg >>= EXYNOS_EMUL_DATA_SHIFT;
865 temp_code = reg & EXYNOS_EMUL_DATA_MASK;
866 temp = code_to_temp(data, temp_code);
867 }
868out:
869 return sprintf(buf, "%d\n", temp * MCELSIUS);
870}
871
872static ssize_t exynos_tmu_emulation_store(struct device *dev,
873 struct device_attribute *attr,
874 const char *buf, size_t count)
875{
876 struct platform_device *pdev = container_of(dev,
877 struct platform_device, dev);
878 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
879 unsigned int reg;
880 int temp;
881
882 if (data->soc == SOC_ARCH_EXYNOS4210)
883 goto out;
884
885 if (!sscanf(buf, "%d\n", &temp) || temp < 0)
886 return -EINVAL;
887
888 mutex_lock(&data->lock);
889 clk_enable(data->clk);
890
891 reg = readl(data->base + EXYNOS_EMUL_CON);
892
893 if (temp) {
894 /* Both CELSIUS and MCELSIUS type are available for input */
895 if (temp > MCELSIUS)
896 temp /= MCELSIUS;
897
898 reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) |
899 (temp_to_code(data, (temp / MCELSIUS))
900 << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE;
901 } else {
902 reg &= ~EXYNOS_EMUL_ENABLE;
903 }
904
905 writel(reg, data->base + EXYNOS_EMUL_CON);
906
907 clk_disable(data->clk);
908 mutex_unlock(&data->lock);
909
910out:
911 return count;
912}
913
914static DEVICE_ATTR(emulation, 0644, exynos_tmu_emulation_show,
915 exynos_tmu_emulation_store);
916static int create_emulation_sysfs(struct device *dev)
917{
918 return device_create_file(dev, &dev_attr_emulation);
919}
920static void remove_emulation_sysfs(struct device *dev)
921{
922 device_remove_file(dev, &dev_attr_emulation);
923}
924#else
925static inline int create_emulation_sysfs(struct device *dev) { return 0; }
926static inline void remove_emulation_sysfs(struct device *dev) {}
927#endif
928
f22d9c03 929static int __devinit exynos_tmu_probe(struct platform_device *pdev)
9d97e5c8 930{
f22d9c03
ADK		 931 struct exynos_tmu_data *data;
932 struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
7e0b55e6 933 int ret, i;
9d97e5c8 934
17be868e
ADK		 935 if (!pdata)
936 pdata = exynos_get_driver_data(pdev);
937
9d97e5c8
DK		 938 if (!pdata) {
939 dev_err(&pdev->dev, "No platform init data supplied.\n");
940 return -ENODEV;
941 }
79e093c3
ADK		 942 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
943 GFP_KERNEL);
9d97e5c8
DK		 944 if (!data) {
945 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
946 return -ENOMEM;
947 }
948
949 data->irq = platform_get_irq(pdev, 0);
950 if (data->irq < 0) {
9d97e5c8 951 dev_err(&pdev->dev, "Failed to get platform irq\n");
79e093c3 952 return data->irq;
9d97e5c8
DK		 953 }
954
f22d9c03 955 INIT_WORK(&data->irq_work, exynos_tmu_work);
9d97e5c8
DK		 956
957 data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
958 if (!data->mem) {
9d97e5c8 959 dev_err(&pdev->dev, "Failed to get platform resource\n");
79e093c3 960 return -ENOENT;
9d97e5c8
DK		 961 }
962
79e093c3 963 data->base = devm_request_and_ioremap(&pdev->dev, data->mem);
9d97e5c8 964 if (!data->base) {
9d97e5c8 965 dev_err(&pdev->dev, "Failed to ioremap memory\n");
79e093c3 966 return -ENODEV;
9d97e5c8
DK		 967 }
968
79e093c3 969 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
f22d9c03 970 IRQF_TRIGGER_RISING, "exynos-tmu", data);
9d97e5c8
DK		 971 if (ret) {
972 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
79e093c3 973 return ret;
9d97e5c8
DK		 974 }
975
976 data->clk = clk_get(NULL, "tmu_apbif");
977 if (IS_ERR(data->clk)) {
9d97e5c8 978 dev_err(&pdev->dev, "Failed to get clock\n");
79e093c3 979 return PTR_ERR(data->clk);
9d97e5c8
DK		 980 }
981
f22d9c03
ADK		 982 if (pdata->type == SOC_ARCH_EXYNOS ||
983 pdata->type == SOC_ARCH_EXYNOS4210)
984 data->soc = pdata->type;
985 else {
986 ret = -EINVAL;
987 dev_err(&pdev->dev, "Platform not supported\n");
988 goto err_clk;
989 }
990
9d97e5c8
DK		 991 data->pdata = pdata;
992 platform_set_drvdata(pdev, data);
993 mutex_init(&data->lock);
994
f22d9c03 995 ret = exynos_tmu_initialize(pdev);
9d97e5c8
DK		 996 if (ret) {
997 dev_err(&pdev->dev, "Failed to initialize TMU\n");
998 goto err_clk;
999 }
1000
f22d9c03 1001 exynos_tmu_control(pdev, true);
9d97e5c8 1002
7e0b55e6
ADK		 1003 /* Register the sensor with thermal management interface */
1004 (&exynos_sensor_conf)->private_data = data;
1005 exynos_sensor_conf.trip_data.trip_count = pdata->trigger_level0_en +
1006 pdata->trigger_level1_en + pdata->trigger_level2_en +
1007 pdata->trigger_level3_en;
1008
1009 for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
1010 exynos_sensor_conf.trip_data.trip_val[i] =
1011 pdata->threshold + pdata->trigger_levels[i];
1012
1013 exynos_sensor_conf.cooling_data.freq_clip_count =
1014 pdata->freq_tab_count;
1015 for (i = 0; i < pdata->freq_tab_count; i++) {
1016 exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
1017 pdata->freq_tab[i].freq_clip_max;
1018 exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
1019 pdata->freq_tab[i].temp_level;
1020 }
1021
1022 ret = exynos_register_thermal(&exynos_sensor_conf);
1023 if (ret) {
1024 dev_err(&pdev->dev, "Failed to register thermal interface\n");
1025 goto err_clk;
1026 }
bbf63be4
JL		 1027
1028 ret = create_emulation_sysfs(&pdev->dev);
1029 if (ret)
1030 dev_err(&pdev->dev, "Failed to create emulation mode sysfs node\n");
1031
9d97e5c8 1032 return 0;
9d97e5c8
DK		 1033err_clk:
1034 platform_set_drvdata(pdev, NULL);
1035 clk_put(data->clk);
9d97e5c8
DK		 1036 return ret;
1037}
1038
f22d9c03 1039static int __devexit exynos_tmu_remove(struct platform_device *pdev)
9d97e5c8 1040{
f22d9c03 1041 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
9d97e5c8 1042
bbf63be4
JL		 1043 remove_emulation_sysfs(&pdev->dev);
1044
f22d9c03 1045 exynos_tmu_control(pdev, false);
9d97e5c8 1046
7e0b55e6
ADK		 1047 exynos_unregister_thermal();
1048
9d97e5c8
DK		 1049 clk_put(data->clk);
1050
9d97e5c8
DK		 1051 platform_set_drvdata(pdev, NULL);
1052
9d97e5c8
DK		 1053 return 0;
1054}
1055
08cd6753 1056#ifdef CONFIG_PM_SLEEP
f22d9c03 1057static int exynos_tmu_suspend(struct device *dev)
9d97e5c8 1058{
f22d9c03 1059 exynos_tmu_control(to_platform_device(dev), false);
9d97e5c8
DK		 1060
1061 return 0;
1062}
1063
f22d9c03 1064static int exynos_tmu_resume(struct device *dev)
9d97e5c8 1065{
08cd6753
RW		 1066 struct platform_device *pdev = to_platform_device(dev);
1067
f22d9c03
ADK		 1068 exynos_tmu_initialize(pdev);
1069 exynos_tmu_control(pdev, true);
9d97e5c8
DK		 1070
1071 return 0;
1072}
08cd6753 1073
f22d9c03
ADK		 1074static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1075 exynos_tmu_suspend, exynos_tmu_resume);
1076#define EXYNOS_TMU_PM (&exynos_tmu_pm)
9d97e5c8 1077#else
f22d9c03 1078#define EXYNOS_TMU_PM NULL
9d97e5c8
DK		 1079#endif
1080
f22d9c03 1081static struct platform_driver exynos_tmu_driver = {
9d97e5c8 1082 .driver = {
f22d9c03 1083 .name = "exynos-tmu",
9d97e5c8 1084 .owner = THIS_MODULE,
f22d9c03 1085 .pm = EXYNOS_TMU_PM,
caa5cbd5 1086 .of_match_table = of_match_ptr(exynos_tmu_match),
9d97e5c8 1087 },
f22d9c03
ADK		 1088 .probe = exynos_tmu_probe,
1089 .remove = __devexit_p(exynos_tmu_remove),
17be868e 1090 .id_table = exynos_tmu_driver_ids,
9d97e5c8
DK		 1091};
1092
f22d9c03 1093module_platform_driver(exynos_tmu_driver);
9d97e5c8 1094
f22d9c03 1095MODULE_DESCRIPTION("EXYNOS TMU Driver");
9d97e5c8
DK		 1096MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1097MODULE_LICENSE("GPL");
f22d9c03 1098MODULE_ALIAS("platform:exynos-tmu");
Linux kernel - Deliverables
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