[deliverable/linux.git] / drivers / thermal / intel_quark_dts_thermal.c

/*
 * intel_quark_dts_thermal.c
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2015 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * Contact Information:
 *  Ong Boon Leong <boon.leong.ong@intel.com>
 *  Intel Malaysia, Penang
 *
 * BSD LICENSE
 *
 * Copyright(c) 2015 Intel Corporation.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   * Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   * Neither the name of Intel Corporation nor the names of its
 *     contributors may be used to endorse or promote products derived
 *     from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Quark DTS thermal driver is implemented by referencing
 * intel_soc_dts_thermal.c.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/thermal.h>
#include <asm/cpu_device_id.h>
#include <asm/iosf_mbi.h>

#define X86_FAMILY_QUARK	0x5
#define X86_MODEL_QUARK_X1000	0x9

/* DTS reset is programmed via QRK_MBI_UNIT_SOC */
#define QRK_DTS_REG_OFFSET_RESET	0x34
#define QRK_DTS_RESET_BIT		BIT(0)

/* DTS enable is programmed via QRK_MBI_UNIT_RMU */
#define QRK_DTS_REG_OFFSET_ENABLE	0xB0
#define QRK_DTS_ENABLE_BIT		BIT(15)

/* Temperature Register is read via QRK_MBI_UNIT_RMU */
#define QRK_DTS_REG_OFFSET_TEMP		0xB1
#define QRK_DTS_MASK_TEMP		0xFF
#define QRK_DTS_OFFSET_TEMP		0
#define QRK_DTS_OFFSET_REL_TEMP		16
#define QRK_DTS_TEMP_BASE		50

/* Programmable Trip Point Register is configured via QRK_MBI_UNIT_RMU */
#define QRK_DTS_REG_OFFSET_PTPS		0xB2
#define QRK_DTS_MASK_TP_THRES		0xFF
#define QRK_DTS_SHIFT_TP		8
#define QRK_DTS_ID_TP_CRITICAL		0
#define QRK_DTS_SAFE_TP_THRES		105

/* Thermal Sensor Register Lock */
#define QRK_DTS_REG_OFFSET_LOCK		0x71
#define QRK_DTS_LOCK_BIT		BIT(5)

/* Quark DTS has 2 trip points: hot & catastrophic */
#define QRK_MAX_DTS_TRIPS	2
/* If DTS not locked, all trip points are configurable */
#define QRK_DTS_WR_MASK_SET	0x3
/* If DTS locked, all trip points are not configurable */
#define QRK_DTS_WR_MASK_CLR	0

#define DEFAULT_POLL_DELAY	2000

struct soc_sensor_entry {
	bool locked;
	u32 store_ptps;
	u32 store_dts_enable;
	enum thermal_device_mode mode;
	struct thermal_zone_device *tzone;
};

static struct soc_sensor_entry *soc_dts;

static int polling_delay = DEFAULT_POLL_DELAY;
module_param(polling_delay, int, 0644);
MODULE_PARM_DESC(polling_delay,
	"Polling interval for checking trip points (in milliseconds)");

static DEFINE_MUTEX(dts_update_mutex);

static int soc_dts_enable(struct thermal_zone_device *tzd)
{
	u32 out;
	struct soc_sensor_entry *aux_entry = tzd->devdata;
	int ret;

	ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
					QRK_DTS_REG_OFFSET_ENABLE, &out);
	if (ret)
		return ret;

	if (out & QRK_DTS_ENABLE_BIT) {
		aux_entry->mode = THERMAL_DEVICE_ENABLED;
		return 0;
	}

	if (!aux_entry->locked) {
		out |= QRK_DTS_ENABLE_BIT;
		ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
					QRK_DTS_REG_OFFSET_ENABLE, out);
		if (ret)
			return ret;

		aux_entry->mode = THERMAL_DEVICE_ENABLED;
	} else {
		aux_entry->mode = THERMAL_DEVICE_DISABLED;
		pr_info("DTS is locked. Cannot enable DTS\n");
		ret = -EPERM;
	}

	return ret;
}

static int soc_dts_disable(struct thermal_zone_device *tzd)
{
	u32 out;
	struct soc_sensor_entry *aux_entry = tzd->devdata;
	int ret;

	ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
					QRK_DTS_REG_OFFSET_ENABLE, &out);
	if (ret)
		return ret;

	if (!(out & QRK_DTS_ENABLE_BIT)) {
		aux_entry->mode = THERMAL_DEVICE_DISABLED;
		return 0;
	}

	if (!aux_entry->locked) {
		out &= ~QRK_DTS_ENABLE_BIT;
		ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
					QRK_DTS_REG_OFFSET_ENABLE, out);

		if (ret)
			return ret;

		aux_entry->mode = THERMAL_DEVICE_DISABLED;
	} else {
		aux_entry->mode = THERMAL_DEVICE_ENABLED;
		pr_info("DTS is locked. Cannot disable DTS\n");
		ret = -EPERM;
	}

	return ret;
}

static int _get_trip_temp(int trip, unsigned long *temp)
{
	int status;
	u32 out;

	mutex_lock(&dts_update_mutex);
	status = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
				QRK_DTS_REG_OFFSET_PTPS, &out);
	mutex_unlock(&dts_update_mutex);

	if (status)
		return status;

	/*
	 * Thermal Sensor Programmable Trip Point Register has 8-bit
	 * fields for critical (catastrophic) and hot set trip point
	 * thresholds. The threshold value is always offset by its
	 * temperature base (50 degree Celsius).
	 */
	*temp = (out >> (trip * QRK_DTS_SHIFT_TP)) & QRK_DTS_MASK_TP_THRES;
	*temp -= QRK_DTS_TEMP_BASE;

	return 0;
}

static inline int sys_get_trip_temp(struct thermal_zone_device *tzd,
				int trip, unsigned long *temp)
{
	return _get_trip_temp(trip, temp);
}

static inline int sys_get_crit_temp(struct thermal_zone_device *tzd,
				unsigned long *temp)
{
	return _get_trip_temp(QRK_DTS_ID_TP_CRITICAL, temp);
}

static int update_trip_temp(struct soc_sensor_entry *aux_entry,
				int trip, unsigned long temp)
{
	u32 out;
	u32 temp_out;
	u32 store_ptps;
	int ret;

	mutex_lock(&dts_update_mutex);
	if (aux_entry->locked) {
		ret = -EPERM;
		goto failed;
	}

	ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
				QRK_DTS_REG_OFFSET_PTPS, &store_ptps);
	if (ret)
		goto failed;

	/*
	 * Protection against unsafe trip point thresdhold value.
	 * As Quark X1000 data-sheet does not provide any recommendation
	 * regarding the safe trip point threshold value to use, we choose
	 * the safe value according to the threshold value set by UEFI BIOS.
	 */
	if (temp > QRK_DTS_SAFE_TP_THRES)
		temp = QRK_DTS_SAFE_TP_THRES;

	/*
	 * Thermal Sensor Programmable Trip Point Register has 8-bit
	 * fields for critical (catastrophic) and hot set trip point
	 * thresholds. The threshold value is always offset by its
	 * temperature base (50 degree Celsius).
	 */
	temp_out = temp + QRK_DTS_TEMP_BASE;
	out = (store_ptps & ~(QRK_DTS_MASK_TP_THRES <<
		(trip * QRK_DTS_SHIFT_TP)));
	out |= (temp_out & QRK_DTS_MASK_TP_THRES) <<
		(trip * QRK_DTS_SHIFT_TP);

	ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
				QRK_DTS_REG_OFFSET_PTPS, out);

failed:
	mutex_unlock(&dts_update_mutex);
	return ret;
}

static inline int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip,
				unsigned long temp)
{
	return update_trip_temp(tzd->devdata, trip, temp);
}

static int sys_get_trip_type(struct thermal_zone_device *thermal,
		int trip, enum thermal_trip_type *type)
{
	if (trip)
		*type = THERMAL_TRIP_HOT;
	else
		*type = THERMAL_TRIP_CRITICAL;

	return 0;
}

static int sys_get_curr_temp(struct thermal_zone_device *tzd,
				unsigned long *temp)
{
	u32 out;
	int ret;

	mutex_lock(&dts_update_mutex);
	ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
					QRK_DTS_REG_OFFSET_TEMP, &out);
	mutex_unlock(&dts_update_mutex);

	if (ret)
		return ret;

	/*
	 * Thermal Sensor Temperature Register has 8-bit field
	 * for temperature value (offset by temperature base
	 * 50 degree Celsius).
	 */
	out = (out >> QRK_DTS_OFFSET_TEMP) & QRK_DTS_MASK_TEMP;
	*temp = out - QRK_DTS_TEMP_BASE;

	return 0;
}

static int sys_get_mode(struct thermal_zone_device *tzd,
				enum thermal_device_mode *mode)
{
	struct soc_sensor_entry *aux_entry = tzd->devdata;
	*mode = aux_entry->mode;
	return 0;
}

static int sys_set_mode(struct thermal_zone_device *tzd,
				enum thermal_device_mode mode)
{
	int ret;

	mutex_lock(&dts_update_mutex);
	if (mode == THERMAL_DEVICE_ENABLED)
		ret = soc_dts_enable(tzd);
	else
		ret = soc_dts_disable(tzd);
	mutex_unlock(&dts_update_mutex);

	return ret;
}

static struct thermal_zone_device_ops tzone_ops = {
	.get_temp = sys_get_curr_temp,
	.get_trip_temp = sys_get_trip_temp,
	.get_trip_type = sys_get_trip_type,
	.set_trip_temp = sys_set_trip_temp,
	.get_crit_temp = sys_get_crit_temp,
	.get_mode = sys_get_mode,
	.set_mode = sys_set_mode,
};

static void free_soc_dts(struct soc_sensor_entry *aux_entry)
{
	if (aux_entry) {
		if (!aux_entry->locked) {
			mutex_lock(&dts_update_mutex);
			iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
					QRK_DTS_REG_OFFSET_ENABLE,
					aux_entry->store_dts_enable);

			iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
					QRK_DTS_REG_OFFSET_PTPS,
					aux_entry->store_ptps);
			mutex_unlock(&dts_update_mutex);
		}
		thermal_zone_device_unregister(aux_entry->tzone);
		kfree(aux_entry);
	}
}

static struct soc_sensor_entry *alloc_soc_dts(void)
{
	struct soc_sensor_entry *aux_entry;
	int err;
	u32 out;
	int wr_mask;

	aux_entry = kzalloc(sizeof(*aux_entry), GFP_KERNEL);
	if (!aux_entry) {
		err = -ENOMEM;
		return ERR_PTR(-ENOMEM);
	}

	/* Check if DTS register is locked */
	err = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
					QRK_DTS_REG_OFFSET_LOCK,
					&out);
	if (err)
		goto err_ret;

	if (out & QRK_DTS_LOCK_BIT) {
		aux_entry->locked = true;
		wr_mask = QRK_DTS_WR_MASK_CLR;
	} else {
		aux_entry->locked = false;
		wr_mask = QRK_DTS_WR_MASK_SET;
	}

	/* Store DTS default state if DTS registers are not locked */
	if (!aux_entry->locked) {
		/* Store DTS default enable for restore on exit */
		err = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
					QRK_DTS_REG_OFFSET_ENABLE,
					&aux_entry->store_dts_enable);
		if (err)
			goto err_ret;

		/* Store DTS default PTPS register for restore on exit */
		err = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
					QRK_DTS_REG_OFFSET_PTPS,
					&aux_entry->store_ptps);
		if (err)
			goto err_ret;
	}

	aux_entry->tzone = thermal_zone_device_register("quark_dts",
			QRK_MAX_DTS_TRIPS,
			wr_mask,
			aux_entry, &tzone_ops, NULL, 0, polling_delay);
	if (IS_ERR(aux_entry->tzone)) {
		err = PTR_ERR(aux_entry->tzone);
		goto err_ret;
	}

	mutex_lock(&dts_update_mutex);
	err = soc_dts_enable(aux_entry->tzone);
	mutex_unlock(&dts_update_mutex);
	if (err)
		goto err_aux_status;

	return aux_entry;

err_aux_status:
	thermal_zone_device_unregister(aux_entry->tzone);
err_ret:
	kfree(aux_entry);
	return ERR_PTR(err);
}

static const struct x86_cpu_id qrk_thermal_ids[] __initconst  = {
	{ X86_VENDOR_INTEL, X86_FAMILY_QUARK, X86_MODEL_QUARK_X1000 },
	{}
};
MODULE_DEVICE_TABLE(x86cpu, qrk_thermal_ids);

static int __init intel_quark_thermal_init(void)
{
	int err = 0;

	if (!x86_match_cpu(qrk_thermal_ids) || !iosf_mbi_available())
		return -ENODEV;

	soc_dts = alloc_soc_dts();
	if (IS_ERR(soc_dts)) {
		err = PTR_ERR(soc_dts);
		goto err_free;
	}

	return 0;

err_free:
	free_soc_dts(soc_dts);
	return err;
}

static void __exit intel_quark_thermal_exit(void)
{
	free_soc_dts(soc_dts);
}

module_init(intel_quark_thermal_init)
module_exit(intel_quark_thermal_exit)

MODULE_DESCRIPTION("Intel Quark DTS Thermal Driver");
MODULE_AUTHOR("Ong Boon Leong <boon.leong.ong@intel.com>");
MODULE_LICENSE("Dual BSD/GPL");
Commit	Line	Data
8c187693 OBL	1	/*
	2	* intel_quark_dts_thermal.c
	3	*
	4	* This file is provided under a dual BSD/GPLv2 license. When using or
	5	* redistributing this file, you may do so under either license.
	6	*
	7	* GPL LICENSE SUMMARY
	8	*
	9	* Copyright(c) 2015 Intel Corporation.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of version 2 of the GNU General Public License as
	13	* published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* Contact Information:
	21	* Ong Boon Leong <boon.leong.ong@intel.com>
	22	* Intel Malaysia, Penang
	23	*
	24	* BSD LICENSE
	25	*
	26	* Copyright(c) 2015 Intel Corporation.
	27	*
	28	* Redistribution and use in source and binary forms, with or without
	29	* modification, are permitted provided that the following conditions
	30	* are met:
	31	*
	32	* * Redistributions of source code must retain the above copyright
	33	* notice, this list of conditions and the following disclaimer.
	34	* * Redistributions in binary form must reproduce the above copyright
	35	* notice, this list of conditions and the following disclaimer in
	36	* the documentation and/or other materials provided with the
	37	* distribution.
	38	* * Neither the name of Intel Corporation nor the names of its
	39	* contributors may be used to endorse or promote products derived
	40	* from this software without specific prior written permission.
	41	*
	42	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	43	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	44	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	45	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	46	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	47	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	48	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	49	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	50	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	51	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	52	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	53	*
	54	* Quark DTS thermal driver is implemented by referencing
	55	* intel_soc_dts_thermal.c.
	56	*/
	57
	58	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	59
	60	#include <linux/module.h>
	61	#include <linux/slab.h>
	62	#include <linux/interrupt.h>
	63	#include <linux/thermal.h>
	64	#include <asm/cpu_device_id.h>
65	#include <asm/iosf_mbi.h>
66
67	#define X86_FAMILY_QUARK 0x5
68	#define X86_MODEL_QUARK_X1000 0x9
69
70	/* DTS reset is programmed via QRK_MBI_UNIT_SOC */
71	#define QRK_DTS_REG_OFFSET_RESET 0x34
72	#define QRK_DTS_RESET_BIT BIT(0)
73
74	/* DTS enable is programmed via QRK_MBI_UNIT_RMU */
75	#define QRK_DTS_REG_OFFSET_ENABLE 0xB0
76	#define QRK_DTS_ENABLE_BIT BIT(15)
77
78	/* Temperature Register is read via QRK_MBI_UNIT_RMU */
79	#define QRK_DTS_REG_OFFSET_TEMP 0xB1
80	#define QRK_DTS_MASK_TEMP 0xFF
81	#define QRK_DTS_OFFSET_TEMP 0
82	#define QRK_DTS_OFFSET_REL_TEMP 16
83	#define QRK_DTS_TEMP_BASE 50
84
85	/* Programmable Trip Point Register is configured via QRK_MBI_UNIT_RMU */
86	#define QRK_DTS_REG_OFFSET_PTPS 0xB2
87	#define QRK_DTS_MASK_TP_THRES 0xFF
88	#define QRK_DTS_SHIFT_TP 8
89	#define QRK_DTS_ID_TP_CRITICAL 0
90	#define QRK_DTS_SAFE_TP_THRES 105
91
92	/* Thermal Sensor Register Lock */
93	#define QRK_DTS_REG_OFFSET_LOCK 0x71
94	#define QRK_DTS_LOCK_BIT BIT(5)
95
96	/* Quark DTS has 2 trip points: hot & catastrophic */
97	#define QRK_MAX_DTS_TRIPS 2
98	/* If DTS not locked, all trip points are configurable */
99	#define QRK_DTS_WR_MASK_SET 0x3
100	/* If DTS locked, all trip points are not configurable */
101	#define QRK_DTS_WR_MASK_CLR 0
102
103	#define DEFAULT_POLL_DELAY 2000
104
105	struct soc_sensor_entry {
106	bool locked;
107	u32 store_ptps;
108	u32 store_dts_enable;
109	enum thermal_device_mode mode;
110	struct thermal_zone_device *tzone;
111	};
112
113	static struct soc_sensor_entry *soc_dts;
114
115	static int polling_delay = DEFAULT_POLL_DELAY;
116	module_param(polling_delay, int, 0644);
117	MODULE_PARM_DESC(polling_delay,
118	"Polling interval for checking trip points (in milliseconds)");
119
120	static DEFINE_MUTEX(dts_update_mutex);
121
122	static int soc_dts_enable(struct thermal_zone_device *tzd)
123	{
124	u32 out;
125	struct soc_sensor_entry *aux_entry = tzd->devdata;
126	int ret;
127
128	ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
129	QRK_DTS_REG_OFFSET_ENABLE, &out);
130	if (ret)
131	return ret;
132
133	if (out & QRK_DTS_ENABLE_BIT) {
134	aux_entry->mode = THERMAL_DEVICE_ENABLED;
135	return 0;
136	}
137
138	if (!aux_entry->locked) {
139	out \|= QRK_DTS_ENABLE_BIT;
140	ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
141	QRK_DTS_REG_OFFSET_ENABLE, out);
142	if (ret)
143	return ret;
144
145	aux_entry->mode = THERMAL_DEVICE_ENABLED;
146	} else {
147	aux_entry->mode = THERMAL_DEVICE_DISABLED;
148	pr_info("DTS is locked. Cannot enable DTS\n");
149	ret = -EPERM;
150	}
151
152	return ret;
153	}
154
155	static int soc_dts_disable(struct thermal_zone_device *tzd)
156	{
157	u32 out;
158	struct soc_sensor_entry *aux_entry = tzd->devdata;
159	int ret;
160
161	ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
162	QRK_DTS_REG_OFFSET_ENABLE, &out);
163	if (ret)
164	return ret;
165
166	if (!(out & QRK_DTS_ENABLE_BIT)) {
167	aux_entry->mode = THERMAL_DEVICE_DISABLED;
168	return 0;
169	}
170
171	if (!aux_entry->locked) {
172	out &= ~QRK_DTS_ENABLE_BIT;
173	ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
174	QRK_DTS_REG_OFFSET_ENABLE, out);
175
176	if (ret)
177	return ret;
178
179	aux_entry->mode = THERMAL_DEVICE_DISABLED;
180	} else {
181	aux_entry->mode = THERMAL_DEVICE_ENABLED;
182	pr_info("DTS is locked. Cannot disable DTS\n");
183	ret = -EPERM;
184	}
185
186	return ret;
187	}
188
189	static int _get_trip_temp(int trip, unsigned long *temp)
190	{
191	int status;
192	u32 out;
193
194	mutex_lock(&dts_update_mutex);
195	status = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
196	QRK_DTS_REG_OFFSET_PTPS, &out);
197	mutex_unlock(&dts_update_mutex);
198
199	if (status)
200	return status;
201
202	/*
203	* Thermal Sensor Programmable Trip Point Register has 8-bit
204	* fields for critical (catastrophic) and hot set trip point
205	* thresholds. The threshold value is always offset by its
206	* temperature base (50 degree Celsius).
207	*/
208	temp = (out >> (trip QRK_DTS_SHIFT_TP)) & QRK_DTS_MASK_TP_THRES;
209	*temp -= QRK_DTS_TEMP_BASE;
210
211	return 0;
212	}
213
214	static inline int sys_get_trip_temp(struct thermal_zone_device *tzd,
215	int trip, unsigned long *temp)
216	{
217	return _get_trip_temp(trip, temp);
218	}
219
220	static inline int sys_get_crit_temp(struct thermal_zone_device *tzd,
221	unsigned long *temp)
222	{
223	return _get_trip_temp(QRK_DTS_ID_TP_CRITICAL, temp);
224	}
225
226	static int update_trip_temp(struct soc_sensor_entry *aux_entry,
227	int trip, unsigned long temp)
228	{
229	u32 out;
230	u32 temp_out;
231	u32 store_ptps;
232	int ret;
233
234	mutex_lock(&dts_update_mutex);
235	if (aux_entry->locked) {
236	ret = -EPERM;
237	goto failed;
238	}
239
240	ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
241	QRK_DTS_REG_OFFSET_PTPS, &store_ptps);
242	if (ret)
243	goto failed;
244
245	/*
246	* Protection against unsafe trip point thresdhold value.
247	* As Quark X1000 data-sheet does not provide any recommendation
248	* regarding the safe trip point threshold value to use, we choose
249	* the safe value according to the threshold value set by UEFI BIOS.
250	*/
251	if (temp > QRK_DTS_SAFE_TP_THRES)
252	temp = QRK_DTS_SAFE_TP_THRES;
253
254	/*
255	* Thermal Sensor Programmable Trip Point Register has 8-bit
256	* fields for critical (catastrophic) and hot set trip point
257	* thresholds. The threshold value is always offset by its
258	* temperature base (50 degree Celsius).
259	*/
260	temp_out = temp + QRK_DTS_TEMP_BASE;
261	out = (store_ptps & ~(QRK_DTS_MASK_TP_THRES <<
262	(trip * QRK_DTS_SHIFT_TP)));
263	out \|= (temp_out & QRK_DTS_MASK_TP_THRES) <<
264	(trip * QRK_DTS_SHIFT_TP);
265
266	ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
267	QRK_DTS_REG_OFFSET_PTPS, out);
268
269	failed:
270	mutex_unlock(&dts_update_mutex);
271	return ret;
272	}
273
274	static inline int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip,
275	unsigned long temp)
276	{
277	return update_trip_temp(tzd->devdata, trip, temp);
278	}
279
280	static int sys_get_trip_type(struct thermal_zone_device *thermal,
281	int trip, enum thermal_trip_type *type)
282	{
283	if (trip)
284	*type = THERMAL_TRIP_HOT;
285	else
286	*type = THERMAL_TRIP_CRITICAL;
287
288	return 0;
289	}
290
291	static int sys_get_curr_temp(struct thermal_zone_device *tzd,
292	unsigned long *temp)
293	{
294	u32 out;
295	int ret;
296
297	mutex_lock(&dts_update_mutex);
298	ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
299	QRK_DTS_REG_OFFSET_TEMP, &out);
300	mutex_unlock(&dts_update_mutex);
301
302	if (ret)
303	return ret;
304
305	/*
306	* Thermal Sensor Temperature Register has 8-bit field
307	* for temperature value (offset by temperature base
308	* 50 degree Celsius).
309	*/
310	out = (out >> QRK_DTS_OFFSET_TEMP) & QRK_DTS_MASK_TEMP;
311	*temp = out - QRK_DTS_TEMP_BASE;
312
313	return 0;
314	}
315
316	static int sys_get_mode(struct thermal_zone_device *tzd,
317	enum thermal_device_mode *mode)
318	{
319	struct soc_sensor_entry *aux_entry = tzd->devdata;
320	*mode = aux_entry->mode;
321	return 0;
322	}
323
324	static int sys_set_mode(struct thermal_zone_device *tzd,
325	enum thermal_device_mode mode)
326	{
327	int ret;
328
329	mutex_lock(&dts_update_mutex);
330	if (mode == THERMAL_DEVICE_ENABLED)
331	ret = soc_dts_enable(tzd);
332	else
333	ret = soc_dts_disable(tzd);
334	mutex_unlock(&dts_update_mutex);
335
336	return ret;
337	}
338
339	static struct thermal_zone_device_ops tzone_ops = {
340	.get_temp = sys_get_curr_temp,
341	.get_trip_temp = sys_get_trip_temp,
342	.get_trip_type = sys_get_trip_type,
343	.set_trip_temp = sys_set_trip_temp,
344	.get_crit_temp = sys_get_crit_temp,
345	.get_mode = sys_get_mode,
346	.set_mode = sys_set_mode,
347	};
348
349	static void free_soc_dts(struct soc_sensor_entry *aux_entry)
350	{
351	if (aux_entry) {
352	if (!aux_entry->locked) {
353	mutex_lock(&dts_update_mutex);
354	iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
355	QRK_DTS_REG_OFFSET_ENABLE,
356	aux_entry->store_dts_enable);
357
358	iosf_mbi_write(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_WRITE,
359	QRK_DTS_REG_OFFSET_PTPS,
360	aux_entry->store_ptps);
361	mutex_unlock(&dts_update_mutex);
362	}
363	thermal_zone_device_unregister(aux_entry->tzone);
364	kfree(aux_entry);
365	}
366	}
367
368	static struct soc_sensor_entry *alloc_soc_dts(void)
369	{
370	struct soc_sensor_entry *aux_entry;
371	int err;
372	u32 out;
373	int wr_mask;
374
375	aux_entry = kzalloc(sizeof(*aux_entry), GFP_KERNEL);
376	if (!aux_entry) {
377	err = -ENOMEM;
378	return ERR_PTR(-ENOMEM);
379	}
380
381	/* Check if DTS register is locked */
382	err = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
383	QRK_DTS_REG_OFFSET_LOCK,
384	&out);
385	if (err)
386	goto err_ret;
387
388	if (out & QRK_DTS_LOCK_BIT) {
389	aux_entry->locked = true;
390	wr_mask = QRK_DTS_WR_MASK_CLR;
391	} else {
392	aux_entry->locked = false;
393	wr_mask = QRK_DTS_WR_MASK_SET;
394	}
395
396	/* Store DTS default state if DTS registers are not locked */
397	if (!aux_entry->locked) {
398	/* Store DTS default enable for restore on exit */
399	err = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
400	QRK_DTS_REG_OFFSET_ENABLE,
401	&aux_entry->store_dts_enable);
402	if (err)
403	goto err_ret;
404
405	/* Store DTS default PTPS register for restore on exit */
406	err = iosf_mbi_read(QRK_MBI_UNIT_RMU, QRK_MBI_RMU_READ,
407	QRK_DTS_REG_OFFSET_PTPS,
408	&aux_entry->store_ptps);
409	if (err)
410	goto err_ret;
411	}
412
413	aux_entry->tzone = thermal_zone_device_register("quark_dts",
414	QRK_MAX_DTS_TRIPS,
415	wr_mask,
416	aux_entry, &tzone_ops, NULL, 0, polling_delay);
417	if (IS_ERR(aux_entry->tzone)) {
418	err = PTR_ERR(aux_entry->tzone);
419	goto err_ret;
420	}
421
422	mutex_lock(&dts_update_mutex);
423	err = soc_dts_enable(aux_entry->tzone);
424	mutex_unlock(&dts_update_mutex);
425	if (err)
426	goto err_aux_status;
427
428	return aux_entry;
429
430	err_aux_status:
431	thermal_zone_device_unregister(aux_entry->tzone);
432	err_ret:
433	kfree(aux_entry);
434	return ERR_PTR(err);
435	}
436
437	static const struct x86_cpu_id qrk_thermal_ids[] __initconst = {
438	{ X86_VENDOR_INTEL, X86_FAMILY_QUARK, X86_MODEL_QUARK_X1000 },
439	{}
440	};
441	MODULE_DEVICE_TABLE(x86cpu, qrk_thermal_ids);
442
443	static int __init intel_quark_thermal_init(void)
444	{
445	int err = 0;
446
447	if (!x86_match_cpu(qrk_thermal_ids) \|\| !iosf_mbi_available())
448	return -ENODEV;
449
450	soc_dts = alloc_soc_dts();
451	if (IS_ERR(soc_dts)) {
452	err = PTR_ERR(soc_dts);
453	goto err_free;
454	}
455
456	return 0;
457
458	err_free:
459	free_soc_dts(soc_dts);
460	return err;
461	}
462
463	static void __exit intel_quark_thermal_exit(void)
464	{
465	free_soc_dts(soc_dts);
466	}
467
468	module_init(intel_quark_thermal_init)
469	module_exit(intel_quark_thermal_exit)
470
471	MODULE_DESCRIPTION("Intel Quark DTS Thermal Driver");
472	MODULE_AUTHOR("Ong Boon Leong <boon.leong.ong@intel.com>");
473	MODULE_LICENSE("Dual BSD/GPL");