[deliverable/linux.git] / drivers / thermal / samsung / exynos_tmu.h

/*
 * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
 *
 *  Copyright (C) 2011 Samsung Electronics
 *  Donggeun Kim <dg77.kim@samsung.com>
 *  Amit Daniel Kachhap <amit.daniel@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef _EXYNOS_TMU_H
#define _EXYNOS_TMU_H
#include <linux/cpu_cooling.h>

#include "exynos_thermal_common.h"

enum calibration_type {
	TYPE_ONE_POINT_TRIMMING,
	TYPE_ONE_POINT_TRIMMING_25,
	TYPE_ONE_POINT_TRIMMING_85,
	TYPE_TWO_POINT_TRIMMING,
	TYPE_NONE,
};

enum calibration_mode {
	SW_MODE,
	HW_MODE,
};

enum soc_type {
	SOC_ARCH_EXYNOS4210 = 1,
	SOC_ARCH_EXYNOS4412,
	SOC_ARCH_EXYNOS5250,
	SOC_ARCH_EXYNOS5440,
};

/**
 * EXYNOS TMU supported features.
 * TMU_SUPPORT_EMULATION - This features is used to set user defined
 *			temperature to the TMU controller.
 * TMU_SUPPORT_MULTI_INST - This features denotes that the soc
 *			has many instances of TMU.
 * TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
 *			be reloaded.
 * TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
 *			be registered for falling trips also.
 * TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
 *			state(active/idle) can be checked.
 * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
 *			sample time.
 * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
 *			sensors shares some common registers.
 * TMU_SUPPORT - macro to compare the above features with the supplied.
 */
#define TMU_SUPPORT_EMULATION			BIT(0)
#define TMU_SUPPORT_MULTI_INST			BIT(1)
#define TMU_SUPPORT_TRIM_RELOAD			BIT(2)
#define TMU_SUPPORT_FALLING_TRIP		BIT(3)
#define TMU_SUPPORT_READY_STATUS		BIT(4)
#define TMU_SUPPORT_EMUL_TIME			BIT(5)
#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)

#define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)

/**
 * struct exynos_tmu_register - register descriptors to access registers and
 * bitfields. The register validity, offsets and bitfield values may vary
 * slightly across different exynos SOC's.
 * @triminfo_data: register containing 2 pont trimming data
 * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
 * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
 * @triminfo_ctrl: trim info controller register.
 * @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl
	reg.
 * @tmu_ctrl: TMU main controller register.
 * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
 * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
 * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
 * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
 * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
 * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
	register.
 * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
 * @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl
	register.
 * @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl
	register.
 * @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in
	tmu_ctrl register.
 * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
 * @tmu_status: register drescribing the TMU status.
 * @tmu_cur_temp: register containing the current temperature of the TMU.
 * @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp
	register.
 * @threshold_temp: register containing the base threshold level.
 * @threshold_th0: Register containing first set of rising levels.
 * @threshold_th0_l0_shift: shift bits of level0 threshold temperature.
 * @threshold_th0_l1_shift: shift bits of level1 threshold temperature.
 * @threshold_th0_l2_shift: shift bits of level2 threshold temperature.
 * @threshold_th0_l3_shift: shift bits of level3 threshold temperature.
 * @threshold_th1: Register containing second set of rising levels.
 * @threshold_th1_l0_shift: shift bits of level0 threshold temperature.
 * @threshold_th1_l1_shift: shift bits of level1 threshold temperature.
 * @threshold_th1_l2_shift: shift bits of level2 threshold temperature.
 * @threshold_th1_l3_shift: shift bits of level3 threshold temperature.
 * @threshold_th2: Register containing third set of rising levels.
 * @threshold_th2_l0_shift: shift bits of level0 threshold temperature.
 * @threshold_th3: Register containing fourth set of rising levels.
 * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
 * @tmu_inten: register containing the different threshold interrupt
	enable bits.
 * @inten_rise_shift: shift bits of all rising interrupt bits.
 * @inten_rise_mask: mask bits of all rising interrupt bits.
 * @inten_fall_shift: shift bits of all rising interrupt bits.
 * @inten_fall_mask: mask bits of all rising interrupt bits.
 * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
 * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
 * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
 * @inten_rise3_shift: shift bits of rising 3 interrupt bits.
 * @inten_fall0_shift: shift bits of falling 0 interrupt bits.
 * @inten_fall1_shift: shift bits of falling 1 interrupt bits.
 * @inten_fall2_shift: shift bits of falling 2 interrupt bits.
 * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
 * @tmu_intstat: Register containing the interrupt status values.
 * @tmu_intclear: Register for clearing the raised interrupt status.
 * @emul_con: TMU emulation controller register.
 * @emul_temp_shift: shift bits of emulation temperature.
 * @emul_time_shift: shift bits of emulation time.
 * @emul_time_mask: mask bits of emulation time.
 * @tmu_irqstatus: register to find which TMU generated interrupts.
 * @tmu_pmin: register to get/set the Pmin value.
 */
struct exynos_tmu_registers {
	u32	triminfo_data;
	u32	triminfo_25_shift;
	u32	triminfo_85_shift;

	u32	triminfo_ctrl;
	u32	triminfo_reload_shift;

	u32	tmu_ctrl;
	u32	buf_vref_sel_shift;
	u32	buf_vref_sel_mask;
	u32	therm_trip_mode_shift;
	u32	therm_trip_mode_mask;
	u32	therm_trip_en_shift;
	u32	buf_slope_sel_shift;
	u32	buf_slope_sel_mask;
	u32	calib_mode_shift;
	u32	calib_mode_mask;
	u32	therm_trip_tq_en_shift;
	u32	core_en_shift;

	u32	tmu_status;

	u32	tmu_cur_temp;
	u32	tmu_cur_temp_shift;

	u32	threshold_temp;

	u32	threshold_th0;
	u32	threshold_th0_l0_shift;
	u32	threshold_th0_l1_shift;
	u32	threshold_th0_l2_shift;
	u32	threshold_th0_l3_shift;

	u32	threshold_th1;
	u32	threshold_th1_l0_shift;
	u32	threshold_th1_l1_shift;
	u32	threshold_th1_l2_shift;
	u32	threshold_th1_l3_shift;

	u32	threshold_th2;
	u32	threshold_th2_l0_shift;

	u32	threshold_th3;
	u32	threshold_th3_l0_shift;

	u32	tmu_inten;
	u32	inten_rise_shift;
	u32	inten_rise_mask;
	u32	inten_fall_shift;
	u32	inten_fall_mask;
	u32	inten_rise0_shift;
	u32	inten_rise1_shift;
	u32	inten_rise2_shift;
	u32	inten_rise3_shift;
	u32	inten_fall0_shift;
	u32	inten_fall1_shift;
	u32	inten_fall2_shift;
	u32	inten_fall3_shift;

	u32	tmu_intstat;

	u32	tmu_intclear;

	u32	emul_con;
	u32	emul_temp_shift;
	u32	emul_time_shift;
	u32	emul_time_mask;

	u32	tmu_irqstatus;
	u32	tmu_pmin;
};

/**
 * struct exynos_tmu_platform_data
 * @threshold: basic temperature for generating interrupt
 *	       25 <= threshold <= 125 [unit: degree Celsius]
 * @threshold_falling: differntial value for setting threshold
 *		       of temperature falling interrupt.
 * @trigger_levels: array for each interrupt levels
 *	[unit: degree Celsius]
 *	0: temperature for trigger_level0 interrupt
 *	   condition for trigger_level0 interrupt:
 *		current temperature > threshold + trigger_levels[0]
 *	1: temperature for trigger_level1 interrupt
 *	   condition for trigger_level1 interrupt:
 *		current temperature > threshold + trigger_levels[1]
 *	2: temperature for trigger_level2 interrupt
 *	   condition for trigger_level2 interrupt:
 *		current temperature > threshold + trigger_levels[2]
 *	3: temperature for trigger_level3 interrupt
 *	   condition for trigger_level3 interrupt:
 *		current temperature > threshold + trigger_levels[3]
 * @trigger_type: defines the type of trigger. Possible values are,
 *	THROTTLE_ACTIVE trigger type
 *	THROTTLE_PASSIVE trigger type
 *	SW_TRIP trigger type
 *	HW_TRIP
 * @trigger_enable[]: array to denote which trigger levels are enabled.
 *	1 = enable trigger_level[] interrupt,
 *	0 = disable trigger_level[] interrupt
 * @max_trigger_level: max trigger level supported by the TMU
 * @gain: gain of amplifier in the positive-TC generator block
 *	0 <= gain <= 15
 * @reference_voltage: reference voltage of amplifier
 *	in the positive-TC generator block
 *	0 <= reference_voltage <= 31
 * @noise_cancel_mode: noise cancellation mode
 *	000, 100, 101, 110 and 111 can be different modes
 * @type: determines the type of SOC
 * @efuse_value: platform defined fuse value
 * @min_efuse_value: minimum valid trimming data
 * @max_efuse_value: maximum valid trimming data
 * @first_point_trim: temp value of the first point trimming
 * @second_point_trim: temp value of the second point trimming
 * @default_temp_offset: default temperature offset in case of no trimming
 * @cal_type: calibration type for temperature
 * @cal_mode: calibration mode for temperature
 * @freq_clip_table: Table representing frequency reduction percentage.
 * @freq_tab_count: Count of the above table as frequency reduction may
 *	applicable to only some of the trigger levels.
 * @registers: Pointer to structure containing all the TMU controller registers
 *	and bitfields shifts and masks.
 * @features: a bitfield value indicating the features supported in SOC like
 *	emulation, multi instance etc
 *
 * This structure is required for configuration of exynos_tmu driver.
 */
struct exynos_tmu_platform_data {
	u8 threshold;
	u8 threshold_falling;
	u8 trigger_levels[MAX_TRIP_COUNT];
	enum trigger_type trigger_type[MAX_TRIP_COUNT];
	bool trigger_enable[MAX_TRIP_COUNT];
	u8 max_trigger_level;
	u8 gain;
	u8 reference_voltage;
	u8 noise_cancel_mode;

	u32 efuse_value;
	u32 min_efuse_value;
	u32 max_efuse_value;
	u8 first_point_trim;
	u8 second_point_trim;
	u8 default_temp_offset;

	enum calibration_type cal_type;
	enum calibration_mode cal_mode;
	enum soc_type type;
	struct freq_clip_table freq_tab[4];
	unsigned int freq_tab_count;
	const struct exynos_tmu_registers *registers;
	unsigned int features;
};

/**
 * struct exynos_tmu_init_data
 * @tmu_count: number of TMU instances.
 * @tmu_data: platform data of all TMU instances.
 * This structure is required to store data for multi-instance exynos tmu
 * driver.
 */
struct exynos_tmu_init_data {
	int tmu_count;
	struct exynos_tmu_platform_data tmu_data[];
};

#endif /* _EXYNOS_TMU_H */
Commit	Line	Data
9d97e5c8	1	/*
0c1836a6	2	* exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
9d97e5c8 DK	3	*
	4	* Copyright (C) 2011 Samsung Electronics
	5	* Donggeun Kim <dg77.kim@samsung.com>
0c1836a6	6	* Amit Daniel Kachhap <amit.daniel@samsung.com>
9d97e5c8 DK	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
0c1836a6 ADK	23	#ifndef _EXYNOS_TMU_H
0c1836a6 ADK	24	#define _EXYNOS_TMU_H
7e0b55e6	25	#include <linux/cpu_cooling.h>
9d97e5c8	26
0c1836a6 ADK	27	#include "exynos_thermal_common.h"
0c1836a6 ADK	28
9d97e5c8 DK	29	enum calibration_type {
9d97e5c8 DK	30	TYPE_ONE_POINT_TRIMMING,
1928457e ADK	31	TYPE_ONE_POINT_TRIMMING_25,
1928457e ADK	32	TYPE_ONE_POINT_TRIMMING_85,
9d97e5c8 DK	33	TYPE_TWO_POINT_TRIMMING,
	34	TYPE_NONE,
	35	};
	36
bb34b4c8 ADK	37	enum calibration_mode {
	38	SW_MODE,
	39	HW_MODE,
	40	};
	41
f22d9c03 ADK	42	enum soc_type {
f22d9c03 ADK	43	SOC_ARCH_EXYNOS4210 = 1,
14ddfaec LM	44	SOC_ARCH_EXYNOS4412,
14ddfaec LM	45	SOC_ARCH_EXYNOS5250,
a0395eee	46	SOC_ARCH_EXYNOS5440,
f22d9c03	47	};
7e0b55e6	48
f4dae753 ADK	49	/**
	50	* EXYNOS TMU supported features.
	51	* TMU_SUPPORT_EMULATION - This features is used to set user defined
	52	* temperature to the TMU controller.
	53	* TMU_SUPPORT_MULTI_INST - This features denotes that the soc
	54	* has many instances of TMU.
	55	* TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
	56	* be reloaded.
	57	* TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
	58	* be registered for falling trips also.
	59	* TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
	60	* state(active/idle) can be checked.
	61	* TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
	62	* sample time.
	63	* TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
	64	* sensors shares some common registers.
	65	* TMU_SUPPORT - macro to compare the above features with the supplied.
	66	*/
	67	#define TMU_SUPPORT_EMULATION BIT(0)
	68	#define TMU_SUPPORT_MULTI_INST BIT(1)
	69	#define TMU_SUPPORT_TRIM_RELOAD BIT(2)
	70	#define TMU_SUPPORT_FALLING_TRIP BIT(3)
	71	#define TMU_SUPPORT_READY_STATUS BIT(4)
	72	#define TMU_SUPPORT_EMUL_TIME BIT(5)
	73	#define TMU_SUPPORT_SHARED_MEMORY BIT(6)
	74
	75	#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
	76
b8d582b9 ADK	77	/**
	78	* struct exynos_tmu_register - register descriptors to access registers and
	79	* bitfields. The register validity, offsets and bitfield values may vary
	80	* slightly across different exynos SOC's.
	81	* @triminfo_data: register containing 2 pont trimming data
	82	* @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
	83	* @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
	84	* @triminfo_ctrl: trim info controller register.
	85	* @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl
	86	reg.
	87	* @tmu_ctrl: TMU main controller register.
	88	* @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
	89	* @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
	90	* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
	91	* @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
	92	* @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
	93	* @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
	94	register.
	95	* @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
1928457e ADK	96	* @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl
	97	register.
	98	* @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl
	99	register.
b8d582b9 ADK	100	* @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in
	101	tmu_ctrl register.
	102	* @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
	103	* @tmu_status: register drescribing the TMU status.
	104	* @tmu_cur_temp: register containing the current temperature of the TMU.
	105	* @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp
	106	register.
	107	* @threshold_temp: register containing the base threshold level.
	108	* @threshold_th0: Register containing first set of rising levels.
	109	* @threshold_th0_l0_shift: shift bits of level0 threshold temperature.
	110	* @threshold_th0_l1_shift: shift bits of level1 threshold temperature.
	111	* @threshold_th0_l2_shift: shift bits of level2 threshold temperature.
	112	* @threshold_th0_l3_shift: shift bits of level3 threshold temperature.
	113	* @threshold_th1: Register containing second set of rising levels.
	114	* @threshold_th1_l0_shift: shift bits of level0 threshold temperature.
	115	* @threshold_th1_l1_shift: shift bits of level1 threshold temperature.
	116	* @threshold_th1_l2_shift: shift bits of level2 threshold temperature.
	117	* @threshold_th1_l3_shift: shift bits of level3 threshold temperature.
	118	* @threshold_th2: Register containing third set of rising levels.
	119	* @threshold_th2_l0_shift: shift bits of level0 threshold temperature.
	120	* @threshold_th3: Register containing fourth set of rising levels.
	121	* @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
	122	* @tmu_inten: register containing the different threshold interrupt
	123	enable bits.
	124	* @inten_rise_shift: shift bits of all rising interrupt bits.
	125	* @inten_rise_mask: mask bits of all rising interrupt bits.
	126	* @inten_fall_shift: shift bits of all rising interrupt bits.
	127	* @inten_fall_mask: mask bits of all rising interrupt bits.
	128	* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
	129	* @inten_rise1_shift: shift bits of rising 1 interrupt bits.
	130	* @inten_rise2_shift: shift bits of rising 2 interrupt bits.
	131	* @inten_rise3_shift: shift bits of rising 3 interrupt bits.
	132	* @inten_fall0_shift: shift bits of falling 0 interrupt bits.
	133	* @inten_fall1_shift: shift bits of falling 1 interrupt bits.
	134	* @inten_fall2_shift: shift bits of falling 2 interrupt bits.
	135	* @inten_fall3_shift: shift bits of falling 3 interrupt bits.
	136	* @tmu_intstat: Register containing the interrupt status values.
	137	* @tmu_intclear: Register for clearing the raised interrupt status.
	138	* @emul_con: TMU emulation controller register.
	139	* @emul_temp_shift: shift bits of emulation temperature.
	140	* @emul_time_shift: shift bits of emulation time.
	141	* @emul_time_mask: mask bits of emulation time.
a0395eee ADK	142	* @tmu_irqstatus: register to find which TMU generated interrupts.
a0395eee ADK	143	* @tmu_pmin: register to get/set the Pmin value.
b8d582b9 ADK	144	*/
	145	struct exynos_tmu_registers {
	146	u32 triminfo_data;
	147	u32 triminfo_25_shift;
	148	u32 triminfo_85_shift;
	149
	150	u32 triminfo_ctrl;
	151	u32 triminfo_reload_shift;
	152
	153	u32 tmu_ctrl;
	154	u32 buf_vref_sel_shift;
	155	u32 buf_vref_sel_mask;
	156	u32 therm_trip_mode_shift;
	157	u32 therm_trip_mode_mask;
	158	u32 therm_trip_en_shift;
	159	u32 buf_slope_sel_shift;
	160	u32 buf_slope_sel_mask;
1928457e ADK	161	u32 calib_mode_shift;
1928457e ADK	162	u32 calib_mode_mask;
b8d582b9 ADK	163	u32 therm_trip_tq_en_shift;
	164	u32 core_en_shift;
	165
	166	u32 tmu_status;
	167
	168	u32 tmu_cur_temp;
	169	u32 tmu_cur_temp_shift;
	170
	171	u32 threshold_temp;
	172
	173	u32 threshold_th0;
	174	u32 threshold_th0_l0_shift;
	175	u32 threshold_th0_l1_shift;
	176	u32 threshold_th0_l2_shift;
	177	u32 threshold_th0_l3_shift;
	178
	179	u32 threshold_th1;
	180	u32 threshold_th1_l0_shift;
	181	u32 threshold_th1_l1_shift;
	182	u32 threshold_th1_l2_shift;
	183	u32 threshold_th1_l3_shift;
	184
	185	u32 threshold_th2;
	186	u32 threshold_th2_l0_shift;
	187
	188	u32 threshold_th3;
	189	u32 threshold_th3_l0_shift;
	190
	191	u32 tmu_inten;
	192	u32 inten_rise_shift;
	193	u32 inten_rise_mask;
	194	u32 inten_fall_shift;
	195	u32 inten_fall_mask;
	196	u32 inten_rise0_shift;
	197	u32 inten_rise1_shift;
	198	u32 inten_rise2_shift;
	199	u32 inten_rise3_shift;
	200	u32 inten_fall0_shift;
	201	u32 inten_fall1_shift;
	202	u32 inten_fall2_shift;
	203	u32 inten_fall3_shift;
	204
	205	u32 tmu_intstat;
	206
	207	u32 tmu_intclear;
	208
	209	u32 emul_con;
	210	u32 emul_temp_shift;
	211	u32 emul_time_shift;
	212	u32 emul_time_mask;
a0395eee ADK	213
	214	u32 tmu_irqstatus;
	215	u32 tmu_pmin;
b8d582b9 ADK	216	};
b8d582b9 ADK	217
9d97e5c8	218	/**
f22d9c03	219	* struct exynos_tmu_platform_data
9d97e5c8 DK	220	* @threshold: basic temperature for generating interrupt
9d97e5c8 DK	221	* 25 <= threshold <= 125 [unit: degree Celsius]
4f0a6847 JL	222	* @threshold_falling: differntial value for setting threshold
4f0a6847 JL	223	* of temperature falling interrupt.
9d97e5c8 DK	224	* @trigger_levels: array for each interrupt levels
	225	* [unit: degree Celsius]
	226	* 0: temperature for trigger_level0 interrupt
	227	* condition for trigger_level0 interrupt:
	228	* current temperature > threshold + trigger_levels[0]
	229	* 1: temperature for trigger_level1 interrupt
	230	* condition for trigger_level1 interrupt:
	231	* current temperature > threshold + trigger_levels[1]
	232	* 2: temperature for trigger_level2 interrupt
	233	* condition for trigger_level2 interrupt:
	234	* current temperature > threshold + trigger_levels[2]
	235	* 3: temperature for trigger_level3 interrupt
	236	* condition for trigger_level3 interrupt:
	237	* current temperature > threshold + trigger_levels[3]
bb34b4c8 ADK	238	* @trigger_type: defines the type of trigger. Possible values are,
	239	* THROTTLE_ACTIVE trigger type
	240	* THROTTLE_PASSIVE trigger type
	241	* SW_TRIP trigger type
	242	* HW_TRIP
	243	* @trigger_enable[]: array to denote which trigger levels are enabled.
	244	* 1 = enable trigger_level[] interrupt,
	245	* 0 = disable trigger_level[] interrupt
	246	* @max_trigger_level: max trigger level supported by the TMU
9d97e5c8 DK	247	* @gain: gain of amplifier in the positive-TC generator block
	248	* 0 <= gain <= 15
	249	* @reference_voltage: reference voltage of amplifier
	250	* in the positive-TC generator block
	251	* 0 <= reference_voltage <= 31
f22d9c03 ADK	252	* @noise_cancel_mode: noise cancellation mode
	253	* 000, 100, 101, 110 and 111 can be different modes
	254	* @type: determines the type of SOC
	255	* @efuse_value: platform defined fuse value
bb34b4c8 ADK	256	* @min_efuse_value: minimum valid trimming data
	257	* @max_efuse_value: maximum valid trimming data
	258	* @first_point_trim: temp value of the first point trimming
	259	* @second_point_trim: temp value of the second point trimming
	260	* @default_temp_offset: default temperature offset in case of no trimming
9d97e5c8	261	* @cal_type: calibration type for temperature
bb34b4c8	262	* @cal_mode: calibration mode for temperature
7e0b55e6 ADK	263	* @freq_clip_table: Table representing frequency reduction percentage.
	264	* @freq_tab_count: Count of the above table as frequency reduction may
	265	* applicable to only some of the trigger levels.
b8d582b9 ADK	266	* @registers: Pointer to structure containing all the TMU controller registers
b8d582b9 ADK	267	* and bitfields shifts and masks.
f4dae753 ADK	268	* @features: a bitfield value indicating the features supported in SOC like
f4dae753 ADK	269	* emulation, multi instance etc
9d97e5c8	270	*
f22d9c03	271	* This structure is required for configuration of exynos_tmu driver.
9d97e5c8	272	*/
f22d9c03	273	struct exynos_tmu_platform_data {
9d97e5c8	274	u8 threshold;
4f0a6847	275	u8 threshold_falling;
bb34b4c8 ADK	276	u8 trigger_levels[MAX_TRIP_COUNT];
	277	enum trigger_type trigger_type[MAX_TRIP_COUNT];
	278	bool trigger_enable[MAX_TRIP_COUNT];
	279	u8 max_trigger_level;
9d97e5c8 DK	280	u8 gain;
9d97e5c8 DK	281	u8 reference_voltage;
f22d9c03	282	u8 noise_cancel_mode;
bb34b4c8	283
f22d9c03	284	u32 efuse_value;
bb34b4c8 ADK	285	u32 min_efuse_value;
	286	u32 max_efuse_value;
	287	u8 first_point_trim;
	288	u8 second_point_trim;
	289	u8 default_temp_offset;
9d97e5c8 DK	290
9d97e5c8 DK	291	enum calibration_type cal_type;
bb34b4c8	292	enum calibration_mode cal_mode;
f22d9c03	293	enum soc_type type;
7e0b55e6 ADK	294	struct freq_clip_table freq_tab[4];
7e0b55e6 ADK	295	unsigned int freq_tab_count;
b8d582b9	296	const struct exynos_tmu_registers *registers;
f4dae753	297	unsigned int features;
9d97e5c8	298	};
cebe7373 ADK	299
	300	/**
	301	* struct exynos_tmu_init_data
	302	* @tmu_count: number of TMU instances.
	303	* @tmu_data: platform data of all TMU instances.
	304	* This structure is required to store data for multi-instance exynos tmu
	305	* driver.
	306	*/
	307	struct exynos_tmu_init_data {
	308	int tmu_count;
	309	struct exynos_tmu_platform_data tmu_data[];
	310	};
	311
0c1836a6	312	#endif /* _EXYNOS_TMU_H */