thermal: exynos: remove TMU_SUPPORT_READY_STATUS flag
[deliverable/linux.git] / drivers / thermal / samsung / exynos_tmu.h
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9d97e5c8 1/*
0c1836a6 2 * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
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3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
0c1836a6 6 * Amit Daniel Kachhap <amit.daniel@samsung.com>
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7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
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23#ifndef _EXYNOS_TMU_H
24#define _EXYNOS_TMU_H
7e0b55e6 25#include <linux/cpu_cooling.h>
9d97e5c8 26
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27#include "exynos_thermal_common.h"
28
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29enum calibration_type {
30 TYPE_ONE_POINT_TRIMMING,
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31 TYPE_ONE_POINT_TRIMMING_25,
32 TYPE_ONE_POINT_TRIMMING_85,
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33 TYPE_TWO_POINT_TRIMMING,
34 TYPE_NONE,
35};
36
f22d9c03 37enum soc_type {
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38 SOC_ARCH_EXYNOS3250 = 1,
39 SOC_ARCH_EXYNOS4210,
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40 SOC_ARCH_EXYNOS4412,
41 SOC_ARCH_EXYNOS5250,
923488a5 42 SOC_ARCH_EXYNOS5260,
14a11dc7 43 SOC_ARCH_EXYNOS5420_TRIMINFO,
a0395eee 44 SOC_ARCH_EXYNOS5440,
f22d9c03 45};
7e0b55e6 46
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47/**
48 * EXYNOS TMU supported features.
49 * TMU_SUPPORT_EMULATION - This features is used to set user defined
50 * temperature to the TMU controller.
51 * TMU_SUPPORT_MULTI_INST - This features denotes that the soc
52 * has many instances of TMU.
53 * TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
54 * be reloaded.
55 * TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
56 * be registered for falling trips also.
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57 * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
58 * sample time.
9025d563 59 * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
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60 * sensors shares some common registers.
61 * TMU_SUPPORT - macro to compare the above features with the supplied.
62 */
63#define TMU_SUPPORT_EMULATION BIT(0)
64#define TMU_SUPPORT_MULTI_INST BIT(1)
65#define TMU_SUPPORT_TRIM_RELOAD BIT(2)
66#define TMU_SUPPORT_FALLING_TRIP BIT(3)
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67#define TMU_SUPPORT_EMUL_TIME BIT(4)
68#define TMU_SUPPORT_ADDRESS_MULTIPLE BIT(5)
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69
70#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
71
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72/**
73 * struct exynos_tmu_register - register descriptors to access registers and
74 * bitfields. The register validity, offsets and bitfield values may vary
75 * slightly across different exynos SOC's.
b8d582b9 76 * @tmu_ctrl: TMU main controller register.
b8d582b9 77 * @tmu_cur_temp: register containing the current temperature of the TMU.
b8d582b9 78 * @threshold_th0: Register containing first set of rising levels.
b8d582b9 79 * @threshold_th1: Register containing second set of rising levels.
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80 * @tmu_inten: register containing the different threshold interrupt
81 enable bits.
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82 * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
83 * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
84 * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
85 * @inten_rise3_shift: shift bits of rising 3 interrupt bits.
86 * @inten_fall0_shift: shift bits of falling 0 interrupt bits.
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87 * @tmu_intstat: Register containing the interrupt status values.
88 * @tmu_intclear: Register for clearing the raised interrupt status.
89 * @emul_con: TMU emulation controller register.
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90 */
91struct exynos_tmu_registers {
b8d582b9 92 u32 tmu_ctrl;
b8d582b9 93
b8d582b9 94 u32 tmu_cur_temp;
b8d582b9 95
b8d582b9 96 u32 threshold_th0;
b8d582b9 97 u32 threshold_th1;
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98
99 u32 tmu_inten;
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100 u32 inten_rise0_shift;
101 u32 inten_rise1_shift;
102 u32 inten_rise2_shift;
103 u32 inten_rise3_shift;
104 u32 inten_fall0_shift;
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105
106 u32 tmu_intstat;
107
108 u32 tmu_intclear;
109
110 u32 emul_con;
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111};
112
9d97e5c8 113/**
f22d9c03 114 * struct exynos_tmu_platform_data
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115 * @threshold: basic temperature for generating interrupt
116 * 25 <= threshold <= 125 [unit: degree Celsius]
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117 * @threshold_falling: differntial value for setting threshold
118 * of temperature falling interrupt.
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119 * @trigger_levels: array for each interrupt levels
120 * [unit: degree Celsius]
121 * 0: temperature for trigger_level0 interrupt
122 * condition for trigger_level0 interrupt:
123 * current temperature > threshold + trigger_levels[0]
124 * 1: temperature for trigger_level1 interrupt
125 * condition for trigger_level1 interrupt:
126 * current temperature > threshold + trigger_levels[1]
127 * 2: temperature for trigger_level2 interrupt
128 * condition for trigger_level2 interrupt:
129 * current temperature > threshold + trigger_levels[2]
130 * 3: temperature for trigger_level3 interrupt
131 * condition for trigger_level3 interrupt:
132 * current temperature > threshold + trigger_levels[3]
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133 * @trigger_type: defines the type of trigger. Possible values are,
134 * THROTTLE_ACTIVE trigger type
135 * THROTTLE_PASSIVE trigger type
136 * SW_TRIP trigger type
137 * HW_TRIP
138 * @trigger_enable[]: array to denote which trigger levels are enabled.
139 * 1 = enable trigger_level[] interrupt,
140 * 0 = disable trigger_level[] interrupt
141 * @max_trigger_level: max trigger level supported by the TMU
ac951af5 142 * @non_hw_trigger_levels: number of defined non-hardware trigger levels
9d97e5c8 143 * @gain: gain of amplifier in the positive-TC generator block
9c7a87f1 144 * 0 < gain <= 15
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145 * @reference_voltage: reference voltage of amplifier
146 * in the positive-TC generator block
9c7a87f1 147 * 0 < reference_voltage <= 31
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148 * @noise_cancel_mode: noise cancellation mode
149 * 000, 100, 101, 110 and 111 can be different modes
150 * @type: determines the type of SOC
151 * @efuse_value: platform defined fuse value
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152 * @min_efuse_value: minimum valid trimming data
153 * @max_efuse_value: maximum valid trimming data
154 * @first_point_trim: temp value of the first point trimming
155 * @second_point_trim: temp value of the second point trimming
156 * @default_temp_offset: default temperature offset in case of no trimming
86f5362e 157 * @test_mux; information if SoC supports test MUX
9d97e5c8 158 * @cal_type: calibration type for temperature
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159 * @freq_clip_table: Table representing frequency reduction percentage.
160 * @freq_tab_count: Count of the above table as frequency reduction may
161 * applicable to only some of the trigger levels.
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162 * @registers: Pointer to structure containing all the TMU controller registers
163 * and bitfields shifts and masks.
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164 * @features: a bitfield value indicating the features supported in SOC like
165 * emulation, multi instance etc
9d97e5c8 166 *
f22d9c03 167 * This structure is required for configuration of exynos_tmu driver.
9d97e5c8 168 */
f22d9c03 169struct exynos_tmu_platform_data {
9d97e5c8 170 u8 threshold;
4f0a6847 171 u8 threshold_falling;
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172 u8 trigger_levels[MAX_TRIP_COUNT];
173 enum trigger_type trigger_type[MAX_TRIP_COUNT];
174 bool trigger_enable[MAX_TRIP_COUNT];
175 u8 max_trigger_level;
ac951af5 176 u8 non_hw_trigger_levels;
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177 u8 gain;
178 u8 reference_voltage;
f22d9c03 179 u8 noise_cancel_mode;
bb34b4c8 180
f22d9c03 181 u32 efuse_value;
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182 u32 min_efuse_value;
183 u32 max_efuse_value;
184 u8 first_point_trim;
185 u8 second_point_trim;
186 u8 default_temp_offset;
86f5362e 187 u8 test_mux;
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188
189 enum calibration_type cal_type;
f22d9c03 190 enum soc_type type;
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191 struct freq_clip_table freq_tab[4];
192 unsigned int freq_tab_count;
b8d582b9 193 const struct exynos_tmu_registers *registers;
f4dae753 194 unsigned int features;
9d97e5c8 195};
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196
197/**
198 * struct exynos_tmu_init_data
199 * @tmu_count: number of TMU instances.
200 * @tmu_data: platform data of all TMU instances.
201 * This structure is required to store data for multi-instance exynos tmu
202 * driver.
203 */
204struct exynos_tmu_init_data {
205 int tmu_count;
206 struct exynos_tmu_platform_data tmu_data[];
207};
208
0c1836a6 209#endif /* _EXYNOS_TMU_H */
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