[deliverable/linux.git] / drivers / thermal / samsung / exynos_tmu.h

/*
 * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
 *
 *  Copyright (C) 2011 Samsung Electronics
 *  Donggeun Kim <dg77.kim@samsung.com>
 *  Amit Daniel Kachhap <amit.daniel@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef _EXYNOS_TMU_H
#define _EXYNOS_TMU_H
#include <linux/cpu_cooling.h>

#include "exynos_thermal_common.h"

enum calibration_type {
	TYPE_ONE_POINT_TRIMMING,
	TYPE_ONE_POINT_TRIMMING_25,
	TYPE_ONE_POINT_TRIMMING_85,
	TYPE_TWO_POINT_TRIMMING,
	TYPE_NONE,
};

enum soc_type {
	SOC_ARCH_EXYNOS3250 = 1,
	SOC_ARCH_EXYNOS4210,
	SOC_ARCH_EXYNOS4412,
	SOC_ARCH_EXYNOS5250,
	SOC_ARCH_EXYNOS5260,
	SOC_ARCH_EXYNOS5420_TRIMINFO,
	SOC_ARCH_EXYNOS5440,
};

/**
 * EXYNOS TMU supported features.
 * TMU_SUPPORT_EMULATION - This features is used to set user defined
 *			temperature to the TMU controller.
 * TMU_SUPPORT_MULTI_INST - This features denotes that the soc
 *			has many instances of TMU.
 * TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
 *			be reloaded.
 * TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
 *			be registered for falling trips also.
 * TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
 *			state(active/idle) can be checked.
 * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
 *			sample time.
 * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
 *			sensors shares some common registers.
 * TMU_SUPPORT - macro to compare the above features with the supplied.
 */
#define TMU_SUPPORT_EMULATION			BIT(0)
#define TMU_SUPPORT_MULTI_INST			BIT(1)
#define TMU_SUPPORT_TRIM_RELOAD			BIT(2)
#define TMU_SUPPORT_FALLING_TRIP		BIT(3)
#define TMU_SUPPORT_READY_STATUS		BIT(4)
#define TMU_SUPPORT_EMUL_TIME			BIT(5)
#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)

#define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)

/**
 * struct exynos_tmu_register - register descriptors to access registers and
 * bitfields. The register validity, offsets and bitfield values may vary
 * slightly across different exynos SOC's.
 * @triminfo_data: register containing 2 pont trimming data
 * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
 * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
 * @triminfo_ctrl: trim info controller register.
 * @tmu_ctrl: TMU main controller register.
 * @test_mux_addr_shift: shift bits of test mux address.
 * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
 * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
 * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
 * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
 * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
 * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
	register.
 * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
 * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
 * @tmu_status: register drescribing the TMU status.
 * @tmu_cur_temp: register containing the current temperature of the TMU.
 * @threshold_temp: register containing the base threshold level.
 * @threshold_th0: Register containing first set of rising levels.
 * @threshold_th1: Register containing second set of rising levels.
 * @threshold_th2: Register containing third set of rising levels.
 * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
 * @tmu_inten: register containing the different threshold interrupt
	enable bits.
 * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
 * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
 * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
 * @inten_rise3_shift: shift bits of rising 3 interrupt bits.
 * @inten_fall0_shift: shift bits of falling 0 interrupt bits.
 * @tmu_intstat: Register containing the interrupt status values.
 * @tmu_intclear: Register for clearing the raised interrupt status.
 * @intclr_fall_shift: shift bits for interrupt clear fall 0
 * @intclr_rise_shift: shift bits of all rising interrupt bits.
 * @intclr_rise_mask: mask bits of all rising interrupt bits.
 * @intclr_fall_mask: mask bits of all rising interrupt bits.
 * @emul_con: TMU emulation controller register.
 * @emul_temp_shift: shift bits of emulation temperature.
 * @emul_time_shift: shift bits of emulation time.
 * @tmu_irqstatus: register to find which TMU generated interrupts.
 * @tmu_pmin: register to get/set the Pmin value.
 */
struct exynos_tmu_registers {
	u32	triminfo_data;
	u32	triminfo_25_shift;
	u32	triminfo_85_shift;

	u32	triminfo_ctrl;
	u32	triminfo_ctrl1;

	u32	tmu_ctrl;
	u32     test_mux_addr_shift;
	u32	buf_vref_sel_shift;
	u32	buf_vref_sel_mask;
	u32	therm_trip_mode_shift;
	u32	therm_trip_mode_mask;
	u32	therm_trip_en_shift;
	u32	buf_slope_sel_shift;
	u32	buf_slope_sel_mask;
	u32	core_en_shift;

	u32	tmu_status;

	u32	tmu_cur_temp;

	u32	threshold_temp;

	u32	threshold_th0;
	u32	threshold_th1;
	u32	threshold_th2;
	u32	threshold_th3_l0_shift;

	u32	tmu_inten;
	u32	inten_rise0_shift;
	u32	inten_rise1_shift;
	u32	inten_rise2_shift;
	u32	inten_rise3_shift;
	u32	inten_fall0_shift;

	u32	tmu_intstat;

	u32	tmu_intclear;
	u32	intclr_fall_shift;
	u32	intclr_rise_shift;
	u32	intclr_fall_mask;
	u32	intclr_rise_mask;

	u32	emul_con;
	u32	emul_temp_shift;
	u32	emul_time_shift;

	u32	tmu_irqstatus;
	u32	tmu_pmin;
};

/**
 * struct exynos_tmu_platform_data
 * @threshold: basic temperature for generating interrupt
 *	       25 <= threshold <= 125 [unit: degree Celsius]
 * @threshold_falling: differntial value for setting threshold
 *		       of temperature falling interrupt.
 * @trigger_levels: array for each interrupt levels
 *	[unit: degree Celsius]
 *	0: temperature for trigger_level0 interrupt
 *	   condition for trigger_level0 interrupt:
 *		current temperature > threshold + trigger_levels[0]
 *	1: temperature for trigger_level1 interrupt
 *	   condition for trigger_level1 interrupt:
 *		current temperature > threshold + trigger_levels[1]
 *	2: temperature for trigger_level2 interrupt
 *	   condition for trigger_level2 interrupt:
 *		current temperature > threshold + trigger_levels[2]
 *	3: temperature for trigger_level3 interrupt
 *	   condition for trigger_level3 interrupt:
 *		current temperature > threshold + trigger_levels[3]
 * @trigger_type: defines the type of trigger. Possible values are,
 *	THROTTLE_ACTIVE trigger type
 *	THROTTLE_PASSIVE trigger type
 *	SW_TRIP trigger type
 *	HW_TRIP
 * @trigger_enable[]: array to denote which trigger levels are enabled.
 *	1 = enable trigger_level[] interrupt,
 *	0 = disable trigger_level[] interrupt
 * @max_trigger_level: max trigger level supported by the TMU
 * @non_hw_trigger_levels: number of defined non-hardware trigger levels
 * @gain: gain of amplifier in the positive-TC generator block
 *	0 <= gain <= 15
 * @reference_voltage: reference voltage of amplifier
 *	in the positive-TC generator block
 *	0 <= reference_voltage <= 31
 * @noise_cancel_mode: noise cancellation mode
 *	000, 100, 101, 110 and 111 can be different modes
 * @type: determines the type of SOC
 * @efuse_value: platform defined fuse value
 * @min_efuse_value: minimum valid trimming data
 * @max_efuse_value: maximum valid trimming data
 * @first_point_trim: temp value of the first point trimming
 * @second_point_trim: temp value of the second point trimming
 * @default_temp_offset: default temperature offset in case of no trimming
 * @test_mux; information if SoC supports test MUX
 * @cal_type: calibration type for temperature
 * @freq_clip_table: Table representing frequency reduction percentage.
 * @freq_tab_count: Count of the above table as frequency reduction may
 *	applicable to only some of the trigger levels.
 * @registers: Pointer to structure containing all the TMU controller registers
 *	and bitfields shifts and masks.
 * @features: a bitfield value indicating the features supported in SOC like
 *	emulation, multi instance etc
 *
 * This structure is required for configuration of exynos_tmu driver.
 */
struct exynos_tmu_platform_data {
	u8 threshold;
	u8 threshold_falling;
	u8 trigger_levels[MAX_TRIP_COUNT];
	enum trigger_type trigger_type[MAX_TRIP_COUNT];
	bool trigger_enable[MAX_TRIP_COUNT];
	u8 max_trigger_level;
	u8 non_hw_trigger_levels;
	u8 gain;
	u8 reference_voltage;
	u8 noise_cancel_mode;

	u32 efuse_value;
	u32 min_efuse_value;
	u32 max_efuse_value;
	u8 first_point_trim;
	u8 second_point_trim;
	u8 default_temp_offset;
	u8 test_mux;

	enum calibration_type cal_type;
	enum soc_type type;
	struct freq_clip_table freq_tab[4];
	unsigned int freq_tab_count;
	const struct exynos_tmu_registers *registers;
	unsigned int features;
};

/**
 * struct exynos_tmu_init_data
 * @tmu_count: number of TMU instances.
 * @tmu_data: platform data of all TMU instances.
 * This structure is required to store data for multi-instance exynos tmu
 * driver.
 */
struct exynos_tmu_init_data {
	int tmu_count;
	struct exynos_tmu_platform_data tmu_data[];
};

#endif /* _EXYNOS_TMU_H */
Commit	Line	Data
9d97e5c8	1	/*
0c1836a6	2	* exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
9d97e5c8 DK	3	*
	4	* Copyright (C) 2011 Samsung Electronics
	5	* Donggeun Kim <dg77.kim@samsung.com>
0c1836a6	6	* Amit Daniel Kachhap <amit.daniel@samsung.com>
9d97e5c8 DK	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
0c1836a6 ADK	23	#ifndef _EXYNOS_TMU_H
0c1836a6 ADK	24	#define _EXYNOS_TMU_H
7e0b55e6	25	#include <linux/cpu_cooling.h>
9d97e5c8	26
0c1836a6 ADK	27	#include "exynos_thermal_common.h"
0c1836a6 ADK	28
9d97e5c8 DK	29	enum calibration_type {
9d97e5c8 DK	30	TYPE_ONE_POINT_TRIMMING,
1928457e ADK	31	TYPE_ONE_POINT_TRIMMING_25,
1928457e ADK	32	TYPE_ONE_POINT_TRIMMING_85,
9d97e5c8 DK	33	TYPE_TWO_POINT_TRIMMING,
	34	TYPE_NONE,
	35	};
	36
f22d9c03	37	enum soc_type {
1fe56dc1 CC	38	SOC_ARCH_EXYNOS3250 = 1,
1fe56dc1 CC	39	SOC_ARCH_EXYNOS4210,
14ddfaec LM	40	SOC_ARCH_EXYNOS4412,
14ddfaec LM	41	SOC_ARCH_EXYNOS5250,
923488a5	42	SOC_ARCH_EXYNOS5260,
14a11dc7	43	SOC_ARCH_EXYNOS5420_TRIMINFO,
a0395eee	44	SOC_ARCH_EXYNOS5440,
f22d9c03	45	};
7e0b55e6	46
f4dae753 ADK	47	/**
	48	* EXYNOS TMU supported features.
	49	* TMU_SUPPORT_EMULATION - This features is used to set user defined
	50	* temperature to the TMU controller.
	51	* TMU_SUPPORT_MULTI_INST - This features denotes that the soc
	52	* has many instances of TMU.
	53	* TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
	54	* be reloaded.
	55	* TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
	56	* be registered for falling trips also.
	57	* TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
	58	* state(active/idle) can be checked.
	59	* TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
	60	* sample time.
9025d563	61	* TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
f4dae753 ADK	62	* sensors shares some common registers.
	63	* TMU_SUPPORT - macro to compare the above features with the supplied.
	64	*/
	65	#define TMU_SUPPORT_EMULATION BIT(0)
	66	#define TMU_SUPPORT_MULTI_INST BIT(1)
	67	#define TMU_SUPPORT_TRIM_RELOAD BIT(2)
	68	#define TMU_SUPPORT_FALLING_TRIP BIT(3)
	69	#define TMU_SUPPORT_READY_STATUS BIT(4)
	70	#define TMU_SUPPORT_EMUL_TIME BIT(5)
9025d563	71	#define TMU_SUPPORT_ADDRESS_MULTIPLE BIT(6)
f4dae753 ADK	72
	73	#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
	74
b8d582b9 ADK	75	/**
	76	* struct exynos_tmu_register - register descriptors to access registers and
	77	* bitfields. The register validity, offsets and bitfield values may vary
	78	* slightly across different exynos SOC's.
	79	* @triminfo_data: register containing 2 pont trimming data
	80	* @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
	81	* @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
	82	* @triminfo_ctrl: trim info controller register.
b8d582b9	83	* @tmu_ctrl: TMU main controller register.
86f5362e	84	* @test_mux_addr_shift: shift bits of test mux address.
b8d582b9 ADK	85	* @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
	86	* @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
	87	* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
	88	* @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
	89	* @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
	90	* @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
	91	register.
	92	* @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
b8d582b9 ADK	93	* @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
	94	* @tmu_status: register drescribing the TMU status.
	95	* @tmu_cur_temp: register containing the current temperature of the TMU.
b8d582b9 ADK	96	* @threshold_temp: register containing the base threshold level.
b8d582b9 ADK	97	* @threshold_th0: Register containing first set of rising levels.
b8d582b9	98	* @threshold_th1: Register containing second set of rising levels.
b8d582b9	99	* @threshold_th2: Register containing third set of rising levels.
b8d582b9 ADK	100	* @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
	101	* @tmu_inten: register containing the different threshold interrupt
	102	enable bits.
b8d582b9 ADK	103	* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
	104	* @inten_rise1_shift: shift bits of rising 1 interrupt bits.
	105	* @inten_rise2_shift: shift bits of rising 2 interrupt bits.
	106	* @inten_rise3_shift: shift bits of rising 3 interrupt bits.
	107	* @inten_fall0_shift: shift bits of falling 0 interrupt bits.
b8d582b9 ADK	108	* @tmu_intstat: Register containing the interrupt status values.
b8d582b9 ADK	109	* @tmu_intclear: Register for clearing the raised interrupt status.
74429c2f NKC	110	* @intclr_fall_shift: shift bits for interrupt clear fall 0
	111	* @intclr_rise_shift: shift bits of all rising interrupt bits.
	112	* @intclr_rise_mask: mask bits of all rising interrupt bits.
	113	* @intclr_fall_mask: mask bits of all rising interrupt bits.
b8d582b9 ADK	114	* @emul_con: TMU emulation controller register.
	115	* @emul_temp_shift: shift bits of emulation temperature.
	116	* @emul_time_shift: shift bits of emulation time.
a0395eee ADK	117	* @tmu_irqstatus: register to find which TMU generated interrupts.
a0395eee ADK	118	* @tmu_pmin: register to get/set the Pmin value.
b8d582b9 ADK	119	*/
	120	struct exynos_tmu_registers {
	121	u32 triminfo_data;
	122	u32 triminfo_25_shift;
	123	u32 triminfo_85_shift;
	124
	125	u32 triminfo_ctrl;
923488a5	126	u32 triminfo_ctrl1;
b8d582b9 ADK	127
b8d582b9 ADK	128	u32 tmu_ctrl;
86f5362e	129	u32 test_mux_addr_shift;
b8d582b9 ADK	130	u32 buf_vref_sel_shift;
	131	u32 buf_vref_sel_mask;
	132	u32 therm_trip_mode_shift;
	133	u32 therm_trip_mode_mask;
	134	u32 therm_trip_en_shift;
	135	u32 buf_slope_sel_shift;
	136	u32 buf_slope_sel_mask;
b8d582b9 ADK	137	u32 core_en_shift;
	138
	139	u32 tmu_status;
	140
	141	u32 tmu_cur_temp;
b8d582b9 ADK	142
	143	u32 threshold_temp;
	144
	145	u32 threshold_th0;
b8d582b9	146	u32 threshold_th1;
b8d582b9	147	u32 threshold_th2;
b8d582b9 ADK	148	u32 threshold_th3_l0_shift;
	149
	150	u32 tmu_inten;
b8d582b9 ADK	151	u32 inten_rise0_shift;
	152	u32 inten_rise1_shift;
	153	u32 inten_rise2_shift;
	154	u32 inten_rise3_shift;
	155	u32 inten_fall0_shift;
b8d582b9 ADK	156
	157	u32 tmu_intstat;
	158
	159	u32 tmu_intclear;
74429c2f NKC	160	u32 intclr_fall_shift;
	161	u32 intclr_rise_shift;
	162	u32 intclr_fall_mask;
	163	u32 intclr_rise_mask;
b8d582b9 ADK	164
	165	u32 emul_con;
	166	u32 emul_temp_shift;
	167	u32 emul_time_shift;
a0395eee ADK	168
	169	u32 tmu_irqstatus;
	170	u32 tmu_pmin;
b8d582b9 ADK	171	};
b8d582b9 ADK	172
9d97e5c8	173	/**
f22d9c03	174	* struct exynos_tmu_platform_data
9d97e5c8 DK	175	* @threshold: basic temperature for generating interrupt
9d97e5c8 DK	176	* 25 <= threshold <= 125 [unit: degree Celsius]
4f0a6847 JL	177	* @threshold_falling: differntial value for setting threshold
4f0a6847 JL	178	* of temperature falling interrupt.
9d97e5c8 DK	179	* @trigger_levels: array for each interrupt levels
	180	* [unit: degree Celsius]
	181	* 0: temperature for trigger_level0 interrupt
	182	* condition for trigger_level0 interrupt:
	183	* current temperature > threshold + trigger_levels[0]
	184	* 1: temperature for trigger_level1 interrupt
	185	* condition for trigger_level1 interrupt:
	186	* current temperature > threshold + trigger_levels[1]
	187	* 2: temperature for trigger_level2 interrupt
	188	* condition for trigger_level2 interrupt:
	189	* current temperature > threshold + trigger_levels[2]
	190	* 3: temperature for trigger_level3 interrupt
	191	* condition for trigger_level3 interrupt:
	192	* current temperature > threshold + trigger_levels[3]
bb34b4c8 ADK	193	* @trigger_type: defines the type of trigger. Possible values are,
	194	* THROTTLE_ACTIVE trigger type
	195	* THROTTLE_PASSIVE trigger type
	196	* SW_TRIP trigger type
	197	* HW_TRIP
	198	* @trigger_enable[]: array to denote which trigger levels are enabled.
	199	* 1 = enable trigger_level[] interrupt,
	200	* 0 = disable trigger_level[] interrupt
	201	* @max_trigger_level: max trigger level supported by the TMU
ac951af5	202	* @non_hw_trigger_levels: number of defined non-hardware trigger levels
9d97e5c8 DK	203	* @gain: gain of amplifier in the positive-TC generator block
	204	* 0 <= gain <= 15
	205	* @reference_voltage: reference voltage of amplifier
	206	* in the positive-TC generator block
	207	* 0 <= reference_voltage <= 31
f22d9c03 ADK	208	* @noise_cancel_mode: noise cancellation mode
	209	* 000, 100, 101, 110 and 111 can be different modes
	210	* @type: determines the type of SOC
	211	* @efuse_value: platform defined fuse value
bb34b4c8 ADK	212	* @min_efuse_value: minimum valid trimming data
	213	* @max_efuse_value: maximum valid trimming data
	214	* @first_point_trim: temp value of the first point trimming
	215	* @second_point_trim: temp value of the second point trimming
	216	* @default_temp_offset: default temperature offset in case of no trimming
86f5362e	217	* @test_mux; information if SoC supports test MUX
9d97e5c8	218	* @cal_type: calibration type for temperature
7e0b55e6 ADK	219	* @freq_clip_table: Table representing frequency reduction percentage.
	220	* @freq_tab_count: Count of the above table as frequency reduction may
	221	* applicable to only some of the trigger levels.
b8d582b9 ADK	222	* @registers: Pointer to structure containing all the TMU controller registers
b8d582b9 ADK	223	* and bitfields shifts and masks.
f4dae753 ADK	224	* @features: a bitfield value indicating the features supported in SOC like
f4dae753 ADK	225	* emulation, multi instance etc
9d97e5c8	226	*
f22d9c03	227	* This structure is required for configuration of exynos_tmu driver.
9d97e5c8	228	*/
f22d9c03	229	struct exynos_tmu_platform_data {
9d97e5c8	230	u8 threshold;
4f0a6847	231	u8 threshold_falling;
bb34b4c8 ADK	232	u8 trigger_levels[MAX_TRIP_COUNT];
	233	enum trigger_type trigger_type[MAX_TRIP_COUNT];
	234	bool trigger_enable[MAX_TRIP_COUNT];
	235	u8 max_trigger_level;
ac951af5	236	u8 non_hw_trigger_levels;
9d97e5c8 DK	237	u8 gain;
9d97e5c8 DK	238	u8 reference_voltage;
f22d9c03	239	u8 noise_cancel_mode;
bb34b4c8	240
f22d9c03	241	u32 efuse_value;
bb34b4c8 ADK	242	u32 min_efuse_value;
	243	u32 max_efuse_value;
	244	u8 first_point_trim;
	245	u8 second_point_trim;
	246	u8 default_temp_offset;
86f5362e	247	u8 test_mux;
9d97e5c8 DK	248
9d97e5c8 DK	249	enum calibration_type cal_type;
f22d9c03	250	enum soc_type type;
7e0b55e6 ADK	251	struct freq_clip_table freq_tab[4];
7e0b55e6 ADK	252	unsigned int freq_tab_count;
b8d582b9	253	const struct exynos_tmu_registers *registers;
f4dae753	254	unsigned int features;
9d97e5c8	255	};
cebe7373 ADK	256
	257	/**
	258	* struct exynos_tmu_init_data
	259	* @tmu_count: number of TMU instances.
	260	* @tmu_data: platform data of all TMU instances.
	261	* This structure is required to store data for multi-instance exynos tmu
	262	* driver.
	263	*/
	264	struct exynos_tmu_init_data {
	265	int tmu_count;
	266	struct exynos_tmu_platform_data tmu_data[];
	267	};
	268
0c1836a6	269	#endif /* _EXYNOS_TMU_H */