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Add copy_to_iter(), copy_from_iter() and iov_iter_zero()
[deliverable/linux.git] / drivers / thermal / samsung / exynos_tmu_data.c
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e6b7991e
ADK		 1/*
2 * exynos_tmu_data.c - Samsung EXYNOS tmu data file
3 *
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#include "exynos_thermal_common.h"
24#include "exynos_tmu.h"
25#include "exynos_tmu_data.h"
26
27#if defined(CONFIG_CPU_EXYNOS4210)
b8d582b9
ADK		 28static const struct exynos_tmu_registers exynos4210_tmu_registers = {
29 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
30 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
31 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
32 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
33 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
34 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
35 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
36 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
37 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
38 .tmu_status = EXYNOS_TMU_REG_STATUS,
39 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
40 .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
41 .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
42 .tmu_inten = EXYNOS_TMU_REG_INTEN,
b8d582b9
ADK		 43 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
44 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
45 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
46 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
a4463c4f 47 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
b8d582b9 48 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
74429c2f 49 .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
b8d582b9 50};
cebe7373
ADK		 51
52struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
53 .tmu_data = {
54 {
55 .threshold = 80,
56 .trigger_levels[0] = 5,
57 .trigger_levels[1] = 20,
58 .trigger_levels[2] = 30,
59 .trigger_enable[0] = true,
60 .trigger_enable[1] = true,
61 .trigger_enable[2] = true,
62 .trigger_enable[3] = false,
63 .trigger_type[0] = THROTTLE_ACTIVE,
64 .trigger_type[1] = THROTTLE_ACTIVE,
65 .trigger_type[2] = SW_TRIP,
66 .max_trigger_level = 4,
67 .gain = 15,
68 .reference_voltage = 7,
69 .cal_type = TYPE_ONE_POINT_TRIMMING,
70 .min_efuse_value = 40,
71 .max_efuse_value = 100,
72 .first_point_trim = 25,
73 .second_point_trim = 85,
74 .default_temp_offset = 50,
75 .freq_tab[0] = {
76 .freq_clip_max = 800 * 1000,
77 .temp_level = 85,
78 },
79 .freq_tab[1] = {
80 .freq_clip_max = 200 * 1000,
81 .temp_level = 100,
82 },
83 .freq_tab_count = 2,
84 .type = SOC_ARCH_EXYNOS4210,
85 .registers = &exynos4210_tmu_registers,
f4dae753 86 .features = TMU_SUPPORT_READY_STATUS,
cebe7373 87 },
e6b7991e 88 },
cebe7373 89 .tmu_count = 1,
e6b7991e
ADK		 90};
91#endif
92
1fe56dc1
CC		 93#if defined(CONFIG_SOC_EXYNOS3250)
94static const struct exynos_tmu_registers exynos3250_tmu_registers = {
95 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
96 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
97 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
98 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
99 .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
100 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
101 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
102 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
103 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
104 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
105 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
106 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
107 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
108 .tmu_status = EXYNOS_TMU_REG_STATUS,
109 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
110 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
111 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
112 .tmu_inten = EXYNOS_TMU_REG_INTEN,
113 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
114 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
115 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
116 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
117 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
118 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
119 .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
120 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
121 .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
122 .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
123 .emul_con = EXYNOS_EMUL_CON,
124 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
125 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
126 .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
127};
128
129#define EXYNOS3250_TMU_DATA \
130 .threshold_falling = 10, \
131 .trigger_levels[0] = 70, \
132 .trigger_levels[1] = 95, \
133 .trigger_levels[2] = 110, \
134 .trigger_levels[3] = 120, \
135 .trigger_enable[0] = true, \
136 .trigger_enable[1] = true, \
137 .trigger_enable[2] = true, \
138 .trigger_enable[3] = false, \
139 .trigger_type[0] = THROTTLE_ACTIVE, \
140 .trigger_type[1] = THROTTLE_ACTIVE, \
141 .trigger_type[2] = SW_TRIP, \
142 .trigger_type[3] = HW_TRIP, \
143 .max_trigger_level = 4, \
144 .gain = 8, \
145 .reference_voltage = 16, \
146 .noise_cancel_mode = 4, \
147 .cal_type = TYPE_TWO_POINT_TRIMMING, \
148 .efuse_value = 55, \
149 .min_efuse_value = 40, \
150 .max_efuse_value = 100, \
151 .first_point_trim = 25, \
152 .second_point_trim = 85, \
153 .default_temp_offset = 50, \
154 .freq_tab[0] = { \
155 .freq_clip_max = 800 * 1000, \
156 .temp_level = 70, \
157 }, \
158 .freq_tab[1] = { \
159 .freq_clip_max = 400 * 1000, \
160 .temp_level = 95, \
161 }, \
162 .freq_tab_count = 2, \
163 .registers = &exynos3250_tmu_registers, \
164 .features = (TMU_SUPPORT_EMULATION | \
165 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
166 TMU_SUPPORT_EMUL_TIME)
167#endif
168
169#if defined(CONFIG_SOC_EXYNOS3250)
170struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
171 .tmu_data = {
172 {
173 EXYNOS3250_TMU_DATA,
174 .type = SOC_ARCH_EXYNOS3250,
175 .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
176 },
177 },
178 .tmu_count = 1,
179};
180#endif
181
14ddfaec
LM		 182#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
183static const struct exynos_tmu_registers exynos4412_tmu_registers = {
b8d582b9
ADK		 184 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
185 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
186 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
187 .triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
188 .triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
189 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
86f5362e 190 .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
b8d582b9
ADK		 191 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
192 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
193 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
194 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
195 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
196 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
197 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
198 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
199 .tmu_status = EXYNOS_TMU_REG_STATUS,
200 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
201 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
202 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
203 .tmu_inten = EXYNOS_TMU_REG_INTEN,
b8d582b9
ADK		 204 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
205 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
206 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
207 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
208 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
a4463c4f 209 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
b8d582b9 210 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
74429c2f
NKC		 211 .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
212 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
213 .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
214 .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
b8d582b9
ADK		 215 .emul_con = EXYNOS_EMUL_CON,
216 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
217 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
218 .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
219};
cebe7373 220
14ddfaec 221#define EXYNOS4412_TMU_DATA \
cebe7373 222 .threshold_falling = 10, \
4f11b85a
LM		 223 .trigger_levels[0] = 70, \
224 .trigger_levels[1] = 95, \
cebe7373
ADK		 225 .trigger_levels[2] = 110, \
226 .trigger_levels[3] = 120, \
227 .trigger_enable[0] = true, \
228 .trigger_enable[1] = true, \
229 .trigger_enable[2] = true, \
230 .trigger_enable[3] = false, \
231 .trigger_type[0] = THROTTLE_ACTIVE, \
232 .trigger_type[1] = THROTTLE_ACTIVE, \
233 .trigger_type[2] = SW_TRIP, \
234 .trigger_type[3] = HW_TRIP, \
235 .max_trigger_level = 4, \
236 .gain = 8, \
237 .reference_voltage = 16, \
238 .noise_cancel_mode = 4, \
239 .cal_type = TYPE_ONE_POINT_TRIMMING, \
240 .efuse_value = 55, \
241 .min_efuse_value = 40, \
242 .max_efuse_value = 100, \
243 .first_point_trim = 25, \
244 .second_point_trim = 85, \
245 .default_temp_offset = 50, \
246 .freq_tab[0] = { \
4f11b85a
LM		 247 .freq_clip_max = 1400 * 1000, \
248 .temp_level = 70, \
cebe7373
ADK		 249 }, \
250 .freq_tab[1] = { \
4f11b85a
LM		 251 .freq_clip_max = 400 * 1000, \
252 .temp_level = 95, \
cebe7373
ADK		 253 }, \
254 .freq_tab_count = 2, \
14ddfaec 255 .registers = &exynos4412_tmu_registers, \
f4dae753
ADK		 256 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
257 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
258 TMU_SUPPORT_EMUL_TIME)
14ddfaec 259#endif
cebe7373 260
14ddfaec
LM		 261#if defined(CONFIG_SOC_EXYNOS4412)
262struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
263 .tmu_data = {
264 {
265 EXYNOS4412_TMU_DATA,
266 .type = SOC_ARCH_EXYNOS4412,
86f5362e 267 .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
14ddfaec
LM		 268 },
269 },
270 .tmu_count = 1,
271};
272#endif
273
274#if defined(CONFIG_SOC_EXYNOS5250)
cebe7373
ADK		 275struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
276 .tmu_data = {
14ddfaec
LM		 277 {
278 EXYNOS4412_TMU_DATA,
279 .type = SOC_ARCH_EXYNOS5250,
280 },
cebe7373
ADK		 281 },
282 .tmu_count = 1,
e6b7991e
ADK		 283};
284#endif
90542546 285
923488a5
NKC		 286#if defined(CONFIG_SOC_EXYNOS5260)
287static const struct exynos_tmu_registers exynos5260_tmu_registers = {
288 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
289 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
290 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
291 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
292 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
293 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
294 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
295 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
296 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
297 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
298 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
299 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
300 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
301 .tmu_status = EXYNOS_TMU_REG_STATUS,
302 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
303 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
304 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
305 .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
306 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
307 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
308 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
309 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
310 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
311 .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
312 .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
313 .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
314 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
315 .intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
316 .intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
317 .emul_con = EXYNOS5260_EMUL_CON,
318 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
319 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
320 .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
321};
322
323#define __EXYNOS5260_TMU_DATA \
324 .threshold_falling = 10, \
325 .trigger_levels[0] = 85, \
326 .trigger_levels[1] = 103, \
327 .trigger_levels[2] = 110, \
328 .trigger_levels[3] = 120, \
329 .trigger_enable[0] = true, \
330 .trigger_enable[1] = true, \
331 .trigger_enable[2] = true, \
332 .trigger_enable[3] = false, \
333 .trigger_type[0] = THROTTLE_ACTIVE, \
334 .trigger_type[1] = THROTTLE_ACTIVE, \
335 .trigger_type[2] = SW_TRIP, \
336 .trigger_type[3] = HW_TRIP, \
337 .max_trigger_level = 4, \
338 .gain = 8, \
339 .reference_voltage = 16, \
340 .noise_cancel_mode = 4, \
341 .cal_type = TYPE_ONE_POINT_TRIMMING, \
342 .efuse_value = 55, \
343 .min_efuse_value = 40, \
344 .max_efuse_value = 100, \
345 .first_point_trim = 25, \
346 .second_point_trim = 85, \
347 .default_temp_offset = 50, \
348 .freq_tab[0] = { \
349 .freq_clip_max = 800 * 1000, \
350 .temp_level = 85, \
351 }, \
352 .freq_tab[1] = { \
353 .freq_clip_max = 200 * 1000, \
354 .temp_level = 103, \
355 }, \
356 .freq_tab_count = 2, \
357 .registers = &exynos5260_tmu_registers, \
358
359#define EXYNOS5260_TMU_DATA \
360 __EXYNOS5260_TMU_DATA \
361 .type = SOC_ARCH_EXYNOS5260, \
362 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
363 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
364 TMU_SUPPORT_EMUL_TIME)
365
366struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
367 .tmu_data = {
368 { EXYNOS5260_TMU_DATA },
369 { EXYNOS5260_TMU_DATA },
370 { EXYNOS5260_TMU_DATA },
371 { EXYNOS5260_TMU_DATA },
372 { EXYNOS5260_TMU_DATA },
373 },
374 .tmu_count = 5,
375};
376#endif
377
14a11dc7
NKC		 378#if defined(CONFIG_SOC_EXYNOS5420)
379static const struct exynos_tmu_registers exynos5420_tmu_registers = {
380 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
381 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
382 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
383 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
384 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
385 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
386 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
387 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
388 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
389 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
390 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
391 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
392 .tmu_status = EXYNOS_TMU_REG_STATUS,
393 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
394 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
395 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
396 .tmu_inten = EXYNOS_TMU_REG_INTEN,
397 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
398 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
399 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
400 /* INTEN_RISE3 Not availble in exynos5420 */
401 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
402 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
403 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
404 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
405 .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
406 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
407 .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
408 .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
409 .emul_con = EXYNOS_EMUL_CON,
410 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
411 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
412 .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
413};
414
415#define __EXYNOS5420_TMU_DATA \
416 .threshold_falling = 10, \
417 .trigger_levels[0] = 85, \
418 .trigger_levels[1] = 103, \
419 .trigger_levels[2] = 110, \
420 .trigger_levels[3] = 120, \
421 .trigger_enable[0] = true, \
422 .trigger_enable[1] = true, \
423 .trigger_enable[2] = true, \
424 .trigger_enable[3] = false, \
425 .trigger_type[0] = THROTTLE_ACTIVE, \
426 .trigger_type[1] = THROTTLE_ACTIVE, \
427 .trigger_type[2] = SW_TRIP, \
428 .trigger_type[3] = HW_TRIP, \
429 .max_trigger_level = 4, \
430 .gain = 8, \
431 .reference_voltage = 16, \
432 .noise_cancel_mode = 4, \
433 .cal_type = TYPE_ONE_POINT_TRIMMING, \
434 .efuse_value = 55, \
435 .min_efuse_value = 40, \
436 .max_efuse_value = 100, \
437 .first_point_trim = 25, \
438 .second_point_trim = 85, \
439 .default_temp_offset = 50, \
440 .freq_tab[0] = { \
441 .freq_clip_max = 800 * 1000, \
442 .temp_level = 85, \
443 }, \
444 .freq_tab[1] = { \
445 .freq_clip_max = 200 * 1000, \
446 .temp_level = 103, \
447 }, \
448 .freq_tab_count = 2, \
449 .registers = &exynos5420_tmu_registers, \
450
451#define EXYNOS5420_TMU_DATA \
452 __EXYNOS5420_TMU_DATA \
453 .type = SOC_ARCH_EXYNOS5250, \
454 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
455 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
456 TMU_SUPPORT_EMUL_TIME)
457
458#define EXYNOS5420_TMU_DATA_SHARED \
459 __EXYNOS5420_TMU_DATA \
460 .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
461 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
462 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
463 TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
464
465struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
466 .tmu_data = {
467 { EXYNOS5420_TMU_DATA },
468 { EXYNOS5420_TMU_DATA },
469 { EXYNOS5420_TMU_DATA_SHARED },
470 { EXYNOS5420_TMU_DATA_SHARED },
471 { EXYNOS5420_TMU_DATA_SHARED },
472 },
473 .tmu_count = 5,
474};
475#endif
476
90542546
ADK		 477#if defined(CONFIG_SOC_EXYNOS5440)
478static const struct exynos_tmu_registers exynos5440_tmu_registers = {
479 .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
480 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
481 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
482 .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
483 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
484 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
485 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
486 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
487 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
488 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
489 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
1928457e
ADK		 490 .calib_mode_shift = EXYNOS_TMU_CALIB_MODE_SHIFT,
491 .calib_mode_mask = EXYNOS_TMU_CALIB_MODE_MASK,
90542546
ADK		 492 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
493 .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
494 .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
495 .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
496 .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
497 .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
498 .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
499 .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
90542546
ADK		 500 .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
501 .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
502 .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
503 .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
504 .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
505 .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
506 .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
74429c2f
NKC		 507 .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
508 .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
509 .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
510 .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
90542546
ADK		 511 .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
512 .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
513 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
514 .tmu_pmin = EXYNOS5440_TMU_PMIN,
515};
516
517#define EXYNOS5440_TMU_DATA \
518 .trigger_levels[0] = 100, \
519 .trigger_levels[4] = 105, \
520 .trigger_enable[0] = 1, \
521 .trigger_type[0] = SW_TRIP, \
522 .trigger_type[4] = HW_TRIP, \
523 .max_trigger_level = 5, \
524 .gain = 5, \
525 .reference_voltage = 16, \
526 .noise_cancel_mode = 4, \
527 .cal_type = TYPE_ONE_POINT_TRIMMING, \
528 .cal_mode = 0, \
529 .efuse_value = 0x5b2d, \
530 .min_efuse_value = 16, \
531 .max_efuse_value = 76, \
532 .first_point_trim = 25, \
533 .second_point_trim = 70, \
534 .default_temp_offset = 25, \
535 .type = SOC_ARCH_EXYNOS5440, \
536 .registers = &exynos5440_tmu_registers, \
537 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
9025d563 538 TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
90542546
ADK		 539
540struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
541 .tmu_data = {
542 { EXYNOS5440_TMU_DATA } ,
543 { EXYNOS5440_TMU_DATA } ,
544 { EXYNOS5440_TMU_DATA } ,
545 },
546 .tmu_count = 3,
547};
548#endif
Linux kernel - Deliverables
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